JPH11110980A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To release a limit of a preservation term of stored data and to improve reliability by setting a specified memory cell among plural memory cells as a highly reliable area, storing the specified data in this area and adjusting the size of the memory sector of the highly reliable area with a command from the outside. SOLUTION: When a special sector specified command is stored in an SSE signal generation circuit 502, first of all, a write-in control circuit 501 makes nonvolatile memory transistors 505, 506 in the SSE signal generation circuit 502 an erase state. The nonvolatile memory transistor 507 is commonly connected respectively in its source line and floating gate FG to be erased similarly. The nonvolatile memory transistors 508, 506 are in the similar relation also. Thus, the transistors 507, 508 are erased similarly also. From such a state, the transistors 506, 505 are made respectively a program, a non-program, and the transistor 508, 507 are respectively turned off and on.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device capable of increasing the number of rewritable times and having a small decrease in cell current even when the holding time is long. .

[0002]

2. Description of the Related Art In recent years, FRAM (Ferro-electric Rando)
m Access Memory), EPROM (Erasable and Progr
ammable Read Only Memory), EEPROM (Electric
Non-volatile semiconductor memories such as Al Erasable and Programmable Read Only Memory) have attracted attention. EPRO
In M and EEPROM, data is stored by storing charge in a floating gate and detecting a change in threshold voltage due to the presence or absence of a charge by a control gate. The EEPROM includes a flash EEPROM which erases data in the entire memory chip or divides a memory cell array into arbitrary blocks and erases data in each block unit.

[0003] Memory cells constituting a flash EEPROM are roughly classified into a split gate type and a stacked gate type. Split gate type flash EE
A PROM is disclosed in WO 92/18980 (G11C 13/00). FIG. 3 shows the publication (WO92 / 1898).
0) Split gate type memory cell 1
01 shows a cross-sectional structure.

An N-type source S and a drain D are formed on a P-type single crystal silicon substrate 102. Source S
A floating gate FG is formed on a channel CH sandwiched between the gate and the drain D via a first insulating film 103. The control gate CG is formed over the floating gate FG with the second insulating film 104 interposed. Part of the control gate CG is arranged on the channel CH via the first insulating film 103,
The selection gate 105 is configured. Second insulating film 104
The data is stored by storing electrons in the floating gate FG surrounded by.

[0005]

In the case where electrons are stored in the floating gate FG, the cell current flowing through the memory cell decreases as the number of times of rewriting increases, so that stable writing and reading of data cannot be performed. This is because the second insulating film 1
04 is deteriorated, making it difficult for electrons to escape from the floating gate FG.
And then return to the floating gate FG again, the potential of the floating gate FG decreases, and the floating gate F
This is probably because a channel is formed under G, which makes it difficult.

[0006] Further, there is a limit to the retention period of the stored data, and there is a disadvantage that after a certain period, the data changes and reliability is lost. This is because F is in the erased state.
This is because electrons leak into G and enter G, resulting in a change to an electron injection state.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a specific memory cell among a plurality of memory cells is set as a high-reliability area, and a long-reliable area is set in the area. It is characterized in that data to be held for a period or data with a large number of rewrites is stored, and the size of the memory sector in the high reliability area can be adjusted by an external command.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile semiconductor memory device according to the present invention will be described. In the non-volatile semiconductor memory device of the present invention, some sectors of the non-volatile semiconductor memory are set as special sectors (high-reliability areas). At the time of writing and reading, the memory cells which have been written at the same time are read at the same time. As a result, the cell current at the time of reading flows twice as much as usual, and the number of rewritable times and the holding time can be increased.

FIG. 6 is a diagram in which the nonvolatile semiconductor memory of the present invention is divided in sector units. In FIG. 6, the number of sectors as special sectors can be increased or decreased. For example, only the first sector is a special sector, and the other sectors are used normally. Also, the first and second sectors are special sectors,
Others may be used normally. In the conventional memory, A0 to A3 and their inverted signals * A0 to A3 (* indicates inversion) are commonly applied to the address decoders of all sectors, but in the present invention, the address signal A0 and its inverted The inverted signal * A0 is applied so as to be independently and independently controllable, and A0 and its inverted signal * are applied to the other sectors.
A0 is commonly applied.

Therefore, by setting A0 and its inverted signal * A0 to the same value, for example, "H" for each sector,
The setting of the special sector is selected. FIG. 4 shows an example of the address decoder of each sector. A0, A1, A2, A3 in FIG.
Address data is applied to each of the four bits. This address data is transferred to 16 AND gates 400 to 4
Decode at 15. In the case of a general decoder, one AND gate becomes “H” for one address.

However, in FIG. 4, A0 and * A0 are always set to "H" so that two AND gates are set to "H" for one address. Thereby, for example, the AND gates 400 and 401 become “H” at the same time, and two word lines can be simultaneously selected. Now, assume that the bit of A0 for the first sector is ignored in FIG. That is, A0 and * A0 for the first sector are always set to “H” regardless of the input address. And, for the second to fourth sectors
A normal input address signal is applied to A0 and * A0. Then, only the first sector becomes a special sector.

Next, it is assumed that only the bits of A0 and * A0 for the second sector are similarly ignored. Then, the second sector becomes a special sector. As described above, if the bits of A0 and * A0 for each sector are ignored, the corresponding sector becomes a special sector. Therefore, the size (amount) of the memory sector in the high reliability area can be adjusted from outside.

FIG. 7 shows a split gate type memory cell 1.
1 shows an overall configuration of a flash EEPROM 121 using the same. The memory cell array 122 includes a plurality of memory cells 101 arranged in a matrix.
The control gates CG of the memory cells 101 arranged in the row direction are connected to common word lines WLa to WLz. The drains D of the memory cells 101 arranged in the column direction have common bit lines BLa to BLz.
It is connected to the. Source S of all memory cells 101
Are connected to a common source line SL.

Each word line WLa-WLz is connected to a row decoder 123, and each bit line BLa-BLz is connected to a column decoder 124. The row address and column address applied from the outside are applied to the address pin 1
25. The row address and the column address are sent from the address pin 125 to the address buffer 12.
6 to the address latch 127. Of the addresses latched by the address latch 127, the row address is transferred to the row decoder 123, and the column address is transferred to the column decoder 124.

The memory cell array 122 is divided into a special sector array (for example, word lines WLa to WLn) and a normal sector array (for example, word lines WLy to WLz). The decoder 123 selects two word lines WLa to WLn (for example, WLm and WLn) corresponding to the row address latched by the address latch 127, and selects the selected word lines WLm and WLn, the gate voltage control circuit 134, Connect.

The column decoder 124 selects bit lines BLa to BLz (for example, BLm) corresponding to the column address latched by the address latch 127, and connects the selected bit line BLm to the drain voltage control circuit 133. . The gate voltage control circuit 134 is connected to the word lines WLm and WLn connected via the row decoder 123.
Is controlled in accordance with each operation mode shown in FIG. The drain voltage control circuit 133 is connected to the column decoder 1
24, the potential of the bit line BLm connected via
Is controlled in accordance with each operation mode shown in FIG.

The common source line SL is connected to the source voltage control circuit 1
32. The source voltage control circuit 132
The potential of the common source line SL is controlled according to each operation mode shown in FIG. Data specified externally is input to the data pin 128. The data is transferred from the data pin 128 to the column decoder 124 via the input buffer 129. The column decoder 124 controls the potentials of the bit lines BLa to BLz selected as described above in accordance with the data, as described later.

Data read from an arbitrary memory cell 101 is transferred from the bit lines BLa to BLz to the sense amplifier group 130 via the column decoder 124. The sense amplifier group 130 includes several sense amplifiers (not shown).
It is composed of The column decoder 124 connects the selected bit line BLm to each sense amplifier. As described later, the data determined by the sense amplifier group 130 is output from the output buffer 131 to the outside via the data pin 128.

The operation of each of the circuits (123 to 134) is controlled by the control core circuit 140. In the present invention, two word lines (for example, WLm and WLn) corresponding to memory cells whose sources are commonly connected are simultaneously selected from the word lines WLa to WLz. As a result, the same data is written to two memory cells. Therefore, if the two memory cells are read simultaneously, the read cell current is doubled.

It is assumed that memory cells 300 and 301 are selected as special sector memory cells to which the same data is written. The memory cell 300 and the memory cell 301 are in a page (sector) unit relationship having a common source and a bit line. Word lines WLm and W of memory cells 300 and 301
The method of simultaneously selecting Ln follows FIG. 6 described above.

FIG. 9 shows the address buffer 126 of FIG.
Specific examples of the address latch 127 and the row decoder 123 will be described. FIG. 9 shows a configuration in which the bit of A0 is ignored and two word lines specified by A0 are simultaneously selected. The bit signal of A0 in the input address is applied to the address pin 301. The bit signals of A1 and A2 in the input address are applied to address pins 302 and 303.

The bit signal of A0 is supplied to a NOR gate 304 for chip enable functioning as an address buffer.
, And is latched by a latch circuit 305 (comprising a flip-flop) as an address latch. A chip enable signal is applied to a terminal 306, and a clock signal is applied to a terminal 307. The latch circuit 305 outputs an inverted signal *
A0 and the non-inverted signal A0 are generated, and the first to fourth selection circuits 30
The inverted signals * A0 and the non-inverted signal A0 are commonly applied to address decoders 8 to 311 and not to be selected as a special sector.

First to fourth selection circuits 308 to 311
Is an SSE (Special Sector Enable) circuit 312
Select whether to pass the inverted signal * A0 and the non-inverted signal A0 as they are, or to forcibly set the two signals to the "H" level in accordance with the control signal from the CPU. For example, when a control signal of “L, H, H, H” is applied from the SSE circuit 312 to the first to fourth selection circuits 308 to 311, the first selection circuit 308 generates “H, H”. The second to fourth selection circuits 309 to 311 pass the input inverted signal * A0 and non-inverted signal A0 as they are. Thus, the first
The inverted signal * A0 of H and the non-inverted signal A0 are supplied to the decoder of the sector 313, and the second to fourth selecting circuits 309 to 311 are supplied to the second to fourth sectors 314 to 316.
A0 and * A0 signals are applied. At this time, the A1 bit signal is applied from the address pin 302 to the first to fourth sectors 313 to 316 and the decoders of all the sectors via the NOR gate 317 and the latch circuit 318. The same applies to the A2 bit signal from the address pin 303.

As a result, a signal in which the A0 bit is ignored is applied to only the first sector 313, and two word lines are simultaneously selected in the first sector 313. To increase the area of the special sector, for example, a signal in which the A0 bit is ignored may be added to the second sector 314 in addition to the first sector 313. That is, “L, L, H,
H ”to the first to fourth selection circuits 308 to 31
Apply to 1.

Using the block of FIG. 9 as described above,
When a user switches the control signal of the SSE circuit 312 from outside the memory, a special sector can be selected and used. In the nonvolatile memory shown in FIG. 9, when a sector selected as a special sector is selected, the address input A0 is ignored, so that external address data is applied to A1 to An to access a normal sector. In this case, it is applied to A0 to An.

FIG. 8 shows a specific circuit example of the first to fourth selection circuits 308 to 311. An inverted signal * A0 and a non-inverted signal A0 are applied to the terminals 319 and 320 from the latch circuit 305. A control signal is applied to the terminal 321 from the SSE circuit 312. When “L” is applied to the terminal 321, the output terminals 324 and 325 of the NAND gates 322 and 323 are forced to “H”. When "H" is applied to the terminal 321, the inverted signal * A0 and the non-inverted signal A0 appear at the output terminals 324 and 325 as they are.

FIG. 1 shows that a user sets a desired special sector from the outside of the nonvolatile semiconductor memory device of the present invention by a program, and once the setting is made, the special sector can be immediately specified by simply turning on the power to the memory device. FIG. 3 shows a block diagram for enabling this. The special sector can be specified externally from the nonvolatile semiconductor memory device.
This is performed by the command (data) applied to the I / O terminal. The command causes the write control circuit 501 to operate and
The E signal generation circuit 502 holds data indicating whether or not to make a special sector based on the command. Then SS
An “L” level SSE signal is generated from E signal generation circuit 502.

Further, once the command is held, the SSE signal generation circuit 502 immediately generates the SSE signal by simply turning on the power to the memory device. This SSE
The signal is generated before the memory cell operates, and a special sector of the memory cell can be designated. A command for designating a special sector is stored in the command register 503 of FIG. FIG. 10 shows this state. When both the * CE (chip enable) signal and the * WE (write enable) signal applied to the command register 503 become "L", the command (data) from the I / O terminal is stored in the command register 503.

The first command, SSEPM (special sector enable program mode), is a setup command, and indicates that the mode is a mode for designating a special sector. The next command, SSEP (Special Sector Enable Program), has information on which sector is a special sector.

The write control circuit 501 and the step-up power supply 504 start the circuit operation according to the SSEPM. Next, when SSEP is applied to the write control circuit 501, the write control circuit 501 performs a program operation on the designated SSE signal generation circuit. There are as many SSE signal generation circuits as the number of sectors designated as special sectors. The SSE signal generation circuit 502 in FIG. 1 shows one of the plurality of SSE signal generation circuits. When programming a nonvolatile memory transistor incorporated in the SSE signal generation circuit 502, the voltage of a word line, a bit line, and a source line is generated from the write control circuit 501.

Now, it is assumed that a command for designating a special sector is stored in the SSE signal generating circuit 502. First, the write control circuit 501 puts the nonvolatile memory transistors 505 and 506 of the SSE signal generation circuit 502 into an erased state. This is performed with the voltage setting of FIG. 2 as described later.
The nonvolatile memory transistor 507 includes a source line and an FG
(Floating gates) are connected in common,
Similarly erased. Non-volatile memory transistor 508
And the nonvolatile memory transistor 506 have a similar relationship.

Therefore, the nonvolatile memory transistor 5
07 and 508 are also erased at the same time. From this state, the nonvolatile memory transistor 506 is now set according to the voltage setting of FIG.
Is programmed (electrons are injected into the FG), and the non-volatile memory transistor 505 is not programmed, the non-volatile memory transistor 508 is turned off and the non-volatile memory transistor 507 is turned on. This ON information is stored in the latch circuit 509 and is derived as a * SSE signal.

The storage timing in the latch circuit 509 will be described with reference to FIG. By command
It is assumed that SSEPM rises as shown in FIG. 11C and SSEP subsequently rises. Then, the latch circuit 50
9 is connected to the power supply voltage L shown in FIG.
Is added. The power supply voltage L rises as the power supply rises and falls as the SSEPM falls. Then, the latch circuit 509 temporarily becomes inactive.

On the other hand, the signal shown in FIG. 11F is applied to the bases of the transmission transistors 515 and 516 to turn on. FIG. 11F is generated according to FIG. Therefore, power is turned on after a signal is applied to the latch circuit 509. FIG. 11E shows the time t.
0, the nonvolatile memory transistor 507
Of the latch circuit 509 and the transistor 51
6. A current flows through the nonvolatile memory transistor 507. Then, the output terminal 517 of the latch circuit 509 changes to the “L” state. That is, the word line is set to 2 as * SSE.
The control signal for the actual selection is obtained. At this time, the latch circuits of the other plurality of SSE signal generation circuits (not shown) are inverted, and an “H” signal is generated as * SSE.

Next, the range of the special sector is determined,
The case where the power of the flash EEPROM b is turned off after the SSE signal generation circuit is once programmed and used again will be described. When the power supply rises as shown in FIG. 11A, the power-up rises as shown in FIG. 11B. Then, the volatile memory transistor 50
7 and 508, FG data remains, and when a bias is applied, the nonvolatile memory transistor 507 immediately turns on and the nonvolatile memory transistor 508 immediately turns off. Therefore, data is held in the latch circuit 509 in accordance with the rise of the power supply. Since this operation is performed sufficiently faster than a memory cell requiring a read operation, reading and writing in a special sector can be performed without any trouble.

Next, each operation mode (erase mode, write mode, read mode) of the flash EEPROM 121 will be described with reference to FIGS. (A) Erase Mode In the erase mode, the potentials of the common source line SL and all the bit lines BLa to BLz are set to the ground level (= 0).
V). 14 is applied to the selected word line WLm.
To 15 V is supplied, and the potentials of the other word lines (non-selected word lines) WLa to WLl and WLn to WLz are set to the ground level. Therefore, the selected word line W
The control gate CG of each memory cell 101 connected to Lm is raised to 14 to 15V.

When the capacitance between the source S and the substrate 102 and the floating gate FG is compared with the capacitance between the control gate CG and the floating gate FG, the former is overwhelmingly larger. Therefore, the control gate CG becomes 14 to 1
When the voltage is 5 V and the source is 0 V, a high electric field is generated between the control gate CG and the floating gate FG. As a result, the Fowler-Nordheim Tunnel current
Current, hereinafter referred to as an FN tunnel current) flows, electrons in the floating gate FG are drawn out to the control gate CG side, and data stored in the memory cell 101 is erased.

This erase operation is performed by selecting the selected word line WL.
This is performed for all the memory cells 101 connected to m. Note that by simultaneously selecting a plurality of word lines WLa to WLz, an erase operation can be performed on all the memory cells 101 connected to each word line. The erasing operation of dividing the memory cell array 122 into arbitrary blocks for each of a plurality of sets of word lines WLa to WLz and erasing data in each block is called block erasing.

(B) Write Mode In the write mode, the potentials of the bit lines BLa to BLz are set to the ground for the cell for performing the program (injecting electrons into the floating gate FG), and are set to the high potential for the other cells. To Here, according to the present invention, one data that is to be stably held even when the number of rewrites increases is stored in the memory cell 3.
00 and the memory cell 301 are simultaneously stored.

In this case, 2 V is supplied to the word lines WLm and WLn, and the other word lines (non-selected word lines) WLa to WLl and WLo to WLz are set to the ground level. 12 V is supplied to the common source line SL. Then, the memory cell 300 and the memory cell 30
1 are written simultaneously.

Incidentally, in the memory cell 101, the threshold voltage Vth of the transistor constituted by the control gate CG, the source S and the drain D is 0.5V. Therefore, in the selected memory cell 101, the electrons in the drain D move into the channel CH in the inverted state.
Therefore, a current (cell current) flows from the source S to the drain D.
Flows. On the other hand, since 12 V is applied to the source S,
Due to the coupling between the source S and the floating gate FG via the capacitance, the potential of the floating gate FG is raised. Therefore, a high electric field is generated between the control gate CG and the floating gate FG. Accordingly, the electrons in the channel CH are accelerated to become hot electrons, and the hot electrons are injected into the floating gate FG as shown by an arrow A in FIG. As a result, charges are accumulated in the floating gate FG of the selected memory cell 101, and 1-bit data is written and stored.

(C) Read Mode In the read mode, the selected memory cell 101
4V is supplied to the word line WLm and the word line WLn connected to the control gate CG, and the other word lines (non-selected word lines) WLa to WLl and WLo to WLz
Is set to the ground level. 2 V is supplied to the bit line BLm connected to the drains D of the selected memory cells 300 and 301, and the potentials of the other bit lines (unselected bit lines) BLa to BLl and BLn to BLz are set to the ground level. To be.

As described above, since electrons are extracted from the floating gate FG of the memory cell 101 in the erased state, the floating gate FG is positively charged. Further, since electrons are injected into the floating gate FG of the memory cell 101 in the written state, the floating gate FG
Is negatively charged. Therefore, the channel CH immediately below the floating gate FG of the memory cell 101 in the erased state is on, and the channel CH immediately below the floating gate FG of the memory cell 101 in the written state is off. Therefore, when 4 V is applied to the control gate CG, the current (cell current) flowing from the drain D to the source S is larger in the erased memory cell 101 than in the written memory cell 101.

That is, only a small cell current flows through the memory cells 300 and 301. Conversely, the memory cells 300, 3
01 is not programmed (erase state), and if the floating gates FG of the memory cells 300 and 301 are positively charged, a current twice as large as the normal cell current flows.
By determining the magnitude of the cell current value Id between the memory cells 101 by each sense amplifier in the sense amplifier group 130, the value of the data stored in the memory cell 101 can be read. For example, the memory cell 1 in the erased state
Reading is performed with the data value of 01 being “1” and the data value of the memory cell 101 in the written state being “0”. That is, each memory cell 101 can store two values of the data value “1” in the erased state and the data value “0” in the written state.

FIG. 5 shows the relationship between the number of rewrites and the cell current. The number of times of rewriting is expressed in logarithm. The cell current A indicates a case where one memory cell is normally read, and the cell current B indicates a case where data is simultaneously read from two memory cells of the present invention. Assuming that the reference current for discriminating between 0 and 1 is Iref, it can be seen that the number of rewrites has increased tenfold. It is clear that the number of rewrites has increased significantly.

According to the present invention, the data retention time in which electrons can be retained in the floating gate of the memory cell is similarly improved. For example, when a memory cell is in an erased state, the floating gate of the memory cell is in a high positive state from which electrons are extracted. When the floating gate is in a high positive state, the floating gate takes in a large amount of electrons from the surroundings, so that its potential gradually decreases. Then, it becomes difficult to form a channel below the floating gate, and the cell current value decreases. However, according to the present invention, the reduction is halved and the life is extended.

[0047]

According to the present invention, it is possible to obtain a nonvolatile semiconductor memory device in which a decrease in cell current is small even if the number of times of rewriting increases. According to the present invention, the same data is simultaneously written and read to two or more memory cells, so that important data can be retained for a long time and the number of rewritable times can be increased. Further, according to the present invention, the size (amount) of the memory sector in the high reliability area can be adjusted by an external command, so that the user can select the memory sector only by changing the program software.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a diagram illustrating an operation mode applied to a memory cell of the nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a sectional view of a memory cell of the nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a specific circuit example of a row decoder 123 of the nonvolatile semiconductor memory device of the present invention.

FIG. 5 is a diagram showing the relationship between the number of rewrites and the cell current in a nonvolatile semiconductor memory device.

FIG. 6 is a diagram showing a sector of a memory having a special sector.

FIG. 7 is a block diagram showing an entire nonvolatile semiconductor memory device of the present invention.

FIG. 8 is a circuit diagram showing a specific example of first to fourth selection circuits;

FIG. 9 is a block diagram when the nonvolatile semiconductor memory device of the present invention is externally programmed.

FIG. 10 is a waveform chart for describing FIG. 9;

FIG. 11 is a waveform chart for explaining FIG. 9;

[Explanation of symbols]

 101 memory cell 122 memory cell array WLA to WLZ word line BLA to BLZ bit line SL common source line 308 to 311 first to fourth selection circuits 313 to 316 first to fourth sectors

Claims (5)

[Claims] A specific memory cell among a plurality of memory cells is set as a high-reliability area, and data to be held for a long period of time or data with a large number of rewrites is stored in the high-reliability area. The size of the non-volatile semiconductor memory device can be adjusted by an external command. 2. A method according to claim 1, wherein a specific memory sector among a plurality of memory sectors is set as a high-reliability area. Wherein the simultaneously written memory cells are simultaneously read and the size of the memory sector in the high reliability area can be adjusted by an external command. 3. A specific memory sector among a plurality of memory sectors is set as a high-reliability area, and in this area, writing is performed simultaneously on two or more memory cells while writing is performed. A non-volatile semiconductor memory device which simultaneously reads the memory cells simultaneously written, wherein at least one bit data of address data corresponding to a memory sector in a high reliability area is externally commanded. Inverted signal and non-inverted signal are equalized, so that two or more memory cells are simultaneously selected in the memory sectors in the high reliability area, and the number of memory sectors in the high reliability area can be adjusted from outside. A nonvolatile semiconductor memory device characterized by the following. 4. A specific memory sector among a plurality of memory sectors is set as a high-reliability area. In this area, writing is performed simultaneously on two or more memory cells when writing is performed, and reading is performed when reading is performed. A nonvolatile semiconductor memory device configured to simultaneously read the memory cells written at the same time, comprising: a latch circuit that latches an inverted signal and a non-inverted signal of one bit of address data; And a plurality of selection circuits for respectively supplying an inverted signal and a non-inverted signal from the latch circuit to the plurality of memory sectors, and generated from one of the plurality of selection circuits in response to an external command. The values of the inverted signal and the non-inverted signal are made equal, and two or more memory cells are The nonvolatile semiconductor memory device which is characterized in that so as to be selected upon. 5. A specific memory sector among a plurality of memory sectors is set as a high-reliability area, and in this area, writing is performed simultaneously on two or more memory cells while writing is performed. A non-volatile semiconductor memory device that simultaneously reads the memory cells written simultaneously, comprising: an SSE circuit that holds selection data of the specific memory sector in response to an external command; Selecting means for changing a signal of address data applied to the specific memory sector in accordance with an output signal, wherein the size of a memory sector in a high reliability area can be adjusted by the command. Semiconductor memory device.