JP3621237B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and relates to a semiconductor integrated circuit having an internal step-down circuit.
In a semiconductor integrated circuit, as the degree of integration progresses, it is necessary to lower the driving voltage in order to ensure transistor reliability and reduce current consumption. However, since the drive voltage cannot be freely set due to the external interface or the like, the drive voltage supplied from the outside is converted using an internal step-down circuit to obtain a desired voltage.
[0002]
[Prior art]
11 and 12 show circuit diagrams of examples of conventional circuits. PMOS-type step-down circuit shown in FIG. 11, an internal voltage Vii by differentially amplifying a reference voltage Vref in the differential amplifier circuit 10 the internal voltage Vii, and applies the amplified voltage to the gate of the p-channel MOS transistor _{P 1} Set to a constant value.
[0003]
NMOS type step-down circuit shown in FIG. 12, by connecting a voltage divider circuit by a p-channel MOS transistors n-channel MOS transistors _{N 1} and resistor _R 1 that drain diode connection of _{P 2, R 2,} the R 1, _{R 2} The voltage V ₁ at the connection point is supplied to the differential amplifier circuit 10. Applying a voltage difference between the voltages _{V 1} and the reference voltage Vref obtained here to the gate of the MOS transistor _{P 2,} applying a drain voltage of the MOS transistor _{P 2} to the gate of n-channel MOS transistor _{N 2.} And outputting the internal voltage Vii from the source of the MOS transistor _{N 2.}
[0004]
[Problems to be solved by the invention]
Since the conventional pMOS step-down circuit performs a feedback operation, there is a risk of oscillation if the phase margin is not sufficient. For example, when the load change is large in active / standby, it is difficult to obtain the phase margin. The voltage Vii becomes unstable. Further, since driving the gate of the p-channel MOS transistors P _1, the change in drain-source current Ids is a problem such as easily give sharp noise to the power supply voltage V _CC.
[0005]
Further, the conventional nMOS type step-down circuit, while being fed back voltages V ₁ by the gate voltage generator of the MOS transistor N _2, stabilized designed for the change of the load is not changed easily. Further, since the output of the MOS transistor N ₂ is not fed back, there is no possibility of oscillation, and the voltage between the gate and source of the MOS transistor N ₂ does not change suddenly, so that it is less likely to give noise to the power supply voltage _VCC compared with the pMOS type step-down circuit. .
[0006]
However, this circuit because it does not feed back the output of the MOS transistor N _2, the internal circuits such as a DRAM that uses an internal voltage Vii persists standby mode internal voltage Vii rises. For this reason, the threshold VIH for high level determination generated from the internal voltage Vii fluctuates between the first access to the DRAM after the standby mode has continued for a long time and when the access continues several times. The precharge voltage Vpr of the sense amplifier generated from the internal voltage Vii varies. As a result, there is a problem that the margin for low level determination is reduced.
[0007]
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and a semiconductor capable of suppressing a rise in internal voltage during standby and suppressing a change in VIH of a DRAM as an internal circuit and reducing a margin for low level determination. An object is to provide an integrated circuit.
[0008]
[Means for Solving the Problems]
1 and 3 are reference diagrams of the present invention, and FIG. 2 shows a principle diagram of the present invention.
[0010]
The invention described in claim 1 includes an internal step-down circuit that steps down a voltage supplied from the outside and supplies it to the internal circuit as shown in FIG.
A rise suppressing means M1 for restraining an increase in the internal voltage during standby of the internal circuit;
The rise suppression means M1 detects the internal voltage, generates a feedback voltage, and applies it to the back gate of the n-channel MOS transistor Q2 that drives the transistor Q1 that outputs the internal voltage of the internal voltage down converter.
[0011]
Therefore, when the internal voltage rises during standby, the feedback voltage applied to the back gate of the n-channel MOS transistor that drives the transistor that outputs the internal voltage changes, and the threshold value of the driving MOS transistor changes. The internal voltage can be kept substantially constant by changing the driving force of the output transistor.
[0012]
According to a second aspect of the invention, in a semiconductor integrated circuit according to claim 1,
The rise suppressing means differentially amplifies the internal voltage with a reference voltage to generate the feedback voltage.
As a result, the feedback voltage can be generated even when the feedback voltage is lower than the detected value of the internal voltage.
[0013]
According to a third aspect of the invention, in the semiconductor integrated circuit according to claim 1,
The rise suppression means divides the internal voltage to generate the feedback voltage.
As a result, the feedback voltage can be generated with a simple circuit.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 shows a circuit diagram of the first embodiment of the present invention. In the same figure, a voltage dividing circuit composed of an n-channel MOS transistor N ₁ and a resistor R ₁ , R ₂ diode-connected to the drain of a p-channel MOS transistor P ₂ is connected to a voltage V at a connection point of the resistors R ₁ , R _{2. 1} is supplied to the differential amplifier circuit 10. The amplified voltage differential voltage between the voltage _{V 1} and the reference voltage Vref obtained here is applied to the gate of the MOS transistor _{P 2,} applying a drain voltage of the MOS transistor _{P 2} to the gate of n-channel MOS transistor _{N 2.} The internal voltage Vii is output from the source of the MOS transistor N ₂ to the output line 12. Supply voltage _{V SS} is applied to the back gate MOS transistor _{N 2.}
[0016]
The output line 12 is connected to a feedback circuit as a rise suppression means comprising a low-pass filter 14 and a differential amplifier circuit 18. The low-pass filter 14 is composed of a resistor R ₃ and a MOS capacitor C ₁ , removes high-frequency component noise of the internal voltage Vii, and supplies it to the differential amplifier circuit 18. The differential amplifier circuit 18 performs differential amplification between the internal voltage Vii from which noise has been removed and the reference voltage Vref, and applies the amplified voltage of the difference voltage as a back gate voltage Vb to the back gate of the diode-connected MOS transistor N _1. To do.
[0017]
Here, the relationship between the gate-source current IVii internal voltage Vii and the MOS transistor _{N 2} is as shown in FIG. The relationship between MOS transistors N ₁ of the back gate-source voltage Vbs and the threshold voltage is as shown in FIG. That is, the internal voltage by the threshold of the MOS transistor _{N 1} and the back gate voltage Vb of the MOS transistors _{N 1} when the internal voltage Vii rises is increased is reduced becomes the standby mode, the gate voltage of the MOS transistor _{N 2} is reduced Vii is kept substantially constant.
[0018]
FIG. 7 shows a circuit diagram of a second embodiment of the present invention. In the same figure, a voltage dividing circuit composed of an n-channel MOS transistor N ₁ and a resistor R ₁ , R ₂ diode-connected to the drain of a p-channel MOS transistor P ₂ is connected to a voltage V at a connection point of the resistors R ₁ , R _{2. 1} is supplied to the differential amplifier circuit 10. The amplified voltage differential voltage between the voltage _{V 1} and the reference voltage Vref obtained here is applied to the gate of the MOS transistor _{P 2,} applying a drain voltage of the MOS transistor _{P 2} to the gate of n-channel MOS transistor _{N 2.} The internal voltage Vii is output from the source of the MOS transistor N ₂ to the output line 12. Supply voltage _{V SS} is applied to the back gate MOS transistor _{N 2.}
[0019]
The output line 12 is connected to a feedback circuit 20 as a rise suppression means by voltage dividing resistors R ₄ and R ₅ and a MOS capacitor C ₂ that forms a low-pass filter together with the resistor R ₄ . Feedback circuit dividing the internal voltage Vii min, and applied to the back gate MOS transistor N ₁ by removing the noise of the high frequency component as a back gate voltage Vb. This embodiment is a circuit when the feedback circuit 20 does not require amplification. Back gate voltage Vb of the MOS transistors _{N 1} when the internal voltage Vii rises is the threshold of the MOS transistor _{N 1} is decreased rise a standby mode, the internal voltage Vii by the gate voltage of the MOS transistor _{N 2} is reduced In this direction, Vii is held substantially constant.
[0020]
FIG. 8 shows a circuit diagram of a third embodiment of the present invention. In the same figure, a voltage dividing circuit composed of an n-channel MOS transistor N ₁ and a resistor R ₁ , R ₂ diode-connected to the drain of a p-channel MOS transistor P ₂ is connected to a voltage V at a connection point of the resistors R ₁ , R _{2. 1} is supplied to the differential amplifier circuit 10. The amplified voltage differential voltage between the voltage _{V 1} and the reference voltage Vref obtained here is applied to the gate of the MOS transistor _{P 2,} applying a drain voltage of the MOS transistor _{P 2} to the gate of n-channel MOS transistor _{N 2.} The internal voltage Vii is output from the source of the MOS transistor N ₂ to the output line 12. Supply voltage _{V SS} is applied to the back gate MOS transistor _{N 2.} The output line 12 is provided with a feedback circuit 22 as a rise suppression means comprising voltage dividing resistors R ₆ , R ₇ , R ₈ and analog switches 23, 24. The analog switches 23 and 24 are switched by the signal rasz supplied from the terminal 25 and the inverted signal of the inverter 26, only the analog switch 23 is turned on in the standby mode, and the voltage at the connection point of the resistors R ₆ and R ₇ is output. In the active mode, only the analog switch 24 is turned on, and the voltage at the connection point of the resistors R ₇ and R ₈ is output. The output voltage of the analog switches 23 and 24 is applied to the MOS transistors _{N 1} of the back gate as a back gate voltage Vf. That is, the divided voltage of the internal voltage Vii, which is high in a small partial pressure ratio is applied to the back gate transistor N ₁ is the standby mode to the active mode.
[0021]
This reduces the back-gate voltage Vf of the MOS transistors N ₁ when the internal voltage Vii rises a standby mode, the gate voltage of the MOS transistor N ₂ is an internal voltage Vii is kept substantially constant by reducing.
FIG. 9 shows a circuit diagram of a fourth embodiment of the present invention. In the same figure, a voltage dividing circuit composed of an n-channel MOS transistor N ₁ and a resistor R ₁ , R ₂ diode-connected to the drain of a p-channel MOS transistor P ₂ is connected to a voltage V at a connection point of the resistors R ₁ , R _{2. 1} is supplied to the differential amplifier circuit 10. The amplified voltage differential voltage between the voltage _{V 1} and the reference voltage Vref obtained here is applied to the gate of the MOS transistor _{P 2,} applying a drain voltage of the MOS transistor _{P 2} to the gate of n-channel MOS transistor _{N 2.} The internal voltage Vii is output from the source of the MOS transistor N ₂ to the output line 12.
[0022]
The output line 12 is connected to a feedback circuit as a rise suppression means comprising a low-pass filter 14 and a differential amplifier circuit 28. The low-pass filter 14 includes a resistor R ₃ and a MOS capacitor C ₁ , removes a high-frequency component such as noise contained in the internal voltage Vii, and supplies it to the differential amplifier circuit 28. The differential amplifier circuit 28 performs differential amplification of an internal voltage Vii removed the reference voltage Vref and noise is applied to amplified voltage of the difference voltage to the back gate MOS transistor N _2. The back gate of the MOS transistor _{N 1} is the power supply voltage _{V SS} is applied.
[0023]
Here, the internal voltage Vii rises back gate voltage of the MOS transistor N ₁ is decreased becomes standby mode, MOS threshold voltage of the transistor N ₂ is increased, substantially internal voltage Vii by the source voltage drops Held constant.
FIG. 10 shows a circuit diagram of a fifth embodiment of the present invention. In the same figure, a voltage dividing circuit composed of an n-channel MOS transistor N ₁ and a resistor R ₁ , R ₂ diode-connected to the drain of a p-channel MOS transistor P ₂ is connected to a voltage V at a connection point of the resistors R ₁ , R _{2. 2} is supplied to the differential amplifier circuit 10. Further, the series connection circuit of the rise suppression means to the resistor R ₁ in parallel with the resistor R10 and the switch SW is connected. A signal rasz is supplied from the terminal 30 to the switch SW. The amplified voltage differential voltage between the voltage _{V 2} and the reference voltage Vref obtained here is applied to the gate of the MOS transistor _{P 2,} applying a drain voltage of the MOS transistor _{P 2} to the gate of n-channel MOS transistor _{N 2.} The internal voltage Vii is output from the source of the MOS transistor N ₂ to the output line 12. Supply voltage _{V SS} is applied to the back gate MOS transistor _{N 2.}
[0024]
Here, the switch SW is turned on in the standby mode by the signal rasz and turned off in the active mode. That is, the synthesis of the source voltage of the MOS transistor _{N 1} is in active mode resistor _R 1, have been divided by _{R 2} minute connected resistor _{R 10} in parallel with the resistor _{R 1} is in the standby mode resistors _{R 1, R 10} resistance is reduced, the gate voltage of the MOS transistor _{N 2} is reduced source voltage of the MOS transistor _{N 1} is reduced. As a result, the internal voltage Vii is kept constant.
[0025]
【The invention's effect】
As described above, according to the first aspect of the present invention, when the internal voltage rises during standby, the feedback voltage applied to the back gate of the n-channel MOS transistor that drives the transistor that outputs the internal voltage changes. The internal voltage can be kept substantially constant by changing the threshold value of the driving MOS transistor and changing the driving force of the output transistor .
[0029]
According to the second aspect of the present invention, the feedback voltage can be generated even when the feedback voltage is higher than the detected value of the internal voltage.
[0030]
According to the third aspect of the present invention, the feedback voltage can be generated with a simple circuit.
[Brief description of the drawings]
FIG. 1 is a reference diagram of the present invention.
FIG. 2 is a principle diagram of the present invention.
FIG. 3 is a reference diagram of the present invention.
FIG. 4 is a circuit diagram of a first embodiment of the present invention.
FIG. 5 is a characteristic diagram for explaining the present invention.
FIG. 6 is a characteristic diagram for explaining the present invention.
FIG. 7 is a circuit diagram of a second embodiment of the present invention.
FIG. 8 is a circuit diagram of a third embodiment of the present invention.
FIG. 9 is a circuit diagram of a fourth embodiment of the present invention.
FIG. 10 is a circuit diagram of a fifth embodiment of the present invention.
FIG. 11 is a circuit diagram of a conventional circuit.
FIG. 12 is a circuit diagram of a conventional circuit.
[Explanation of symbols]
10, 18, 28 Differential amplifier circuit 12 Output line 14 Low-pass filter 20, 22 Feedback circuit P1, P2 P-channel MOS transistor N1, N2 n-channel MOS transistor R1-R10 Resistance C1, C2 MOS capacitance M1 Increase suppression means

Claims (3)

An internal step-down circuit that steps down the voltage supplied from the outside and supplies it to the internal circuit as an internal voltage;
An increase suppression means for suppressing an increase in the internal voltage during standby of the internal circuit;
The rise suppression means detects the internal voltage, generates a feedback voltage, and applies it to a back gate of an n-channel MOS transistor that drives a transistor that outputs the internal voltage of the internal voltage down converter. circuit. The semiconductor integrated circuit according to claim 1,
The rise suppression means differentially amplifies the internal voltage with a reference voltage to generate the feedback voltage . The semiconductor integrated circuit according to claim 1 ,
2. The semiconductor integrated circuit according to claim 1, wherein the rise suppression means divides the internal voltage to generate the feedback voltage .

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