JP3802409B2 - Bias circuit and power supply device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bias circuit and a power supply device, and more particularly to a bias circuit including a startup circuit when power is turned on, and a power supply device including the bias circuit.
[0002]
[Prior art]
A bias circuit that supplies a predetermined bias required for operation to a power supply device, etc., is activated to shorten the activation time of the reference voltage source circuit that generates a reference voltage based on the power supply voltage and the reference voltage source circuit when the power is turned on. And a start-up circuit for outputting a signal.
[0003]
Specifically, as shown in FIG. 7, the conventional bias circuit includes a startup circuit 101, a reference voltage source circuit 102, a high potential side power supply terminal 103, a low potential side power supply terminal 104, and an output terminal 105. The start-up circuit 101 includes a P-channel MOS transistor 106 that generates a level shift voltage of the power supply voltage of the high potential side power supply terminal 103, a capacitor 107 that holds the level shift voltage, and a high potential side power supply terminal at one end. A capacitor 108 to which a power supply voltage 103 is applied, an N-channel MOS transistor 109 to which a level shift voltage is applied to the gate and a source / drain path is connected between the other end of the capacitor 108 and the low-potential-side power supply terminal 104; Is supplied with the voltage at the other end of the capacitor 108 and outputs an activation signal. A P channel in which the reference voltage source circuit 102 folds a constant current generated by the N channel MOS transistor 115, the N channel MOS transistor 114, and the resistor 116 to generate a reference voltage at the output terminal 105. A current mirror circuit 112 a including a MOS transistor 112 and a P-channel MOS transistor 113 is provided.
[0004]
Immediately after the power supply voltage of the high potential side power supply terminal 103 is turned on with the power supply voltage of the low potential side power supply terminal 104 as a reference, the gate voltage of the N channel MOS transistor 111 rises by the capacitor 108 and the N channel MOS transistor 111 Is turned on and the current mirror circuit 112a is triggered by the drain current which is the start signal, and the drain current instantaneously flows to the P-channel MOS transistor 112 and the P-channel MOS transistor 113, whereby the N-channel MOS transistor 115 and the N-channel MOS transistor The constant current generated by the resistor 114 and the resistor 116 instantaneously rises, the gate-source voltage of the P-channel MOS transistor 112 is instantaneously output as the reference voltage, and the power supply voltage at the high potential side power supply terminal 103 further increases. If, to charge the capacitor 108 by turning on N-channel MOS transistor 109, N-channel MOS transistor 111 gate voltage drops of N-channel MOS transistor 111 is turned off, it operates to start-up operation is completed. In addition, when the power is turned off, the power supply voltage at the high potential side power supply terminal 103 decreases, the N channel MOS transistor 109 is turned on by the holding voltage of the capacitor 107 and the capacitor 108 is discharged, and the capacitor 107 is not shown in the figure. The battery is discharged through a path extending from the substrate 106 to the high-potential side power supply terminal 103 to return to the initial state.
[0005]
[Problems to be solved by the invention]
However, in the conventional bias circuit shown in FIG. 7, the power supply is turned off immediately after the high potential power supply terminal 103 is turned on with the power supply voltage of the low potential power supply terminal 104 as a reference, and the high potential power supply terminal 103 is halfway. When the power supply is turned on again when the power supply voltage of the power supply voltage is reduced, the power supply voltage of the high potential side power supply terminal 103 may rise while the N-channel MOS transistor 109 remains on due to the retained voltage of the capacitor 107. At this time, since the N-channel MOS transistor 111 remains in an OFF state, a start signal is not output, and there is a problem that the start time of the reference voltage source circuit 102, that is, the start time of the bias circuit cannot be shortened.
[0006]
The present invention has been made in view of such a problem. Even when the power is turned off immediately after the power is turned on and the power is turned on again, the start signal is output to start the reference voltage source circuit. It is an object of the present invention to provide a bias circuit capable of reducing time and a power supply device including the bias circuit.
[0007]
[Means for Solving the Problems]
The bias circuit according to the present invention includes a first transistor that generates a level shift voltage of a power supply voltage of a first power supply, a first capacitor that holds the level shift voltage, and a second capacitor that is supplied with the power supply voltage at one end. And the second transistor, and the level shift voltage is applied to the gate, and the source / drain path is connected to the other end of the second capacitor and the second power source via the source / drain path of the second transistor. A start-up circuit having a third transistor connected in between and a fourth transistor that outputs a start-up signal when a voltage at the other end of the second capacitor is applied to the gate; and triggered by the start-up signal And a reference voltage source circuit that has a current mirror circuit that folds a constant current and generates a reference voltage, and controls the second transistor. It is characterized in.
[0008]
A first P-channel transistor whose source is connected to the high-potential-side power supply terminal; a first capacitor connected between the drain and gate of the first P-channel transistor and the low-potential-side power supply terminal; A first N-channel transistor whose gate is connected to the drain; a second capacitor connected between the high-potential side power supply terminal and the drain of the first N-channel transistor; A first N-channel transistor connected to the source of the first N-channel transistor, a source connected to the low-potential-side power supply terminal, a gate connected to the drain of the first N-channel transistor, and a source connected to the low-potential Start-up circuit having a third N-channel transistor connected to the side power supply terminal, and a constant current as a reference A reference voltage source circuit having a current mirror circuit for generating a pressure, and the current mirror circuit is triggered by the drain current of the third N-channel transistor to start the reference voltage source circuit The second N-channel transistor is turned off before, and the second N-channel transistor is turned on after the activation.
[0009]
A first P-channel transistor whose source is connected to the high-potential-side power supply terminal; a first capacitor connected between the drain and gate of the first P-channel transistor and the low-potential-side power supply terminal; A first N-channel transistor whose gate is connected to the drain and whose source is connected to the low-potential-side power supply terminal; and a second N-channel transistor whose source is connected to the drain of the first N-channel transistor; A second capacitor connected between the high potential side power supply terminal and the drain of the second N-channel transistor; a gate connected to the drain of the second N-channel transistor; and a source connected to the low potential Start-up circuit having a third N-channel transistor connected to the side power supply terminal, and a constant current as a reference A reference voltage source circuit having a current mirror circuit for generating a pressure, and the current mirror circuit is triggered by the drain current of the third N-channel transistor to start the reference voltage source circuit The second N-channel transistor is turned off before, and the second N-channel transistor is turned on after the activation.
[0010]
An inverter to which a power down signal is applied, a first transistor for generating a level shift voltage of the output voltage of the inverter, a first capacitor for holding the level shift voltage, and the output voltage at one end. A second capacitor, a second transistor, and the level shift voltage is applied to the gate, and the source / drain path is between the other end of the second capacitor and the power supply via the source / drain path of the second transistor. A start-up circuit having a third transistor connected to the first transistor and a fourth transistor that outputs a start signal by applying a voltage at the other end of the second capacitor to the gate, and triggered by the start signal A current mirror circuit that folds back a constant current and generates a reference voltage; A voltage source circuit; and a reset circuit that stops the operation of the current mirror circuit by the power-down signal when in a power-down state and short-circuits the gate of the third transistor and the gate of the fourth transistor to the power source. It is characterized by providing.
[0011]
Also, an inverter to which a power down signal is given, a first P channel transistor whose source is connected to the output of the inverter, and between the drain and gate of the first P channel transistor and the low potential side power supply terminal A first capacitor connected; a first N-channel transistor having a gate connected to the drain; and a second N-channel transistor connected between the output of the inverter and the drain of the first N-channel transistor. A capacitor, a second N-channel transistor having a drain connected to the source of the first N-channel transistor and a source connected to the low-potential side power supply terminal, and a gate connected to the drain of the first N-channel transistor A third N-channel transistor connected and having a source connected to the low potential side power supply terminal; A startup circuit having a reference voltage source circuit having a current mirror circuit for generating a reference voltage by folding back a constant current, and stopping the operation of the current mirror circuit by the power down signal in the power down state and the first N A bias circuit comprising: a reset circuit that short-circuits the gate of the channel transistor and the gate of the third N-channel transistor to the low-potential side power supply terminal; and when the power-down state is released, The current mirror circuit is triggered by the drain current of the third N-channel transistor and the second N-channel transistor is turned off before the reference voltage source circuit is activated, and after the activation, the second N-channel transistor is It is in an on state.
[0012]
Also, an inverter to which a power down signal is given, a first P channel transistor whose source is connected to the output of the inverter, and between the drain and gate of the first P channel transistor and the low potential side power supply terminal A first capacitor connected; a first N-channel transistor having a gate connected to the drain and a source connected to the low-potential side power supply terminal; and a source connected to a drain of the first N-channel transistor. A second N-channel transistor, a second capacitor connected between the output of the inverter and the drain of the second N-channel transistor, and a gate connected to the drain of the second N-channel transistor. A third N-channel transistor connected and having a source connected to the low potential side power supply terminal; A startup circuit having a reference voltage source circuit having a current mirror circuit for generating a reference voltage by folding back a constant current, and stopping the operation of the current mirror circuit by the power down signal in the power down state and the first N A bias circuit comprising: a reset circuit that short-circuits the gate of the channel transistor and the gate of the third N-channel transistor to the low-potential side power supply terminal; and when the power-down state is released, The current mirror circuit is triggered by the drain current of the third N-channel transistor and the second N-channel transistor is turned off before the reference voltage source circuit is activated, and after the activation, the second N-channel transistor is It is in an on state.
[0013]
Furthermore, the power supply device of the present invention is provided with a first transistor that generates a level shift voltage of the power supply voltage of the first power supply, a first capacitor that holds the level shift voltage, and the power supply voltage applied to one end. The second capacitor, the second transistor, the gate is supplied with the level shift voltage, and the source / drain path is connected to the other end of the second capacitor and the second power source via the source / drain path of the second transistor. A start-up circuit comprising: a third transistor connected between the first transistor and a fourth transistor that outputs a start signal when a voltage of the other end of the second capacitor is applied to a gate; and the start signal A reference voltage source circuit that has a current mirror circuit that generates a reference voltage that is triggered by the constant current and generates a reference voltage, and controls the second transistor; And no bias circuit, characterized by comprising a power supply circuit including a transistor for supplying a predetermined bias current is a current source wherein the reference voltage is supplied to the gate, a.
[0014]
An inverter to which a power down signal is applied, a first transistor for generating a level shift voltage of the output voltage of the inverter, a first capacitor for holding the level shift voltage, and the output voltage at one end. A second capacitor, a second transistor, and the level shift voltage is applied to the gate, and the source / drain path is between the other end of the second capacitor and the power supply via the source / drain path of the second transistor. A start-up circuit having a third transistor connected to the first transistor and a fourth transistor that outputs a start signal by applying a voltage at the other end of the second capacitor to the gate, and triggered by the start signal A current mirror circuit that folds back a constant current and generates a reference voltage; A voltage source circuit; and a reset circuit that stops the operation of the current mirror circuit by the power-down signal when in a power-down state and short-circuits the gate of the third transistor and the gate of the fourth transistor to the power source. , And a power supply circuit including a transistor that supplies a predetermined bias current as a current source to which the reference voltage is applied to the gate.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a bias circuit according to the first embodiment of the present invention. As shown in FIG. 1, the bias circuit according to the first embodiment of the present invention includes a startup circuit 1, a reference voltage source circuit 2, a high potential side power supply terminal 3, a low potential side power supply terminal 4, and an output. And a terminal 5.
[0016]
The startup circuit 1 includes a P-channel MOS transistor 6, a capacitor 7, a capacitor 8, an N-channel MOS transistor 9, an N-channel MOS transistor 10, and an N-channel MOS transistor 11.
[0017]
The source of the P channel MOS transistor 6 is connected to the high potential side power supply terminal 3, and the capacitor 7 is connected between the drain and gate of the P channel MOS transistor 6 connected to each other and the low potential side power supply terminal 4.
[0018]
The gate of N channel MOS transistor 9 is connected to the drain of P channel MOS transistor 6.
[0019]
Capacitor 8 is connected between high potential side power supply terminal 3 and the drain of N channel MOS transistor 9.
[0020]
The drain of N channel MOS transistor 10 is connected to the source of N channel MOS transistor 9, and the source of N channel MOS transistor 10 is connected to low potential side power supply terminal 4.
[0021]
The gate of N channel MOS transistor 11 is connected to the drain of N channel MOS transistor 9, and the source of N channel MOS transistor 11 is connected to low potential side power supply terminal 4.
[0022]
The reference voltage source circuit 2 includes a current mirror circuit 12 a that folds back a constant current and generates a reference voltage at the output terminal 5, an N channel MOS transistor 14, an N channel MOS transistor 15, and a resistor 16.
[0023]
The current mirror circuit 12 a includes a P channel MOS transistor 12 and a P channel MOS transistor 13.
[0024]
The source of the P channel MOS transistor 12 is connected to the high potential side power supply terminal 3, and the drain and gate of the P channel MOS transistor 12 are connected to each other.
[0025]
The gate of P channel MOS transistor 12 is connected to the drain of N channel MOS transistor 11 of start-up circuit 1 and output terminal 5.
[0026]
The source of P channel MOS transistor 13 is connected to high potential side power supply terminal 3, and the gate of P channel MOS transistor 13 is connected to the gate of P channel MOS transistor 12.
[0027]
The drain of N channel MOS transistor 14 is connected to the drain of P channel MOS transistor 12.
[0028]
A resistor 16 is connected between the source of the N-channel MOS transistor 14 and the low potential side power supply terminal 4.
[0029]
The drain and gate of N channel MOS transistor 15 are connected to each other, and the drain of N channel MOS transistor 15 is connected to the drain of P channel MOS transistor 13.
[0030]
The source of N channel MOS transistor 15 is connected to low potential side power supply terminal 4, and the gate of N channel MOS transistor 15 is connected to the gate of N channel MOS transistor 14 and the gate of N channel MOS transistor 10 of startup circuit 1.
[0031]
Next, the operation will be described. FIG. 2 is an explanatory diagram of the operation of the bias circuit according to the first embodiment of the present invention.
[0032]
As shown in FIG. 2, first, at time t0, the power supply voltage V3 of the high potential side power supply terminal 3 is turned on with reference to the power supply voltage V4 of the low potential side power supply terminal 4, and rises toward a predetermined power supply voltage VDD2. The gate voltage V2 of the N channel MOS transistor 11 is also increased by the capacitor 8.
[0033]
At this time, both N-channel MOS transistor 10 and N-channel MOS transistor 11 are off.
[0034]
Next, at time t1 after time t0, when the gate voltage V2 of the N-channel MOS transistor 11 reaches the threshold voltage VTH11 of the N-channel MOS transistor 11, the N-channel MOS transistor 11 is turned on, and the N-channel which is the start signal The current mirror circuit 12a is triggered by the drain current of the MOS transistor 11, and the drain current instantaneously flows in the P-channel MOS transistor 12 and the P-channel MOS transistor 13, whereby the N-channel MOS transistor 15, the N-channel MOS transistor 14, and the resistor 16 As a result, the constant current generated by the above instantaneously rises, and the gate-source voltage of the P-channel MOS transistor 12 is instantaneously output to the output terminal 5 as the reference voltage from the reference voltage source circuit 2.
[0035]
If the threshold voltage of the N channel MOS transistor 15 is VTH15, the threshold voltage of the N channel MOS transistor 14 is VTH14, the value of the resistor 16 is R, and the constant current value is I, the N channel MOS transistor 15 Is equal to the gate voltage of the N-channel MOS transistor 14.
A constant current of I = (VTH15−VTH14) ÷ R is generated.
[0036]
At this time, since the gate voltage of N channel MOS transistor 15 is applied, N channel MOS transistor 10 is also turned on.
[0037]
At this time, since the power supply voltage V3 of the high potential side power supply terminal 3 reaches the threshold voltage VTH6 of the P-channel MOS transistor 6, the gate voltage V1 of the N-channel MOS transistor 9 starts to rise.
[0038]
Next, at time t2 after time t1, when the power supply voltage V3 of the high potential side power supply terminal 3 reaches the sum of the threshold voltage VTH6 of the P-channel MOS transistor 6 and the threshold voltage VTH9 of the N-channel MOS transistor 9, N Channel MOS transistor 9 is turned on, capacitor 8 is charged, and has a time constant of the product of the sum of the on resistance of N channel MOS transistor 9 and the on resistance of N channel MOS transistor 10 and the capacitance of capacitor 8 As a result, the gate voltage V2 of the N-channel MOS transistor 11 decreases.
[0039]
Next, at time t3 after time t2, when the gate voltage V2 of the N channel MOS transistor 11 reaches the threshold voltage VTH11 of the N channel MOS transistor 11, the N channel MOS transistor 11 is turned off and the start-up operation is completed.
[0040]
Next, at time t4 after time t3, the power is temporarily turned off in the middle of turning on the power, the power supply voltage V3 of the high potential side power supply terminal 3 becomes a voltage VDD1 lower than the power supply voltage VDD2, and at time t5 after time t4. When the power supply voltage V3 of the high potential side power supply terminal 3 falls to a voltage VDD0 lower than the threshold voltage VTH11 of the N-channel MOS transistor 11, the gate voltage V2 of the N-channel MOS transistor 11 is pushed down by the capacitor 8, and the N-channel MOS transistor 9 is turned on, the drain voltage of the N channel MOS transistor 10 is pushed down, the source and drain of the N channel MOS transistor 10 are switched, and the threshold voltage VTH10 of the N channel MOS transistor 10 is connected to the gate of the N channel MOS transistor 10. Nearby electricity There therefore remaining, the N-channel MOS transistor 10 is turned on as reverse direction transistor, the capacitor 8 is discharged.
[0041]
At this time, the gate voltage V2 of the N channel MOS transistor 11 is lower than the voltage VDD0 by the threshold voltage VTH10 of the N channel MOS transistor 10.
[0042]
From time t4, the capacitor 7 holds the gate voltage V1 of the N-channel MOS transistor 9 at a voltage lower than the voltage VDD1 by the threshold voltage VTH6 of the P-channel MOS transistor 6.
[0043]
Next, at time t6 after time t5, when the power is turned on again, the power supply voltage V3 of the high potential side power supply terminal 3 starts to rise again toward the predetermined power supply voltage VDD2, but the N-channel MOS transistor 10 returns to the forward transistor, the gate voltage of the N-channel MOS transistor 10 is still lower than the threshold voltage VTH10 of the N-channel MOS transistor 10 and is turned off, and the N-channel MOS transistor 9 is turned on even though the N-channel MOS transistor 9 is turned on. 8 causes the gate voltage V2 of the N channel MOS transistor 11 to rise again.
[0044]
Next, at time t7 after time t6, when the gate voltage V2 of the N-channel MOS transistor 11 reaches the threshold voltage VTH11 of the N-channel MOS transistor 11, the N-channel MOS transistor 11 is turned on, and the N-channel which is the start signal The current mirror circuit 12a is triggered by the drain current of the MOS transistor 11, and the drain current instantaneously flows in the P-channel MOS transistor 12 and the P-channel MOS transistor 13, whereby the N-channel MOS transistor 15, the N-channel MOS transistor 14, and the resistor 16 As a result, the constant current generated by the above instantaneously rises, and the gate-source voltage of the P-channel MOS transistor 12 is instantaneously output to the output terminal 5 as the reference voltage from the reference voltage source circuit 2.
[0045]
At this time, since the gate voltage of the N channel MOS transistor 15 is applied, the N channel MOS transistor 10 is also turned on and charging of the capacitor 8 is started. The on resistance of the N channel MOS transistor 9 and the N channel MOS transistor 10 The gate voltage V2 of the N-channel MOS transistor 11 decreases with a characteristic having a time constant of the product of the sum of the on-resistance and the capacitance of the capacitor 8.
[0046]
Next, at time t8 after time t7, when the gate voltage V2 of the N channel MOS transistor 11 reaches the threshold voltage VTH11 of the N channel MOS transistor 11, the N channel MOS transistor 11 is turned off and the start-up operation is completed.
[0047]
Further, when the power is normally turned off, the power supply voltage of the high potential side power supply terminal 3 is lowered, the N channel MOS transistor 9 is turned on by the holding voltage of the capacitor 7, and the N channel MOS transistor 10 is also turned on. The capacitor 8 is discharged, and the capacitor 7 is discharged through a path from the substrate of the P-channel MOS transistor 6 (not shown) to the high potential side power supply terminal 3 to return to the initial state.
[0048]
As described above, according to the bias circuit of the first embodiment of the present invention, the P-channel MOS transistor 6 that generates the level shift voltage of the power supply voltage of the high potential side power supply terminal 3 and the level shift voltage are held. A capacitor 7 to which the power supply voltage of the high potential side power supply terminal 3 is applied at one end, an N-channel MOS transistor 10, and a source / drain path to which a level shift voltage is applied to the gate and the source / drain path of the N-channel MOS transistor 10 N-channel MOS transistor 9 connected between the other end of capacitor 8 and low-potential-side power supply terminal 4 through a path, and an N-channel that outputs a start signal when the voltage of the other end of capacitor 8 is applied to the gate A start-up circuit 1 having a MOS transistor 11 and a curl for generating a reference voltage by folding back a constant current And a reference voltage source circuit 2 having a mirror circuit 12a. The N-channel MOS transistor 10 is turned off before the reference voltage source circuit 2 is activated when the current mirror circuit 12a is triggered by the activation signal. Since the MOS transistor 10 is controlled to be in the on state, even when the power is turned off immediately after the power is turned on and the power is turned on again, the start signal is output and the start time of the reference voltage source circuit 2 is set. The effect that it can shorten is acquired.
[0049]
Next, FIG. 3 is a configuration diagram of a bias circuit according to the second embodiment of the present invention. The difference between the configuration of the bias circuit of the first embodiment of the present invention shown in FIG. 1 and the configuration of the bias circuit of the second embodiment of the present invention shown in FIG. 3 is the startup circuit 1 shown in FIG. Is the part where the N channel MOS transistor 9 is changed to the N channel MOS transistor 9a, and specifically the part where the N channel MOS transistor 10 is changed to the N channel MOS transistor 10a. Therefore, the same components are denoted by the same reference numerals, and detailed description thereof is omitted.
[0050]
As shown in FIG. 3, the bias circuit according to the second embodiment of the present invention includes a start-up circuit 1a, a reference voltage source circuit 2, a high potential side power supply terminal 3, a low potential side power supply terminal 4, and an output. And a terminal 5.
[0051]
The start-up circuit 1a includes a P-channel MOS transistor 6, a capacitor 7, a capacitor 8, an N-channel MOS transistor 9a, an N-channel MOS transistor 10a, and an N-channel MOS transistor 11.
[0052]
The source of the P channel MOS transistor 6 is connected to the high potential side power supply terminal 3, and the capacitor 7 is connected between the drain and gate of the P channel MOS transistor 6 connected to each other and the low potential side power supply terminal 4.
[0053]
The gate of N channel MOS transistor 9 a is connected to the drain of P channel MOS transistor 6, and the source of N channel MOS transistor 9 a is connected to low potential side power supply terminal 4.
[0054]
The source of N channel MOS transistor 10a is connected to the drain of N channel MOS transistor 9a.
[0055]
Capacitor 8 is connected between high potential side power supply terminal 3 and the drain of N channel MOS transistor 10a.
[0056]
The gate of N channel MOS transistor 11 is connected to the drain of N channel MOS transistor 10 a, and the source of N channel MOS transistor 11 is connected to low potential side power supply terminal 4.
[0057]
The reference voltage source circuit 2 includes a current mirror circuit 12 a that folds back a constant current and generates a reference voltage at the output terminal 5, an N channel MOS transistor 14, an N channel MOS transistor 15, and a resistor 16.
[0058]
The current mirror circuit 12 a includes a P channel MOS transistor 12 and a P channel MOS transistor 13.
[0059]
The source of the P channel MOS transistor 12 is connected to the high potential side power supply terminal 3, and the drain and gate of the P channel MOS transistor 12 are connected to each other.
[0060]
The gate of P channel MOS transistor 12 is connected to the drain of N channel MOS transistor 11 of start-up circuit 1 a and output terminal 5.
[0061]
The source of P channel MOS transistor 13 is connected to high potential side power supply terminal 3, and the gate of P channel MOS transistor 13 is connected to the gate of P channel MOS transistor 12.
[0062]
The drain of N channel MOS transistor 14 is connected to the drain of P channel MOS transistor 12.
[0063]
A resistor 16 is connected between the source of the N-channel MOS transistor 14 and the low potential side power supply terminal 4.
[0064]
The drain and gate of N channel MOS transistor 15 are connected to each other, and the drain of N channel MOS transistor 15 is connected to the drain of P channel MOS transistor 13.
[0065]
The source of N channel MOS transistor 15 is connected to low potential side power supply terminal 4, and the gate of N channel MOS transistor 15 is connected to the gate of N channel MOS transistor 14 and the gate of N channel MOS transistor 10a of startup circuit 1a.
[0066]
In the configuration of the bias circuit according to the first embodiment of the present invention shown in FIG. 1, the source / drain path of the N channel MOS transistor 9 and the source / drain path of the N channel MOS transistor 10 are connected in series. Also in the configuration of the bias circuit of the second embodiment of the present invention shown in FIG. 3, the source / drain path of the N channel MOS transistor 9a and the source / drain path of the N channel MOS transistor 10a are connected in series. The operation of the bias circuit according to the second embodiment of the present invention is the same as that of the bias circuit according to the first embodiment of the present invention shown in FIG.
[0067]
Therefore, according to the bias circuit of the second embodiment of the present invention shown in FIG. 3, the same effect as the bias circuit of the first embodiment of the present invention shown in FIG. 1 can be obtained.
[0068]
Next, FIG. 4 is a configuration diagram of a bias circuit according to a third embodiment of the present invention. The difference between the configuration of the bias circuit according to the first embodiment of the present invention shown in FIG. 1 and the configuration of the bias circuit according to the third embodiment of the present invention shown in FIG. 4 enables power-down control. Therefore, the start-up circuit 1 shown in FIG. 1 is changed to the start-up circuit 1b, and a power-down signal input terminal 17, a reset circuit 20, and a reset circuit 22 are added. These are only parts where a CMOS inverter 18 and a CMOS inverter 19 are added and the P-channel MOS transistor 6 and the capacitor 8 are changed to be connected to the output of the CMOS inverter 19. Therefore, the same components are denoted by the same reference numerals, and detailed description thereof is omitted.
[0069]
As shown in FIG. 4, the bias circuit 26 according to the third embodiment of the present invention includes a startup circuit 1b, a reference voltage source circuit 2, a high potential power supply terminal 3, a low potential power supply terminal 4, An output terminal 5, a power down signal input terminal 17, a reset circuit 20, and a reset circuit 22 are provided.
[0070]
The start-up circuit 1b includes a P-channel MOS transistor 6, a capacitor 7, a capacitor 8, an N-channel MOS transistor 9, an N-channel MOS transistor 10, an N-channel MOS transistor 11, a CMOS inverter 18, and a CMOS inverter 19. .
[0071]
A power-down signal is applied to the input of the CMOS inverter 18 from the power-down signal input terminal 17.
[0072]
The input of the CMOS inverter 19 is connected to the output of the CMOS inverter 18.
[0073]
The source of P channel MOS transistor 6 is connected to the output of CMOS inverter 19.
[0074]
A capacitor 7 is connected between the drain and gate of the P channel MOS transistor 6 connected to each other and the low potential side power supply terminal 4.
[0075]
The gate of N channel MOS transistor 9 is connected to the drain of P channel MOS transistor 6.
[0076]
Capacitor 8 is connected between the output of CMOS inverter 19 and the drain of N channel MOS transistor 9.
[0077]
The drain of N channel MOS transistor 10 is connected to the source of N channel MOS transistor 9, and the source of N channel MOS transistor 10 is connected to low potential side power supply terminal 4.
[0078]
The gate of N channel MOS transistor 11 is connected to the drain of N channel MOS transistor 9, and the source of N channel MOS transistor 11 is connected to low potential side power supply terminal 4.
[0079]
The reference voltage source circuit 2 includes a current mirror circuit 12 a that folds back a constant current and generates a reference voltage at the output terminal 5, an N channel MOS transistor 14, an N channel MOS transistor 15, and a resistor 16.
[0080]
The current mirror circuit 12 a includes a P channel MOS transistor 12 and a P channel MOS transistor 13.
[0081]
The source of the P channel MOS transistor 12 is connected to the high potential side power supply terminal 3, and the drain and gate of the P channel MOS transistor 12 are connected to each other.
[0082]
The gate of P channel MOS transistor 12 is connected to the drain of N channel MOS transistor 11 of startup circuit 1 b and output terminal 5.
[0083]
The source of P channel MOS transistor 13 is connected to high potential side power supply terminal 3, and the gate of P channel MOS transistor 13 is connected to the gate of P channel MOS transistor 12.
[0084]
The drain of N channel MOS transistor 14 is connected to the drain of P channel MOS transistor 12.
[0085]
A resistor 16 is connected between the source of the N-channel MOS transistor 14 and the low potential side power supply terminal 4.
[0086]
The drain and gate of N channel MOS transistor 15 are connected to each other, and the drain of N channel MOS transistor 15 is connected to the drain of P channel MOS transistor 13.
[0087]
The source of N channel MOS transistor 15 is connected to low potential side power supply terminal 4, and the gate of N channel MOS transistor 15 is connected to the gate of N channel MOS transistor 14 and the gate of N channel MOS transistor 10 of startup circuit 1b.
[0088]
The reset circuit 20 includes a P-channel MOS transistor 21, the source of the P-channel MOS transistor 21 is connected to the high potential side power supply terminal 3, the gate of the P-channel MOS transistor 21 is connected to the output of the CMOS inverter 19, The drain of P channel MOS transistor 21 is connected to the gate of P channel MOS transistor 12.
[0089]
The reset circuit 22 includes an N-channel MOS transistor 23, an N-channel MOS transistor 24, and an N-channel MOS transistor 25. The source of the N-channel MOS transistor 23 is connected to the low potential side power supply terminal 4, The gate of the channel MOS transistor 23 is connected to the output of the CMOS inverter 18, the drain of the N channel MOS transistor 23 is connected to the gate of the N channel MOS transistor 9, and the source of the N channel MOS transistor 24 is connected to the low potential side power supply terminal 4. N channel MOS transistor 24 has its gate connected to the output of CMOS inverter 18, N channel MOS transistor 24 has its drain connected to the gate of N channel MOS transistor 11, and N channel MOS transistor The source of 25 is connected to the low potential side power supply terminal 4, the gate of the N channel MOS transistor 25 is connected to the output of the CMOS inverter 18, and the drain of the N channel MOS transistor 25 is connected to the gate of the N channel MOS transistor 15. .
[0090]
Note that the power of the CMOS inverter 18 and the CMOS inverter 19 is supplied from the high potential side power supply terminal 3 and the low potential side power supply terminal 4 although not shown.
[0091]
Next, the operation will be described. Here, the power-down state refers to a state in which only the reference voltage output from the output terminal 5 is stopped when the power supply voltages of the high potential side power supply terminal 3 and the low potential side power supply terminal 4 are turned on.
[0092]
First, in the power-down state in which the power supply voltages of the high-potential-side power supply terminal 3 and the low-potential-side power supply terminal 4 are turned on, the power-down signal input terminal 17 is fixed to the logic L level from the outside. The output of 18 becomes a logic H level, and the output of the CMOS inverter 19 becomes a logic L level.
[0093]
Therefore, the P-channel MOS transistor 21 of the reset circuit 20 is turned on and the gate of the P-channel MOS transistor 12 is short-circuited to the high potential side power supply terminal 3, and at the same time, the N-channel MOS transistor 23 of the reset circuit 22 is turned on. The gate of the MOS transistor 9 is short-circuited to the low potential side power supply terminal 4, the N channel MOS transistor 24 is turned on, the gate of the N channel MOS transistor 11 is shorted to the low potential side power supply terminal 4, and the N channel MOS transistor 25 is turned on. Thus, the gate of the N channel MOS transistor 15 is short-circuited to the low potential side power supply terminal 4.
[0094]
As a result, the current mirror circuit 12a stably stops operating, and the reference voltage output from the output terminal 5 is stopped.
[0095]
Next, when the power down state is canceled while the power supply voltages of the high potential side power supply terminal 3 and the low potential side power supply terminal 4 are turned on, the external power down signal is fixed at the logic H level. The output of the CMOS inverter 18 becomes a logic L level, and the output of the CMOS inverter 19 becomes a logic H level.
[0096]
Therefore, the logic H level output voltage of the CMOS inverter 19 becomes approximately the same as the power supply voltage of the high potential side power supply terminal 3, the P channel MOS transistor 21 of the reset circuit 20 is turned off, and the N channel of the reset circuit 22 is turned off. Since the MOS transistor 23, the N-channel MOS transistor 24, and the N-channel MOS transistor 25 are all turned off, the same operation as the start-up operation of the bias circuit according to the first embodiment of the present invention shown in FIG. 1 is performed. become.
[0097]
The above is the operation in the state where the power supply voltages of the high potential side power supply terminal 3 and the low potential side power supply terminal 4 are turned on, while the power down signal input terminal 17 is fixed to the logic L level. When the power supply voltages of the high potential side power supply terminal 3 and the low potential side power supply terminal 4 are turned on, the output voltage of the CMOS inverter 19 remains at the low potential side power supply terminal 4 even if the power supply voltage of the high potential side power supply terminal 3 rises. Since the voltage is about the same as the power supply voltage, the power down state is maintained without starting up, and the high potential side power supply terminal 3 and the low potential in the state where the power down signal input terminal 17 is fixed at the logic H level. When the power supply voltage of the side power supply terminal 4 is turned on, as the power supply voltage of the high potential side power supply terminal 3 rises, the high voltage is output as the output voltage of the CMOS inverter 19. Since the power supply voltage and comparable voltage side power supply terminal 3 rises, eventually, so that the startup operation similar to the bias circuit of the first embodiment of the present invention shown in FIG. 1 is performed.
[0098]
As described above, according to the bias circuit of the third embodiment of the present invention, the CMOS inverter 18 and the CMOS inverter 19 to which the power down signal is applied, and the level shift voltage of the output voltage of the CMOS inverter 19 are generated. P-channel MOS transistor 6, capacitor 7 for holding a level shift voltage, capacitor 8 to which the output voltage of CMOS inverter 19 is applied at one end, N-channel MOS transistor 10, and a source-drain path with a level shift voltage applied to the gate N channel MOS transistor 9 connected between the other end of capacitor 8 and low potential side power supply terminal 4 via the source / drain path of N channel MOS transistor 10, and the voltage of the other end of capacitor 8 is applied to the gate. N channel MOS transistor that outputs the start signal A startup circuit 1b having a transistor 11, a reference voltage source circuit 2 having a current mirror circuit 12a for generating a reference voltage by folding back a constant current, and stopping the operation of the current mirror circuit 12a by a power-down signal in a power-down state. And a reset circuit 22 for short-circuiting the gate of the N-channel MOS transistor 9 and the gate of the N-channel MOS transistor 11 to the low-potential side power supply terminal 4, and when the power-down state is released, the start signal Since the current mirror circuit 12a is triggered by this and the N-channel MOS transistor 10 is turned off before the reference voltage source circuit 2 is activated, and the N-channel MOS transistor 10 is turned on after the activation, immediately after power-on Power off and power on again Even when the like, it is possible to reduce the startup time of the reference voltage source circuit 2 outputs a start signal, there is an advantage that it is possible to perform stable power-down control.
[0099]
Next, FIG. 5 is a configuration diagram of a bias circuit according to a fourth embodiment of the present invention. The difference between the configuration of the bias circuit of the third embodiment of the present invention shown in FIG. 4 and the configuration of the bias circuit of the fourth embodiment of the present invention shown in FIG. 5 is the startup circuit 1b shown in FIG. Is changed to the start-up circuit 1c. Specifically, the N-channel MOS transistor 9 is replaced with the N-channel MOS transistor 9a, similarly to the configuration of the bias circuit of the second embodiment of the present invention shown in FIG. Only the portion where the N-channel MOS transistor 10 is changed to the N-channel MOS transistor 10a is changed. Therefore, the same components are denoted by the same reference numerals, and detailed description thereof is omitted.
[0100]
As shown in FIG. 5, the bias circuit according to the fourth embodiment of the present invention includes a startup circuit 1c, a reference voltage source circuit 2, a high potential side power supply terminal 3, a low potential side power supply terminal 4, and an output. A terminal 5, a power down signal input terminal 17, a reset circuit 20, and a reset circuit 22 are provided.
[0101]
The startup circuit 1c includes a P channel MOS transistor 6, a capacitor 7, a capacitor 8, an N channel MOS transistor 9a, an N channel MOS transistor 10a, an N channel MOS transistor 11, a CMOS inverter 18, and a CMOS inverter 19. .
[0102]
A power-down signal is applied to the input of the CMOS inverter 18 from the power-down signal input terminal 17.
[0103]
The input of the CMOS inverter 19 is connected to the output of the CMOS inverter 18.
[0104]
The source of P channel MOS transistor 6 is connected to the output of CMOS inverter 19.
[0105]
A capacitor 7 is connected between the drain and gate of the P channel MOS transistor 6 connected to each other and the low potential side power supply terminal 4.
[0106]
The gate of N channel MOS transistor 9 a is connected to the drain of P channel MOS transistor 6, and the source of N channel MOS transistor 9 a is connected to low potential side power supply terminal 4.
[0107]
The source of N channel MOS transistor 10a is connected to the drain of N channel MOS transistor 9a.
[0108]
Capacitor 8 is connected between the output of CMOS inverter 19 and the drain of N channel MOS transistor 10a.
[0109]
The gate of N channel MOS transistor 11 is connected to the drain of N channel MOS transistor 10 a, and the source of N channel MOS transistor 11 is connected to low potential side power supply terminal 4.
[0110]
The reference voltage source circuit 2 includes a current mirror circuit 12 a that folds back a constant current and generates a reference voltage at the output terminal 5, an N channel MOS transistor 14, an N channel MOS transistor 15, and a resistor 16.
[0111]
The current mirror circuit 12 a includes a P channel MOS transistor 12 and a P channel MOS transistor 13.
[0112]
The source of the P channel MOS transistor 12 is connected to the high potential side power supply terminal 3, and the drain and gate of the P channel MOS transistor 12 are connected to each other.
[0113]
The gate of P channel MOS transistor 12 is connected to the drain of N channel MOS transistor 11 of startup circuit 1 c and output terminal 5.
[0114]
The source of P channel MOS transistor 13 is connected to high potential side power supply terminal 3, and the gate of P channel MOS transistor 13 is connected to the gate of P channel MOS transistor 12.
[0115]
The drain of N channel MOS transistor 14 is connected to the drain of P channel MOS transistor 12.
[0116]
A resistor 16 is connected between the source of the N-channel MOS transistor 14 and the low potential side power supply terminal 4.
[0117]
The drain and gate of N channel MOS transistor 15 are connected to each other, and the drain of N channel MOS transistor 15 is connected to the drain of P channel MOS transistor 13.
[0118]
The source of N channel MOS transistor 15 is connected to low potential side power supply terminal 4, and the gate of N channel MOS transistor 15 is connected to the gate of N channel MOS transistor 14 and the gate of N channel MOS transistor 10a of startup circuit 1c.
[0119]
The reset circuit 20 includes a P-channel MOS transistor 21, the source of the P-channel MOS transistor 21 is connected to the high potential side power supply terminal 3, the gate of the P-channel MOS transistor 21 is connected to the output of the CMOS inverter 19, The drain of P channel MOS transistor 21 is connected to the gate of P channel MOS transistor 12.
[0120]
The reset circuit 22 includes an N-channel MOS transistor 23, an N-channel MOS transistor 24, and an N-channel MOS transistor 25. The source of the N-channel MOS transistor 23 is connected to the low potential side power supply terminal 4, The gate of channel MOS transistor 23 is connected to the output of CMOS inverter 18, the drain of N channel MOS transistor 23 is connected to the gate of N channel MOS transistor 9 a, and the source of N channel MOS transistor 24 is connected to low potential side power supply terminal 4. Connected, the gate of the N channel MOS transistor 24 is connected to the output of the CMOS inverter 18, the drain of the N channel MOS transistor 24 is connected to the gate of the N channel MOS transistor 11, and the N channel MOS transistor The source of the transistor 25 is connected to the low potential side power supply terminal 4, the gate of the N channel MOS transistor 25 is connected to the output of the CMOS inverter 18, and the drain of the N channel MOS transistor 25 is connected to the gate of the N channel MOS transistor 15. The
[0121]
In the configuration of the bias circuit according to the third embodiment of the present invention shown in FIG. 4, the source / drain path of the N channel MOS transistor 9 and the source / drain path of the N channel MOS transistor 10 are connected in series. Also in the configuration of the bias circuit of the fourth embodiment of the present invention shown in FIG. 5, the source / drain path of the N channel MOS transistor 9a and the source / drain path of the N channel MOS transistor 10a are connected in series. The operation of the bias circuit of the fourth embodiment of the present invention shown is the same as the operation of the bias circuit of the third embodiment of the present invention shown in FIG.
[0122]
Therefore, according to the bias circuit of the fourth embodiment of the present invention shown in FIG. 5, the same effect as the bias circuit of the third embodiment of the present invention shown in FIG. 4 can be obtained.
[0123]
Next, FIG. 6 is a configuration diagram of a power supply device according to a fifth embodiment of the present invention. As shown in FIG. 6, the power supply device according to the fifth embodiment of the present invention includes a bias circuit 26 according to the third embodiment of the present invention illustrated in FIG. 4, a band gap reference circuit 27 serving as a power supply circuit, , A high potential side power supply terminal 28, a low potential side power supply terminal 29, a power down control terminal 30, and an output terminal 31. The same components as those of the bias circuit 26 according to the third embodiment of the present invention shown in FIG. 4 and the power supply device according to the fifth embodiment of the present invention shown in FIG. Description is omitted.
[0124]
The band gap reference circuit 27 includes a P channel MOS transistor 32, a P channel MOS transistor 33, a P channel MOS transistor 34, an N channel MOS transistor 35, an N channel MOS transistor 36, a P channel MOS transistor 37, A channel MOS transistor 38, a resistor 39, a capacitor 40, a resistor 41, an NPN transistor 42, a resistor 43, an NPN transistor 44, and a resistor 45 are provided.
[0125]
The power down signal input terminal 17 of the bias circuit 26 is connected to the power down control terminal 30, the high potential side power supply terminal 3 of the bias circuit 26 is connected to the high potential side power supply terminal 28, and the low potential side power supply terminal of the bias circuit 26. 4 is connected to the low potential side power supply terminal 29, and the output terminal 5 of the bias circuit 26 is connected to the gate of the P channel MOS transistor 32 and the gate of the P channel MOS transistor 37.
[0126]
When the reference voltage is supplied from the output terminal 5 of the bias circuit 26, the P-channel MOS transistor 32 and the P-channel MOS transistor 37 each operate as a constant current source that supplies a predetermined bias current.
[0127]
The source of P channel MOS transistor 32 is connected to high potential side power supply terminal 28, and the drain of P channel MOS transistor 32 is connected to the source of P channel MOS transistor 33 and the source of P channel MOS transistor 34.
[0128]
The drain and gate of N channel MOS transistor 35 are connected to each other, the drain of N channel MOS transistor 35 is connected to the drain of P channel MOS transistor 33, and the source of N channel MOS transistor 35 is connected to low potential side power supply terminal 29. Is done.
[0129]
The drain of N channel MOS transistor 36 is connected to the drain of P channel MOS transistor 34, the gate of N channel MOS transistor 36 is connected to the gate of N channel MOS transistor 35, and the source of N channel MOS transistor 36 is the low potential side power supply. Connected to terminal 29.
[0130]
The source of P channel MOS transistor 37 is connected to high potential side power supply terminal 28, the drain of N channel MOS transistor 38 is connected to the drain of P channel MOS transistor 37 and output terminal 31, and the gate of N channel MOS transistor 38 is connected to the drain. The drain of the P channel MOS transistor 34 is connected, and the source of the N channel MOS transistor 38 is connected to the low potential side power supply terminal 29.
[0131]
For phase compensation, a resistor 39 and a capacitor 40 are connected in series between the drain of the N channel MOS transistor 38 and the gate of the N channel MOS transistor 38.
[0132]
The emitter of the NPN transistor 42 is connected to the low potential side power supply terminal 29, the collector and base of the NPN transistor 42 are connected to each other, the collector of the NPN transistor 42 is connected to one end of the resistor 41, and the other end of the resistor 41 is N Connected to the drain of channel MOS transistor 38.
[0133]
The emitter of the NPN transistor 44 is connected to the low potential side power supply terminal 29, the collector and base of the NPN transistor 44 are connected to each other, the collector of the NPN transistor 44 is connected to one end of the resistor 45, and the other end of the resistor 45 is connected to the resistor The other end of the resistor 43 is connected to the drain of the N-channel MOS transistor 38.
[0134]
The gate of the P-channel MOS transistor 34 as the non-inverting input terminal of the differential pair consisting of the P-channel MOS transistor 33 and the P-channel MOS transistor 34 is connected to the collector of the NPN transistor 42, and the P-channel MOS transistor 33 as the inverting input terminal Are connected to the connection point of the resistor 43 and the resistor 45.
[0135]
Next, the operation of the band gap reference circuit 27 in a steady state in which the power supply voltages of the high potential side power supply terminal 28 and the low potential side power supply terminal 29 are turned on and a predetermined reference voltage is output from the bias circuit 26 to the output terminal 5 is performed. explain.
[0136]
Note that each base current is ignored on the assumption that the DC current amplification factor hFE of the NPN transistor 42 and the NPN transistor 44 is sufficiently large, the gate voltage of the P-channel MOS transistor 34 is set to the non-inverting input voltage VG34, and the gate voltage of the P-channel MOS transistor 33 is set. Is the inverted input voltage VG33, the collector current of the NPN transistor 42 is IC42, the base-emitter voltage of the NPN transistor 42 is VBE42, the emitter junction area of the NPN transistor 42 is 1, the collector current of the NPN transistor 44 is IC44, The base-emitter voltage of the NPN transistor 44 is VBE44, the emitter junction area of the NPN transistor 44 is n, the value of the resistor 41 is R41, the value of the resistor 43 is R43, and the value of the resistor 45 is R45. The drain voltage of N-channel MOS transistor 38 and VD38.
[0137]
Since VG34 = VG33 in the steady state, the relationship of VBE42 = VBE44 + R45 × IC44 and VD38 = VBE44 + (R43 + R45) × IC44 is established. From this, VD38 = VBE42 + (R43 ÷ R45) × (VBE42−VBE44) From the relationship that the reverse saturation current of the emitter junction is proportional to the junction area and the relationship of R41 × IC42 = R43 × IC44, assuming that the thermal voltage is VT, VD38 = VBE42 + (R43 ÷ R45) × VT A relationship of × ln (n × R43 ÷ R41) is obtained.
[0138]
Accordingly, the band gap reference voltage VD38 is output from the output terminal 31.
[0139]
Next, the operation including the bias circuit 26 will be described. First, in the power-down state in which the power supply voltages of the high-potential-side power supply terminal 28 and the low-potential-side power supply terminal 29 are turned on, the power-down control terminal 30 is fixed to the logic L level from the outside. Is stopped, the P-channel MOS transistor 32 and the P-channel MOS transistor 37 are turned off, and the bandgap reference voltage VD38 from the output terminal 31 is turned off.
[0140]
At this time, since all the bias currents in the band gap reference circuit 27 are cut off, the power consumption of the band gap reference circuit 27 becomes zero.
[0141]
Next, when the power down state is canceled while the power supply voltages of the high potential side power supply terminal 28 and the low potential side power supply terminal 29 are turned on, the power down control terminal 30 is fixed to the logic H level from the outside. Therefore, the bias circuit 26 performs a start-up operation, the reference voltage output is instantaneously output from the output terminal 5, the P-channel MOS transistor 32 and the P-channel MOS transistor 37 are instantaneously turned on, and the band gap reference is instantaneously output from the output terminal 31. The voltage VD38 is output.
[0142]
On the other hand, when the power supply voltage of the high potential side power supply terminal 28 and the low potential side power supply terminal 29 is turned on in a state where the power down control terminal 30 is fixed at the logic L level, the bias circuit 26 does not start up and remains as it is. The band gap reference circuit 27 enters a power down state.
[0143]
The bias circuit 26 also performs a start-up operation when the power supply voltages of the high potential side power supply terminal 28 and the low potential side power supply terminal 29 are turned on while the power down control terminal 30 is fixed at the logic H level. The reference voltage output is instantaneously output from the output terminal 5, the P-channel MOS transistor 32 and the P-channel MOS transistor 37 are instantaneously turned on, and the band gap reference voltage VD 38 is instantaneously output from the output terminal 31.
[0144]
As described above, according to the power supply device of the fifth embodiment of the present invention, the CMOS inverter 18 and the CMOS inverter 19 to which the power down signal is applied, and the level shift voltage of the output voltage of the CMOS inverter 19 are generated. P-channel MOS transistor 6, capacitor 7 for holding a level shift voltage, capacitor 8 to which the output voltage of CMOS inverter 19 is applied at one end, N-channel MOS transistor 10, and a source-drain path with a level shift voltage applied to the gate N channel MOS transistor 9 connected between the other end of capacitor 8 and low potential side power supply terminal 4 via the source / drain path of N channel MOS transistor 10, and the voltage of the other end of capacitor 8 is applied to the gate. N channel MOS transistor that outputs the start signal A start-up circuit 1b having a star 11, a reference voltage source circuit 2 having a current mirror circuit 12a that folds back a constant current and generates a reference voltage, and stops operation of the current mirror circuit 12a by a power-down signal in a power-down state. And a reset circuit 22 for short-circuiting the gate of the N-channel MOS transistor 9 and the gate of the N-channel MOS transistor 11 to the low-potential side power supply terminal 4, and when the power-down state is released, the start signal The bias circuit 26 is controlled so that the N channel MOS transistor 10 is turned off before the current mirror circuit 12a is triggered and the reference voltage source circuit 2 is activated, and the N channel MOS transistor 10 is turned on after the activation. The reference voltage is applied to the gate And a bandgap reference circuit 27 including a P-channel MOS transistor 32 and a P-channel MOS transistor 37 that supply a predetermined bias current as a source, so that the power is turned off immediately after the power is turned on and the power is turned on again. Even in such a case, it is possible to achieve an effect that a startup time can be shortened and a power supply device capable of performing stable power-down control can be realized.
[0145]
The power supply device according to the fifth embodiment of the present invention shown in FIG. 6 includes the bias circuit 26 of the third embodiment of the present invention shown in FIG. 4, but the sixth embodiment of the present invention. As the power supply apparatus, the bias circuit of the fourth embodiment of the present invention shown in FIG. 5 may be provided in place of the bias circuit 26. If power-down control is not required, the seventh embodiment of the present invention may be used. As a power supply device according to the second embodiment, the bias circuit according to the first embodiment of the present invention shown in FIG. 1 or the bias circuit according to the second embodiment of the present invention shown in FIG. You may make it prepare.
[0146]
The bandgap reference circuit 27 in the power supply device according to the fifth embodiment of the present invention shown in FIG. 6 includes the NPN transistor 42 and the NPN transistor 44, but can be replaced with a diode.
[0147]
In addition, the power supply device according to the fifth embodiment of the present invention shown in FIG. 6 includes a band gap reference circuit 27 as a power supply circuit. Any power supply circuit including a transistor that supplies the bias current can be replaced, and the same effect can be obtained.
[0148]
【The invention's effect】
The effect of the present invention is that a bias circuit that can output a start signal and shorten the start time of the reference voltage source circuit even when the power is turned off immediately after the power is turned on and the power is turned on again, and A power supply device including the bias circuit can be realized.
[0149]
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a bias circuit according to a first embodiment of the present invention.
FIG. 2 is an operation explanatory diagram of the bias circuit according to the first embodiment of the present invention.
FIG. 3 is a configuration diagram of a bias circuit according to a second embodiment of the present invention.
FIG. 4 is a configuration diagram of a bias circuit according to a third embodiment of the present invention.
FIG. 5 is a configuration diagram of a bias circuit according to a fourth embodiment of the present invention.
FIG. 6 is a configuration diagram of a power supply device according to a fifth embodiment of the present invention.
FIG. 7 is a configuration diagram of a conventional bias circuit.
[Explanation of symbols]
1, 1a, 1b, 1c, 101 Startup circuit
2,102 Reference voltage source circuit
3, 103 High potential side power supply terminal
4,104 Low potential side power supply terminal
5,105 Output terminal
6, 106 P-channel MOS transistor
7, 107 capacitors
8,108 capacitors
9, 9a, 109 N-channel MOS transistor
10, 10a N-channel MOS transistor
11, 111 N-channel MOS transistor
12, 112 P-channel MOS transistor
12a, 112a Current mirror circuit
13, 113 P-channel MOS transistor
14, 114 N-channel MOS transistor
15, 115 N-channel MOS transistor
16, 116 resistance
17 Power-down signal input terminal
18 CMOS inverter
19 CMOS inverter
20 Reset circuit
21 P-channel MOS transistor
22 Reset circuit
23 N-channel MOS transistor
24 N-channel MOS transistor
25 N-channel MOS transistor
26 Bias circuit
27 Bandgap reference circuit
28 High-potential side power supply terminal
29 Low potential power supply terminal
30 Power-down control terminal
31 Output terminal
32 P-channel MOS transistor
33 P-channel MOS transistor
34 P-channel MOS transistor
35 N-channel MOS transistor
36 N-channel MOS transistor
37 P-channel MOS transistor
38 N-channel MOS transistor
39 Resistance
40 capacitors
41 Resistance
42 NPN transistor
43 Resistance
44 NPN transistor
45 resistance

Claims (8)

A first transistor for generating a level shift voltage of the power supply voltage of the first power supply, a first capacitor for holding the level shift voltage, a second capacitor to which the power supply voltage is applied at one end, a second capacitor A third level transistor is connected between the other end of the second capacitor and the second power source via the source / drain path of the second transistor with the level shift voltage applied to the gate. And a fourth transistor that outputs a start signal when a voltage at the other end of the second capacitor is applied to the gate, and a reference current triggered by the start signal is turned back to reference And a reference voltage source circuit having a current mirror circuit for generating a voltage and controlling the second transistor. Circuit. A first P-channel transistor whose source is connected to the high-potential-side power supply terminal; a first capacitor connected between the drain and gate of the first P-channel transistor and the low-potential-side power supply terminal; Connected to the drain, a second capacitor connected between the high-potential-side power supply terminal and the drain of the first N-channel transistor, and a drain connected to the first N-channel transistor. A second N-channel transistor connected to the source of the N-channel transistor and having a source connected to the low-potential-side power supply terminal; a gate connected to the drain of the first N-channel transistor; A start-up circuit having a third N-channel transistor connected to the terminal, and a reference voltage by folding back a constant current A reference voltage source circuit having a generated current mirror circuit, and before the reference voltage source circuit is started by the current mirror circuit being triggered by the drain current of the third N-channel transistor 2. The bias circuit according to claim 1, wherein the second N-channel transistor is turned off, and the second N-channel transistor is turned on after the activation. A first P-channel transistor whose source is connected to the high-potential-side power supply terminal; a first capacitor connected between the drain and gate of the first P-channel transistor and the low-potential-side power supply terminal; Is connected to the drain, the source is connected to the low-potential power supply terminal, the second N-channel transistor whose source is connected to the drain of the first N-channel transistor, A second capacitor connected between a high-potential side power supply terminal and the drain of the second N-channel transistor, a gate connected to the drain of the second N-channel transistor, and a source connected to the low-potential side power supply A start-up circuit having a third N-channel transistor connected to the terminal, and a reference voltage by folding back a constant current A reference voltage source circuit having a generated current mirror circuit, and before the reference voltage source circuit is started by the current mirror circuit being triggered by the drain current of the third N-channel transistor 2. The bias circuit according to claim 1, wherein the second N-channel transistor is turned off, and the second N-channel transistor is turned on after the activation. An inverter to which a power down signal is given, a first transistor for generating a level shift voltage of the output voltage of the inverter, a first capacitor for holding the level shift voltage, and a second capacitor to which the output voltage is given at one end The level shift voltage is applied to the gate and the source / drain path is connected between the other end of the second capacitor and the power source via the source / drain path of the second transistor. A start-up circuit having a third transistor to be output, and a fourth transistor that outputs a start-up signal when a voltage at the other end of the second capacitor is applied to the gate, and a constant current triggered by the start-up signal And a reference voltage for controlling the second transistor having a current mirror circuit for generating a reference voltage A reset circuit that stops the operation of the current mirror circuit by the power-down signal when in a power-down state, and short-circuits the gate of the third transistor and the gate of the fourth transistor to the power source. A bias circuit comprising: An inverter to which a power-down signal is applied, a first P-channel transistor whose source is connected to the output of the inverter, and a drain and a gate of the first P-channel transistor and a low potential side power supply terminal. A first capacitor having a gate connected to the drain; a second capacitor connected between the output of the inverter and a drain of the first N-channel transistor; A second N-channel transistor having a drain connected to the source of the first N-channel transistor and a source connected to the low-potential-side power supply terminal; and a gate connected to the drain of the first N-channel transistor. A third N-channel transistor having a source connected to the low potential side power supply terminal A start-up circuit, a reference voltage source circuit having a current mirror circuit for generating a reference voltage by turning back a constant current, and stopping the operation of the current mirror circuit by the power-down signal in the power-down state and the first N-channel A bias circuit comprising: a reset circuit that short-circuits the gate of the transistor and the gate of the third N-channel transistor to the low-potential side power supply terminal; and when the power-down state is released, the third circuit The current mirror circuit is triggered by the drain current of the N-channel transistor and the second N-channel transistor is turned off before the reference voltage source circuit is activated, and the second N-channel transistor is turned on after the activation. A bias circuit characterized by being in a state. An inverter to which a power-down signal is applied, a first P-channel transistor whose source is connected to the output of the inverter, and a drain and a gate of the first P-channel transistor and a low potential side power supply terminal. A first N-channel transistor having a gate connected to the drain and a source connected to the low-potential side power supply terminal; and a source connected to the drain of the first N-channel transistor. Two N-channel transistors, a second capacitor connected between the output of the inverter and the drain of the second N-channel transistor, and a gate connected to the drain of the second N-channel transistor. A third N-channel transistor having a source connected to the low potential side power supply terminal A start-up circuit, a reference voltage source circuit having a current mirror circuit for generating a reference voltage by turning back a constant current, and stopping the operation of the current mirror circuit by the power-down signal in the power-down state and the first N-channel A bias circuit comprising: a reset circuit that short-circuits the gate of the transistor and the gate of the third N-channel transistor to the low-potential side power supply terminal; and when the power-down state is released, the third circuit The current mirror circuit is triggered by the drain current of the N-channel transistor and the second N-channel transistor is turned off before the reference voltage source circuit is activated, and the second N-channel transistor is turned on after the activation. A bias circuit characterized by being in a state. A first transistor for generating a level shift voltage of the power supply voltage of the first power supply, a first capacitor for holding the level shift voltage, a second capacitor to which the power supply voltage is applied at one end, a second capacitor And a third drain connected between the other end of the second capacitor and the second power source via the source / drain path of the second transistor. And a fourth transistor that outputs a start signal when a voltage at the other end of the second capacitor is applied to the gate, and a reference current triggered by the start signal is turned back to reference A bias circuit including a current mirror circuit for generating a voltage and a reference voltage source circuit for controlling the second transistor; and a gate Serial reference voltage becomes a given current source power supply, characterized in that it comprises a power supply circuit including a transistor for supplying a predetermined bias current. An inverter to which a power down signal is given, a first transistor for generating a level shift voltage of the output voltage of the inverter, a first capacitor for holding the level shift voltage, and a second capacitor to which the output voltage is given at one end The level shift voltage is applied to the gate and the source / drain path is connected between the other end of the second capacitor and the power source via the source / drain path of the second transistor. A start-up circuit having a third transistor to be output, and a fourth transistor that outputs a start-up signal when a voltage at the other end of the second capacitor is applied to the gate, and a constant current triggered by the start-up signal And a reference voltage for controlling the second transistor having a current mirror circuit for generating a reference voltage A reset circuit that stops the operation of the current mirror circuit by the power-down signal when in a power-down state, and short-circuits the gate of the third transistor and the gate of the fourth transistor to the power source. A power supply apparatus comprising: a bias circuit including: a power supply circuit including a transistor that supplies a predetermined bias current as a current source when the reference voltage is applied to a gate.

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