JP3621051B2 - MEMORY CONTROLLER, FLASH MEMORY SYSTEM PROVIDED WITH MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory controller, a flash memory system, and a flash memory control method, and more particularly, to a memory controller, a flash memory system, and a flash memory control method capable of performing a series of data write processing on the flash memory at higher speed.
[0002]
[Prior art]
In recent years, flash memories, particularly NAND flash memories, are often used as semiconductor memories used for memory cards, silicon disks, and the like. In the NAND flash memory, when a memory cell is changed from an erased state (logical value = 1) to a written state (logical value = 0), this can be performed in units of memory cells. When changing from the written state (0) to the erased state (1), this cannot be performed in units of memory cells, and can be performed only in predetermined erase units composed of a plurality of memory cells. Such a batch erase operation is generally called “block erase”.
[0003]
As described above, in the flash memory, the memory cell can be changed from the written state to the erased state only in units of blocks. Therefore, in order to write new data to a block in which data has already been written, A process is required in which all memory cells included in the block are erased, and then new data is written. Therefore, when writing new data to a block that already contains data, to prevent the data already stored in this block from being lost, move the data contained in this block to another erased block. It is necessary to let
[0004]
Therefore, when the host computer instructs to write new data to a block in which data is already stored, the new data and data already stored in this block are written into the erased block. Such processing is called “inter-block transfer”. Thereafter, all the memory cells included in the transfer source block are erased, so that the transfer source block becomes a new erased block.
[0005]
As described above, in the conventional flash memory system, it is necessary to execute inter-block transfer every time the host computer requests to write new data to a block in which data is already stored.
[0006]
[Problems to be solved by the invention]
However, there is a problem that a long time is required for a series of transfer processing between blocks.
[0007]
That is, in the inter-block transfer process, the memory controller needs to read the data stored in the transfer source block and write the data to the transfer destination block one page at a time. In order to transfer all the data stored in the page to the transfer destination block, a time substantially proportional to the number of pages constituting one block is required.
[0008]
Therefore, even if the data requested to be written by the host computer is data for one page, if some data has already been stored in the block where the data is to be written, a large amount of data is required until the series of processing is completed. Time was needed.
[0009]
For this reason, there is a demand for a memory controller, a flash memory system, and a flash memory control method capable of performing a series of processes necessary for writing the data at a higher speed when the host computer requests data writing. It was.
[0010]
Therefore, an object of the present invention is necessary for writing given data even when some data is already stored in a block to which the data is written when the host computer requests data writing. A memory controller capable of performing a series of processes at a higher speed and a flash memory system including such a memory controller are provided.
[0011]
Another object of the present invention is to write the given data even when some data is already stored in the block to which the data is written when the host computer requests the data writing. It is an object to provide a flash memory control method capable of performing a series of processes necessary for the above at a higher speed.
[0012]
[Means for Solving the Problems]
An object of the present invention is a memory controller that accesses a memory composed of a plurality of blocks, and instructs to write new data to a logical address corresponding to a first block in which data is already stored. In response to this, a first means for transferring a part of the data stored in the first block to the same page of the second block, and writing the new data in the second block The second means, the third means for maintaining the correspondence between the first block and the second block, and a new instruction to write additional data to the logical address. In response to, a fourth means for determining whether or not the additional data can be additionally written to the second block, and a determination that the fourth means is additionally writable In response to this, fifth means for transferring a part of the data stored in the first block to the same page of the second block and writing the additional data to the second block And in response to determining that the fourth means is additionally not writable, all empty pages in the second block are stored in the same page of the first block. And a seventh means for erasing the first block in response to data being written to all pages of the second block. This is achieved by a memory controller characterized by:
[0013]
In a preferred embodiment of the present invention, the first means stores the data stored in the page immediately preceding the page corresponding to the page in which the new data is to be stored from the first page of the first block. Configured to transfer to the same page of the second block This ing.
[0014]
In a further preferred aspect of the present invention, the third means further holds information relating to the empty page of the second block, and the fourth means performs the additional writing based on the information relating to the empty page. It is configured to determine whether or not data can be additionally written to the second block.
[0015]
In a further preferred aspect of the present invention, the empty pages in the second block are continuous from the next page to the last page where the new data is written by the second means.
[0016]
In a further preferred aspect of the present invention, when the page to store the additional data in the second block is not the empty page, the sixth means adds the empty page in the second block to the empty page. Transferring data stored in the same page of the first block, after which the seventh means is arranged to erase all the data stored in the first block .
[0017]
In a further preferred aspect of the present invention, the memory controller further includes the data stored in the second block when the page in which the additional data in the second block is to be stored is not the empty page. An eighth means for transferring a part to the same page of the third block; and a ninth means for writing the additional data to the third block, wherein the third means further comprises the second The correspondence between the block and the third block is maintained.
[0018]
In a further preferred aspect of the present invention, the third means further holds information relating to an empty page of the third block.
[0019]
In a further preferred aspect of the present invention, the memory controller further comprises tenth means for determining whether or not the page to which the additional data is written is the first page of the empty page group in the second block. In response to determining that the tenth means is not the first page, the fifth means is one of the write destinations of the additional data from the first page of the empty page group. Data stored in the same page of the first block is transferred to each page corresponding to the previous page.
[0020]
The object of the present invention is also a memory controller for accessing a memory composed of a plurality of blocks, the means for classifying the blocks into a plurality of groups,
A means for forming a virtual block by virtually combining a plurality of blocks belonging to different groups, and responding to a new data write instruction for a predetermined block constituting the virtual block Means for transferring a part of the data stored in the predetermined block to another block, means for writing the new data newly instructed to write to the other block, and the predetermined block. Means for maintaining the correspondence relationship between the new block and the other block, additional data is given after the new data, and the writing of the additional data is instructed to the logical address corresponding to the predetermined block. In response, the means for determining whether the additional data can be additionally written to the other block, and the other In response to determining that the additional data can be additionally written to a block, a part of the data stored in the predetermined block is transferred to the same page of the other block, and In response to the means for writing the additional write data in the other block, and in response to determining that the additional write data cannot be additionally written to the other block, all the empty pages in the other block Means for transferring data stored in the same page of the predetermined block; means for erasing the predetermined block in response to data being written to all pages of the other block; This is achieved by a memory controller characterized by comprising:
[0021]
The object of the present invention is also achieved by a flash memory system comprising any one of the memory controllers and a flash memory composed of a plurality of blocks.
[0022]
In a preferred embodiment of the present invention, the flash memory system is housed in the same housing.
[0023]
In a further preferred embodiment of the present invention, the housing has a card shape.
[0024]
In a preferred embodiment of the present invention, the third means further holds information relating to a free page of the second block.
[0025]
The object of the present invention is to provide a block corresponding to the predetermined logical address in the address conversion table as a first block in response to an instruction to newly write new data to the predetermined logical address. Changing from the first block to the second block, creating a variable indicating the correspondence between the first block and the second block, and converting a part of the data stored in the first block to the second block In response to the instruction to write new additional data to the predetermined logical address, the step of transferring to the second block; the step of writing the new data to the second block; Determining whether or not the additional data can be additionally written to the second block; and determining that the additional data can be additionally written. In response, a part of the data stored in the first block is transferred to the same page of the second block, and the additional data is written to the second block; Responsive to determining that the data cannot be additionally written, transferring the data stored on the same page of the first block to all free pages in the second block; And a step of erasing the block of the first block in response to data being written to all pages of the second block.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0039]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to a preferred embodiment of the present invention.
[0040]
The flash memory system 1 has a card shape, and as shown in FIG. 1, four flash memory chips 2-0 to 2-3, a controller 3, and a connector 4 are integrated in one card. Composed. The flash memory system 1 is used by being detachably attached to the host computer 5 and used as a kind of external storage device for the host computer 5. Examples of the host computer 5 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.
[0041]
Each of the flash memory chips 2-0 to 2-3 is a semiconductor chip having a storage capacity of 128 Mbytes (1 Gbit). In the flash memory system 1, 512 bytes are used as one page, and this is the minimum access unit. Accordingly, each of these flash memory chips 2-0 to 2-3 includes an address space of 256K pages, and the flash memory chips 2-0 to 2-3 have a total of 1M pages of address space. In the flash memory system 1, these four flash memory chips 2-0 to 2-3 have a storage capacity of 512M bytes (4G bits) and are handled as one large memory having an address space of 1M pages. It is. Therefore, in order to access a specific page from the address space consisting of these 1M pages, 20-bit address information is required. Therefore, the host computer 5 accesses a specific page by supplying 20-bit address information to the flash memory system 1. Hereinafter, the 20-bit address information supplied from the host computer 5 to the flash memory system 1 is referred to as a “host address”.
[0042]
The controller 3 includes a microprocessor 6, a host interface block 7, an SRAM work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, and a flash sequencer block 12. Composed. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip.
[0043]
The microprocessor 6 is a functional block for controlling the operation of the entire functional blocks constituting the controller 3.
[0044]
The host interface block 7 is connected to the connector 4 via the bus 13 and exchanges data, address information, status information, and external command information with the host computer 5 under the control of the microprocessor 6. That is, when the flash memory system 1 is attached to the host computer 5, the flash memory system 1 and the host computer 5 are connected to each other via the bus 13, the connector 4, and the bus 14, and in this state, the host computer 5 The data supplied to the flash memory system 1 is taken into the controller 3 through the host interface block 7 as an entrance, and the data etc. supplied from the controller 3 to the host computer 5 exits the host interface block 7. To the host computer 5. The host interface block 7 further includes a task file register (not shown) for temporarily storing a host address and an external command supplied from the host computer 5 and an error register (not shown) that is set when an error occurs. Z).
[0045]
The SRAM work area 8 is a work area in which data necessary for controlling the flash memory chips 2-0 to 2-3 by the microprocessor 6 is temporarily stored, and includes a plurality of SRAM cells.
[0046]
The buffer 9 is a buffer for temporarily storing data read from the flash memory chips 2-0 to 2-3 and data to be written to the flash memory chips 2-0 to 2-3. That is, data read from the flash memory chips 2-0 to 2-3 is held in the buffer 9 until the host computer 5 can receive the data, and should be written to the flash memory chips 2-0 to 2-3. The data is held in the buffer 9 until the flash memory chips 2-0 to 2-3 are writable and an error correction code is generated by the ECC block 11 described later.
[0047]
The flash memory interface block 10 exchanges data, address information, status information, and internal command information with the flash memory chips 2-0 to 2-3 via the bus 15, and each flash memory chip 2-0. This is a functional block for supplying corresponding chip selection signals # 0 to # 3 to 2-3. The chip selection signals # 0 to # 3 are based on the upper 2 bits of the internal address generated based on the host address supplied from the host computer 5 when data reading or writing is requested from the host computer 5. One of them is a signal to be activated. Specifically, if the upper 2 bits of the internal address are “00”, the chip selection signal # 0 is activated, if it is “01”, the chip selection signal # 1 is activated, and if it is “10”. The chip selection signal # 2 is activated, and if it is “11”, the chip selection signal # 3 is activated. The flash memory chips 2-0 to 2-3 in which the corresponding chip selection signal is activated are in a selected state, and data can be read or written. The “internal command” is a command for the controller 3 to control the flash memory chips 2-0 to 2-3, and is distinguished from an “external command” for the host computer 5 to control the flash memory system 1. Is done.
[0048]
The ECC block 11 generates an error correction code to be added to the data to be written to the flash memory chips 2-0 to 2-3, and based on the error correction code added to the read data, the error included in the read data is corrected. This is a functional block for correction.
[0049]
The flash sequencer block 12 is a functional block for controlling data transfer between the flash memory chips 2-0 to 2-3 and the buffer 9. The flash sequencer block 12 includes a plurality of registers (not shown), and reads data from the flash memory chips 2-0 to 2-3 or flash memory chips 2-0 to 2 under the control of the microprocessor 6. When values necessary for writing data to -3 are set in these registers, a series of operations necessary for reading or writing data is automatically executed.
[0050]
Next, a specific structure of each flash memory cell constituting each flash memory chip 2-0 to 2-3 will be described.
[0051]
FIG. 2 is a cross-sectional view schematically showing the structure of each flash memory cell 16 constituting the flash memory chips 2-0 to 2-3.
[0052]
As shown in FIG. 2, the flash memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed so as to cover P-type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 And a control gate electrode 23 formed on the substrate. A plurality of flash memory cells 16 having such a configuration are connected in series in the flash memory chips 2-0 to 2-3 to form a NAND flash memory.
[0053]
The flash memory cell 16 is in either “erased state” or “written state” depending on whether electrons are injected into the floating gate electrode 21. The fact that the flash memory cell 16 is in the erased state means that the data “1” is held in the flash memory cell 16, and the fact that the flash memory cell 16 is in the written state means that the flash memory cell 16 This means that data “0” is held in. That is, the flash memory cell 16 can hold 1-bit data.
[0054]
As shown in FIG. 2, the erased state refers to a state where electrons are not injected into the floating gate electrode 21. The flash memory cell 16 in the erased state is a depletion type transistor, and a P-type semiconductor substrate between the source diffusion region 18 and the drain diffusion region 19 regardless of whether or not a read voltage is applied to the control gate electrode 23. A channel 24 is formed on the surface 17. Therefore, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not the read voltage is applied to the control gate electrode 23.
[0055]
FIG. 3 is a cross-sectional view schematically showing the flash memory cell 16 in the written state.
[0056]
As shown in FIG. 3, the writing state refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. The flash memory cell 16 in the write state is an enhancement type transistor, and when the read voltage is not applied to the control gate electrode 23, the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19 is used. When a read voltage is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. It is formed. Therefore, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated when the read voltage is not applied to the control gate electrode 23, and the source diffusion region when the read voltage is applied to the control gate electrode 23. The region 18 and the drain diffusion region 19 are electrically connected.
[0057]
Here, whether the selected flash memory cell 16 is in the erased state or in the written state can be read as follows. That is, a read voltage is applied to the control gate electrodes 23 of all the flash memory cells 16 other than the selected flash memory cell 16 among a plurality of flash memory cells 16 connected in series. It is detected whether or not a current flows through the series body of cells 16. As a result, if a current flows through the series body, it is determined that the selected flash memory cell 16 is in an erased state. If no current flows through the series body, the selected flash memory cell 16 is in a writing state. It is judged that. In this way, it is possible to read out whether the data held in any flash memory cell 16 included in the serial body is “0” or “1”. However, in the NAND flash memory, data held in two or more flash memory cells 16 included in one serial body cannot be read simultaneously.
[0058]
When the flash memory cell 16 that is in the erased state is changed to the written state, a positive high voltage is applied to the control gate electrode 23, whereby electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. Is done. Electrons can be injected into the floating gate electrode 21 using an FN tunnel current. On the other hand, when the flash memory cell 16 that is in the written state is changed to the erased state, a negative high voltage is applied to the control gate electrode 23, and as a result, it is accumulated in the floating gate electrode 21 through the tunnel oxide film 20. Electrons are discharged.
[0059]
Next, a specific configuration of the address space of each flash memory chip 2-0 to 2-3 will be described.
[0060]
FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory chip 2-0.
[0061]
As shown in FIG. 4, the address space of the flash memory chip 2-0 is configured by 8192 blocks including blocks # 0 to # 8191. Although not shown in FIG. 4, the flash memory chips 2-1 to 2-3 are also configured by 8192 blocks including blocks # 0 to # 8191 as in the flash memory chip 2-0. . Each of these blocks has a storage capacity of 16 Kbytes.
[0062]
Here, each block is a data erasing unit. That is, in the flash memory chips 2-0 to 2-3, the state of each flash memory cell 16 cannot be changed from the written state to the erased state, and the flash memory cell 16 is changed from the written state to the erased state. In the case of changing to, all flash memory cells 16 included in the block to which the flash memory cell 16 belongs are collectively erased. On the contrary, in the flash memory chips 2-0 to 2-3, the state of each flash memory cell 16 can be changed from the erased state to the written state.
[0063]
Further, as shown in FIG. 4, each block # 0 to # 8191 constituting the flash memory chip 2-0 includes 32 pages each including pages # 0 to # 31. Also, the blocks # 0 to # 8191 constituting the flash memory chips 2-1 to 2-3 are each composed of 32 pages, as are the blocks # 0 to # 8191 constituting the flash memory chip 2-0. It is configured.
[0064]
Each of these pages is an access unit for reading and writing data. As shown in FIG. 4, 8 bits consisting of bits b0 to b7 are defined as 1 byte, and a user area 25 of 512 bytes and a redundant area 26 of 16 bytes, respectively. Consists of. The user area 25 is an area in which user data supplied from the host computer 5 is stored, and the redundant area 26 has an error correction code for the user data stored in the corresponding user area 25 and a corresponding logical block address. This is the area to be stored. The corresponding logical block address is information indicating by which logical block address the block is accessed, and details thereof will be described later.
[0065]
Thus, each page is composed of a 512-byte user area 25 and a 16-byte redundant area 26, so that each page is composed of 8 × (512 bytes + 16 bytes) = 4224 flash memory cells. Become.
[0066]
As described above, each of the flash memory chips 2-0 to 2-3 is configured by 8192 physical blocks. Of these, 8000 physical blocks are blocks that can actually store data (hereinafter, “ The remaining 192 blocks are treated as “redundant blocks”. The redundant block is an empty block waiting for data writing. The address space of the flash memory chips 2-0 to 2-3 is composed only of actual use blocks. When a defect occurs in a physical block and becomes unusable, the number of physical blocks allocated as redundant blocks is reduced by the number of blocks in which the defect has occurred.
[0067]
Since the flash memory chips 2-0 to 2-3 having such a configuration are handled as one large memory having an address space of 1M pages as described above, the address space consisting of these 1M pages is changed to a specific page. To access, a 20-bit host address is used as described above. Of the 20-bit host address, the upper 15 bits are used to specify the flash memory chip and the block included in the specified flash memory chip, and the remaining 5 bits (lower 5 bits) are the specified block. Used to specify the pages included in the.
[0068]
The flash memory chip and block using the upper 15 bits of the host address are identified by dividing the upper 15 bits of the host address by “8000” and accessed by the quotient (0 to 3) obtained by the division. The flash memory chip to be determined is determined, and the “logical block address” is determined by the remainder (0 to 7999). Such a logical block address is converted into a “physical block address” in an “address conversion table” to be described later, whereby a block to be actually accessed is specified.
[0069]
Here, the necessity of converting a logical block address into a physical block address using an address conversion table will be described.
[0070]
As described above, the flash memory cells 16 constituting the flash memory chips 2-0 to 2-3 can be changed from the erased state to the written state in units of memory cells. Changing to the erased state cannot be performed in units of memory cells, but can be performed only in units of blocks. For this reason, when data is written to a certain page, it is necessary that all flash memory cells 16 constituting the user area 25 of the page are in an erased state. The page in which even one flash memory cell 16 constituting the user area 25 of the page is in a write state cannot be directly overwritten with data different from this. Therefore, in order to write new data different from this to a page in which data has already been written, all the flash memory cells 16 constituting the block to which this page belongs are temporarily erased, and then new data is written. Processing is required.
[0071]
Therefore, when overwriting old data stored in a page with new data, in order to prevent the data stored in the other page included in the block to which this page belongs from being lost, It is necessary to move the stored data to another block. Therefore, the relationship between the logical block address obtained from the host address and the physical block address on the flash memory chips 2-0 to 2-3 corresponding to the logical block address is instructed by the host computer 5 to overwrite data. Change dynamically every time. For this reason, in order to access the flash memory chips 2-0 to 2-3 from the host computer 5, the relationship between the logical block address and the physical block address on the flash memory corresponding to the logical block address is determined. This is because an address conversion table in which the information shown is stored is required. Details of the address conversion table will be described later.
[0072]
Next, various work data stored in the SRAM work area 8 will be described. In the SRAM work area 8, at least an address conversion table 27, an erased block queue 28, and an internal variable 30 are stored.
[0073]
FIG. 5 is a schematic diagram showing the data structure of the address conversion table 27 stored in the SRAM work area 8.
[0074]
As shown in FIG. 5, the address conversion table 27 is composed of four tables consisting of tables # 0 to # 3, and each table is composed of 8000 flags and 8000 physical block address storage areas. The These tables # 0 to # 3 correspond to the flash memory chips 2-0 to 2-3, respectively.
[0075]
Corresponding physical block addresses (13 bits) are stored in 8000 physical block address storage areas # 0 to # 7999 in the tables # 0 to # 3, respectively. The address conversion information indicating the corresponding relationship is formed. That is, the physical block address storage areas # 0 to # 7999 in the table # 0 are assigned physical block addresses of 8000 actual used blocks constituting the flash memory chip 2-0, and these assigned logical block addresses. And the physical block address stored therein have a correspondence relationship. Similarly, the physical block address storage areas # 0 to # 7999 in the tables # 1 to # 3 are allocated with physical block addresses of 8000 actually used blocks constituting the flash memory chips 2-1 to 2-3, respectively. It is done.
[0076]
For example, if the upper 15 bits of the host address supplied from the host computer 5 are “101010101010101B”, the quotient when this is divided by 8000 is “2” and the remainder is “5845”. 2 is selected, and if the physical block address stored here, for example, the stored physical block address is “0000000011111B”, “31” is read as the physical block address. Thus, the conversion from the logical block address # 5845 in the flash memory chip 2-2 to the physical block address # 31 in the flash memory chip 2-2 is completed.
[0077]
The 8000 flags # 0 to # 7999 in each table # 0 to # 3 correspond to the physical block address storage areas # 0 to # 7999 in the table, respectively, and the corresponding physical block address storage areas Indicates whether the physical block address stored in is a valid value. Specifically, if the flag is “1”, it indicates that the physical block address stored in the corresponding physical block address storage area is a valid value, and if the flag is “0”, the corresponding physical block address is stored. Indicates that the physical block address stored in the block address storage area is not a valid value. Therefore, it means that a physical block address is not yet associated with a logical block address whose corresponding flag is “0”.
[0078]
As described above, the address conversion table 27 includes 32000 flags and 32000 physical block storage areas. Each flag needs to store 1-bit information. Needs to store 13-bit information, the address conversion table 27 occupies about 56 kbytes of the storage capacity of the SRAM work area 8.
[0079]
The address conversion table 27 is generated as follows.
[0080]
Of the blocks constituting the flash memory chips 2-0 to 2-3, the redundant area 26 included in each head page (page # 0) of the block storing data has the block as described above. A corresponding logical block address indicating which logical block address corresponds is included, and the corresponding logical block address stored in each head page of each block is controlled by the microprocessor 6 under the control of the flash memory interface block 10. Is read through. When the corresponding logical block address is read, it is determined whether or not the block is an erased empty block under the control of the microprocessor 6.
[0081]
Here, in the erased empty block, the corresponding logical block address stored in the redundant area 26 should be “all 1 (1111111111111B)”. That is, as described above, the corresponding logical block address is only from # 0 (0000000000000000B) to # 7999 (1111100111111B). Therefore, when this is all 1 (1111111111111B), the corresponding block is an erased empty block. It can be judged that there is. On the other hand, when the corresponding logical block address is “0000000000000000B” to “1111100111111B”, the corresponding logical block address is a valid logical block address.
[0082]
Therefore, the microprocessor 6 refers to the corresponding logical block address included in the redundant area 26 of the pages # 0 to # 3 of each block, and if this indicates a valid logical block address number instead of all 1, the chip Among the physical block address storage areas belonging to the table corresponding to the number, the physical block address storage area to which the same logical block address as the read corresponding logical block address is assigned is stored in the physical block address. The block address is stored and the corresponding flag is set to “1”. For example, if the block from which the corresponding logical block address is read belongs to the flash memory chip 2-0, the physical block address is “10”, and the read corresponding logical block address is “123”, table # 0 "10" is written as the physical block address to the physical block address storage area # 123 to which "123" is assigned as the logical block address, and the corresponding flag # 123 is set to " 1 ”.
[0083]
The processing as described above is performed for all the blocks in which data is stored, whereby the creation of the address conversion table 27 is completed.
[0084]
Next, the data structure of the erased block queue 28 stored in the SRAM work area 8 will be described.
[0085]
FIG. 6 is a schematic diagram showing the data structure of the erased block queue 28 stored in the SRAM work area 8.
[0086]
As shown in FIG. 6, the erased block queue 28 is configured by eight queues including queues # 0 to # 7. Each of these queues # 0 to # 7 uses a 2-byte storage area of the SRAM work area 8, and a physical block address is stored as 13-bit data. Therefore, the erased block queue 28 occupies 16 bytes of the storage capacity of the SRAM work area 8.
[0087]
Of the queues # 0 to # 7 constituting the erased block queue 28, the queues # 0 and # 1 are queues for the flash memory 2-0, and the queues # 0 and # 1 include the flash memory 2-0. Are stored, that is, physical block addresses of blocks in which all flash memory cells 16 constituting the user area 25 and the redundant area 26 are in the erased state. Similarly, queues # 2 and # 3 are queues for the flash memory 2-1, queues # 4 and # 5 are queues for the flash memory 2-2, and queues # 6 and # 7 are flash queues. This is a queue for the memory 2-3.
[0088]
The generation of the erased block queue 28 is performed when the above-described address conversion table 27 is generated under the control of the microprocessor 6.
[0089]
That is, as described above, the redundant area 26 included in page # 0 to page # 3 of each block constituting the flash memory chips 2-0 to 2-3 includes the corresponding logical block address, and the address conversion. When the table 27 is generated, a block whose corresponding logical block address is “all 1 (1111111111111B)” is searched under the control of the microprocessor 6. As a result of such a search, a maximum of 192 erased blocks are detected for each flash memory chip to become redundant blocks, and a maximum of two redundant blocks are selected from these, and the physical block address corresponds to the corresponding flash memory chip. Are stored in two queues.
[0090]
Next, the data structure of the internal variable 30 stored in the SRAM work area 8 will be described.
[0091]
FIG. 7 is a schematic diagram showing the data structure of the internal variable 30 stored in the SRAM work area 8.
[0092]
As shown in FIG. 7, the internal variable 30 is composed of variables # 0 to # 3. These variables # 0 to # 3 are variables for the flash memory chips # 2-0 to # 2-3, respectively, a transfer destination block address storage area 31, a transfer source block address storage area 32, and a start page storage area 33, respectively. And a flag 34. In both the transfer destination block address storage area 31 and the transfer source block address storage area 32, the physical block address is stored as 13-bit data, and in the start page storage area 33, the page number is determined as 5-bit data. Stored. The flag 34 is 1-bit data. Therefore, the internal variable 30 occupies 16 bytes of the storage capacity of the SRAM work area 8.
[0093]
The physical block address stored in the transfer destination block address storage area 31 is the physical block address of the block that is the transfer destination in the “partial transfer” described in detail below, and is stored in the transfer source block address storage area 32. The physical block address is the physical block address of the block that is the transfer source in the “partial transfer”. The page number stored in the start page storage area 33 is the last page (page #) among the pages # 0 to # 31 in the physical block indicated by the physical block address stored in the transfer destination block address storage area 31. 31) is the page number of the first page in one or two or more consecutive empty pages. Therefore, in the physical block, pages after the start page are guaranteed to be empty pages in which no data is stored. If the flag 34 is “1”, it indicates that the contents of the corresponding transfer destination block address storage area 31, transfer source block address storage area 32, and start page storage area 33 are valid. If present, it indicates that these are not valid values.
[0094]
Next, a data write operation by the flash memory system 1 according to the present embodiment will be described.
[0095]
The data write operation by the flash memory system 1 according to the present embodiment is classified into three, a new write operation, a partial transfer operation, and an additional write operation.
[0096]
FIG. 8 is a flowchart for determining which write operation is performed. Hereinafter, the writing operation to be selected will be described with reference to the flowchart shown in FIG.
[0097]
First, when a host address and an external write command are supplied from the host computer 5 to the controller 3 (step S1), the host address and the external write command are stored in a task file register (not shown) included in the host interface block 7. Stored temporarily. Further, when write data is supplied to the controller 3, it is sent to the ECC block 11 under the control of the microprocessor 6. The ECC block 11 that has received the supply of the write data analyzes this to generate an error collection code, and temporarily holds it.
[0098]
Next, whether or not the host addresses stored in the task file register (not shown) are correct addresses, that is, whether or not these host addresses indicate an originally nonexistent address or an invalid address. Determined by the host interface block 7.
[0099]
As a result of the determination, if it is determined that the host address stored in the task file register (not shown) is a valid address, the host address is converted into an internal address. On the other hand, if it is determined that this is an abnormal address, an error register (not shown) of the host interface block 7 is set, and the host computer 5 refers to the contents of the register to generate an error. I can know.
[0100]
Conversion to the internal address is performed as follows.
[0101]
First, under the control of the microprocessor 6, the upper 15 bits are extracted from the 20-bit host address and divided by "8000" (step S2). The quotient (0-3) and remainder (0-7999) obtained by the division are “chip number” and “logical block address”, respectively, and the address conversion table 27 is based on the chip number and logical block address. Are read out (step S3). For example, if the upper 15 bits of the host address are “00000011110100B”, the quotient when dividing by 8000 is “00B (0)” and the remainder is “0111110100B (500)”. Is # 0 and the logical block address is # 500. Based on this, the flag # 500 in the table # 0 is read.
[0102]
When the corresponding flag in the address conversion table 27 is read in this way, it is next determined whether the content is “1” or “0” (step S4). As a result, if the content of the read flag is “0”, it means that a valid physical block address is not stored in the corresponding physical block address storage area, and a new write operation is selected. (Step S5). Details of the new writing operation will be described later.
[0103]
On the other hand, if the content of the read flag is “1”, it means that a valid physical block address is stored in the corresponding physical block address storage area, so that the content is read. The read 13-bit physical block address constitutes an internal address together with the chip number and the lower 5 bits of the host address. Thus, the conversion to the internal address is completed (step S6).
[0104]
Next, the corresponding flag 34 in the internal variable 30 is read based on the chip number (the upper 2 bits of the internal address) (step S7). For example, if the chip number is “00B (0)”, the flag 34 included in the variable # 0 is read. In this manner, when the corresponding flag 34 in the internal variable 30 is read, it is next determined whether the content is “1” or “0” (step S8). As a result, if the content of the read flag 34 is “0”, the partial transfer operation described in detail below is selected (step S9).
[0105]
On the other hand, if the content of the read flag 34 is “1”, an additional writing determination (step S10) is performed to determine whether or not the additional writing operation can be performed. If it is determined that the write operation can be performed, the additional write operation described below is selected, and if it is determined that the additional write operation cannot be performed, the partial transfer operation is selected. Is done.
[0106]
As described above, it is determined which of the new writing operation, the partial transfer operation, and the additional writing operation should be executed.
[0107]
Next, a new write operation will be described.
[0108]
FIG. 9 is a flowchart showing a new writing operation.
[0109]
As shown in FIG. 9, in the new write operation (step S5), first, a predetermined queue among the queues # 0 to # 7 constituting the erased block queue 28 is controlled under the control of the microprocessor 6. The physical block address selected and stored is read (step S11). As described above, the physical block address stored in each queue of the erased block queue 28 is the erased block, that is, all the flash memory cells 16 constituting the user area 25 and the redundant area 26 are in the erased state. This is the physical block address (13 bits) of the block.
[0110]
When the physical block address of the erased block is read, this is stored in the corresponding physical block address storage area in the address conversion table 27, and the corresponding flag is rewritten to “1” (step S12). For example, if the upper 15 bits of the host address are “00000011110100B” as in the above example, the quotient when divided by 8000 is “00B (0)”, and the remainder is “0111110100B (500)”. Thus, the physical block address of the erased block is stored in the physical block address storage area # 500 in the table # 0 of the address conversion table 27, and the flag # 500 in the table # 0 is rewritten to “1”.
[0111]
Then, under the control of the microprocessor 6, the chip number, the physical block address, and the lower 5 bits of the host address are combined in this order, and the combined address becomes an internal address (step S13).
[0112]
When the generation of the internal address is completed in this manner, a predetermined setting is made for a register (not shown) included in the flash sequencer block 12 under the control of the microprocessor 6, and when the generation is completed, the flash sequencer block 12 A series of write operations are executed (step S14). As a result, the user data given from the host computer 5 is written to a predetermined page in a predetermined block indicated by the internal address.
[0113]
In this case, for the block to be written, not only the page to which user data is to be written, but also the logical block addresses corresponding to the redundant areas 26 of all pages # 0 to # 31 constituting the block. Is written. As a result, the block becomes a “used block”, and the user data cannot be directly overwritten thereafter.
[0114]
Thus, the new writing operation (step S5) is completed.
[0115]
Next, the partial transfer operation will be described.
[0116]
FIG. 10 is a flowchart showing the partial transfer operation, and FIGS. 11A and 11B are schematic diagrams showing the data storage states of the transfer source block and the transfer destination block in the partial transfer operation.
[0117]
As shown in FIG. 10, in the partial transfer operation (step S9), first, a predetermined queue is selected from the queues # 0 to # 7 constituting the erased block queue 28 under the control of the microprocessor 6. Then, the stored physical block address is read (step S21).
[0118]
When the physical block address of the erased block is read, the internal variable 30 is updated based on this (Step S22). Here, in updating the internal variable 30, any one of the variables # 0 to # 3 is first selected based on the chip number, and the erased block queue 28 is stored in the transfer destination block address storage area 31 constituting the selected variable. The physical block address read out is stored, the physical block address read out from the address conversion table 27 is stored in the transfer source block address storage area 32, and the write target page (page #i) is stored in the start page storage area 33. ) Is stored as the page number (page # i + 1) of the next page. Further, the flag 34 is set to “1”. Here, the page to be written (page #i) refers to a page specified by the lower 5 bits of the internal address. Hereinafter, the block specified by the physical block address stored in the transfer destination block address storage area 31 is referred to as “transfer destination block”, and the block specified by the physical block address stored in the transfer source block address storage area 32 is referred to as “transfer destination block”. This is called a “transfer source block”.
[0119]
When the update of the internal variable 30 is completed, the address conversion table 27 is then updated (step S23). In updating the address conversion table 27, the physical block address read from the erased block queue 28 is overwritten in the corresponding physical block address storage area.
[0120]
Next, the data stored in the pages from page # 0 in the transfer source block to the page (page # i-1) immediately before the page to be written (page #i) is the same page in the transfer destination block. (Step S24). That is, the operation of the first half of inter-block transfer is performed. When step S24 is completed, as shown in FIG. 11A, pages # 0 to # i-1 of the transfer destination block become valid pages (hatched portions), and pages #i to # 31 become empty pages. Become. Here, “valid page” means a page in which a write operation is prohibited regardless of whether or not actually valid user data is stored. In the valid page, the corresponding logical block address is written in the corresponding redundant area 26, and in the empty page, the corresponding logical block address in the corresponding redundant area 26 is all 1 (1111111111111B).
[0121]
When step S24 is completed, the data instructed to be written by the host computer 5 is then written to the write target page (page #i) of the transfer destination block (step S25). When step S25 is completed, as shown in FIG. 11B, pages # 0 to #i of the transfer destination block become valid pages, and pages # i + 1 to # 31 become empty pages.
[0122]
Thus, the partial transfer operation (step S9) is completed. In the partial transfer operation, it is important that the operation in the latter half of the inter-block transfer is omitted. Therefore, when a partial transfer operation is performed, two physical blocks are assigned to a certain logical block address.
[0123]
Next, additional writing determination will be described.
[0124]
FIG. 12 is a flowchart showing the additional write determination.
[0125]
As shown in FIG. 12, in the additional write determination (step S10), first, based on the chip number (the upper 2 bits of the internal address), the corresponding transfer destination block address storage area 31 in the internal variable 30 is stored. The contents are read (step S31). Next, the read 13-bit physical block address is compared with the physical block address read from the address conversion table 27, and it is determined whether or not they match (step S32).
[0126]
As a result, if they do not match, the contents of the transfer source block address storage area 32 and the start page storage area 33 are read (step S33), from page # i + 1 to the last page (page # 31) in the transfer source block. The data stored in this page is transferred to the same page in the transfer destination block (step S34). That is, the operation of the latter half of inter-block transfer is performed.
[0127]
FIG. 13 is a schematic diagram showing the data storage state of the transfer source block and the transfer destination block in step S34.
[0128]
As shown in FIG. 13, in step S34, the operation of the latter half of the inter-block transfer omitted in the above-described partial transfer operation (step S9) is performed, whereby all pages constituting the transfer destination block are performed. # 0 to # 31 are valid pages.
[0129]
When step S34 is completed, the transfer source block is then erased as a new empty block (step S35), and the corresponding flag 34 is reset to “0” (step S36). As a result, the state in which two physical blocks are assigned to one logical block address is eliminated. Thereafter, the partial transfer operation (step S9) described above is performed, whereby the data instructed to be written by the host computer 5 is written into a predetermined block.
[0130]
On the other hand, if the result of determination in step S32 is that they match, the contents of the start page storage area 33 are read (step S37), and the lower 5 bits of the internal address, that is, the page to be written (page #j) And the start page (page # i + 1) are compared (step S38).
[0131]
As a result, if the page number of the page to be written (page #j) is smaller than the page number of the start page (page # i + 1), steps S33 to S36 described above are executed, and then the partial transfer operation (step S9) is performed. Executed. On the other hand, if the page number of the page to be written (page #j) is equal to or greater than the page number of the start page (page # i + 1), an additional writing operation described in detail below is selected (step S39). ).
[0132]
Thus, the additional writing determination (step S10) is completed. Thus, in the additional write determination (step S10), either the additional write operation (step S39) or the partial transfer operation (step S9) is selected.
[0133]
Next, the additional writing operation will be described.
[0134]
FIG. 14 is a flowchart showing the additional write operation, and FIGS. 15A to 15C are schematic diagrams showing data storage states of the transfer source block and the transfer destination block in the additional write operation.
[0135]
The additional writing operation (step S39) is performed depending on whether the page to be written (page #j) matches the start page (page # i + 1) (j = i + 1) or not (j> i + 1). Different. Therefore, as shown in FIG. 14, in the additional writing operation, it is first determined whether or not the page to be written (page #j) matches the start page (page # i + 1) (step S41). .
[0136]
As a result, when the page to be written (page #j) and the start page (page # i + 1) match (j = i + 1), for the page to be written (page #j) in the transfer destination block. Data is written (step S43). As a result, as shown in FIG. 15A, pages # 0 to #j (= i + 1) of the transfer destination block are valid pages, and pages # j + 1 to # 31 are empty pages. It becomes. When step S43 is completed, the contents of the start page storage area 33 of the internal variable 30 are then updated to the page number (page # j + 1) of the page next to the page to be written (page #j) (step S44). ).
[0137]
On the other hand, if the page to be written (page #j) and the start page (page # i + 1) do not match (j> i + 1), the page to be written (page # i + 1) from the start page (page # i + 1) in the transfer source block. The data stored in the pages up to the previous page (page # j-1) of page #j) is transferred to the same page in the transfer destination block (step S42). That is, intermediate transfer is performed. As a result, as shown in FIG. 15B, pages # 0 to # j-1 of the transfer destination block become valid pages, and pages #j to # 31 become empty pages. When step S42 is completed, data is written to page #j in step S43 described above, and as a result, as shown in FIG. 15C, pages # 0 to #j (= i + 1) of the transfer destination block. Are valid pages, and pages # j + 1 to # 31 are empty pages. Thereafter, step S44 described above is executed, and the content of the start page storage area 33 is updated to page # j + 1.
[0138]
When the data writing is completed in this way, it is next determined whether or not the page to be written (page #j) is the last page (page # 31) (step S45). As a result, if the page to be written (page #j) is the last page (page # 31), the transfer source block is erased as a free block (step S46), and the corresponding flag 34 is reset to “0”. (Step S47). On the other hand, if the page to be written (page #j) is other than the last page (page # 31), the series of processes is terminated without executing steps S46 and S47.
[0139]
Thus, the additional writing operation (step S39) is completed.
[0140]
The above is the data write operation by the flash memory system 1 according to the present embodiment.
[0141]
In the flash memory system 1 according to this embodiment, a state in which two physical blocks are allocated to one logical block address occurs by performing the partial transfer operation (step S9). For this reason, when the host computer 5 gives an instruction to read data from the block, the internal variable 30 is referred to and the physical block in which correct data is written can be read.
[0142]
However, in this case, since it is necessary to refer to the internal variable 30 every time data reading is instructed from the host computer 5, a data write instruction to the same logical block address is performed after the partial transfer operation is performed. When an instruction other than the above is issued from the host computer 5, the inter-block transfer may be completed by executing the above-described steps S33 to S35 before executing the instruction. In this case, even if the host computer 5 instructs to read data for any logical block address, this can be performed by the same read processing as the normal flash memory system 1.
[0143]
Next, when partial transfer operation (step S9) is performed, power is shut off in a state where two physical blocks are assigned to one logical block address, and then power is turned on again. Will be described.
[0144]
When power is shut down in a state where two physical blocks are assigned to one logical block address, two physical blocks are used as physical blocks corresponding to a certain logical block address in the creation of the address conversion table 27 performed at startup. A block should be found. That is, two physical blocks having the same corresponding logical block address should be found. When such a logical block address is found, a complete operation described in detail below is executed under the control of the microprocessor 6.
[0145]
FIG. 16 is a flowchart showing the completion operation, and FIG. 17 is a schematic diagram showing the data storage state of the transfer source block and the transfer destination block in the completion operation.
[0146]
As shown in FIG. 16, in the completion operation, first, the last pages (page # 31) of two physical blocks having the same corresponding logical block address are respectively read to determine which is an empty page. Here, the determination of which is an empty page is made based on the corresponding logical block address included in the redundant area 26 of these pages, and the one where the corresponding logical block address is all 1 (1111111111111B) is an empty page. It is determined that there is. As a result of the determination, a block in which the last page (page # 31) is an empty page is a transfer destination block in the partial transfer operation, and a block in which the last page (page # 31) is a valid page is in the partial transfer operation. It can be determined that the block is a transfer source block (step S51).
[0147]
When the determination of the transfer destination block / transfer source block for the two physical blocks is completed in this way, the physical block address of the transfer destination block is stored in the corresponding physical block address storage area in the address conversion table 27. At the same time, the corresponding flag is set to “1” (step S52).
[0148]
Next, the pages constituting the transfer destination block are sequentially read back in order from page # 30, thereby detecting the range of empty pages (step S53). For example, if a valid corresponding logical block address is read in page # 20, it is detected that pages # 21 to # 31 are empty blocks.
[0149]
When the range of the empty block is detected, next, the data of the page corresponding to the transfer source block is transferred to each empty page of the transfer destination block (step S54). That is, the operation of the latter half of inter-block transfer is performed. As a result, as shown in FIG. 17, all pages # 0 to # 31 of the transfer destination block become valid pages. FIG. 17 shows the operation when it is detected in step S53 that pages # 21 to # 31 of the transfer destination block are empty blocks. Then, the transfer source block is erased to be an empty block (step S55), and the series of processing ends.
[0150]
Thus, the completion operation is completed.
[0151]
As described above, in the flash memory system 1 according to the present embodiment, for the logical block address to which data has already been assigned, that is, the logical block address for which the corresponding flag in the address conversion table 27 is “1”. Even if the host computer 5 instructs to write data, the inter-block transfer is not immediately performed as in the prior art, but the partial write operation in which the operation of the latter half of the inter-block transfer is omitted is performed. Therefore, the next write operation can be performed when the host computer 5 next instructs the same block to write data. In the additional write operation, as described above, since the number of pages to be transferred is zero or a small number, a series of transfers is performed as compared with a case where the transfer between blocks is performed every time data writing is instructed from the host computer 5. The time required for this process is greatly reduced. In particular, under the situation where the host computer 5 sequentially instructs writing data one page at a time for a plurality of consecutive pages, the effect of speeding up by the flash memory system 1 according to the present embodiment is significant.
[0152]
Next, another preferred embodiment of the present invention will be described.
[0153]
The configuration of the flash memory system 39 according to another preferred embodiment of the present invention is basically the same as that of the flash memory system 1 according to the above embodiment as shown in FIG. 1 and is stored in the SRAM work area 8. The difference is that the internal variable 30 is replaced with the internal variable 40.
[0154]
FIG. 18 is a schematic diagram showing the data structure of the internal variable 40 stored in the SRAM work area 8.
[0155]
As shown in FIG. 18, the internal variable 40 is composed of variables # 0 to # 3, which are a first block address storage area 41, a second block address storage area 42, and a third block address storage area 43, respectively. , A first start page storage area 44, a second start page storage area 45, a first flag 46 and a second flag 47. In the first to third block address storage areas 41 to 43, physical block addresses are stored as 13-bit data, respectively, and in the first and second start page storage areas 44 and 45, page numbers are respectively stored. Is stored as 5-bit data. Each of the first and second flags 46 and 47 is 1-bit data. Therefore, the internal variable 40 occupies 28 bytes of the storage capacity of the SRAM work area 8.
[0156]
If the first flag 46 is “1”, it indicates that the content of the variable is valid, and if it is “0”, the content of the variable is invalid. That is, the first flag 46 is a flag corresponding to the flag 34 in the above embodiment. The second flag 47 is valid only when the first flag 46 is “1”. If this flag is “1”, the first to third block address storage areas 41 to 43 are used. Indicates that the contents of the first and second start page storage areas 44 and 45 are all valid, and if “0”, the first and second block address storage areas 41 and 42 and the first start page storage area The contents of the page storage area 44 are all valid, and the contents of the third block address storage area 43 and the second start page storage area 45 are invalid.
[0157]
The first block address storage area 41 corresponds to the transfer source block address storage area 32 in the above embodiment, and the second block address storage area 42 corresponds to the transfer destination block address storage area 31 in the above embodiment. To do. In addition, the first start page storage area 44 corresponds to the start page storage area 33 in the above embodiment.
[0158]
Next, a data write operation by the flash memory system 39 according to the present embodiment will be described.
[0159]
The data write operation in the flash memory system 39 according to the present embodiment is classified into five, that is, a new write operation, first and second partial transfer operations, and first and second additional write operations. The method for determining which of these write operations is selected is basically the same as the flowchart shown in FIG. 8, but in step S7, it is based on the chip number (the upper 2 bits of the internal address). The corresponding first flag 46 in the internal variable 40 is read out. As a result, if this is “0”, the first partial transfer operation is selected.
[0160]
The first partial transfer operation is basically the same as the partial transfer operation (step S9) in the above embodiment, but in step S22, one of the variables # 0 to # 3 is first selected based on the chip number. The physical block address read from the erased block queue 28 is stored in the second block address storage area 42 constituting the selected variable, and read from the address conversion table 27 in the first block address storage area 41. The issued physical block address is stored, and the page number (page # i + 1) of the next page of the page to be written (page #i) is stored in the first start page storage area 44. Further, the first flag 46 is set to “1”, and the second flag 47 is reset to “0”.
[0161]
Hereinafter, the block specified by the physical block address stored in the first block address storage area 41 is referred to as “first block”, and is specified by the physical block address stored in the second block address storage area 42. This block is called “second block”. A block specified by the physical block address stored in the third block address storage area 43 is referred to as a “third block”.
[0162]
In step S24, the data stored in the pages from the page # 0 in the first block to the page (page # i-1) immediately preceding the page to be written (page #i) is stored in the second block. In step S25, the data instructed to be written by the host computer 5 is written to the page to be written (page #i) of the second block.
[0163]
Next, additional writing determination in this embodiment will be described.
[0164]
FIG. 19 is a flowchart showing the additional write determination by the flash memory system 39 according to the present embodiment.
[0165]
As shown in FIG. 19, in the additional write determination (step S10) in this embodiment, first, the corresponding second flag 47 in the internal variable 40 is based on the chip number (the upper 2 bits of the internal address). Is read (step S61). When the corresponding second flag 47 in the internal variable 40 is read, it is next determined whether the content is “1” or “0” (step S62). As a result, if the content of the read second flag 47 is “0”, the content of the second block address storage area 42 is read (step S63). The contents of the block address storage area 43 are read (step S64).
[0166]
When the content of the second block address storage area 42 is read because the content of the second flag 47 is “0” (step S 63), the physical block read from the content and the address conversion table 27. The address is compared, and it is determined whether or not they match (step S65).
[0167]
As a result, if the two do not match, the contents of the first block address storage area 41 and the first start page storage area 44 are read (step S66) and specified by the contents of the first block address storage area 41 Among the pages in the first block, the data stored in the pages from the page (page # i + 1) specified by the contents of the first start page storage area 44 to the last page (page # 31) are stored. Then, it is transferred to the same page in the second block specified by the contents of the second block address storage area 42 (step S67). That is, the operation of the latter half of inter-block transfer is performed. Such an operation is the same as the transfer operation shown in FIG.
[0168]
When step S67 is completed, the first block is then erased into a new empty block (step S68), and the corresponding first flag 46 is reset to “0” (step S69). ). As a result, the state in which two physical blocks are assigned to one logical block address is eliminated. Thereafter, the above-described first partial transfer operation (step S9) is performed.
[0169]
On the other hand, if the result of determination in step S65 is that they match, the contents of the first start page storage area 44 are read (step S70), and the lower 5 bits of the internal address, that is, the page to be written (page #J) is compared with the start page (page # i + 1) (step S71).
[0170]
As a result, if the page number of the page to be written (page #j) is smaller than the page number of the start page (page # i + 1), a second partial transfer operation (step S72) described in detail below is performed. If the page number of the page to be written (page #j) is greater than or equal to the page number of the start page (page # i + 1), the first additional write operation is selected (step S39). The first additional write operation is basically the same as the partial transfer operation (step S39) in the above embodiment, but in step S44, the contents of the first start page storage area 44 corresponding to the internal variable 40 are stored. Is updated to the page number (page # j + 1) of the next page of the page to be written (page #j). In step S47, the first flag 46 corresponding to the internal variable 40 is reset to “0”.
[0171]
Here, the second partial transfer operation (step S72) will be described.
[0172]
FIG. 20 is a flowchart showing the second partial transfer operation, and FIGS. 21A and 21B are schematic diagrams showing the data storage states of the first to third blocks in the second partial transfer operation. is there.
[0173]
As shown in FIG. 20, in the second partial transfer operation (step S72), first, a predetermined number of queues # 0 to # 7 constituting the erased block queue 28 are controlled under the control of the microprocessor 6. The queue is selected, and the stored physical block address is read (step S91).
[0174]
When the physical block address of the erased block is read, the internal variable 40 is updated based on this (Step S92). Here, in updating the internal variable 40, first, any one of the variables # 0 to # 3 is selected based on the chip number, and the erased block queue is stored in the third block address storage area 43 constituting the selected variable. 28 is stored, and the page number (page # j + 1) of the next page of the page to be written (page #j) is stored in the second start page storage area 45. Further, the second flag 47 is set to “1”.
[0175]
When the update of the internal variable 40 is completed, the address conversion table 27 is then updated (step S93). In updating the address conversion table 27, the physical block address read from the erased block queue 28 is overwritten in the corresponding physical block address storage area.
[0176]
Next, the data stored in the page from page # 0 in the second block to the page (page # j-1) immediately before the page to be written (page #j) is stored in the third block. It is transferred to the same page (step S94). That is, the operation of the first half of inter-block transfer is performed. When step S94 is completed, as shown in FIG. 21A, pages # 0 to # j-1 of the third block become valid pages, and pages #j to # 31 become empty pages.
[0177]
When step S94 is completed, the data instructed to be written by the host computer 5 is then written to the write target page (page #j) of the transfer destination block (step S95). When step S95 is completed, as shown in FIG. 21B, pages # 0 to #j of the third block become valid pages, and pages # j + 1 to # 31 become empty pages.
[0178]
Thus, the second partial transfer operation (step S72) is completed. As shown in FIG. 21, when the second partial transfer operation is performed, three physical blocks are assigned to a certain logical block address.
[0179]
Returning to FIG. 19, the additional write determination will be described again.
[0180]
In step S62, when the content of the third block address storage area 43 is read because the content of the second flag 47 is “1” (step S64), the content is read from the address conversion table 27. The physical block addresses thus compared are compared to determine whether or not they match (step S73).
[0181]
As a result, if they do not match, the contents of the first block address storage area 41, the second block address storage area 42, the first start page storage area 44, and the second start page storage area 45 are read ( Step S74). next,
Of the pages in the second block, the data stored in the pages from the second start page (page # j + 1) to the page (page #i) immediately before the first start page (page # i + 1) Are transferred to the same page in the third block (step S75). As a result, as shown in FIG. 22A, pages # 0 to #i of the third block become effective pages, and page # i + 1 becomes an empty page.
[0182]
Next, of the pages in the first block, the data stored in the pages from the first start page (page # i + 1) to the last page (page # 31) are stored in the same page in the third block. Transferred (step S76). As a result, as shown in FIG. 22B, all pages # 0 to # 31 of the third block become valid pages.
[0183]
Then, the first block and the second block are erased to become a new empty block (step S77), and the corresponding first flag 46 and second flag 47 are reset to “0”. (Step S69). As a result, the state in which three physical blocks are assigned to one logical block address is canceled. Thereafter, the above-described first partial transfer operation (step S9) is performed.
[0184]
On the other hand, if they match in step S73, the contents of the second start page storage area 45 are read (step S78), and the lower 5 bits of the internal address, that is, the page to be written (page #k) And the second start page (page # j + 1) are compared (step S79).
[0185]
As a result, if the page number of the page to be written (page #k) is smaller than the page number of the second start page (page # j + 1), among the pages in the second block, the second start page ( Data stored in pages from page # j + 1) to the page immediately before the first start page (page # i + 1) (page #i) is transferred to the same page in the third block (step S80). Next, the second block is erased (step S81). As a result, the third block becomes a new second block and the second block becomes an empty block, and the internal variable 40 is updated based on this (step S82). Here, in updating the internal variable 40, the contents of the corresponding third block address storage area 43 are copied to the second block address storage area 42, and the second flag 47 is reset to "0". The When the update of the internal variable 40 is completed, the second partial transfer operation (step S72) described above is executed.
[0186]
On the other hand, if the page number of the page to be written (page #k) is greater than or equal to the page number of the second start page (page # j + 1) in step S73, the second additional write operation described in detail below is performed. Selected (step S83).
[0187]
Thus, the additional writing determination (step S10) is completed. Thus, in the additional write determination (step S10) in the present embodiment, the first partial transfer operation (step S9), the second partial transfer operation (step S72), and the first additional write operation (step S10). In S39), one of the second additional write operations (step S83) is selected.
[0188]
Next, the second additional writing operation (step S83) will be described.
[0189]
FIG. 23 is a flowchart showing the second additional write operation, and FIGS. 24A to 24C and FIGS. 25A to 25C show the first to second write operations in the second additional write operation. It is the schematic which shows the data storage state of 3 blocks.
[0190]
The second additional write operation (step S83) is performed when the page to be written (page #k) matches the second start page (page # j + 1) (k = j + 1) and does not match (k The operation differs depending on> j + 1). Therefore, as shown in FIG. 23, in the second additional write operation, it is first determined whether or not the page to be written (page #k) matches the second start page (page # j + 1). (Step S101).
[0191]
As a result, when the page to be written (page #k) matches the second start page (page # j + 1) (k = j + 1), the page to be written (page #k) in the third block. ) Is written (step S102). As a result, as shown in FIG. 24A, pages # 0 to #k (= j + 1) of the third block are valid pages, and pages # k + 1 to # 31 is an empty page. When step S102 is completed, it is next determined whether or not the page to be written (page #k) matches the previous page (page #i) of the first start page (step S103). As a result, if the page to be written (page #k) does not match the page immediately before the first start page (page #i) (k ≠ i), the second start of the internal variable 40 The contents of the page storage area 45 are updated to the page number (page # k + 1) of the page next to the page to be written (page #k) (step S104).
[0192]
On the other hand, if the page to be written (page #k) matches the page immediately before the first start page (page #i) (k = i), the second block is erased as a block. After making it an empty block (step S105), the internal variable 40 is updated (step S106). Here, in updating the internal variable 40, the contents of the corresponding third block address storage area 43 are copied to the second block address storage area 42, and the second flag 47 is reset to "0". The As a result, the third block becomes a new second block, and the second block becomes an empty block.
[0193]
In step S101, if the page to be written (page #k) does not match the second start page (page # j + 1) (k> j + 1), the page to be written (page #k) 1 start page (page # i + 1) is compared (step S107). As a result, if the page to be written (page #k) is equal to or lower than the first start page (page # i + 1), the page to be written (page # j + 1) from the second start page (page # j + 1) in the second block. Data stored in the pages up to the previous page (page # k-1) of page #k) is transferred to the same page in the third block (step S108). As a result, as shown in FIG. 24B, pages # 0 to # k-1 of the third block become valid pages, and pages #k to # 31 become empty pages. When step S108 is completed, data is written to page #k by step S102 described above, and as a result, as shown in FIG. 24C, pages # 0 to #k (= j + 1) of the third block. ) Are valid pages, and pages # k + 1 to # 31 are empty pages. Thereafter, the data writing in step S102 and the comparison in step S103 are executed, and step S104 or steps S105 and S106 are executed based on the result.
[0194]
If the result of comparison in step S107 is that the page to be written (page #k) is larger than the first start page (page # i + 1), the second start page (page # j + 1) in the second block. To the first page (page # i + 1) before the first start page (page # i + 1), the data stored in the page is transferred to the same page of the third block (step S109). As a result, as shown in FIG. 25A, pages # 0 to #i of the third block are valid pages, and pages # i + 1 to # 31 are empty pages. When step S109 is completed, next, from the first start page (page # i + 1) in the first block to the page (page # k-1) immediately before the page to be written (page #k). The data stored in the page is transferred to the same page in the third block (step S110). As a result, as shown in FIG. 25B, pages # 0 to # k-1 of the third block become valid pages, and pages #k to # 31 become empty pages. When the transfer operation from the second block to the third block (step S109) and the transfer operation from the first block to the third block (step S110) are completed in this way, Data is written to the page to be written (page #k) (step S111). As a result, as shown in FIG. 25C, pages # 0 to #k (= j + 1) of the third block. Are valid pages, and pages # k + 1 to # 31 are empty pages.
[0195]
When the data writing is completed in this way, it is next determined whether or not the page to be written (page #k) is the last page (page # 31) (step S112). As a result, if the page to be written (page #k) is the last page (page # 31), the first and second blocks are erased into empty blocks (step S113), and the corresponding first flag 46 is reset to “0” (step S114). On the other hand, if the page to be written (page #k) is other than the final page (page # 31), the above-described steps S105 and S106 are executed, whereby the third block becomes a second block, The second block becomes an empty block.
[0196]
Thus, the second additional write operation (step S83) is completed.
[0197]
The above is the data write operation by the flash memory system 39 according to the present embodiment.
[0198]
Further, in the state where two or three physical blocks are allocated to one logical block address by performing the first partial transfer operation (step S9) or the second partial transfer operation (step S72). When the power is turned off and then turned on again, inter-block transfer is completed by the same operation as the completion operation in the above embodiment.
[0199]
As described above, the flash memory system 39 according to the present embodiment is configured so that three physical blocks can be allocated to one logical block address in addition to the effects of the flash memory system 1 according to the above-described embodiment. The possibility that the additional writing operation is selected is further increased. As a result, a series of data write operations can be executed at a higher speed than the flash memory system 1 according to the above embodiment.
[0200]
Next, still another preferred embodiment of the present invention will be described.
[0201]
The configuration of a flash memory system 49 according to still another preferred embodiment of the present invention is basically the same as that of the flash memory system 1 according to the above embodiment as shown in FIG. 1, and is stored in the SRAM work area 8. The address conversion table 27 is replaced with the address conversion table 57, the erased block queue 28 is replaced with the erased block queue 58, and the internal variable 30 is replaced with the internal variable 50.
[0202]
The flash memory system 49 according to the present embodiment is a “virtual block system” flash memory system. First, the virtual block method will be described.
[0203]
In the virtual block type flash memory system, four actual use blocks selected one by one from each of the flash memory chips 2-0 to 2-3 are virtually combined to form a “virtual block”. Thereby, 8000 virtual blocks including virtual blocks # 0 to # 7999 are configured.
[0204]
FIG. 26 is a diagram illustrating an example of virtual block mapping.
[0205]
In the example shown in FIG. 26, physical block # 150 included in flash memory chip 2-0, physical block # 6811 included in flash memory chip 2-1, physical block # 8191 included in flash memory chip 2-2, Physical blocks # 3048 included in the flash memory chip 2-3 are virtually combined to form one virtual block. Thus, in this embodiment, it is necessary that the four physical blocks constituting one virtual block are included in different flash memory chips. In this way, a maximum of 8000 virtual blocks are configured.
[0206]
27 is a diagram showing a virtual page structure of the virtual block shown in FIG.
[0207]
As shown in FIG. 27, the virtual block is handled as one block composed of 128 virtual pages including virtual page # 0 to page # 127. Here, among the virtual blocks, 32 pages included in the portion including the physical block # 150 are given 4i (i is a physical page number) as a virtual page number, and are included in the portion including the physical block # 6811. 32 pages are given a virtual page number of 4i + 1, and 32 pages included in the part consisting of physical block # 8191 are given a virtual page number of 4i + 2 and included in a part consisting of physical block # 3048 These 32 pages are given 4i + 3 as the virtual page number. These virtual page numbers correspond to the lower 7 bits of the host address. Therefore, these virtual pages # 0 to # 127 are respectively accessed by successive host addresses. For this reason, when the host computer 5 instructs to write data to consecutive host addresses, parallel operation can be performed in each block, so that a series of write operations can be performed faster than in a normal flash memory system. Can be executed.
[0208]
Next, the relationship between the virtual block and the four physical blocks that constitute it will be described.
[0209]
FIG. 28 is a schematic diagram showing the data structure of the address conversion table 57 showing the relationship between 8000 virtual blocks and the four physical blocks constituting each virtual block.
[0210]
As shown in FIG. 28, the address conversion table 57 includes 8000 virtual blocks including virtual blocks # 0 to # 7999 arranged in this order, and each of these virtual blocks # 0 to # 7999 has a cell #. It consists of four cells and one flag consisting of j-0 to cell # j-3 (j is a virtual block address). For example, virtual block # 0 is composed of cell # 0-0 to cell # 0-3 and a flag, and virtual block # 1 is composed of cell # 1-0 to cell # 1-3 and a flag. Therefore, the address conversion table 57 is composed of 32000 cells and 8000 flags. Here, slot # 0 constituting cell # j-0 corresponds to flash memory chip 2-0, slot # 1 constituting cell # j-1 corresponds to flash memory chip 2-1, and cell #j -2 corresponds to the flash memory chip 2-2, and slot # 3 that configures the cell # j-3 corresponds to the flash memory chip 2-3.
[0211]
In cells # j-0 to # j-3 included in each virtual block, the addresses (physical block addresses) of the physical blocks constituting the virtual block are stored.
[0212]
A flag included in each virtual block indicates whether the virtual block is valid or invalid. Specifically, if the flag indicates “1”, the virtual block is valid, and if the flag indicates “0”, the virtual block is invalid. Therefore, the contents stored in the cells # j-0 to # j-3 included in the virtual block whose flag indicates “0” are ignored.
[0213]
The address conversion table 57 is generated as follows.
[0214]
In the virtual block method, among the physical blocks constituting the flash memory chips 2-0 to 2-3, the redundant area 26 included in each head page (physical page # 0) of the block in which data is stored , A virtual block address indicating to which virtual block the block belongs is included, and the virtual block address stored in each head page of each block is controlled by the microprocessor 6 under the control of the flash memory interface block 10. Is read through.
[0215]
If the virtual block address included in the redundant area 26 of the first page (physical page # 0) of each physical block indicates an address of a valid virtual block instead of all 1, cells constituting the address conversion table 57 Among these, the physical block address of the physical block is stored in the cell specified by the chip number and the read virtual block address. For example, if the read virtual block address from the physical block # 12 belonging to the flash memory chip 2-0 is “123”, “12” is written as the physical block address in the cell # 123-0.
[0216]
Such processing is performed for all physical blocks in which data is stored. Thereby, the generation of the address conversion table 57 is completed.
[0217]
Next, the data structure of the erased block queue 58 stored in the SRAM work area 8 will be described.
[0218]
FIG. 29 is a schematic diagram showing the data structure of the erased block queue 58 stored in the SRAM work area 8.
[0219]
As shown in FIG. 29, the erased block queue 58 is composed of six queue sets including queue sets # 0 to # 5, which are respectively queue # k-0 to queue # k-3 (k is , A queue set number). For example, the queue set # 0 includes queues # 0-0 to # 0-3, and the queue set # 1 includes queues # 1-0 to # 1-3. Therefore, the erased block queue 30 is composed of 24 queues. Here, queue # k-0 corresponds to flash memory chip 2-0, queue # k-1 corresponds to flash memory chip 2-1, and queue # k-2 corresponds to flash memory chip 2-2. Queue # k-3 corresponds to the flash memory chip 2-3.
[0220]
In queues # k-0 to # k-3 constituting each queue set # 0 to # 5, physical block addresses of physical blocks in which all flash memory cells 16 constituting the user area 25 are in the erased state are stored. Stored. Therefore, for example, when the erased physical block # 153 belonging to the flash memory chip 2-0 is registered in the erased block queue 58, the physical block address “00000101001001B” is the queue # 0-0 to # 5-0. Stored in either Similarly, for example, when an erased block # 6552 belonging to the flash memory chip 2-2 is registered in the erased block queue 30, the physical block address “11001100111000B” is stored in the queues # 0-2 to # 5- 2 is stored.
[0221]
In this manner, the physical block addresses of up to six erased blocks are registered in the erased block queue 58 for each of the flash memory chips 2-0 to 2-3, whereby up to six queue sets # 0 to # 5 are registered. Is generated.
[0222]
The generation of the erased block queue 58 is performed when the above-described address conversion table 57 is generated under the control of the microprocessor 6 and is stored in these queues from among the redundant blocks waiting for data writing. A physical block to be registered is selected.
[0223]
Next, the data structure of the internal variable 50 stored in the SRAM work area 8 will be described.
[0224]
The internal variable 50 has the same data structure as the internal variable 30 shown in FIG. Variables # 0 to # 3 constituting the internal variable 50 respectively correspond to slots # 0 to # 3 of the virtual block.
[0225]
Next, a data write operation by the flash memory system 49 according to the present embodiment will be described.
[0226]
First, when the host computer 5 instructs to write data to a virtual page with a used virtual block in which data has already been stored, basically the same operation as the partial transfer operation (step S9) described above. Thus, partial transfer is performed only to the corresponding physical block among the four physical blocks constituting the virtual block.
[0227]
FIG. 30 is a schematic diagram showing the data storage state of the transfer source block and the transfer destination block when the host computer 5 instructs to write data to the virtual page 4i + 1 of the virtual block #n.
[0228]
The virtual page 4i + 1 corresponds to the physical page #i of the physical block belonging to the slot # 1 among the four physical blocks constituting the virtual block #n. Therefore, when the host computer 5 instructs the virtual page 4i + 1 to write data, first, under the control of the microprocessor 6, a predetermined one of the queue sets # 0 to # 7 constituting the erased block queue 58 is determined. Slot # 1 of the queue set is selected, and the stored physical block address is read (step S21).
[0229]
When the physical block address of the erased block is read, the internal variable 50 is updated based on this (Step S22). Here, in updating the internal variable 50, first, the variable # 1 is selected based on the slot number, and the physical read out from the erased block queue 58 in the transfer destination block address storage area 31 constituting the selected variable. The block address is stored, the physical block address read from the address conversion table 57 is stored in the transfer source block address storage area 32, and the next page of the physical page to be written (page #i) is stored in the start page storage area 33. The page number (page # i + 1) is stored. Further, the flag 34 is set to “1”.
[0230]
When the update of the internal variable 50 is completed, the address conversion table 57 is then updated (step S23). In updating the address conversion table 57, the physical block address read from the erased block queue 58 is overwritten in the corresponding cell # n-1.
[0231]
Next, the data stored in the pages from the physical page # 0 in the transfer source block to the previous page (page # i-1) of the physical page to be written (page #i) is stored in the transfer destination block. It is transferred to the same page (step S24). That is, the operation of the first half of inter-block transfer is performed. When step S24 is completed, as shown in FIG. 30A, pages # 0 to # i-1 of the transfer destination block become valid pages, and pages #i to # 31 become empty pages.
[0232]
When step S24 is completed, the data instructed to be written by the host computer 5 is written to the physical page (page #i) to be written in the transfer destination block (step S25). When step S25 is completed, as shown in FIG. 30B, physical pages # 0 to #i of the transfer destination block become valid pages, and physical pages # i + 1 to # 31 become empty pages.
[0233]
Thus, the partial transfer operation (step S9) is completed.
[0234]
After such partial transfer is performed, when the host computer 5 instructs to write data to the virtual page 4j + 1 (j> i) of the virtual block #n, the above-described additional write operation (step S39). As a result, a series of data write operations are executed at high speed.
[0235]
Further, when the partial transfer operation (step S9) is performed, the power is shut off in a state where two physical blocks are allocated to one cell, and then the power is turned on again. The transfer between blocks is completed by the same operation as the completion operation in the aspect.
[0236]
As described above, the present invention can also be applied to the virtual block type flash memory system 49.
[0237]
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.
[0238]
For example, in the flash memory systems 1, 39, and 49 according to the above embodiment, the internal variables 30, 40, and 50 are made up of variables # 0 to # 3 corresponding to the flash memory chips 2-0 to 2-3, respectively. Thus, each flash memory chip is configured to record one set of transfer destination blocks and transfer source blocks one by one, but one set of transfer destination blocks and transfer source blocks is combined into one in each flash memory chip. The configuration is not limited, and two or more sets may be recorded.
[0239]
In addition, in the flash memory systems 1, 39, and 49 according to the above-described embodiments, when two physical blocks having the same corresponding logical block address are found at the time of startup, the completion operation including steps S51 to S55 is executed. However, in the present invention, it is not essential to perform the completion operation, and the internal variable 30, using the physical block address of these two blocks and the start page of the transfer destination block, are not necessary. The contents of 40 and 50 may be reproduced in the state immediately before the power is shut off.
[0240]
In the flash memory systems 1 and 49 according to the above embodiment, two physical blocks can be assigned to one logical block address (cell). In the flash memory system 39 according to the above embodiment, Although three physical blocks can be assigned to one logical block address, four or more physical blocks may be assigned to one logical block address.
[0241]
In the flash memory system 49 according to the above-described embodiment, a virtual block is configured by physical blocks selected one by one from the flash memory chips 2-0 to 2-3, but a plurality of independent registers are provided. A flash memory chip called a “bank type” divided into banks may be used, and a virtual block may be configured by a plurality of blocks belonging to different banks. If a “bank type” flash memory chip is used, a virtual block can be configured by one flash memory chip.
[0242]
In the flash memory system 1, 39, 49 according to the above embodiment, each block is composed of 32 pages. However, the number of pages constituting each block is not limited to 32. The number may be 16 or 64, for example. The present invention can obtain a more remarkable effect as the number of pages constituting each block increases.
[0243]
In the flash memory systems 1, 39, and 49 according to the above embodiment, when data is written to an empty block, all pages # 0 to ## of the block are independent of the page to which user data is to be written. The corresponding logical block address is stored in the redundant area 26 of 31. However, it is not essential to store the corresponding logical block address in the redundant area 26 of all pages # 0 to # 31. At least the first page (page It is sufficient to write this into the redundant area 26 of # 0) and the last page (page # 31).
[0244]
Further, in the flash memory system 1, 39, 49 according to the above embodiment, the address conversion tables 27, 57 relating to all physical blocks storing data are expanded on the SRAM work area 8. However, it is not essential to expand the address conversion table relating to all these physical blocks, and only a part of them may be expanded. In this case, the storage capacity required for the SRAM work area 8 can be reduced. However, when only the address translation table related to some physical blocks is expanded in this way, it is necessary to update the address translation table every time access to a physical block not included in the address translation table is requested. .
[0245]
In the above embodiment, the flash memory systems 1, 39, and 49 have a card shape, and the four flash memory chips 2-0 to 2-3 and the controller 3 are integrated in one card. However, the flash memory system according to the present invention is not limited to a card shape, and may have another shape, for example, a stick shape.
[0246]
Further, in the above embodiment, the flash memory systems 1, 39 and 49 are configured by integrating the four flash memory chips 2-0 to 2-3 and the controller 3 in one card. The flash memory chips 2-0 to 2-3 and the controller 3 do not have to be integrated in the same casing, and may be packaged in separate casings. In this case, the housing in which the flash memory chips 2-0 to 2-3 are packaged and the housing in which the controller 3 is packaged have connectors for realizing electrical and mechanical connections with the other. With such a connector, the housing in which the flash memory chips 2-0 to 2-3 are packaged is detachably attached to the housing in which the controller 3 is packaged. Furthermore, the flash memory chips 2-0 to 2-3 do not have to be integrated in the same casing, and may be packaged in separate casings.
[0247]
In the flash memory systems 1, 39, and 49 according to the above embodiments, each flash memory chip 2-0 to 2-3 is a semiconductor chip having a storage capacity of 128 Mbytes (1 Gbit). The storage capacity of the flash memory chips 2-0 to 2-3 is not limited to 128 Mbytes (1 Gbit), but may be a different capacity, for example, 32 Mbytes (256 Mbits).
[0248]
Further, in the flash memory systems 1, 39, and 49 according to the above embodiments, 512 bytes are set as one page, which is the minimum access unit. However, the minimum access unit is not limited to 512 bytes and is different from this. It may be a capacity.
[0249]
In the flash memory systems 1, 39, and 49 according to the above-described embodiments, each flash memory cell 16 configuring the flash memory chips 2-0 to 2-3 holds 1-bit data. By controlling the amount of electrons to be injected into the gate electrode 21 in a plurality of stages, data of 2 bits or more may be held.
[0250]
In the flash memory systems 1 and 39 according to the above embodiment, the erased block queue 30 is configured by assigning two queues to the flash memory chips 2-0 to 2-3, respectively. The number of queues assigned to each flash memory chip 2-0 to 2-3 is not limited to two, but may be other numbers, for example, one or eight.
[0251]
Furthermore, in the flash memory systems 1, 39, and 49 according to the above embodiments, a NAND flash memory chip is used as the flash memory chip 2, but the flash memory that can be controlled by the present invention is limited to the NAND type. It is also possible to control other types, for example, an AND type flash memory.
[0252]
In the present invention, the means does not necessarily mean a physical means, but includes cases where the functions of the means are realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.
[0253]
The present invention can be realized as a PC card based on a unified standard published by PCMCIA (Personal Computer Memory Card International Association). Furthermore, in recent years, with the development of high integration technology of semiconductor elements, more compact miniaturized memory cards such as “CompactFlash” proposed by CFA (CompactFlash Association) and “MMC (MultiMediaCard)” proposed by MultiMediaCardAssociation. The present invention can be applied to “Memory Stick” proposed by Sony Corporation and “SD Memory Card” proposed by Matsushita Electric Industrial Co., Ltd.
[0254]
【The invention's effect】
As described above, according to the present invention, when data write is requested from the host computer, even if some data is already stored in the block to which the data is to be written, the given data A memory controller capable of performing a series of processes required for writing data at a higher speed and a flash memory system including such a memory controller are provided.
[0255]
In addition, according to the present invention, when a data write is requested from the host computer, it is necessary to write the given data even if some data is already stored in the block to which the data is to be written. A flash memory control method capable of performing a series of processes at a higher speed is provided.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to a preferred embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically showing the structure of each flash memory cell 16 constituting the flash memory chips 2-0 to 2-3.
FIG. 3 is a cross-sectional view schematically showing a flash memory cell 16 in a write state.
FIG. 4 is a diagram schematically showing a structure of an address space of a flash memory chip 2-0.
5 is a schematic diagram showing a data structure of an address conversion table 27 stored in the SRAM work area 8. FIG.
6 is a schematic diagram showing a data structure of an erased block queue 28 stored in the SRAM work area 8. FIG.
7 is a schematic diagram showing a data structure of an internal variable 30 stored in the SRAM work area 8. FIG.
FIG. 8 is a flowchart for determining the type of write operation;
FIG. 9 is a flowchart showing a new writing operation.
FIG. 10 is a flowchart showing a partial transfer operation.
FIG. 11 is a schematic diagram showing a data storage state of a transfer source block and a transfer destination block in a partial transfer operation.
FIG. 12 is a flowchart showing additional write determination.
FIG. 13 is a schematic diagram showing a data storage state of a transfer source block and a transfer destination block in step S34.
FIG. 14 is a flowchart showing an additional writing operation.
FIG. 15 is a schematic diagram showing a data storage state of a transfer source block and a transfer destination block in an additional write operation.
FIG. 16 is a flowchart showing a completion operation.
FIG. 17 is a schematic diagram illustrating a data storage state of a transfer source block and a transfer destination block in a completion operation.
18 is a schematic diagram showing a data structure of an internal variable 40 stored in the SRAM work area 8. FIG.
FIG. 19 is a flowchart showing additional write determination.
FIG. 20 is a flowchart showing a second partial transfer operation.
FIG. 21 is a schematic diagram showing a data storage state of first to third blocks in a second partial transfer operation;
FIG. 22 is a schematic diagram showing data storage states of first to third blocks in steps S75 to S77.
FIG. 23 is a flowchart showing a second additional write operation.
FIG. 24 is a schematic diagram showing a data storage state of first to third blocks in a second additional write operation.
FIG. 25 is a schematic diagram showing a data storage state of first to third blocks in a second additional write operation.
FIG. 26 is a diagram illustrating an example of virtual block mapping;
FIG. 27 is a diagram showing a virtual page structure of the virtual block shown in FIG. 26;
28 is a schematic diagram showing a data structure of an address conversion table 57. FIG.
29 is a schematic diagram showing a data structure of an erased block queue 58 stored in the SRAM work area 8. FIG.
30 is a schematic diagram showing a data storage state of a transfer source block and a transfer destination block when data is instructed from the host computer 5 to the virtual page 4i + 1 of the virtual block #n. FIG.
[Explanation of symbols]
1 Flash memory system
2-0 to 2-3 flash memory chip
3 Controller
4 Connector
5 Host computer
6 Microprocessor
7 Host interface block
8 SRAM work area
9 buffers
10 Flash memory interface block
11 ECC block
12 Flash sequencer block
13-15 Bus
16 Flash memory cell
17 P-type semiconductor substrate
18 Source diffusion region
19 Drain diffusion region
20 Tunnel oxide film
21 Floating gate electrode
22 Insulating film
23 Control gate electrode
24 channels
25 User area
26 Redundant area
27 Address conversion table
28 Erased block queue
30 internal variables
31 Destination block address storage area
32 Transfer source block address storage area
33 Start page storage area
34 flags
39 Flash memory system
40 internal variables
41 First block address storage area
42 Second block address storage area
43 Third block address storage area
44 Second start page storage area
45 First start page storage area
46 First flag
47 Second flag
49 Flash memory system
50 Internal variables
57 Address conversion table
58 Erased Block Queue

Claims (13)

A memory controller for accessing a memory composed of a plurality of blocks,
A part of the data stored in the first block in response to an instruction to newly write new data to the logical address corresponding to the first block in which data is already stored First means for transferring to the same page of the second block;
Second means for writing the new data into the second block;
Third means for storing relationships between the second block and the first block,
A fourth means for determining whether or not the additional data can be additionally written to the second block in response to a new instruction to write additional data to the logical address. When,
In response to determining that the fourth means is additionally writable, transferring a portion of the data stored in the first block to the same page of the second block; Fifth means for writing the additional data into the second block;
Data stored in the same page of the first block in all empty pages in the second block in response to the determination that the fourth means cannot additionally write A sixth means for transferring
A seventh means for erasing the first block in response to data being written to all pages of the second block;
A memory controller comprising: The first means uses the same page of the second block as the data stored in the page immediately preceding the page corresponding to the page where the new data is to be stored from the first page of the first block. The memory controller according to claim 1, wherein the memory controller is configured to transfer to the memory controller. The third means further holds information about empty pages of the second block ;
The fourth means is configured to determine whether or not the additional data can be additionally written to the second block based on the information about the empty page. The memory controller according to claim 1 or 2. 4. The memory controller according to claim 3 , wherein the empty pages in the second block are continuous from the next page to the last page of the page in which the new data is written by the second means. . When the page in which the additional data in the second block is to be stored is not the empty page, the sixth means is stored in the same page of the first block as the empty page in the second block. 5. The method of claim 1 wherein the seventh means is configured to erase all the data stored in the first block after the data being transferred is transferred. The memory controller according to any one of the above. Further, when the page in which the additional data in the second block is to be stored is not the empty page, a part of the data stored in the second block is transferred to the same page in the third block. 8 means,
A ninth means for writing the additional data into the third block;
The third means is further configured to maintain a correspondence relationship between the second block and the third block.
The memory controller according to claim 1, wherein the memory controller is a memory controller. The memory controller according to claim 6, wherein the third means further holds information related to an empty page of the third block. And a tenth means for determining whether the page to which the additional data is written is the first page of the empty page group in the second block ;
In response to the determination that the tenth means determines that the write destination page is not the first page, the fifth means determines that the write-once data write destination is immediately before the first page of the empty page group. The data stored in the same page of the first block is transferred to each page corresponding to the page of
The memory controller according to claim 1, wherein the memory controller is a memory controller. A memory controller for accessing a memory composed of a plurality of blocks,
Means for classifying each block into a plurality of groups;
Means for forming a virtual block by virtually combining a plurality of blocks belonging to different groups;
Means for transferring a part of data stored in the predetermined block to another block in response to an instruction to newly write new data to the predetermined block constituting the virtual block When,
Means for writing the new data instructed to be newly written into the other block;
Means for storing relationships between the other blocks and the predetermined block,
In response to the fact that additional data is given after the new data and the writing of the additional data is instructed to the logical address corresponding to the predetermined block, the additional data is transferred to the other block. Means for determining whether or not the additional data can be additionally written;
In response to determining that the additional data can be additionally written to the other block, a part of the data stored in the predetermined block is transferred to the same page of the other block. And means for writing the additional data to the other block;
In response to determining that the additional data cannot be additionally written to the other block, all the empty pages in the other block are stored in the same page of the predetermined block. Means for transferring data,
Means for erasing the predetermined block in response to data being written to all pages of the other block;
A memory controller comprising: A flash memory system comprising: the memory controller according to any one of claims 1 to 9; and a flash memory including a plurality of blocks . The flash memory system according to claim 10, wherein the flash memory system is housed in the same casing. The flash memory system according to claim 11, wherein the housing has a card shape . In response to an instruction to newly write new data to a predetermined logical address, the block corresponding to the predetermined logical address in the address conversion table is changed from the first block to the second block. And steps to
Creating a variable indicating the correspondence between the first block and the second block;
Transferring a portion of the data stored in the first block to a second block;
Writing the new data to the second block;
Determining whether or not the additional data can be additionally written to the second block in response to an instruction to write new additional data to the predetermined logical address; ,
In response to determining that the additional data can be additionally written, a part of the data stored in the first block is transferred to the same page of the second block, and the additional data is written. Writing data into the second block;
Steps,
In response to determining that the additional data cannot be additionally written, transferring the data stored in the same page of the first block to all the empty pages in the second block. When,
Erasing the first block in response to data being written to all pages of the second block;
A method of controlling a flash memory, comprising:

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