JP3620235B2 - Liquid crystal display panel and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention belongs to the technical field of an active matrix driving type liquid crystal display panel driven by a TFT (thin film transistor) and a manufacturing method thereof, and in particular, a liquid crystal of a type provided with a black matrix below a TFT, used for a liquid crystal projector or the like. The present invention belongs to the technical field of display panels and manufacturing methods thereof.
[0002]
[Prior art]
Conventionally, in a liquid crystal display panel used as a light valve for this type of liquid crystal projector or the like, projection light is generally incident from the side of the counter substrate that is disposed to face the TFT array substrate with the liquid crystal layer interposed therebetween. Here, when the projection light is incident on a channel formation region composed of an a-Si (amorphous silicon) film or a p-Si (polysilicon) film of a TFT, a photocurrent is generated in this region due to a photoelectric conversion effect. As a result, the transistor characteristics of the TFT deteriorate. For this reason, a plurality of light shielding layers called black matrices are generally formed on the counter substrate at positions facing the respective TFTs. Such a black matrix is made of a metal material such as Cr (chromium) or a material such as resin black in which carbon is dispersed in a photoresist. In addition to shielding light from the a-Si film and p-Si film of the TFT described above. In addition, it has functions such as improving contrast and preventing color mixture of color materials.
[0003]
Further, in this type of liquid crystal display panel, a positive stagger type or coplanar type a-Si or p-Si TFT adopting a top gate structure (that is, a structure in which a gate electrode is provided above the channel on the TFT array substrate). When using, it is necessary to prevent a part of the projection light from entering the TFT channel from the TFT array substrate side as return light by the projection optical system in the liquid crystal projector.
[0004]
For this reason, in Japanese Patent Application Laid-Open No. 9-127497, Japanese Patent Publication No. 3-52611, Japanese Patent Application Laid-Open No. 3-125123, Japanese Patent Application Laid-Open No. 8-171101, etc., a TFT is formed on a TFT array substrate made of a quartz substrate or the like. A liquid crystal display panel is also proposed in which a black matrix is formed at an opposing position (that is, below the TFT). The black matrix thus formed is supposed to be able to shield the return light from the a-Si film and p-Si film of the TFT. In particular, according to this technique, in order to prevent the black matrix from being destroyed or melted by high temperature processing in the TFT forming process performed after the black matrix forming process on the TFT array substrate, It is made of a melting point metal.
[0005]
Further, according to such a conventional technique, a silicate such as NSG (non-doped silicate glass) is formed on the black matrix in order to electrically insulate the black matrix made of a refractory metal from the TFT formation region. An interlayer insulating layer made of glass or the like is provided. The interlayer insulating layer is used as a base, and a TFT is formed thereon by a high temperature process.
[0006]
[Problems to be solved by the invention]
However, the conventional techniques described above have the following problems. That is, first, in a configuration in which a TFT is formed through an interlayer insulating layer, which is a single layer of silicate glass or the like, on a black matrix for shielding return light made of a refractory metal, from the black matrix through the interlayer insulating layer. Contamination (contamination) to the TFT occurs, and contamination to the TFT also occurs from silicate glass such as NSG constituting the interlayer insulating layer. More specifically, a black matrix made of a refractory metal, an interlayer insulating layer made of NSG or the like is included during a high temperature process such as when forming a gate insulating film or forming a channel p-Si layer. Contamination to the TFT formation region occurs due to impurities such as carbon, hydrogen, moisture, or metal elements. For this reason, the transistor characteristics of the finally formed TFT are deteriorated.
[0007]
Furthermore, in the configuration in which the interlayer insulating layer is formed from a single layer such as silicate glass as described above, it is possible to obtain a sufficiently high insulating property while keeping the thickness of the interlayer insulating layer within a limited range, or to locally insulate the interlayer insulating layer. It is difficult to prevent the occurrence of low-quality parts.
[0008]
As described above, according to the conventional manufacturing technique described above, the formation of the light shielding film on the lower side of the TFT increases the contamination from the interlayer insulating layer and the light shielding layer, which are indispensable constituent elements. There is also a problem that the device defect rate increases due to an insulation failure in the interlayer insulating layer.
[0009]
The present invention has been made in view of the above-described problems. Contamination to a switching element such as a TFT is suppressed to a low level, and the light shielding performance against light such as return light from the lower side of the switching element is high. It is an object of the present invention to provide an active matrix driving type liquid crystal display panel having high switching characteristics of a switching element and a method of manufacturing the same.
[0010]
Of the present invention Claim 1 In order to solve the above problems, a liquid crystal display panel has a pair of first and second substrates, a liquid crystal sandwiched between the first and second substrates, and a matrix on the side of the first substrate facing the liquid crystals. Plural provided in the shape Painting Element electrodes, a plurality of switching elements provided on the first substrate at positions adjacent to the plurality of pixel electrodes, respectively, for controlling the switching of the plurality of pixel electrodes, and positions opposed to the plurality of switching elements, respectively. A light shielding layer made of a refractory metal provided between the first substrate and the plurality of switching elements, and at least two types of insulating layers provided between the light shielding layer and the plurality of switching elements. And with The at least two types of insulating layers include a first insulating layer made of silicate glass containing carbon and hydrogen impurities, and a second insulating layer made of a high-temperature silicon oxide film, and the second insulating layer is made of the first insulating layer. Located closer to the switching element than the layer It is characterized by that.
[0011]
Of the present invention Claim 1 According to the liquid crystal display panel, for example, W (tungsten), Ti (titanium), Cr (chromium), Ta (tantalum), Mo (molybdenum), Pd ( palladium A light shielding layer made of a refractory metal such as a refractory metal alone or a refractory metal silicide containing these (for example, WSi (tungsten silicide)) is provided at a position facing a switching element such as a TFT. Therefore, even if light such as return light enters the liquid crystal display panel from the first substrate side, this light can be prevented from entering the switching element.
[0012]
Here, at least two types of insulating layers are provided between the light shielding layer and the plurality of switching elements. These insulating layers are stacked, for example, and function as an interlayer insulating layer having a multilayer structure. For this reason, for example, SiO ₂ An interface always exists between different types of insulating layers, such as an insulating layer made of a Si film and an insulating layer made of an SiN film. If the interlayer insulating layer is composed of a single layer as in the prior art described above and such an interface does not exist, in the manufacturing process of the liquid crystal display panel, particularly in a high temperature process, the light shielding layer or the interlayer insulating layer Impurities such as carbon, hydrogen, moisture, and metal elements present in the layer appear in a switching element formation region such as a TFT on the interlayer insulating layer, and contaminate the switching element. However, in the present invention, some or most of these impurities are trapped at the interface between the two types of insulating layers, so that switching elements such as TFTs reduce contamination from the light-shielding layer and the insulating layer. Formed in the state.
[0013]
Furthermore, since at least two types of insulating layers are provided, the insulating property is ensured and more reliable than the case where the interlayer insulating layer is formed from a single layer as in the prior art in the manufacturing process of the liquid crystal display panel. Can be increased. In addition, combining various processes for forming insulating layers increases the flexibility of the manufacturing process and is necessary depending on the application and specifications. Insulation layer thickness It is also possible to efficiently produce an interlayer insulating layer having a high cost efficiency.
[0014]
As a result, the manufactured liquid crystal display panel has a high light shielding performance against light such as return light from the lower side of the switching element, and also has reduced contamination to the switching element and insulation failure in the insulating layer. Is reduced, and the switching characteristics of the switching element are greatly enhanced.
[0016]
Claim 1 According to the liquid crystal display panel described in 1), the first insulating layer has a high insulating property such as NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), and the like. SiO such as silicate glass ₂ It consists of a system membrane. The second insulating layer is High temperature silicon oxide film (HTO film) Consists of. Here, SiO such as silicate glass such as NSG ₂ The first insulating layer made of a system film contains impurities such as carbon and hydrogen, but is generally easy to form using a CVD method or the like. On the other hand, the second insulating layer made of the HTO film contains almost no impurities such as carbon and hydrogen, and has a lower quality and higher quality than the first insulating layer configured as described above.
[0017]
Here, in order to insulate the light shielding layer from the switching element such as TFT, the first and second insulating layers functioning as the interlayer insulating layer need to have a certain thickness, but the formation is compared as described above. A part or most of the necessary thickness is covered by the first insulating layer that is easy to handle. Since the second insulating layer is located closer to the switching element than the first insulating layer, in the manufacturing process, a part or most of the impurities contained in the first insulating layer is the same as that of the first insulating layer. The switching element is trapped at the interface existing between the second insulating layer and the switching element is thus formed on the high-quality HTO film (second insulating layer). For this reason, switching elements such as TFTs are formed in a state in which contamination from the light shielding layer and the insulating layer is reduced.
[0020]
Here, in order to insulate the light shielding layer from the switching element such as TFT, the first and second insulating layers functioning as the interlayer insulating layer need to have a certain thickness, but the formation is compared as described above. A part or most of the necessary thickness is covered by the second insulating layer that is easy to handle. Since the first insulating layer is located closer to the light shielding layer than the second insulating layer, in the manufacturing process, part or most of the impurities contained in the light shielding layer is the first insulating layer or the first insulating layer. The switching element is trapped at the interface existing between the insulating layer and the second insulating layer, and the switching element is thus formed on the second insulating layer where the contamination from the light shielding layer hardly reaches. For this reason, switching elements such as TFTs are formed in a state in which contamination from the light shielding layer and the insulating layer is reduced.
Claim 2 According to the liquid crystal display panel described in the above, since the light shielding layer is made of a refractory metal silicide, the thermal compatibility with the TFT array substrate containing silicon and the interlayer insulating layer is improved, and the high temperature environment and the normal temperature environment Even in the case where it is placed, the stress generated due to the difference in physical properties such as thermal expansion coefficient between the light shielding layer and the TFT array substrate or the interlayer insulating layer is relieved.
[0021]
Claims of the invention 3 The method for manufacturing a liquid crystal display panel according to claim 1, wherein the liquid crystal display panel is manufactured by sputtering using a refractory metal target on the first substrate, photolithography and etching. A step of forming the light shielding layer from a melting point metal, and a silicate glass containing the carbon and hydrogen impurities on the formed light shielding layer by any one of a CVD method, a plasma CVD method and a low pressure CVD method. Forming the first insulating layer, and forming the second insulating layer made of the high-temperature silicon oxide film on the formed first insulating layer by a low pressure CVD method. And
[0022]
Claims of the invention 3 According to the manufacturing method described in (1), the light shielding layer is formed from the refractory metal by sputtering, photolithography and etching using the refractory metal target. Next, a first insulating layer made of a silicate glass containing carbon and hydrogen impurities such as a highly insulating silicate glass film such as NSG is formed on the light shielding layer by a CVD method, a plasma CVD method or a low pressure CVD method. . Next, a second insulating layer made of a high temperature silicon oxide film (HTO film) is formed on the first insulating layer by a low pressure CVD method. Therefore, after the first insulating layer is formed, impurities contained in the first insulating layer are trapped at the interface existing between the first insulating layer and the second insulating layer. The switching element is formed on a high quality HTO film (second insulating layer).
[0025]
Such an operation and other advantages of the present invention will become apparent from the embodiments described below.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0027]
FIG. 1 is a cross-sectional view of a liquid crystal display panel according to an embodiment of the present invention. In FIG. 1, the scale of each layer and each member is different in order to make each layer and each member recognizable on the drawing. FIG. 2 is a plan view of various electrodes formed on the TFT array substrate 1 shown in FIG.
[0028]
In FIG. 1, a liquid crystal display panel 100 includes a TFT array substrate 1 that constitutes an example of a transparent first substrate, and a counter substrate 2 that constitutes an example of a transparent second substrate disposed opposite thereto. . The TFT array substrate 1 is made of, for example, a quartz substrate, and the counter substrate 2 is made of, for example, a glass substrate.
[0029]
As shown in FIG. 2, the TFT array substrate 1 is provided with a plurality of transparent pixel electrodes 11 in a matrix, and a predetermined alignment process such as a rubbing process is performed on the upper side as shown in FIG. An applied alignment film 12 is provided. The pixel electrode 11 is made of a transparent conductive thin film such as an ITO film (indium tin oxide film). The alignment film 12 is made of an organic thin film such as a polyimide thin film.
[0030]
On the other hand, a common electrode 21 is provided on the entire surface of the counter substrate 2, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the common electrode 21. The common electrode 21 is made of a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.
[0031]
As shown in FIGS. 1 and 2, the TFT array substrate 1 includes a plurality of TFTs 30 as an example of a switching element that controls switching of the plurality of pixel electrodes 11 at positions adjacent to the plurality of pixel electrodes 11, respectively. Is provided.
[0032]
The counter substrate 2 is further provided with a black matrix 23 in a predetermined region facing the TFT 30. Such a black matrix is made of a metal material such as Cr (chromium) or Ni (nickel), or a material such as resin black in which carbon or Ti (titanium) is dispersed in a photoresist. In addition to the light shielding to the (silicon) layer 32, it has functions such as improving contrast and preventing color mixture of color materials.
[0033]
Between the TFT array substrate 1 and the counter substrate 2 which are configured in this way and are arranged so that the pixel electrode 11 and the common electrode 21 face each other, a sealant 52 (see FIGS. 4 and 5) described later is used. Liquid crystal is sealed in the enclosed space, and the liquid crystal layer 50 is formed. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 12 and 22 in a state where an electric field from the pixel electrode 11 is not applied. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing agent 52 is an adhesive for bonding the two substrates 1 and 2 around them.
[0034]
Light shielding layers 3 made of, for example, WSi (tungsten silicide) are provided between the TFT array substrate 1 and the plurality of TFTs 30 at positions facing the TFTs 30 respectively. Further, a first interlayer insulating layer 41 is provided between the light shielding layer 3 and the plurality of TFTs 30. The first interlayer insulating layer 41 is provided to electrically insulate the p-Si layer 32 constituting the TFT 30 from the light shielding layer 3. Further, the first interlayer insulating layer 41 has a function as a base film for the TFT 30 by being formed on the entire surface of the TFT array substrate 1. That is, the TFT 30 has a function of preventing deterioration of the characteristics of the TFT 30 due to roughness during polishing of the surface of the TFT array substrate 1 and dirt remaining after cleaning.
[0035]
The light shielding layer 3 is made of a refractory metal silicide (for example, tungsten silicide WSi) containing at least one of Ti, Cr, W, Ta, Mo, and Pd. Thus, if it comprises refractory metal silicide, that is, if silicon is included in the material of the light-shielding layer 3, the thermal compatibility with the TFT array substrate 1 and the first interlayer insulating layer 41 containing silicon is improved. More specifically, even when placed in a high temperature environment and a normal temperature environment, there is a difference in physical properties such as thermal expansion coefficient between the light shielding layer 3 and the TFT array substrate 1 or the first interlayer insulating layer 41. The resulting stress is relieved.
[0036]
The light shielding layer 3 is grounded or connected to a constant potential source through a predetermined wiring through a contact hole (not shown). For this reason, changing the potential of the light shielding layer 3 does not adversely affect the switching characteristics of the TFT 30. However, the light shielding layer 3 may be electrically floating, or the light shielding layer 3 may be used as a wiring for a storage capacitor (see FIG. 3) described later.
[0037]
The first interlayer insulating layer 41 has a multilayer structure in which a first layer 41a and a second layer 41b as examples of two types of insulating layers are stacked.
[0038]
As a first preferred example of the first interlayer insulating layer 41 having a multilayer structure as described above, the first layer 41a is composed of NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG. SiO such as highly insulating silicate glass such as (boron phosphorus silicate glass) ₂ The second layer 41b is made of an HTO film (high temperature silicon oxide film). In this case, SiO such as silicate glass such as NSG ₂ The first layer 41a made of a system film contains impurities such as carbon and hydrogen, but is generally easy to form using a CVD method or the like as will be described later in the manufacturing process. On the other hand, the second layer 41b made of the HTO film contains almost no impurities such as carbon and hydrogen and has fewer impurities than the first layer 41a and is of high quality. In the first example of the first interlayer insulating layer 41, in order to insulate the light shielding layer 3 from the TFT 30, the first interlayer insulating layer 41 needs to have a certain thickness, but is relatively formed as described above. A part or most of the necessary thickness is covered by the easy first layer 41a. Since the second layer 41b is located closer to the TFT 30 than the first layer 41a (upper side in the figure), in the manufacturing process described later, the impurities contained in the first layer 41a are the same as the first layer 41a. It is trapped at the interface existing between the second layer 41b. The TFT 30 is formed on the second layer 41b made of the high-quality HTO film in this manner in a state where contamination from the light shielding layer 3 and the first interlayer insulating layer 41 is reduced.
[0039]
As a preferred second example of the first interlayer insulating layer 41, the first layer 41a is made of a SiN-based film such as a silicon nitride film, and the second layer 41b is made of SiO such as a highly insulating silicate glass such as NSG. ₂ It consists of a system membrane. In this case, the first layer 41a made of a SiN-based film has a higher ability to trap impurities included in the light shielding layer 3 made of a refractory metal such as WSi than the second layer 41b. In contrast, SiO ₂ The second layer 41b made of a system film can be easily formed as in the first example. In the second example of the first interlayer insulating layer 41, in order to insulate the light shielding layer 3 from the TFT 30, the first interlayer insulating layer 41 still needs a certain thickness, but the formation is compared as described above. The necessary second layer 41b covers a part or most of the necessary thickness. Since the first layer 41a is located closer to the light shielding layer 3 (lower side in the figure) than the second layer 41b, in the manufacturing process described later, impurities contained in the light shielding layer 3 are the first layer. 41a or the interface existing between the first layer 41a and the second layer 41b. The TFT 30 is formed on the second layer 41b where the contamination from the light shielding layer 3 hardly reaches in this way in a state where the contamination from the light shielding layer 3 and the first interlayer insulating layer 41 is reduced.
[0040]
In the first example or the second example of the first interlayer insulating layer 41 described above, assuming that the first interlayer insulating layer 41 is configured from a single layer as in the conventional technique described above, the first interlayer insulating layer is assumed. Since the interface between the first layer 41 a and the second layer 41 b does not exist in the layer 41, especially in the high temperature process in the manufacturing process of the liquid crystal display panel 100, the light shielding layer 3 or the first interlayer insulating layer 41. The existing impurities such as carbon, hydrogen, moisture, and metal elements appear in the TFT 30 forming region on the first interlayer insulating layer 41 and contaminate the TFT 30.
[0041]
Furthermore, since the first and second examples of the first interlayer insulating layer 41 have a multilayer structure in which the first layer 41a and the second layer 41b are laminated, respectively, they are composed of a single layer as in the prior art. For example, there is a low possibility of causing an insulation failure locally, and the reliability as an insulating layer is high. Furthermore, it is easy to improve insulation by a multilayer structure.
[0042]
As shown in FIG. 1, the TFT 30 includes a gate electrode 31 (scanning electrode), a p-Si layer 32 in which a channel is formed by an electric field from the gate electrode 31, and a gate that insulates the gate electrode 31 from the p-Si layer 32. An insulating layer 33, a source region 34 formed in the p-Si layer 32, a source electrode 35 (signal electrode), and a drain region 36 formed in the p-Si layer 32 are provided. A corresponding one of the plurality of pixel electrodes 11 is connected to the drain region 36. As will be described later, the source region 34 and the drain region 36 dope the p-Si layer 32 with a predetermined concentration of n-type or p-type dopant depending on whether an n-type or p-type channel is to be formed. It is formed by. An n-type channel TFT has an advantage of high operating speed, and a p-type channel TFT has an advantage that it is easy to form a p-type channel. The source electrode 35 (signal electrode) may be composed of a transparent conductive thin film such as an ITO film, like the pixel electrode 11, or may be composed of an opaque thin film such as a metal film such as Al or a metal silicide. . Further, a second interlayer insulating layer 42 in which a contact hole 37 leading to the source region 34 and a contact hole 38 leading to the drain region 36 are formed on the gate electrode 31, the gate insulating layer 33 and the first interlayer insulating layer 41, respectively. Is formed. A source electrode 35 (signal electrode) is electrically connected to the source region 34 through a contact hole 37 to the source region 34. Further, a third interlayer insulating layer 43 in which a contact hole 38 to the drain region 36 is formed is formed on the source electrode 35 (signal electrode) and the second insulating layer 42. The pixel electrode 11 is electrically connected to the drain region 36 through a contact hole 38 to the drain region 36. The pixel electrode 11 described above is provided on the upper surface of the third interlayer insulating layer 43 thus configured.
[0043]
Here, in general, in the p-Si layer 32 in which the channel is formed, a photoelectric current is generated due to the photoelectric conversion effect of p-Si when light is incident, and the transistor characteristics of the TFT 30 are deteriorated. In the embodiment, since the plurality of black matrices 23 are formed on the counter substrate 2 at positions facing the respective TFTs 30, it is possible to prevent incident light from directly entering the p-Si layer 32. Further, in addition to or instead of this, if the source electrode 35 (signal electrode) is formed of an opaque metal thin film such as Al so as to cover the gate electrode 31 from above, the p-Si layer together with the black matrix 23 or alone. Incident light (that is, light from above in FIG. 1) can be effectively prevented.
[0044]
As shown in the plan view of FIG. 2, the pixel electrodes 11 configured as described above are arranged in a matrix on the TFT array substrate 1, TFTs 30 are provided adjacent to the pixel electrodes 11, and A source electrode 35 (signal electrode) and a gate electrode 31 (scanning electrode) are provided along the vertical and horizontal boundaries of the pixel electrode 11, respectively. Note that FIG. 2 is for simplification of the matrix arrangement of the pixel electrodes 11 for the sake of explanation, and the actual electrodes are wired between and above the interlayer insulating layer via contact holes and the like. As shown in FIG. 1, it has a three-dimensionally more complicated configuration.
[0045]
Although not shown in FIG. 1, as shown in FIG. 3, the pixel electrodes 11 are each provided with a storage capacitor 70. More specifically, the storage capacitor 70 includes a p-Si layer 32 ′ formed by the same process as the p-Si layer 32, an insulating layer 33 ′ formed by the same process as the gate insulating layer 33, and the gate electrode 31. The storage capacitor electrode (capacitor line) 31 ′, the second and third interlayer insulating layers 42 and 43, and the second and third interlayer insulating layers 42 and 43 formed in the same process as the storage capacitor electrode 31 ′. It consists of a part of the pixel electrode 11 which opposes. Since the storage capacitor 70 is provided in this manner, high-detail display is possible even when the duty ratio is small. The storage capacitor electrode (capacitor line) 31 ′ is provided in parallel with the gate electrode (scanning electrode) 31 on the surface of the TFT array substrate 1 as shown in FIG. Further, as described above, the light shielding layer 3 can be used as the wiring of the storage capacitor 70.
[0046]
The overall configuration of the liquid crystal display panel 100 configured as described above will be described with reference to FIGS. 4 is a plan view of the TFT array substrate 1 as viewed from the side of the counter substrate 2 together with the components formed thereon, and FIG. 5 is a cross-sectional view of FIG. It is H 'sectional drawing.
[0047]
In FIG. 4, a sealing agent 52 is provided on the TFT array substrate 1 along its edge, and a peripheral parting 53 of the counter substrate 2 is defined in parallel with the inside thereof. An X-side drive driver circuit 101 and a mounting terminal 102 are provided along one side of the TFT array substrate 1 in a region outside the sealant 52, and a Y-side drive driver circuit 104 is adjacent to the one side. It is provided along two sides. Further, a plurality of wirings 105 are provided on the remaining side of the TFT array substrate 1. Further, silver points 106 made of a conductive agent for providing electrical continuity between the TFT array substrate 1 and the counter substrate 2 are provided at the four corners of the sealant 52. As shown in FIG. 5, the counter substrate 2 having substantially the same contour as the sealing agent 52 shown in FIG. 4 is fixed to the TFT array substrate 1 by the sealing agent 52.
[0048]
The X-side driving driver circuit 101 and the Y-driving driver circuit 104 are electrically connected to the source electrode 35 (signal electrode) and the gate electrode 31 (scanning electrode) by wiring. The X-side driver circuit 101 receives a display signal converted into a form that can be displayed immediately from a control circuit (not shown), and the Y-side driver circuit 104 sequentially pulses the gate electrodes 31 (scanning electrodes). The X-side driver circuit 101 sends a signal voltage corresponding to the display signal to the source electrode 35 (signal electrode) as the gate voltage is sent to. Particularly in this embodiment, since the TFT 30 is a p-Si (polysilicon) type TFT, the X-side driver circuit 101 and the Y-side driver circuit 104 are formed in the same process when the TFT 30 is formed. Is also possible and is advantageous in manufacturing.
[0049]
Instead of providing the X side driving driver circuit 101 and the Y side driving driver circuit 104 on the TFT array substrate 1, for example, the TFT LSI is mounted on the driving LSI mounted on the TAB (tape automated bonding substrate). You may make it connect electrically and mechanically via the anisotropic conductive film provided in the peripheral part of the board | substrate 1. FIG.
[0050]
Although not shown in FIGS. 1 to 5, for example, a TN (twisted nematic) mode, respectively, on the side on which the projection light of the counter substrate 2 enters and the side on which the projection light of the TFT array substrate 1 emits, Depending on the operation mode such as STN (super TN) mode, D-STN (double-STN) mode, and normally white mode / normally black mode, the polarizing film, retardation film, polarizing plate, etc. are in a predetermined direction. It is arranged with.
[0051]
Next, the operation of the present embodiment configured as described above will be described with reference to FIGS.
[0052]
First, the X-side driver circuit 101 that has received a display signal from the control circuit applies a signal voltage to the source electrode 35 (signal electrode) at a timing and magnitude according to the display signal, and in parallel with this, The Y-side driving driver circuit 104 sequentially applies a gate voltage to the electrodes 31 (scanning electrodes) at a predetermined timing, and the TFT 30 is driven. Thereby, in the TFT 30 to which the source voltage is applied when the gate voltage is turned on, a voltage is applied to the pixel electrode 11 through the source region 34 and the channel and drain region 36 formed in the p-Si layer 32. Is done. The voltage of the pixel electrode 11 is maintained by the storage capacitor 70 (see FIG. 3) for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied.
[0053]
When the voltage is applied to the pixel electrode 11 in this manner, the alignment state of the liquid crystal in the portion sandwiched between the pixel electrode 11 and the common electrode 21 in the liquid crystal layer 50 changes. In the normally black mode, incident light is allowed to pass through the liquid crystal portion when a voltage is applied, and the liquid crystal display as a whole. The panel 100 emits light having a contrast corresponding to the display signal.
[0054]
In particular, in this embodiment, since the light shielding layer 3 is provided below the TFT 30, the adverse effect due to the return light is reduced as described above, so that the transistor characteristics of the TFT 30 are improved. In other words, the liquid crystal display panel 100 can display a high-quality image with high contrast and good color.
[0055]
Since the liquid crystal display panel 100 is configured as described above, in addition to the high light shielding performance against the return light from the lower side of the TFT 30, the contamination with respect to the TFT 30 is reduced and the first interlayer insulating layer 41. Insulation failure is reduced, and the transistor characteristics of the TFT 30 are very high. In addition, since the liquid crystal display panel 100 is manufactured by a manufacturing process as will be described later, the occurrence of thermal distortion between the layers due to the provision of the light shielding layer 3 is also reduced. Device defects such as peeling in the layers and cracks in the light shielding layer 3 that cause a reduction in light shielding properties against return light are reduced.
[0056]
Next, FIGS. 6 and 7 show how the transistor characteristics of the TFT 30 are improved by the structure in which the first interlayer insulating layer 41 has the multilayer structure including the first layer 41a and the second layer 41b. Refer to and add consideration. FIG. 6 shows the result of the transistor characteristic test for the liquid crystal display panel 100 shown in FIG. On the other hand, FIG. 7 shows the result of the transistor characteristic test for the comparative example having the configuration in which the first interlayer insulating layer 41 is formed of a single layer of NSG in the configuration of the liquid crystal display panel 100 shown in FIG. 6 and 7, the horizontal axis represents the gate voltage applied to the gate electrode, and the vertical axis represents the drain current flowing at that time. In addition, test results are shown for two states of 15V and 4V as source / drain voltages.
[0057]
Comparing FIG. 6 and FIG. 7, the present embodiment in which the first interlayer insulating layer 41 has a multilayer structure improves the switching characteristics of the transistor far more than the case where the first interlayer insulating layer 41 has a single layer structure. You can see that.
[0058]
In the case of the comparative example shown in FIG. 7 as well, the switching characteristics of the TFT are improved as compared with the example in which the light-shielding layer 3 is not provided and the influence of the return light is received as it is.
[0059]
Next, a manufacturing process of the liquid crystal display panel 100 will be described with reference to FIGS.
[0060]
First, as shown in step (1) in FIG. 8, a TFT array substrate 1 such as a quartz substrate or hard glass is prepared. Where preferably N ₂ (Turn in an inert gas atmosphere such as (nitrogen) and a high temperature of about 1000 ° C. to remove impurities such as carbon and hydrogen in the TFT array substrate 1 and to cause distortion in the TFT array substrate 1 in a high-temperature process to be performed later. Reduce. A light shielding film is formed on the entire surface of the TFT array substrate 1 thus treated by sputtering using a WSi target. Subsequently, a mask corresponding to the pattern of the light-shielding layer 3 is formed on the formed light-shielding film by photolithography, and for example, SF is applied to the light-shielding film through the mask. ₆ / CF ₄ / O ₂ Etching such as chemical dry etching using is performed to leave the light shielding film formed on the entire surface of the substrate only in the region where the TFT 30 is to be formed, thereby forming the light shielding layer 3.
[0061]
Particularly in this manufacturing process, the thermal compatibility between the light-shielding layer 3 made of WSi, which is a refractory metal silicide containing Si, and the TFT array substrate 1 made of a quartz substrate containing Si, etc. is good. This occurs due to a difference in physical properties such as a coefficient of thermal expansion between the light shielding layer 3 and the TFT array substrate 1 when placed in a high temperature environment and a room temperature environment as compared with the case where the substrate 3 is formed. Stress to be reduced.
[0062]
The thickness of the light shielding layer 3 is, for example, 1000 mm or more and 3000 mm or less. By setting the thickness of the light-shielding layer 3 to 1000 mm or more, the characteristics of the TFT 30 are not deteriorated even when return light is incident on the liquid crystal display panel 100 from the TFT array 1 side with a light-shielding rate (transmittance) of 1% or less. Sufficient light shielding properties can be obtained. On the other hand, by setting the thickness of the light shielding layer 3 to 3000 mm or less, the planarization of the upper surface of the light shielding layer 3 on which the first interlayer insulating layer 41 is formed is promoted, and the thickness of the light shielding layer 3 is related to the thickness. Thermal stress can be prevented from becoming excessively large. Further, the thickness of the light shielding layer 3 is more preferably about 1500 to 2500 mm. Within this range, good light-shielding properties can be obtained, and there is almost no problem in level difference in practical use.
[0063]
Furthermore, when performing the sputtering process described above, it is preferable to keep the temperature of the TFT transistor substrate 1 at about 200 ° C. or higher. When sputtering is performed in this way, the generation of thermal stress related to the light shielding layer 3 is further reduced without substantially increasing the transmittance of the light shielding layer 3 (that is, without substantially reducing the light shielding property). The advantage that can be obtained.
[0064]
The light shielding layer 3 is formed so as to cover at least the channel formation region, the source region 34 and the drain region 36 in the p-Si layer 32 of the TFT 30 when viewed from the back surface of the TFT array substrate 1.
[0065]
Next, as shown in steps (2A) and (2B) in FIG. 8, a first interlayer insulating layer 41 having a multilayer structure is formed by laminating the first layer 41a and the second layer 41b.
[0066]
First, as described above, the first layer 41a is made of SiO such as highly insulating silicate glass such as NSG. ₂ A process of forming the first interlayer insulating layer 41 in the case of the first example made of a system film and the second layer 41b made of an HTO film will be described.
[0067]
In the case of this first example, as shown in step (2A) of FIG. 8, on the light shielding layer 3, for example, by a high temperature process of about 680 ° C. by atmospheric pressure or low pressure CVD method, plasma CVD method, etc. Using TEOS (Tetra-Ethyl-Ortho-silicate) gas, TEB (Tetra-ethyl-boatate) gas, TMOP (Tetra-methyl-oxy-phosphate) gas, etc., NSG, PSG, BSG, BPSG, etc. SiO such as insulating silicate glass film ₂ A first layer 41a made of a system film is formed.
[0068]
In the case of this first example, as shown in step (2B) of FIG. 8, a second layer 41b made of an HTO film is formed on the first layer 41a by a low pressure CVD method. The HTO film thus formed is a high quality film that hardly contains impurities such as carbon and hydrogen. Here, the thickness of the first layer 41a is preferably about 8000 mm. With such a thickness, the first layer 41a that can form a considerable part of the thickness of about 10000 mm necessary for the first interlayer insulating layer 41 as a whole to insulate the light shielding layer 3 from the TFT 30 can be covered by the first layer 41a. This is because, on the contrary, even if it is thicker than this, there are problems such as a small difference in actual profit and a difference in level. On the other hand, the thickness of the second layer 41b is preferably about 2000 to 3000 mm. This is because a thickness of this level can sufficiently exhibit the function of trapping impurities from the light shielding layer 3 and the first layer 41a in practice.
[0069]
In the case of this first example, the second layer 41b is formed on the first layer 41a, so that impurities contained in the light shielding layer 3, the first layer 41a, etc. are removed from the first layer 41a and the second layer 41b. So that the p-Si layer 32 and the like of the TFT 30 are not contaminated by impurities from the light shielding layer 3, the first layer 41a, etc., especially during a high temperature process for forming the later TFT 30. To do. As described above, in the first example, the TFT 30 is formed on the second layer 41b made of a high-quality HTO film in a state in which contamination from the light shielding layer 3 and the first interlayer insulating layer 41 is reduced. It becomes possible.
[0070]
Next, as described above, the first layer 41a is formed of a SiN-based film such as a silicon nitride film, and the second layer 41b is formed of SiO such as highly insulating silicate glass such as NSG. ₂ A process of forming the first interlayer insulating layer 41 in the case of the second example made of a system film will be described.
[0071]
In the case of this second example, as shown in step (2A) of FIG. 8, a SiN film such as a silicon nitride film is formed on the light shielding layer 3 by a CVD method, a plasma CVD method or a low pressure CVD method. First layer 41a is formed. The first layer 41a made of a SiN-based film formed in this way has a higher ability to trap impurities contained in the light shielding layer 3 made of a refractory metal such as WSi than the second layer 41b.
[0072]
In the case of this second example, as shown in step (2B) of FIG. 8, on the first layer 41a, for example, by a high temperature process of about 680 ° C. by atmospheric pressure or low pressure CVD method, plasma CVD method or the like. , SiO, such as highly insulating silicate glass films such as NSG, PSG, BSG, BPSG using TEOS gas, TEB gas, TMOP gas, etc. ₂ A first layer 41a made of a system film is formed. Here, the layer thickness of the first layer 41a is preferably about 2000 to 3000 mm in order to sufficiently exhibit the function of trapping impurities from the light shielding layer 3 made of WSi or the like. On the other hand, the thickness of the second layer 41b is preferably about 8000 mm. With such a thickness, the first layer 41a that can form a considerable part of the thickness of about 10000 mm necessary for the first interlayer insulating layer 41 as a whole to insulate the light shielding layer 3 from the TFT 30 can be covered by the first layer 41a. Because.
[0073]
In the case of this second example, by forming the second layer 41b on the first layer 41a, the impurities contained in the light shielding layer 3, the second layer 41b, etc., are separated from the first layer 41a and the first layer 41a. The p-Si layer 32 of the TFT 30 is trapped at the interface existing between the second layer 41b and the impurities of the light shielding layer 3, the second layer 41b, etc., particularly during the high temperature process for forming the TFT 30 later. Avoid contamination. As described above, in the second example, the TFT 30 is placed on the second layer 41b where the contamination from the light shielding layer 3 hardly reaches and the contamination from the light shielding layer 3 and the first interlayer insulating layer 41 is reduced. It becomes possible to form.
[0074]
Further, the first interlayer insulating layer 41 formed to have a multilayer structure in this manner is overlaid by spin coating SOG (spin-on glass: spun glass) or performing CMP (Chemical Mechanical Polishing) treatment. A flat film may be formed. In this way, if the upper surface of the first interlayer insulating layer 41 is planarized by spin coating or CMP, an advantage that the TFT 30 can be easily formed on the upper side later is obtained.
[0075]
Note that the first layer 41a and the second layer 41b may be annealed at about 900 ° C. to further prevent contamination and planarize.
[0076]
As described above, according to the step (2A) and the step (2B) shown in FIG. 8, the first layer 41a and the second layer 41b are stacked to form a multilayer structure, thereby minimizing the contamination on the TFT 30. As compared with the case where the first interlayer insulating layer 41 is formed from a single layer as in the prior art, the insulating properties of the first interlayer insulating layer 41 are limited under the limited layer thickness conditions and manufacturing temperature conditions. Can be reliably increased with high reliability. In addition, by combining the process of forming the first layer 41a and the second layer 41b from various materials, the flexibility of the manufacturing process can be increased, and the first insulating layer and the layer thickness that are necessary depending on applications and specifications can be obtained. It is also possible to efficiently form the one interlayer insulating layer 41 with high economic efficiency.
[0077]
Next, as shown in step (3) of FIG. 8, the flow rate is about 400 to 600 cc / min on the first interlayer insulating layer 41 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C. An a-Si (amorphous silicon) film is formed by low pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like. Thereafter, annealing is performed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that a p-Si (polysilicon) film has a thickness of about 500 to 2000 mm. Solid phase growth is performed to a thickness, preferably about 1000 mm. At this time, when an n-channel TFT 30 is formed, a dopant of a group V element such as Sb (antimony), As (arsenic), or P (phosphorus) is slightly doped by ion implantation or the like. When the TFT 30 is a p-channel type, a dopant of a group III element such as Al (aluminum), B (boron), Ga (gallium), and In (indium) is slightly doped by ion implantation or the like. Note that the p-Si film may be directly formed by a low pressure CVD method or the like without passing through the a-Si film. Alternatively, a p-Si film may be formed by implanting silicon ions into a p-Si film deposited by a low pressure CVD method or the like to make it amorphous (amorphized) and then recrystallizing it by annealing or the like. .
[0078]
Next, as shown in step (4) of FIG. 8, the p-Si layer 32 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably about 1000 ° C., so that a relatively thin thickness of about 300 mm is obtained. The thermal oxide film is formed. Further, a high-temperature silicon oxide film (HTO film) or nitride film is deposited to a relatively thin thickness of about 500 mm by a low pressure CVD method or the like to form a gate insulating layer 33 having a multilayer structure. As a result, the p-Si layer 32 has a thickness of about 300 to 1500 mm, preferably about 350 to 450 mm, and the gate insulating layer 33 has a thickness of about 200 to 1500 mm, preferably Is about 300 mm thick. By shortening the high-temperature thermal oxidation time in this way, it is possible to prevent warping due to heat, particularly when using a large wafer of about 8 inches. However, the gate insulating layer 33 having a single layer structure may be formed only by thermally oxidizing the p-Si layer 32.
[0079]
Next, as shown in step (5) of FIG. 8, after depositing p-Si on the p-Si layer 32 through a gate insulating layer 33 by a low pressure CVD method or the like, a photolithography process using a gate mask. The gate electrode 31 (scanning electrode) is formed by an etching process or the like.
[0080]
However, the gate electrode 31 (scanning electrode) may be formed from a metal film such as Al or a metal silicide film instead of the p-Si layer, or the metal film or metal silicide film and the p-Si film may be formed. You may combine and form in multiple layers. In this case, if the gate electrode 31 (scanning electrode) is arranged as a light-shielding film corresponding to a part or all of the region covered by the black matrix 23, the black matrix 23 can be prevented by the light-shielding property of the metal film or the metal silicide film. It is also possible to omit some or all of the parts. In this case, in particular, there is an advantage that it is possible to prevent the pixel aperture ratio from being lowered due to the bonding deviation between the counter substrate 2 and the TFT array substrate 1.
[0081]
Next, when the TFT 30 is an n-channel TFT having an LDD (Lightly Doped Drain Structure) structure as shown in step (6) of FIG. 9, first, the source region 34 and the p-type p-Si layer 32 are formed on the p-type p-Si layer 32. In order to form a lightly doped region constituting a part of the drain region 36 adjacent to the channel side, the gate electrode 31 is used as a diffusion mask, and a dopant of a group V element such as P is formed at a low concentration (for example, P Ion 1-3 × 10 ¹³ / Cm ² Then, after a resist layer is formed on the gate electrode 31 with a mask wider than the gate electrode 31, a dopant of a group V element such as P is also formed at a high concentration (for example, 1 to 3 × 10 P ions ¹⁵ / Cm ² Dope). When the TFT 30 is a p-channel type, the n-type p-Si layer 32 is doped with a group III element dopant such as B in order to form the source region 34 and the drain region 36. When the LDD structure is used as described above, there is an advantage that the short channel effect can be reduced. In addition, it is not necessary to dope by dividing into two steps of low concentration and high concentration. For example, a TFT having an offset structure may be used without performing low-concentration doping, or a self-aligned TFT may be used by an ion implantation technique using P ions, B ions, or the like using the gate electrode 31 as a mask.
[0082]
In parallel with these steps, an X-side driving driver circuit 101 and a Y-side driving driver circuit 104 having a CMOS (complementary MOS) structure composed of an n-channel p-Si TFT and a p-channel p-Si TFT are provided. It is formed on the periphery of the TFT array substrate 1. Thus, since the TFT 30 is a p-Si TFT, the X-side driver circuit 101 and the Y-side driver circuit 104 can be formed in the same process when the TFT 30 is formed, which is advantageous in manufacturing.
[0083]
Next, as shown in step (7) of FIG. 9, NSG, PSG, BSG, BPSG, etc. using, for example, atmospheric pressure or reduced pressure CVD method or TEOS gas so as to cover the gate electrode 31 (scanning electrode). A second interlayer insulating layer 42 made of a silicate glass film, a nitride film, a silicon oxide film or the like is formed. The thickness of the second interlayer insulating layer 42 is preferably about 5000 to 15000 mm. Then, an annealing process at about 1000 ° C. is performed for about 20 minutes to activate the source region 34 and the drain region 36, and then the contact hole 37 for the source electrode 31 (signal electrode) is formed by reactive etching, reactive ion beam. It is formed by dry etching such as etching. At this time, opening the contact hole 37 by anisotropic etching such as reactive etching or reactive ion beam etching has an advantage that the opening shape can be made substantially the same as the mask shape. However, if the dry etching and the wet etching are combined and opened, the contact hole 37 can be tapered, so that an advantage of preventing disconnection at the time of wiring connection can be obtained. A contact hole for connecting the gate electrode 31 (scanning electrode) to a wiring (not shown) is also opened in the second interlayer insulating layer 42 by the same process as the contact hole 37.
[0084]
Next, as shown in step (8) of FIG. 9, a low resistance metal such as Al or metal silicide is deposited on the second interlayer insulating layer 42 to a thickness of about 1000 to 5000 mm by sputtering or the like. Further, the source electrode 35 (signal electrode) is formed by a photolithography process, a wet etching process, or the like.
[0085]
In this case, if the source electrode 35 (signal electrode) is disposed as a light-shielding film corresponding to a part or all of the region covered by the black matrix 23, the black matrix can be obtained due to the light-shielding property of a metal film such as Al or a metal silicide film. It is also possible to omit part or all of 23. In this case, in particular, there is an advantage that it is possible to prevent the pixel aperture ratio from being lowered due to the bonding deviation between the counter substrate 2 and the TFT array substrate 1.
[0086]
Next, as shown in step (9) of FIG. 9, NSG, PSG, BSG, BPSG is used to cover the source electrode 35 (signal electrode) using, for example, atmospheric pressure or reduced pressure CVD method, TEOS gas, or the like. A third interlayer insulating layer 43 made of a silicate glass film such as a nitride film or a silicon oxide film is formed. The layer thickness of the third interlayer insulating layer 43 is preferably about 5000 to 15000 mm. Alternatively, a flat film may be formed by spin coating an organic film or SOG (spin-on glass) instead of or in addition to such a silicate glass film, or by performing a CMP process.
[0087]
Further, a contact hole 38 for electrically connecting the pixel electrode 11 and the drain region 36 is formed by dry etching such as reactive etching or reactive ion beam etching. At this time, by opening the contact hole 38 by anisotropic etching such as reactive etching or reactive ion beam etching, there is an advantage that the opening shape can be made substantially the same as the mask shape. However, if the dry etching and the wet etching are combined and opened, the contact hole 38 can be tapered, so that there is an advantage that disconnection at the time of wiring connection can be prevented.
[0088]
Next, as shown in step (10) of FIG. 9, a transparent conductive thin film such as an ITO film is deposited on the third interlayer insulating layer 43 to a thickness of about 500 to 2000 mm by sputtering or the like. Further, the pixel electrode 11 is formed by a photolithography process, a wet etching process, or the like. When the liquid crystal display panel 100 is used in a reflective liquid crystal display device, the pixel electrode 11 may be formed from an opaque material having a high reflectance such as Al.
[0089]
Subsequently, after applying a polyimide-based alignment film coating solution on the pixel electrode 11, a rubbing process is performed in a predetermined direction so as to have a predetermined pretilt angle, and the alignment film 12 shown in FIG. Is formed.
[0090]
On the other hand, for the counter substrate 2 shown in FIG. 1, a glass substrate or the like is first prepared, on which a black matrix 23 is sputtered, for example, with metal chrome, at a position corresponding to each of the plurality of TFTs 30. It is formed through an etching process. The black matrix 23 may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist in addition to a metal material such as Cr or Ni. Thereafter, the common electrode 21 is formed by depositing a transparent conductive thin film such as ITO on the entire surface of the counter substrate 2 to a thickness of about 500 to 2000 mm by sputtering or the like. Further, the alignment film 22 is formed by applying a polyimide-based alignment film coating solution over the entire surface of the common electrode 21 and then performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle.
[0091]
Finally, the TFT array substrate 1 and the counter substrate 2 on which the respective layers are formed as described above are bonded to each other with a sealant 52 so that the alignment films 12 and 22 face each other, and a space between the two substrates is obtained by vacuum suction or the like. Further, for example, a liquid crystal formed by mixing a plurality of types of nematic liquid crystals is sucked to form a liquid crystal layer 50 having a predetermined thickness.
[0092]
For the storage capacitor 70 shown in FIG. 3, a p-Si layer 32 ′ is formed on the first interlayer insulating layer 41 by the same process as the p-Si layer 32 described above, and an insulating layer 33 ′ is formed thereon. The gate insulating layer 33 may be formed by the same process, and a storage capacitor electrode (capacitor line) 31 ′ may be formed thereon by the same process as the gate electrode 31.
[0093]
Through the above manufacturing process, the liquid crystal display panel 100 shown in FIG. 1 is completed.
[0094]
As a result, according to the present manufacturing process, the liquid crystal display panel 100 capable of displaying a high-quality image with high contrast and good color can be manufactured relatively easily.
[0095]
In the present embodiment described above, two specific examples are given for the first layer 41a and the second layer 41b having a multilayer structure of the first interlayer insulating layer 41. However, the present embodiment For example, a SiN film, SiO 2 on the light shielding layer 3 is not limited thereto. ₂ It is also possible to constitute the first interlayer insulating layer 41 having a three-layer structure by laminating the system film and the HTO film in this order. It is also possible to form the first interlayer insulating layer 41 having a two-layer structure made of a plurality of different types of NSGs and the like by performing the CVD method at different deposition temperatures. Furthermore, the first layer 41 a of the first interlayer insulating layer 41 can be formed by anodizing the surface of WSi or the like constituting the light shielding layer 3.
[0096]
Since the liquid crystal display panel 100 described above is applied to a color liquid crystal projector, the three liquid crystal display panels 100 are used as RGB light valves, and each panel is connected to a dichroic mirror for RGB color separation. The decomposed light of each color is incident as incident light. Therefore, in each embodiment, the counter substrate 2 is not provided with a color filter. However, in the liquid crystal display panel 100, an RGB color filter may be formed on the counter substrate 2 together with its protective film in a predetermined region facing the pixel electrode 11 where the black matrix 23 is not formed. In this way, the liquid crystal display panel of the present embodiment can be applied to a color liquid crystal display device such as a direct-view type or a reflective type color liquid crystal television other than the liquid crystal projector.
[0097]
In the liquid crystal display panel 100, the incident light is incident from the counter substrate 2 side as in the conventional case. However, since the light shielding layer 3 exists, the incident light is incident from the TFT array substrate 1 side, and the counter substrate 2 You may make it radiate | emit from the side of this. That is, even when the liquid crystal display panel 100 is attached to the liquid crystal projector in this way, it is possible to prevent light from entering the p-Si layer 32 for channel formation and display a high-quality image. .
[0098]
In the liquid crystal display panel 100, a planarization film may be further applied on the third interlayer insulating layer 43 by spin coating or the like in order to suppress poor alignment of liquid crystal molecules on the TFT array substrate 1 side, or by CMP processing. May be applied.
[0099]
The switching element of the liquid crystal display panel 100 has been described as a normal staggered type or coplanar type p-Si TFT. However, it is possible to return to other types of TFTs such as an inverted staggered type TFT or an a-Si TFT. Various forms of application are possible under the problem of preventing light from entering the semiconductor layer for channel formation.
[0100]
Further, in the liquid crystal display panel 100, the liquid crystal layer 50 is made of nematic liquid crystal as an example. However, if polymer dispersed liquid crystal in which liquid crystal is dispersed as fine particles in a polymer is used, the alignment films 12 and 22, and The aforementioned polarizing film, polarizing plate and the like are not necessary, and the advantages of high luminance and low power consumption of the liquid crystal display panel due to the increased light utilization efficiency can be obtained. Further, by forming the pixel electrode 11 from a metal film having a high reflectance such as Al, when the liquid crystal display panel 100 is applied to a reflective liquid crystal display device, the liquid crystal molecules are substantially vertically aligned in the state where no voltage is applied. Also, SH (super homeotropic) type liquid crystal may be used. Furthermore, in the liquid crystal display panel 100, the common electrode 21 is provided on the counter substrate 2 side so as to apply an electric field (longitudinal electric field) perpendicular to the liquid crystal layer 50, but an electric field parallel to the liquid crystal layer 50 ( The pixel electrode 11 is composed of a pair of electrodes for generating a horizontal electric field so as to apply a horizontal electric field (that is, the electrode for generating a vertical electric field is not provided on the side of the counter substrate 2). It is also possible to provide a lateral electric field generating electrode on the side. Using a horizontal electric field in this way is more advantageous in widening the viewing angle than using a vertical electric field. In addition, the present embodiment can be applied to various liquid crystal materials (liquid crystal phases), operation modes, liquid crystal alignments, driving methods, and the like.
[0101]
【The invention's effect】
In the present invention According to the liquid crystal display panel described, the light shielding layer made of a refractory metal is provided between the first substrate and the plurality of switching elements, and at least between the light shielding layer and the plurality of switching elements. Since two types of insulating layers are provided, in addition to high light shielding performance against light such as return light from the lower side of the switching element, contamination to the switching element is reduced and insulation failure in the insulating layer is reduced. As a result, the switching characteristics of the switching element can be greatly enhanced. Furthermore, the product defect rate in manufacturing the liquid crystal display panel can be reduced, and the yield can be improved.
[0102]
The first insulating layer is made of silicate glass containing carbon and hydrogen impurities, and the second insulating layer is a high-temperature silicon oxide film. Since the second insulating layer is located closer to the switching element than the first insulating layer, a switching element such as a TFT can be formed in a state in which contamination from the light shielding layer and the insulating layer is reduced. Therefore, the switching characteristics and light shielding properties of the switching element can be greatly enhanced.
[0103]
According to the liquid crystal display panel of claim 2, since the light shielding layer is made of refractory metal silicide, the thermal compatibility with the TFT array substrate containing silicon and the interlayer insulating layer is improved, and the high temperature environment Even when placed in a room temperature environment, stress generated due to a difference in physical properties such as a coefficient of thermal expansion between the light shielding layer and the TFT array substrate or the interlayer insulating layer is relieved.
[0104]
According to the manufacturing method of claim 3, impurities contained in the first insulating layer are trapped at an interface existing between the first insulating layer and the second insulating layer, and a switching element such as a TFT is provided with high quality. The HTO film (second insulating layer) can be formed with reduced contamination from the light shielding layer and the insulating layer.
[0105]
According to the manufacturing method of claim 4, since the light shielding layer is made of refractory metal silicide, the thermal compatibility with the TFT array substrate and the interlayer insulating layer containing silicon is improved, and the high temperature environment Even when placed in a room temperature environment, the stress generated due to the difference in physical properties such as thermal expansion coefficient between the light shielding layer and the TFT array substrate or the interlayer insulating layer is relieved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration of a liquid crystal display panel according to an embodiment.
FIG. 2 is a plan view of a TFT array substrate constituting the liquid crystal display panel of FIG.
3 is a cross-sectional view of a storage capacitor that constitutes the liquid crystal display panel of FIG. 1;
4 is a plan view showing an overall configuration of the liquid crystal display panel of FIG. 1. FIG.
5 is a cross-sectional view showing an overall configuration of the liquid crystal display panel of FIG. 1. FIG.
FIG. 6 is a characteristic diagram showing characteristics of TFTs provided in the liquid crystal display panel of the present embodiment.
FIG. 7 is a characteristic diagram showing characteristics of TFTs provided in a liquid crystal display panel as a comparative example.
FIG. 8 is a process diagram (part 1) illustrating a manufacturing process of the liquid crystal display panel of FIG. 1 in order.
FIG. 9 is a process diagram (part 2) illustrating the manufacturing process of the liquid crystal display panel of FIG. 1 in order.
[Explanation of symbols]
1 ... TFT array substrate
2 ... Counter substrate
3 ... Light-shielding layer
11: Pixel electrode
12 ... Alignment film
21 ... Common electrode
22 ... Alignment film
23 ... Black matrix
30 ... TFT
31 ... Gate electrode
32 ... p-Si layer
33 ... Gate insulating layer
34 ... Source area
35 ... Source electrode (signal electrode)
36 ... Drain region
37, 38 ... contact holes
41. First interlayer insulating layer
41a: first layer of first interlayer insulating layer
41b ... the second layer of the first interlayer insulating layer
42. Second interlayer insulating layer
43 ... Third interlayer insulating layer
50 ... Liquid crystal layer
52 ... Sealant
70 ... Storage capacity
100 ... Liquid crystal display panel
101... X-side driver circuit
102 ... Mounting terminal
104... Y-side driver circuit

Claims (4)

A pair of first and second substrates;
Liquid crystal sandwiched between the first and second substrates;
A plurality of pixel electrodes provided in a matrix on the side of the first substrate facing the liquid crystal;
A plurality of switching elements provided on the first substrate at positions adjacent to the plurality of pixel electrodes, respectively, for controlling the switching of the plurality of pixel electrodes;
A light-shielding layer containing a refractory metal provided between the first substrate and the plurality of switching elements at positions facing the plurality of switching elements, respectively.
Comprising at least two kinds of insulating layers provided between the light shielding layer and the plurality of switching elements;
The at least two kinds of insulating layers include a first insulating layer made of silicate glass containing carbon and hydrogen impurities, and a second insulating layer made of a high-temperature silicon oxide film,
The liquid crystal display panel, wherein the second insulating layer is located closer to the switching element than the first insulating layer. The liquid crystal display panel according to claim 1 , wherein the light shielding layer is made of a refractory metal silicide. It is a manufacturing method of the liquid crystal display panel according to claim 1,
Forming the light shielding layer containing the refractory metal on the first substrate by sputtering using a refractory metal target and photolithography and etching;
Forming the first insulating layer made of silicate glass containing impurities of carbon and hydrogen on the formed light shielding layer by any one of CVD, plasma CVD, and reduced pressure CVD;
Forming a second insulating layer made of the high-temperature silicon oxide film on the formed first insulating layer by a low pressure CVD method. 4. The method for manufacturing a liquid crystal display panel according to claim 3 , wherein the light shielding layer is made of a refractory metal silicide.

Images