JP3618869B2 - Signal generating apparatus and method, and image processing apparatus using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal generation apparatus and method and an image processing apparatus using the signal generation apparatus. For example, the present invention relates to a signal generation apparatus and method for generating a predetermined signal in accordance with an input clock signal, and an image processing apparatus using the signal generation apparatus. Is.
[0002]
[Prior art]
FIG. 1 is a block diagram showing a configuration example of a high-speed pulse width modulation (PWM) circuit using a triangular wave signal, and has a frequency twice the output PWM signal frequency in consideration of a clock signal in which a clock duty is not secured. The clock signal 2SK is frequency-divided by the frequency dividing circuit 10 to obtain a clock signal SK with a secured clock duty. When this high-speed PWM circuit is used for laser beam control in a laser beam printer (LBP) and a digital copying machine, the clock signals SK and 2SK are synchronized clock signals synchronized with a synchronization trigger signal such as a horizontal synchronization signal.
[0003]
The clock signal SK is input to the level conversion circuit 11 and its signal level is amplified. The output of the level conversion circuit 11 is converted into a triangular wave signal by a time constant circuit composed of a variable resistor R40 and a capacitor C5. Here, in order to ensure the linearity of the slope of the triangular wave signal, the time constant T = R40 × C5 is made sufficiently large with respect to the clock signal SK cycle To. Therefore, the level conversion circuit 11 is necessary to obtain a triangular wave signal having a sufficient amplitude. Further, the amplitude of the triangular wave signal can be set by adjusting the resistance value of the variable resistor R40 of the time constant circuit.
[0004]
The triangular wave signal generated in this way is input to the non-inverting input terminal of the level comparator 13 via the DC component cutting capacitor C6. A DC voltage set to a predetermined value by the variable resistor R39, the capacitor C7 and the resistor R41 is also input to the same terminal, and the triangular wave signal and the DC voltage are added.
[0005]
On the other hand, the modulated digital data Dv is input to a D / A converter (DAC) 13, latched by a clock signal SK, and converted into an analog signal. This analog signal is input to the inverting input terminal of the level comparator 13. Here, the output voltage Da of the D / A converter 13 is generally represented by Expression (1).
Da = Vr−r × i × Dv (1)
However, Vr: Reference voltage r: Reference resistance i: Reference current Dv: An integer of 0 to 255 in the case of 8 bits.
That is, as shown in FIG. 2, the output voltage Da changes uniquely from the analog voltage V00 to VFF with respect to the change from Dv = 0 to 255. Therefore, in order to cause the level comparator 13 to generate a PWM signal having a pulse width T00 to TFF in response to a change in the Dv value, the variable resistors R40 and R39 are provided so as to obtain the triangular wave signal shown in FIG. adjust.
[0007]
[Problems to be solved by the invention]
However, the above-described technique has the following problems.
[0008]
(1) The amplitude adjustment of the triangular wave signal by the variable resistor R40 and the offset level adjustment of the triangular wave signal by the variable resistor R39 change both the minimum pulse width T00 and the maximum pulse width TFF of the output PWM signal. In order to set the range of the pulse width, both adjustments are repeated, and the adjustment takes time.
[0009]
(2) In order to secure an appropriate triangular wave signal amplitude with respect to the output voltage Da of the DAC 12, a voltage of about 12 V is required as a power source of the level converter 11 for converting the input clock signal to a high level. Not suitable for. In addition, a copying machine and an LBP require a high-speed PWM of about 30 MHz for high speed and high definition, but it is difficult to realize a high-speed and inexpensive level converter that covers this frequency.
[0010]
(3) Ensuring the duty of the input clock signal is important for maintaining the symmetry of both slopes of the triangular wave signal. For this purpose, the digital circuit must process the double-frequency clock signal 2SK. This is a major drawback in configuring a high-speed PWM circuit.
[0011]
(4) Since the triangular wave signal generator shown in FIG. 1 has a large time constant, the peak level and offset of the triangular wave signal fluctuate due to jitter contained in the input clock signal, and such a triangular wave signal is used in the PWM circuit. In such a case, jitter occurs in the pulse width of the PWM signal, causing a problem of degrading the image quality in the copying machine and the LBP.
[0012]
(5) Since the triangular wave signal generator shown in FIG. 1 has a large time constant, several tens of clock cycles are required until the amplitude and offset voltage of the triangular wave signal are stabilized with respect to a clock signal having an intermittent period. However, this means that an idling clock is required, which is undesirable in terms of system configuration.
[0013]
The present invention solves the above-described problems, and an object thereof is to accurately generate a desired signal in accordance with an input clock signal.
[0014]
[Means for Solving the Problems]
The present invention has the following configuration as one means for achieving the above object.
[0015]
The signal generating apparatus according to the present invention, input means for inputting a clock signal, a charge mode for charging the device in order to generate a conversion Ete predetermined signal off the discharge mode for discharging the device, the inputted said The charging mode is started based on a clock signal, and when the predetermined signal reaches a first voltage, the charging mode is ended and the discharging mode is started, and when the predetermined signal reaches a second voltage The signal generation means for ending the discharge mode, the predetermined signal and a third voltage larger than the second voltage are compared, and the current of the charge and discharge modes of the signal generation means is determined according to the comparison result Current control means for controlling the value .
[0016]
An image processing apparatus according to the present invention includes the above-described signal generation apparatus, and outputs a signal having a pulse width corresponding to input image data.
[0017]
A signal generation method according to the present invention is a signal generation method for generating a predetermined signal , wherein a clock signal is input, charging of an element is started based on the clock signal, and the predetermined signal is a first voltage. When the predetermined signal reaches the second voltage, the discharge of the element is terminated and the discharge of the element is terminated , and the predetermined signal and the second voltage higher than the second voltage. The three voltages are compared, and the charge and discharge current values are controlled in accordance with the comparison result .
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an image processing apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.
[0019]
[Constitution]
FIG. 3 is a block diagram showing an example of the configuration of a triangular wave signal generating circuit according to an embodiment of the present invention, which generates a triangular wave signal by controlling the charge / discharge current of the capacitor C1.
[0020]
A clock signal SK having the same frequency as the triangular wave signal having a desired frequency is input to the charge / discharge switching control circuit 1, and a signal SK2 for controlling the charge / discharge operation is output. The signal SK2 is input to the charge / discharge current generation circuit 2, and the charge / discharge of the capacitor C1 is controlled. The triangular wave signal generated in the capacitor C1 by charging / discharging is output as a triangular wave signal TRI via the buffer 4.
[0021]
The triangular wave signal TRI output from the buffer 4 is input to the charge / discharge switching timing generation circuit 5. The charge / discharge switching timing generation circuit 5 outputs a signal SK1 for switching between a charging operation and a discharging operation based on a reference voltage V1 for detecting the upper peak voltage of the triangular wave signal TRI and a predetermined reference voltage V2 described later. . The switching signal SK1 is input to the charge / discharge switching control circuit 1.
[0022]
Further, the triangular wave signal TRI output from the buffer 4 is input to the non-inverting input terminal of the level comparator 6. A reference voltage V3 for detecting the peak level of the triangular wave signal TRI is input to the inverting input terminal of the level comparator 6. The output S of the level comparator 6 is input to the charge pump circuit (CP) 7, and the output of CP 7 is input to the error voltage generation circuit (Δ) 9 via the loop filter 8. A control voltage Vcont, which is an output of Δ9, is input to the charge / discharge current generation circuit 2 to control the charge / discharge current.
[0023]
Further, the triangular wave signal TRI output from the buffer 4 is input to the lower vertex limit circuit 3. The lower apex limit circuit 3 supplies a current signal for limiting the lower apex voltage of the triangular wave signal TRI to the capacitor C1 based on the reference voltage V4 for detecting the lower apex voltage of the triangular wave signal TRI.
[0024]
[Operation]
FIG. 4 is a timing chart for explaining the operation of the triangular wave signal generating circuit shown in FIG.
[0025]
FIG. 4A shows an input clock signal SK. The clock signal SK is stopped before time t0 when the generation of the clock signal SK is started. Further, the clock duty of the clock signal SK is not guaranteed, and as shown in the figure, the falling timing exists within the period tdu and is indefinite. Here, during the stop period of the clock signal SK, the signal SK1 is at the H level, the signal SK2 is at the L level, and the triangular wave signal TRI (terminal voltage of the capacitor C1), as shown in FIGS. Suppose that the voltage is V4.
[0026]
When the signal SK1 is at the H level, the charge / discharge switching control circuit 1 causes the signal SK2 to transition to the H level at the rising timing of the clock signal SK. When the signal SK2 is at the H level, the charge / discharge current generation circuit 2 enters the charge mode and sources the charge current Io to the capacitor C1. Therefore, the terminal voltage of the capacitor C1 monotonously rises with a slope determined by the capacitor C1 and the current value Io, as shown in FIG. The current value Io is controlled to a value larger by a predetermined amount than the current value I′o shown in the following equation.
I′o = C1 × (V1−V4) / (To / 2) (2)
Where To: period of the clock signal SK
At time t1 when the terminal voltage of the capacitor C1 reaches V1, the charge / discharge switching timing generation circuit 5 changes the signal SK1 to L level. When the signal SK1 becomes L level, the charge / discharge switching control circuit 1 sets the signal SK2 to L level. When the signal SK2 is at the L level, the charge / discharge current generation circuit 2 enters the discharge mode, and sinks the discharge current Io having a value equal to the charge current from the capacitor C1. Therefore, similarly to the charging operation, the terminal voltage of the capacitor C1 decreases monotonously with the slope determined by the capacitor C1 and the current value Io. Note that the period from time to to time t1 is less than half of the period To.
[0028]
At time t2 when the terminal voltage of the capacitor C1 reaches V2, the charge / discharge switching timing generation circuit 5 changes the signal SK1 to H level. However, the charge / discharge switching control circuit 1 is configured such that the signal SK2 does not transit only when the signal SK1 becomes H level, and the signal SK2 transits to H level at the next rise of the clock signal SK. For this reason, when the terminal voltage of the capacitor C1 drops to V4, the lower vertex voltage limiting circuit 3 outputs a charging current and performs a control operation to hold the terminal voltage of the capacitor C1 at V4.
[0029]
The circuit operation after the rising time t5 of the next clock signal SK repeats the above-described operation.
[0030]
The necessary condition in the above operation is that the falling timing t1 of the clock signal SK having the width of tdu should be before the timing t2. The timing t2 can be arbitrarily set by the reference voltage V2, and can be easily designed so as not to affect the operation even if the duty of the clock signal SK fluctuates to about 80%, for example.
[0031]
[Details of circuit configuration]
● Charge / Discharge Current Generation Circuit Next, the detailed circuit configuration is shown and its operation is explained. FIG. 5 is a circuit diagram showing a configuration example of the charge / discharge current generation circuit 2 and the lower vertex limit circuit 3. The configuration in FIG. 3 is a configuration that takes IC into consideration, and it is assumed that the relative accuracy of the resistance value and the transistor size of the same type appearing in the following description is good, and the circuit symbol shown in FIG. The transistor represents the transistor size. In other words, it is assumed that the following relationship is established between the circuit elements.
Q5 = Q7 / 2 = Q13 / 2 = Q17
R2 = 2 × R3 = 2 × R5 = R9
Q4 = Q12
Q3 = Q8 = Q11
R1 = R4 = R6
R8 = 2 × R7
Q14 / 2 = Q15
[0032]
When the current value of the collector of Q17 (hereinafter referred to as “Q17 / C”) and the current value of Q5 / C is Io by the control voltage Vcont, the current value of Q13 / C becomes 2Io. The circuit is balanced only when the current value of Q3 / C is Io, so the Q11 / C current is Io. In this circuit, a lateral type PNP transistor having a small amplification factor β is considered.
[0033]
An intermediate voltage (V1 + V4) / 2 of a desired triangular wave signal TRI is input to the base of Q9 (hereinafter referred to as “Q9 / B”) as a reference voltage, and the influence of the early effect of the transistor is suppressed as much as possible. Yes. The signal SK2 is differentially input to the current switch composed of Q12 and Q10. The signal Psk2 is in phase with the signal SK2 shown in FIG. However, it is desirable to set the H level of the signal Psk2 to be equal to or lower than the lower vertex level (V4) of the triangular wave signal TRI (V4 in this example) so that Q12 does not saturate, and Q4 is for β compensation of Q12. is there.
[0034]
Q12 is turned on when the signal SK2 is at L level (the signal Nsk2 is at H level), sinks the discharge current Io from the capacitor C1, is turned off when the signal SK2 is at H level, and the capacitor C1 has a charging current. Io is supplied.
[0035]
Thus, the charge / discharge current generating circuit 2 that performs the above-described operation can be realized.
[0036]
Lower vertex limit circuit The reference voltage V4 is input to Q16 / B of the lower vertex limit circuit 3, and the triangular wave signal TRI output from the buffer 4 is input to Q18 / B. Therefore, during a period when the voltage of the triangular wave signal TRI is higher than the reference voltage, Q16 is turned off and no current flows through Q14 / C, and the operation of generating the triangular wave signal is not affected. However, when the voltage of the triangular wave signal TRI reaches the reference voltage V4, Q16 becomes active, Q14 / C generates a charging current, and the voltage of the triangular wave signal TRI is held at the reference voltage V4.
[0037]
Thus, the lower vertex limit circuit 3 that performs the above-described operation can be realized.
[0038]
Charge / Discharge Switching Timing Generating Circuit FIG. 6 is a circuit diagram showing a configuration example of the charge / discharge switching timing generating circuit 5. It is assumed that the following relationship holds for the circuit elements.
R10 = R11
Q19 = Q20
Q22 = Q23
Q24 = Q25 = Q26 = Q27
[0039]
A triangular wave signal TRI is input to Q19 / B, and a reference voltage V1 is input to Q20 / B via a resistor R12. The voltage of Q20 / B when Q22 is turned on is set to the reference voltage V2 shown in the following equation.
V2 = V1−R12 × I3 (3)
[0040]
Since Q19 is turned off when the voltage of the triangular wave signal TRI is increasing, the signal SK1 (Psk1) becomes H level, Q22 is turned off, and the voltage of Q20 / B becomes the reference voltage V1. When the voltage of the triangular wave signal TRI reaches the reference voltage V1, current starts to flow through Q22, Q20 is rapidly turned on by the positive feedback operation, and the signal SK1 is set to L level, and the voltage of Q20 / B is set to the reference voltage V2. To.
[0041]
When the signal SK1 becomes L level, the charge / discharge current generation circuit 2 sinks the discharge current from the capacitor C1, so that the voltage of the triangular wave signal TRI drops. When the voltage of the triangular wave signal TRI reaches the reference voltage V2, current starts to flow through Q23, Q22 is rapidly turned off by the positive feedback operation, and the voltage of Q20 / B becomes the reference voltage V1.
[0042]
Thus, the charge / discharge switching timing generation circuit 5 that performs the above-described operation can be realized.
[0043]
The resistors R10 and R11 are connected to the voltage source Vx through the resistor R13. The voltage source Vx is set as follows. The band gap voltage Vbg that is not affected by the environmental temperature Ta is generally expressed by the following equation using the base-emitter voltage Vbe.
Vbg = Vbe + m × VT≈1.26 [V] (4)
However, VT: k × T / q
k: Boltzmann constant T: absolute temperature q: electron charge m: constant composed of a ratio of resistance and transistor size
Therefore, the voltage source Vx is set as follows.
Vx = Vbg × 10/3 / 3≈4.2 [V] (5)
[0045]
A control current Ib determined by the control voltages Vb and R14 flows through the resistor R13 via the transistor Q21. Here, the H level voltage Vsk1 of Psk1 and Nsk1 is as follows.
Vsk1 = Vx−R13 × Ib−2 × Vbe (6)
[0046]
Here, the bias control circuit shown in FIG. 7 for setting the voltage Vsk1 to the reference voltage V4 will be described. In the figure, it is assumed that the following relationship is established between circuit elements.
R28 = R13
Q28 = Q21
R29 = R14
Q29 = Q30 = Q24 = Q25 = Q26 = Q27
[0047]
At this time, the voltage of Q30 / E becomes the same as that in the equation (6), and is stabilized only when the reference voltage V4 is reached. Therefore, when the control voltage Vb is supplied to the charge / discharge switching timing generation circuit 5 of FIG. 6, the voltage Vsk1 becomes the reference voltage V4.
[0048]
Charging / Discharging Switching Control Circuit FIG. 8 is a circuit diagram showing a first configuration example of the charging / discharging switching control circuit 1. The D input of the D flip-flop (DFF) is at the H level (Vcc), the clock signal SK is input to the clock (CK) input, the signal SK1 is input to the inverted reset (R) input, and Q A signal SK2 is output from the output. Even with such a DFF circuit, the charge / discharge switching control circuit 1 that performs the above-described logic operation can be easily realized.
[0049]
However, the signal SK2 has the following requirements in addition to the logical operation.
[0050]
(1) The logic H level is made lower than the reference voltage V4 (here, V4).
[0051]
(2) The delay time of the rising timing and falling timing of the signal SK1 is made as short as possible so that the upper vertex level of the triangular wave signal does not exceed the reference voltage V1 as much as possible.
[0052]
FIG. 9 is a circuit diagram showing a second configuration example of the charge / discharge switching control circuit 1 in consideration of the above requirements. In the figure, it is assumed that the following relationship is established between circuit elements.
R33 = R34 = R35 = R36 = R37 = R38
Q40 = Q28
R32 = R29
R31 = R28
Other transistors are the same size.
In FIG. 9, the block denoted by reference numeral 93 is a bias conversion circuit for the clock signal SK, the block denoted by reference numeral 92 is an ECL circuit that operates in the same manner as in FIG. 8, and the block denoted by reference numeral 91 is based on the H level voltage Vsk2 of the clock signal SK2. This is a bias circuit for setting the voltage V4.
[0054]
If the reference voltage V4 is set to 2 [V], when the voltage of Q56 / C (Q52 / C) is at the H level (V4 = 2 [V]), the collector-emitter voltage Vce of Q56 (Q52). Is expressed by the following equation.
Vce = Vx−3 × Vbe− (V4−Vbe) = 2.2−2 × Vbe (7)
However, Vx = 4.2 [V]
V4 = 2 [V]
[0055]
Equation (7) means that the ECL circuit 92 is sufficiently operated even if a slight design error (about ± 0.1 V) occurs in the voltage Vx.
[0056]
The operation of the ECL circuit 92 will be described. When the signal SK1 is at L level (Psk1 = 'L'), Q56 is turned on, so that the voltage of Q45 / E is forcibly set to L level. Next, when the signal SK1 becomes H level (Psk1 = 'H'), Q52 is turned on. However, since the clock signal SK is at L level (Psk = 'L') (see FIG. 4), Q56 is also turned on. . At this time, the voltage of Q45 / E remains at the L level by the holding circuit including R35, R36, Q49, and Q53.
[0057]
Next, when the clock signal SK rises, Q51 is turned on, forcing the voltage of Q45 / E to H level. Then, when the Q45 / E voltage becomes H level, Q54 is rapidly turned on, and the ECL circuit 92 enters the holding state and waits for the fall of the signal SK1. The ECL circuit 92 does not respond to the change of the clock signal SK until the signal SK1 becomes H level again. For this reason, the signal obtained from Q45 / E logically satisfies the signal SK2.
[0058]
The signal obtained from Q45 / E is level-shifted at Q46 and input to the bias circuit 91. Since the H level of Psk2 (Nsk2) is the same as the configuration of FIG. 6, it is the reference voltage V4. Further, the signal SK1 is input to the bias circuit 91, and when the signal SK1 becomes L level, the signal SK2 (Psk2) is forcibly changed to L level again, so that the time delay of the falling timing of the signal SK2 can be shortened.
[0059]
● CP
FIG. 10 is a circuit diagram showing a configuration example of CP7 for controlling the charge / discharge current Io to obtain a desired triangular wave signal.
[0060]
The output S of the level comparator 6 is inputted as a differential signal to Q61 and Q62 to which the constant current source I6 is connected to the emitter coupling portion. Q64 / C is connected to constant current source m × I6 (m is a constant) and capacitor C4, and is also connected to Q63 / B. On the other hand, Q65 / C is connected to the power supply Vcc. The voltage of Q63 / E becomes the output signal of CP7.
[0061]
FIG. 11 is a diagram for explaining the operation of CP7. The DC voltage value of Q65 / E is stabilized only when the period T1 satisfies the following equation.
T1 = (1−m) × To (8)
Where To: period of the clock signal SK
The triangular wave signal TRI whose lower vertex voltage is not limited by the reference voltage V4 by the lower vertex voltage limiting circuit 3 is a triangular wave signal having a peak-to-peak level of Vpp shown in FIG. Further, the reference voltage difference (V3−V4) is set so as to satisfy the following expression.
(V3−V4) / Vpp <T1 / To (9)
Vpp = (V1−V3) / m (10)
[0063]
When the expression (9) is satisfied, the lower vertex voltage limiting circuit 3 operates and there is always a period T2 for limiting the lower vertex voltage of the triangular wave signal TRI. The expression (9) can be easily realized by setting the reference voltage (V3-V4) and the constant current source ratio m of CP7 in consideration of the expression (10), and the period T2 can also be designed.
[0064]
When the period T2 exists, the voltage at the rising timing of the triangular wave signal TRI is stabilized at the reference voltage V4. This means that the period T2 of the triangular wave signal TRI only fluctuates even if the clock signal SK has jitter at its rising timing. Since the jitter amount included in the clock signal SK is generally considered to be about 1% of the clock period, when the triangular wave signal TRI generated based on the clock signal SK including jitter is used in the PWM circuit, the clock period The period T2 may be set to a small value that does not affect the PWM characteristics with respect to To.
[0065]
As described above, the upper vertex of the triangular wave signal TRI generated by the triangular wave signal generation circuit of the present embodiment is controlled so as to be stabilized at the reference voltage V1, and the waveform thereof reaches the reference voltage V4 by the charge pump circuit 7. It is uniquely controlled to a desired waveform. For this reason, the reference voltage Vr and the quantized voltage (r × i) in the DAC characteristics shown in the above equation (1) are set to voltages correlated with the reference voltages V1, V3, and V4 for generating the triangular wave signal TRI. This makes it possible to easily realize a PWM circuit that has excellent environmental characteristics and can independently set the maximum and minimum pulse widths. If this triangular wave signal generation circuit is used, the period from the generation of the clock signal SK having an intermittent period to the stabilization of the triangular wave signal TRI can be suppressed to a short time of the clock signal period To in principle.
[0066]
As described above, according to the triangular wave signal generation circuit of this embodiment, the following effects can be obtained.
[0067]
(1) Since the upper and lower vertices of the generated triangular wave signal can be uniquely controlled to desired values, when used in a PWM circuit, the PWM characteristics can be easily set by setting the maximum and minimum pulse widths independently. Can be adjusted in a short time.
[0068]
(2) Since the triangular wave signal is generated by switching the charging and discharging of the capacitor, it is not necessary to supply a high voltage such as 12 V to the circuit, and the slope of the generated triangular wave signal has good linearity. Furthermore, the level converter as described above is not required.
[0069]
(3) It is a system that is practically unaffected by the duty of the input clock and does not require a double frequency clock signal as in the prior art. This is important in systems that require high frequency operation.
[0070]
(4) Since the generated triangular wave signal has a pause period, jitter shorter than the pause period included in the input clock signal does not affect the triangle wave signal. This pause period can be easily set.
[0071]
(5) Even for an input clock signal having an intermittent period, a desired triangular wave signal can be generated in a short period (one cycle of the input clock). This means that almost no idling clock signal is required, which is significant in terms of system configuration.
[0072]
[Other Embodiments]
Note that the present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), or a device (for example, a copier, a facsimile device, etc.) including a single device. You may apply to.
[0073]
Another object of the present invention is to supply a storage medium storing software program codes for implementing the functions of the above-described embodiments to a system or apparatus, and the computer (or CPU or MPU) of the system or apparatus stores the storage medium. Needless to say, this can also be achieved by reading and executing the program code stored in the. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention. As a storage medium for supplying the program code, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.
[0074]
Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.
[0075]
Further, after the program code read from the storage medium is written into a memory provided in a function expansion card inserted in the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the CPU or the like provided in the card or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.
[0076]
【The invention's effect】
As described above, according to the present invention, a desired signal can be accurately generated according to an input clock signal, and image quality deterioration due to jitter of a pulse signal can be prevented .
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a high-speed pulse width modulation (PWM) circuit using a triangular wave signal;
FIG. 2 is a diagram for explaining the operation of the PWM circuit of FIG.
FIG. 3 is a block diagram showing a configuration example of a triangular wave signal generation circuit according to an embodiment of the present invention;
4 is a timing chart for explaining the operation of the triangular wave signal generation circuit shown in FIG. 3;
5 is a circuit diagram showing a configuration example of a charge / discharge current generation circuit and a lower vertex limit circuit shown in FIG. 3;
6 is a circuit diagram showing a configuration example of a charge / discharge switching timing generation circuit shown in FIG. 3;
FIG. 7 is a circuit diagram showing a configuration example of a bias control circuit for setting a reference voltage V4;
8 is a circuit diagram showing a first configuration example of the charge / discharge switching control circuit shown in FIG. 3;
9 is a circuit diagram showing a second configuration example of the charge / discharge switching control circuit shown in FIG. 3;
10 is a circuit diagram showing a configuration example of the CP shown in FIG.
11 is a diagram for explaining the operation of the CP shown in FIG. 10;

Claims (5)

An input means for inputting a clock signal;
A charging mode to charge the device, in order to switch the discharge mode for discharging the Société for generating a predetermined signal, the charge mode and started based on the inputted clock signal, the predetermined signal is a Signal generating means for ending the charge mode and reaching the discharge mode when reaching one voltage, and ending the discharge mode when the predetermined signal reaches a second voltage ;
Current control means for comparing the predetermined signal with a third voltage greater than the second voltage, and controlling the current value of the charge and discharge modes of the signal generating means according to the comparison result; A signal generator characterized by the above. 2. The signal generator according to claim 1, wherein the predetermined signal is a triangular wave signal. The device is a signal generator as claimed in claim 1 or claim 2, characterized in that a capacitor. Comprising the signal generator according to any one of claims 1 to 3 ,
An image processing apparatus that outputs a signal having a pulse width corresponding to input image data. A signal generation method for generating a predetermined signal,
Input clock signal,
Based on the clock signal, charging of the element is started. When the predetermined signal reaches the first voltage, charging of the element is terminated and discharging is started. When the predetermined signal reaches the second voltage While terminating the discharge of the element ,
A signal generation method comprising: comparing the predetermined signal with a third voltage greater than the second voltage, and controlling the current values of the charging and discharging according to the comparison result .

Images