JP3618421B2 - Digital data playback device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital data reproducing apparatus for reproducing digital data recorded on a recording medium such as an optical disk.
[0002]
[Prior art]
In recent years, Viterbi decoding has been known as a method for decoding digital data recorded at high density on a recording medium with high reliability. In such Viterbi decoding, the most probable data series is decoded with respect to the sample value series obtained by A / D converting the read signal read from the recording medium. At this time, since the binary data series of “1” or “0” is decoded based on the change transition of the amplitude value of the read signal, when the recording density is high, and further, when the S / N of the read signal is low In addition, highly reliable reproduced digital data can be obtained.
[0003]
FIG. 1 is a diagram showing a configuration of a digital data reproducing apparatus that reproduces digital data recorded on an optical disc at a high density by applying such Viterbi decoding.
In FIG. 1, an optical pickup 1 irradiates a light beam onto an optical disc 3 that is rotationally driven by a spindle motor 2. Further, the optical pickup 1 photoelectrically converts the reflected light from the optical disk 3 to obtain an analog read signal and supplies it to the amplifier 4. The amplifier 4 supplies the adder 5 with an amplified read signal p obtained by amplifying the amplitude of the read signal as desired. The adder 5 supplies the reproduction analog signal r obtained by adding the amplified read signal p and the reference center voltage Vc to the A / D converter 6. At this time, the reference center voltage Vc is a center voltage serving as a reference at the time of conversion in the A / D converter 6. Therefore, by adding this reference center voltage Vc, the amplified read signal p is converted into a reproduced analog signal r whose center of amplitude is adjusted to the reference center value of the A / D converter 6. The A / D converter 6 converts the reproduced analog signal r into a digital sample value t at every timing of the sampling clock s, and supplies this to the Viterbi decoder 20. The clock generation circuit 7 generates a clock signal that is phase-synchronized with the change period of the series based on the sample value t, and supplies this to the A / D converter 6 as the sampling clock s. The Viterbi decoder 20 decodes the most probable binary data series based on the amplitude change of the sample value t sequentially supplied from the A / D converter 6, and outputs this as reproduced digital data.
[0004]
Here, in an optical disc in which digital data is formed as pits on the disc surface, the pit length on the disc surface increases or decreases due to fluctuations in recording conditions during recording of information and pit forming conditions. There is a thing. As a result, a phenomenon called so-called asymmetry occurs in which the amplitude of the read signal becomes asymmetrical with respect to the reference center voltage Vc of the A / D converter 6.
[0005]
FIG. 2A is a diagram illustrating a waveform example of the reproduction analog signal r and the sample value t in a state where asymmetry is not generated, and FIG.
As shown in FIG. 2B, when asymmetry occurs in the pits formed on the disk surface, an offset occurs in the amplified read signal p, and the center Vr of the amplitude of the reproduced analog signal r is A / It does not coincide with the reference center voltage Vc in the D converter 6. At this time, each sample value t output from the A / D converter 6 is level-shifted by an amount corresponding to the degree of asymmetry. Thus, from the sample value whose entire level is shifted, the original decoding performance of the Viterbi decoder 20 is not exhibited, and therefore, a problem that the data error rate deteriorates occurs.
[0006]
Further, even when the above-described offset occurs in the reproduction analog signal r due to the influence of the element value error and adjustment error of the analog circuit in the preceding stage of the A / D converter 6, the same performance deterioration occurs.
[0007]
[Problems to be solved by the invention]
The present invention has been made to solve such a problem, and even when an offset occurs in the read signal, digital data reproduction that can reproduce digital data without degrading the decoding performance of Viterbi decoding. An object is to provide an apparatus.
[0008]
[Means for Solving the Problems]
A digital data reproducing apparatus according to the present invention is a digital data reproducing apparatus for reproducing the digital data from a recording medium on which digital data is recorded, and a pickup for reading a recorded information from the recording medium and obtaining a read signal An A / D converter that sequentially samples the read signal and converts it into a digital sample value; decoding means for decoding the digital data based on a sequence of the sample value; and interpolating the sample value Interpolating means for obtaining an interpolated sample value, polar pulse generating means for generating a polar pulse signal having a predetermined voltage value having a polarity corresponding to the polarity of the interpolated sample value, and determining an average voltage of the polar pulse signal as an error voltage And adding a correction voltage corresponding to the error voltage to the read signal. Ri and means for performing an offset correction of the read signal.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The digital data reproducing apparatus according to the present invention sequentially samples the read signal read from the recording medium and converts it into a digital sample value, and decodes the digital data based on the sample value sequence, A pulse voltage corresponding to the polarity of the signal is generated, and the offset correction of the read signal is performed with the average voltage value of the pulse voltage.
[0010]
【Example】
Examples of the present invention will be described below.
FIG. 3 is a diagram showing an example of the configuration of the digital data reproducing apparatus according to the present invention.
In FIG. 3, an optical pickup 1 irradiates a light beam onto an optical disk 3 that is rotationally driven by a spindle motor 2. Further, the optical pickup 1 photoelectrically converts the reflected light from the optical disk 3 to obtain a read signal and supplies it to the amplifier 4. The amplifier 4 supplies the adder 5 with an amplified read signal p obtained by amplifying the amplitude of the read signal as desired. The adder 5 supplies the reproduction analog signal r obtained by adding the amplified read signal p and the corrected reference center voltage Vc ′ to the A / D converter 6. The A / D converter 6 converts the reproduced analog signal r into a digital sample value t at every timing of the sampling clock s and supplies it to the Viterbi decoder 20.
[0011]
The clock generation circuit 7 generates a sampling clock s that is phase-synchronized with the change period of the sequence based on the sample value t and has the same timing as the bit change timing of the recording data, and this is generated as described above. s is supplied to the A / D converter 6. The Viterbi decoder 20 decodes the most probable binary data series based on the amplitude change of the sample value t sequentially supplied from the A / D converter 6, and outputs this as reproduced digital data.
[0012]
The polarity pulse generating circuit 8 generates a polarity pulse signal u having a pulse voltage corresponding to the polarity of the sample value t and supplies it to the averaging circuit 9. For example, the polarity pulse generation circuit 8 determines whether the sample value t is a positive value or a negative value based on the MSB (Most Significant Bit) of the sample value t. During a period in which the value t is determined to be a positive value, a positive polarity polarity pulse signal u is generated and supplied to the averaging circuit 9, while the sample value t is a negative value. During the determined period, a negative polarity polarity pulse signal u is generated and supplied to the averaging circuit 9. The averaging circuit 9 is composed of, for example, a low-pass filter, calculates an average voltage value of the polarity pulse signal u, and supplies this average voltage value to the subtracter 10 as an error voltage Ve. The subtracter 10 supplies a voltage value obtained by subtracting the error voltage Ve from the reference center voltage Vc in the A / D converter 6 to the adder 5 as the corrected reference center voltage Vc ′. That is, the corrected reference center voltage Vc ′ subjected to offset correction is obtained by subtracting the error voltage Ve from the reference center voltage Vc.
[0013]
Next, the operation of the digital data reproducing apparatus shown in FIG. 3 will be described.
4 and 5 show a reproduction analog signal r, a sample value t, and a polarity pulse signal obtained when the optical pickup 1 is formed on the optical disc 3 and the recording pit row corresponding to the recording data {100001110001110001} is traced. It is a figure which shows an example of u and the error voltage Ve.
[0014]
Here, FIG. 4 shows signal waveforms when asymmetry occurs in which the recording pit length becomes longer than a predetermined length.
At this time, the amplified read signal p output from the amplifier 4 is generally offset to the negative side, and therefore the reproduced analog signal r is also relative to the reference center voltage Vc in the A / D converter 6. It will be offset to the negative side. Therefore, the period in which the polarity pulse signal u is a negative voltage (−1 volt) is longer than the period in which the polarity pulse signal u is a positive voltage (+1 volt) by an amount corresponding to the offset amount. Therefore, the averaging circuit 9 supplies the negative error voltage Ve having a value corresponding to the offset amount to the subtracter 10. At this time, the corrected reference center voltage Vc ′ obtained by the subtracter 10 becomes higher than the reference center voltage Vc by the absolute value of the error voltage Ve. Therefore, as shown in FIG. 4, the reproduced analog signal r offset to the negative side with respect to the reference center voltage Vc is level-shifted to the positive side by the absolute value of the error voltage Ve. That is, offset correction is performed so that the center of the amplitude of the reproduced analog signal r becomes equal to the reference center voltage Vc in the A / D converter 6.
[0015]
On the other hand, FIG. 5 shows each signal waveform when asymmetry occurs in which the recording pit length becomes shorter than a predetermined length.
At this time, the amplified read signal p output from the amplifier 4 is entirely offset to the positive side. Therefore, the reproduction analog signal r is also positive with respect to the reference center voltage Vc in the A / D converter 6. It will be offset to the side. Therefore, the period in which the polarity pulse signal u is a positive voltage (+1 volt) is longer than the period in which the polarity pulse signal u is a negative voltage (−1 volt) by an amount corresponding to the offset amount. Therefore, the averaging circuit 9 supplies a positive error voltage Ve having a value corresponding to the offset amount to the subtracter 10. At this time, the corrected reference center voltage Vc ′ obtained by the subtracter 10 becomes lower than the reference center voltage Vc by the absolute value of the error voltage Ve. Therefore, as shown in FIG. 5, the reproduced analog signal r that has been offset to the positive side is level-shifted to the negative side by the absolute value of the error voltage Ve. It becomes equal to the reference center voltage Vc in the / D converter 6.
[0016]
As described above, according to the digital data reproducing apparatus, even if an offset occurs in the signal level of the amplified read signal p, the reproduction analog signal is reproduced by the correction circuit including the polarity pulse generating circuit 8, the averaging circuit 9, and the subtractor 10. The offset correction is performed so that the center of the amplitude of the signal r is always equal to the reference center voltage Vc in the A / D converter 6.
[0017]
In the above embodiment, as shown in FIGS. 4 and 5, the error voltage Ve is obtained based on the sample value t sampled at the same timing as the bit change timing of the recording data. Similarly, the error voltage Ve can be obtained from the sample value obtained at the timing of the bit center of the recording data.
[0018]
FIG. 6 shows a digital data reproducing apparatus according to another embodiment of the present invention, in which a clock generating circuit 7 'for generating a sampling clock s is provided at the same timing as the timing of the bit central portion of the recording data. It is a figure which shows a structure.
In FIG. 6, an optical pickup 1 irradiates a light beam onto an optical disk 3 that is rotationally driven by a spindle motor 2. Further, the optical pickup 1 photoelectrically converts the reflected light from the optical disk 3 to obtain a read signal and supplies it to the amplifier 4. The amplifier 4 supplies the adder 5 with an amplified read signal p obtained by amplifying the amplitude of the read signal as desired. The adder 5 supplies the reproduction analog signal r obtained by adding the amplified read signal p and the corrected reference center voltage Vc ′ to the A / D converter 6. The A / D converter 6 converts the reproduced analog signal r into a digital sample value t at every timing of the sampling clock s and supplies it to the Viterbi decoder 20.
[0019]
The clock generation circuit 7 'generates a sampling clock s that is phase-synchronized with the change period of the series based on the sample value t and has the same timing as the bit center portion of the recording data, and this is generated as described above. A clock s is supplied to the A / D converter 6. The Viterbi decoder 20 decodes the most probable binary data series based on the amplitude change of the sample value t sequentially supplied from the A / D converter 6, and outputs this as reproduced digital data.
[0020]
The interpolated sample value generation circuit 10 obtains an average value of two consecutive sample values t and obtains this as an interpolated sample value t ′ at an intermediate sample time point of the sample value t.
The polarity pulse generation circuit 8 generates a polarity pulse signal u having a pulse voltage corresponding to the polarity of the interpolation sample value t ′ and supplies it to the averaging circuit 9. For example, based on the MSB of the interpolation sample value t ′, the polarity pulse generation circuit 8 determines whether the interpolation sample value t ′ is a positive value or a negative value, and this interpolation sample value t ′. During a period in which the value t ′ is determined to be a positive value, a positive voltage polarity pulse signal u is generated and supplied to the averaging circuit 9, while the interpolated sample value t ′ is a negative value. During a period in which it is determined that the negative polarity polarity pulse signal u is generated, it is supplied to the averaging circuit 9. The averaging circuit 9 is composed of, for example, a low-pass filter, calculates an average voltage value of the polarity pulse signal u, and supplies this average voltage value to the subtracter 10 as an error voltage Ve. The subtracter 10 supplies a voltage value obtained by subtracting the error voltage Ve from the reference center voltage Vc in the A / D converter 6 to the adder 5 as the corrected reference center voltage Vc ′. That is, by subtracting the error voltage Ve from the reference center voltage Vc, an offset-corrected reference reference voltage Vc ′ is obtained.
[0021]
FIG. 7 shows a reproduction analog obtained when the optical pickup 1 of the digital data reproduction apparatus shown in FIG. 6 traces a recording pit string corresponding to the recording data {100001110001110001} formed on the optical disk 3. It is a figure which shows each of the signal r, the sample value t, the interpolation sample value t ', the polarity pulse signal u, and the error voltage Ve. FIG. 7 shows signal waveforms when asymmetry occurs in which the recording pit length becomes longer than a predetermined length.
[0022]
Here, when the asymmetry as shown in FIG. 7 occurs, when the error voltage Ve is obtained based on the sample value t as in the apparatus shown in FIG. 3, the sample value t is a positive value. Since both a certain period and a period having a negative value are three clock periods, the error voltage Ve as an average value thereof becomes zero. That is, although the asymmetry is occurring, the reference center voltage Vc is not corrected.
[0023]
Therefore, in the digital data reproducing apparatus shown in FIG. 6, the interpolation sample value generation circuit 10 obtains an interpolation sample value t ′ at an intermediate time between two consecutive sample values t, and the interpolation sample value t ′ The polarity pulse signal u as shown in FIG. 7 is obtained according to the change in polarity.
According to such a configuration, even in a digital data reproducing apparatus to which the A / D converter 6 and the clock generation circuit 7 ′ that are configured to perform sampling at the bit center portion of the recording data are applied, the reference center voltage Vc is reduced. Correction is performed.
[0024]
In the digital data reproducing apparatus shown in the above embodiment, when dropout occurs, the signal level of the reproduced analog signal is fixed to either a positive value or a negative value over a long period of time. At this time, an erroneous error voltage Ve is accumulated during the dropout period. Therefore, immediately after the dropout is completed and the normal operation is restored, there is a problem that an erroneous level correction is performed using the accumulated error voltage Ve.
[0025]
FIG. 8 is a diagram showing the configuration of a digital data reproducing apparatus according to another embodiment of the present invention in which a dropout compensation circuit 11 for compensating for such dropout is provided.
The apparatus shown in FIG. 8 is the same as the apparatus shown in FIG. 3 except that this dropout compensation circuit 11 is provided. The operation of other functional modules is the same as that shown in FIG. It is the same as that of the device.
[0026]
The dropout compensation circuit 11 first detects whether or not a dropout has occurred by monitoring the MSB bit inversion interval of the sample value t. At this time, when the bit inversion interval of the MSB of the sample value t is within a predetermined time, that is, when no dropout occurs, the pulse signal MSB ′ corresponding to the MSB of the sample value t is set to the polarity. This is supplied to the pulse generation circuit 8. On the other hand, when the above bit inversion does not occur even after a predetermined time has elapsed, that is, when dropout is detected, a pulse signal that repeats the logic 1 and logic 0 states with a pulse duty of 50% is designated as the pulse signal MSB. 'Is supplied to the polarity pulse generation circuit 8 as'.
[0027]
FIG. 9 shows a circuit configuration of the dropout compensation circuit 11, and FIG. 10 shows an example of the operation of the dropout compensation circuit 11.
In FIG. 9, the bit inversion detection circuit composed of the flip-flop F1 and the exclusive OR gate EX1 generates a detection pulse EG every time it detects the bit inversion of the MSB at the sample value t, and this is detected by the counter C1 and the SR flip-flop F2, respectively. To supply. When the detection pulse EG is supplied, the counter C1 resets the count value to 0 and then counts the number of clock pulses of the sampling clock s. At this time, the counter C1 is the number of clock pulses such sampling clock s every time the 8 clock count, generates 8 pulse detection signal Q ₈ to which the logical value is inverted. Furthermore, the counter C1 is, during the 16 clock count the number of clock pulses of such a sampling clock s, not supplied such detection pulse EG, if the count value is not reset, generates a 16 pulse detection signal Q ₁₆ This is supplied to the SR flip-flop F2.
[0028]
SR flip-flop F2 is supplied to the take 16 pulse detection signal Q ₁₆ is supplied, the drop-out detection signal DO comprising logic 1 determines that this drop-out occurs, the selector S1, a gate G1~G3 To do. On the other hand, when the detection pulse EG is supplied, the SR flip-flop F2 determines that there is no dropout and supplies a dropout detection signal DO of logic 0 to the selector S1.
[0029]
When the logic of the dropout detection signal DO is 0, the selector S1 supplies the MSB of the sample value t as it is to the polarity pulse generation circuit 8 as the pulse signal MSB ′, while the logic of the dropout detection signal DO is If it is 1, that is, the dropout is determined to be occurring, and supplies it to the polarity pulse generating circuit 8 the 8 pulse detection signal Q ₈ as a pulse signal MSB '.
[0030]
As described above, in the dropout compensation circuit 11 shown in FIG. 9, in an optical disc adopting an EFM modulation code such as a compact disc (hereinafter referred to as CD), the maximum bit inversion interval of the recording data is obtained. However, when bit inversion does not occur over 16 clock periods, it is determined that this is a dropout. During this time, the dropout compensation circuit 11 supplies a pulse signal repeating the logic 1 and logic 0 states with a pulse duty of 50% as shown in FIG. 10 to the polarity pulse generation circuit 8 as a pulse signal MSB ′.
[0031]
Therefore, at this time, the polarity pulse generation circuit 8 generates a polarity pulse signal u in an oscillation state in which the state of +1 volt and the state of −1 volt are alternately repeated at a pulse duty of 50%, This is supplied to the averaging circuit 9. Here, since the average voltage of the polarity pulse signal u having a pulse duty of 50% is 0 volts, the error voltage Ve output from the averaging circuit 9 is 0 at this time.
[0032]
That is, when dropout does not occur, an error voltage Ve corresponding to the inversion interval of the MSB at the sample value t is obtained. On the other hand, during the period when the dropout occurs, the error is fixed at 0 volts. The voltage Ve is obtained.
Therefore, according to the dropout compensation circuit 11, the erroneous error voltage Ve is prevented from being accumulated during the dropout period, so that the correction operation is normally performed even immediately after the recovery from the dropout. It is.
[0033]
Also, it takes time when the digital data playback device itself is started up (before the setting of various servo operations such as focus servo, tracking servo, and spindle servo) and during special playback (track jump, track search, etc.) The inversion operation of the reproduced analog signal does not occur over a period longer than the dropout. At this time, if the operation at the time of occurrence of dropout by the dropout compensation circuit 11 as described above is performed, the circuit may malfunction.
[0034]
FIG. 11 is a diagram showing the configuration of a digital data reproducing apparatus according to another embodiment of the present invention made in view of the above points.
The apparatus shown in FIG. 11 is obtained by providing the synchronization detection circuit 12 in the apparatus shown in FIG. 8, and the operation of other functional modules is shown in FIG. Identical to the device.
[0035]
In FIG. 11, the synchronization detection circuit 12 detects a synchronization signal from the reproduced digital data decoded by Viterbi decoding, and supplies the synchronization detection signal to the dropout compensation circuit 11. The dropout compensation circuit 11 performs the dropout compensation operation as described above only when the synchronization detection signal is stably obtained.
That is, in the digital data reproducing apparatus shown in FIG. 11, the dropout compensation circuit 11 is used in a situation where the synchronization signal cannot be stably obtained, such as when the digital data reproducing apparatus itself is started up or during special reproduction. The operation is stopped.
[0036]
【The invention's effect】
As described above, the digital data reproducing apparatus according to the present invention sequentially samples the read signal read from the recording medium and converts it into digital sample values, and decodes the digital data based on the sample value series. The pulse voltage corresponding to the polarity of the sample value is generated, and the offset correction of the read signal is performed with the average voltage value of the pulse voltage.
[0037]
Therefore, according to the present invention, even if an offset occurs in the read signal read from the recording medium, the offset correction is performed so as to shift the level of the read signal corresponding to the offset. Thus, high-precision digital data reproduction can be realized without degrading the decoding performance of the.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a conventional digital data reproducing apparatus.
FIG. 2 is a diagram illustrating waveform examples of a reproduction analog signal r and a sample value t.
FIG. 3 is a diagram showing a configuration of a digital data reproducing apparatus according to the present invention.
FIG. 4 is a diagram showing an example of operation waveforms by the digital data reproducing apparatus of the present invention.
FIG. 5 is a diagram showing an example of operation waveforms by the digital data reproducing apparatus of the present invention.
FIG. 6 is a diagram showing a configuration of a digital data reproducing apparatus according to another embodiment of the present invention.
FIG. 7 is a diagram showing an example of operation waveforms of a digital data reproducing apparatus according to another embodiment of the present invention.
FIG. 8 is a diagram showing a configuration of a digital data reproducing apparatus according to another embodiment of the present invention.
9 is a diagram showing a circuit configuration of a dropout compensation circuit 11. FIG.
10 is a diagram showing operation waveforms of the dropout compensation circuit 11. FIG.
FIG. 11 is a diagram showing a configuration of a digital data reproducing apparatus according to another embodiment of the present invention.
[Explanation of main part codes]
5 Adder 6 A / D Converter 8 Polarity Pulse Generation Circuit 9 Average Circuit 10 Subtractor 11 Dropout Compensation Circuit

Claims (5)

A digital data reproducing apparatus for reproducing digital data from a recording medium on which digital data is recorded,
A pickup that reads recorded information from the recording medium to obtain a read signal; an A / D converter that sequentially samples the read signal and converts it into a digital sample value;
Decoding means for decoding the digital data based on the sequence of the sample values;
A polarity pulse generating means for generating a polarity pulse signal of a predetermined voltage value having a polarity corresponding to the polarity of the sample value;
Average means for obtaining an average voltage of the polarity pulse signal and using this as an error voltage;
A digital data reproducing apparatus comprising: means for correcting an offset of the read signal by adding a correction voltage corresponding to the error voltage to the read signal. A digital data reproducing apparatus for reproducing digital data from a recording medium on which digital data is recorded,
A pickup that reads recorded information from the recording medium to obtain a read signal; an A / D converter that sequentially samples the read signal and converts it into a digital sample value;
Decoding means for decoding the digital data based on the sequence of the sample values;
Interpolation means for interpolating the sample values to obtain an interpolated sample value;
A polarity pulse generating means for generating a polarity pulse signal of a predetermined voltage value having a polarity corresponding to the polarity of the interpolation sample value;
Average means for obtaining an average voltage of the polarity pulse signal and using this as an error voltage;
A digital data reproducing apparatus comprising: means for correcting an offset of the read signal by adding a correction voltage corresponding to the error voltage to the read signal. The correction voltage, the digital data reproducing apparatus according to claim 1, wherein characterized in that the criteria voltage in the A / D converter is obtained by subtracting the error voltage. Dropout detecting means for detecting dropout, wherein the polarity pulse generating means outputs a pulse signal having a pulse duty of 50% to the polarity pulse signal when the dropout detecting means detects the occurrence of dropout. 3. The digital data reproducing apparatus according to claim 1, wherein the digital data reproducing apparatus is generated as follows. 5. The digital data reproducing apparatus according to claim 4, wherein the dropout detecting means stops the dropout detecting operation when the digital data reproducing apparatus itself is activated or during a special reproduction operation.

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