JPH05334802A - Digital signal reproducing device - Google Patents

Abstract

PURPOSE:To compensate the influence of asymmetry when a recording signal is not a DC free code by reproducing a digital signal making the central level between the projection waveform and the recessed waveform of a short run length pattern as a threshold value. CONSTITUTION:By a positive and a negative peak gates 73, 75, only while a gate signal is sent from a run length detection circuit 74, the digital signal supplied from an A/D converter 71 is supplied to an averaging means 76, 78 respectively. By a slice level generation means 77, the levels of the signal supplied to an input terminal (a) and the signal supplied to the input terminal (b) are added to supply the value of 1/2 thereof to a data slice circuit 72. By the data slice circuit 72, corresponding to when the value of the digital signal supplied from the A/D converter 71 is the value of the digital signal supplied from the slice level generation means 77 or avobe and when or below, the signal having a level '1' and the signal having a level '0' is outputted respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for reproducing digital signals recorded on a recording medium such as an optical disk.

[0002]

2. Description of the Related Art In a reproducing apparatus for a digital signal recorded on a recording medium, a read signal output from a pickup is subjected to a voltage comparison between the read signal level and a predetermined slice level. Signals corresponding to data "1" and "0" are output. At this time, in the optical disc system, there are various read signal variation factors such as a disc reflectance variation, a servo error, a variation of a low frequency component included in data, a variation of a read signal amplitude, and asymmetry. For example, according to the influence of asymmetry, in recording a certain information signal,
When the pit row having the pit length as shown in (a) is ideal, the pit actually recorded has a shorter pit length than that shown in FIG. 1 (a) as shown in FIG. 1 (b). 1
As shown in (c), the pit length becomes longer than that in FIG. 1 (a). Therefore, the read signal actually output from the pickup is different from that at the time of recording, and if a digital signal is output by comparing the voltage with a predetermined slice level, a read error will occur.

For example, when the recording data string as shown in FIG. 2A is recorded on the recording disk, the recording waveform is as shown in FIG. 2B. When there is no asymmetry, the pit shape formed on the disc is a faithful reflection of the recording waveform as shown in FIG. When this is reproduced by the pickup, the read signal waveform becomes a waveform having the level u as the center of amplitude, as shown in FIG. By slicing this read signal waveform at the center level u, the recorded waveform of FIG. 2B is correctly reproduced. On the other hand, when there is asymmetry, the pit shape becomes long and the portion where there is no pit becomes short as shown in FIG. As a result, the read signal waveform output from the pickup has a waveform with the level v as the center of amplitude, as shown in FIG. Due to the asymmetry, the central level v of the read signal waveform rises to a level higher than the central level u in FIG. Therefore, FIG.
The waveform obtained by slicing the signal waveform of (f) at level u is as shown in FIG. 2 (g), and a signal different from that of FIG. 2 (b) is reproduced. However, even if there is asymmetry, it can be seen that the recording waveform of FIG. 2B is correctly reproduced by slicing at the central level v of the read signal waveform. Therefore, in the conventional digital signal reproducing apparatus, a measure is taken by ATC (Automatic Threshold Control) so that the slice level is always set to an optimum value with respect to variations in these pit shapes.

FIG. 3 shows the configuration of a conventional disc playing device. In the apparatus shown in FIG. 3, EFM (Eight to Fourtee)
n Modulation) A disc recorded with a digital signal encoded by modulation is recorded as a pit train. The optical pickup 1 irradiates a light beam 1a onto an optical disc 3 which is driven to rotate by a spindle motor 2, photoelectrically converts the reflected light, and supplies the reflected light to a digital signal reproducing device 4. The digital signal reproducing device 4 supplies signals corresponding to "1" and "0" of digital data to the EFM demodulation circuit 5 according to the level of the supplied signal. The EFM demodulation circuit 5 uses the EF for the supplied signal.
M demodulation is performed and this demodulated signal is supplied to the error correction circuit 6. The error correction circuit 6 performs error correction on the supplied signal and outputs it as a reproduction information signal.

Next, the digital signal reproducing device 4 will be described. The data slice circuit 41 performs level slicing on the read signal from the optical pickup 1 with the level corresponding to the slice level set value 4a as a threshold, and outputs the output signal 4b as a data sampling circuit 42, a low-pass filter 43 and a polarity reversing circuit 44. Supply to each of. Here, the signal 4b has a level corresponding to "1" of the digital data when the level of the read signal is equal to or higher than the threshold value, and has a level corresponding to "0" of the digital data when the level is less than the threshold value. The low-pass filter 43 supplies the average level of the supplied signal to the input terminal a of the difference detection circuit 45. The polarity inverting circuit 44 inverts the waveform polarity of the supplied signal and supplies it to the low-pass filter 46. The low-pass filter 46 supplies the average level of the supplied signal to the input terminal b of the difference detection circuit 45. The difference detection circuit 45 subtracts the levels of the signal supplied to the input terminal a and the signal supplied to the input terminal b, and supplies the difference to the data slice circuit 41 as the slice level set value 4a.
The data sampling circuit 42 includes the data slice circuit 4
The signal 4b from 1 is sampled at a predetermined timing, and EFM is set as "1" and "0" of digital data.
It is supplied to the demodulation circuit 5.

In the configuration of the digital signal reproducing apparatus 4 as described above, the ATC is performed by paying attention to the fact that the EFM code is a DC-free code containing no DC component. That is, since it is a DC-free code, the sum of the pit length is equal to the sum of the lengths of the portions where no pits are present in the disc where the recording pits do not have asymmetry. Difference will occur. This difference is due to the output signal 4b of the data slice circuit 41 having a level corresponding to "1" of the digital data and "0".
Is detected as the difference with the time having the level corresponding to. Then, this time difference is detected as a voltage difference by the low-pass filter 43, the polarity inverting circuit 44, the low-pass filter 46, and the difference detection circuit 45. The slice level of the data slice circuit 41 is controlled by this voltage difference to reproduce the digital signal from the read signal while compensating for the asymmetry of the recording pit.

However, in the conventional digital signal reproducing apparatus having the above-mentioned structure, the code type of the recorded signal needs to be a DC-free code such as an EFM code, and is applicable when the code is not a DC-free code. There was a problem that I could not do it. That is, in the case of a DC-free code, the time when the signal 4b in FIG. 3 has the level corresponding to "1" of the digital data and the time when it has the level corresponding to "0" should be equal as described above. Therefore, it is possible to correctly control the slice level according to the degree of asymmetry. But D
If the code is not a C-free code, these two times are not always equal. Therefore, with the configuration shown in FIG. 3, it is impossible to detect the effect of asymmetry and compensate for it.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and even when the code type of the recording signal is not a DC-free code, the reading is performed while compensating for the influence of the asymmetry of the disk. It is an object of the present invention to provide a digital signal reproducing device capable of reproducing a digital signal from a signal.

[0009]

A digital signal reproducing device according to the present invention is a digital signal reproducing device for reproducing a digital signal from a read signal read from a recording medium on which the digital signal is recorded. A positive peak level detecting means for detecting a positive peak level of a signal changing in a relatively short cycle, and a negative peak level detecting means for detecting a negative peak level of a signal changing in a relatively short cycle of the read signal, Slice level generating means for generating central levels of the positive peak level and negative peak level, and data slicing means for performing data slicing on the read signal using the central level as a threshold value.

[0010]

The digital signal reproducing apparatus according to the present invention having the above-described structure has a positive peak level in a convex waveform of a signal pattern that changes in a relatively short cycle among the read signals output from the pickup, that is, a convex waveform of a short run length pattern. And the negative peak level in the concave waveform is detected. Next, the center level of the detected positive peak level and negative peak level is calculated, and data slicing is performed on the read signal at the obtained center level.

[0011]

EXAMPLES Examples of the present invention will be described below. FIG. 4 shows the configuration of a digital signal reproducing apparatus according to the present invention. The A / D converter 71 converts an input analog signal into a digital signal and supplies the digital signal to each of the data slice circuit 72, the positive peak gate 73, the run length detection circuit 74, and the negative peak gate 75. The run-length detection circuit 74 detects a change in the value of the supplied digital signal from rising to peak to falling during a relatively short predetermined period, and detects the change from rising to peak. The gate signal is provided to the positive peak gate 73 during generation.
Further, the run-length detection circuit 74 detects the change of the value of the supplied digital signal, that is, the decrease-peak point-rise, when it occurs in a relatively short predetermined period, and the decrease-peak point-rise is detected. The gate signal is provided to the negative peak gate 75 while the change is occurring. The positive peak gate 73 is
The digital signal supplied from the A / D converter 71 is supplied to the averaging means 76 only while the gate signal is being sent from the run length detection circuit 74. The averaging means 76 is
The average value of the values of the digital signal supplied from the positive peak gate 73 is supplied to the input terminal a of the slice level generating means 77. The negative peak gate 75 averages the digital signal supplied from the A / D converter 71 only while the gate signal is being sent from the run length detection circuit 74.
Supply to. The averaging means 78 supplies the average value of the digital signal values supplied from the negative peak gate 75 to the input terminal b of the slice level generating means 77. The slice level generation means 77 adds the levels of the signal supplied to the input end a and the signal supplied to the input end b and divides the addition result by 2 to supply the value to the data slice circuit 72. When the value of the digital signal supplied from the A / D converter 71 is equal to or more than the value of the digital signal supplied from the slice level generating means 77, the data slice circuit 72 has a signal level corresponding to "1" of the digital data. And when the value of the digital signal supplied from the A / D converter 71 is less than the value of the digital signal supplied from the slice level generation means 77, a signal having a level corresponding to “0” of the digital data is output. To do.

Next, the operation of the circuit having such a configuration will be described with reference to FIG.
The operation will be described with reference to the operation diagram.

When the read signal output from the optical pickup is a signal such as (c), the read signal (c)
Is converted into digital sample data by the A / D converter 71 as shown in (d). Run length detection circuit 74
In the level change of the digital sample data as shown in (d), this is detected when a change from rising to peak point to falling occurs in a relatively short predetermined period, and while this change is occurring (e ), A level "1" gate signal is generated. The positive peak gate 73 is the run length detection circuit 7
Only while the gate signal of level "1" is being transmitted from 4, the digital sample data as shown in (g) which is the signal of the digital sample data (d) is output. The averaging means 76 calculates the average of the values of the digital sample data and sends the average value (i). further,
In the level change of the digital sample data as shown in (d), the run length detection circuit 74 detects the change of the falling point, the peak point, and the rising point in a relatively short predetermined period, and this change occurs. During this period, a gate signal of level "1" as in (f) is generated. Negative peak gate 75
Outputs the digital sample data such as (h) in which the signal of the digital sample data (d) is passed only while the gate signal of level "1" is transmitted from the run length detection circuit 74. The averaging means 78 calculates the average of the values of the digital sample data and sends the average value (j). The slice level generation means 77
The levels (i) and (j) are added and the addition result is divided by 2 to output a value (k). Data slice circuit 72
Outputs a signal having a level corresponding to “1” of the digital data when each level of the sample data of the digital sample data (d) is equal to or higher than the level of (k), When each level of the sample data is less than the level of (k), a signal having a level corresponding to “0” of the digital data is output as in (l).

In the above embodiment, the averaging means 76 and 78 are independently provided after the outputs of the positive peak gate 73 and the negative peak gate 75, but as shown in FIG. The values of the digital sample data from the A / D converter 71 may be averaged by the averaging means 80 and supplied to the positive peak gate 73 and the negative peak gate 75.

As described above, in the digital signal reproducing apparatus of the present invention, of the read signals output from the pickup, the positive peak level in the convex waveform and the negative peak level in the concave waveform of the pattern with a short run length influence the asymmetry. Paying attention to the fact that it changes according to the degree of
The center level between the positive peak level and the negative peak level is detected, and the obtained center level is used as a threshold to perform data slicing on the read signal. Therefore, according to the digital signal reproducing apparatus of the present invention, the slice level can be correctly controlled according to the presence / absence of asymmetry and the size thereof, and the digital signal can be reproduced correctly.

[0016]

As described above, according to the digital signal reproducing apparatus of the present invention, the center of the positive peak level in the convex waveform and the negative peak level in the concave waveform of the pattern with a short run length in the read signal output from the pickup. Since the digital signal is reproduced by using the level as a threshold value, even if the code type of the recording signal is not a DC-free code, it is possible to reproduce the digital signal from the read signal while reducing the adverse effect due to the asymmetry of the recording pit. Can be done.

[Brief description of drawings]

FIG. 1 is a diagram showing changes in pit length due to asymmetry.

FIG. 2 is a diagram showing a change in a read signal waveform due to asymmetry.

FIG. 3 is a block diagram of a disk playing device.

FIG. 4 is a block diagram of a digital signal reproducing apparatus of the present invention.

FIG. 5 is an operation diagram of the digital signal reproducing apparatus of the present invention.

FIG. 6 is a block diagram of a digital signal reproducing apparatus according to another embodiment of the present invention.

[Explanation of symbols for main parts]

 73 Positive Peak Gate 74 Run Length Detection Circuit 75 Negative Peak Gate 77 Slice Level Generation Circuit

Claims (1)

[Claims] 1. A digital signal reproducing apparatus for reproducing a digital signal from a read signal read from a recording medium on which the digital signal is recorded, wherein the positive peak level of the signal that changes in a relatively short period among the read signals. Positive peak level detecting means, negative peak level detecting means for detecting a negative peak level of a signal that changes in a relatively short period of the read signal, and a center level of the positive peak level and the negative peak level. A digital signal reproducing apparatus, comprising: a slice level generating means for performing the data slicing;