JP3615914B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an exposure method and a method for manufacturing a semiconductor integrated circuit device using the same, and more particularly, an electron beam exposure capable of performing highly accurate exposure even when a wafer is set on a sample stage using an electrostatic adsorption method. The present invention relates to an exposure method for an apparatus and the like, and a method for manufacturing a semiconductor integrated circuit device using the same.
[0002]
[Prior art]
The inventor has examined an electron beam exposure method used in a method for manufacturing a semiconductor integrated circuit device. The following is a technique studied by the present inventor, and its outline is as follows.
[0003]
That is, in the electron beam exposure method, a wafer made of a semiconductor substrate or the like for manufacturing a semiconductor integrated circuit device is set (mounted) on a sample stage (sample stage) installed in a sample chamber in which a vacuum is maintained. ing.
[0004]
In addition, as a document describing the electron beam exposure apparatus (electron beam drawing apparatus), it is described in, for example, December 13, 1988, “December 1988 issue separate volume” p84 to p89 published by the Industrial Research Council. There is something that is.
[0005]
[Problems to be solved by the invention]
However, in the electron beam exposure method described above, the wafer is mounted on a sample stage installed in a sample chamber in which a vacuum is maintained, so that the wafer vacuum adsorption method used in an optical exposure apparatus is used. Therefore, the electrostatic adsorption method is used.
[0006]
Therefore, as a result of the study by the present inventors, when the wafer is set on the sample stage using the electrostatic adsorption method, a leakage current is generated there, the wafer is charged, and the electron beam of the electron beam exposure apparatus When patterning a resist film by exposing (drawing) the resist film with (electron beam), there is a problem that an error occurs in the pattern position of the patterned resist film.
[0007]
For this reason, when forming a pattern on a wafer made of a semiconductor substrate or the like for manufacturing a semiconductor integrated circuit device using the electron beam exposure method, there is a problem that the accuracy of the pattern position is lowered.
[0008]
An object of the present invention is to provide an exposure method such as an electron beam exposure apparatus capable of performing high-precision exposure even when a wafer is set on a sample stage using an electrostatic adsorption method, and manufacture of a semiconductor integrated circuit device using the same. It is to provide a method.
[0009]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
[0011]
In other words, the exposure method of the present invention can be applied to the top surface of a wafer when the wafer is set on a sample table placed in a sample chamber kept in a vacuum of an electron beam exposure apparatus using an electrostatic adsorption method. In the state where the conductive film is deposited on the resist film applied to the substrate, the wafer is set on the sample stage of the exposure apparatus, the conductive film is grounded, and the resist film is exposed.
[0012]
The method for manufacturing a semiconductor integrated circuit device according to the present invention includes a step of forming a pattern of the semiconductor integrated circuit device using the lithography technique and the selective etching technique using the exposure method described above.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description will be omitted.
[0014]
(Embodiment 1)
FIG. 1 is a schematic cross-sectional view for explaining an electron beam exposure method according to Embodiment 1 of the present invention.
[0015]
The electron beam exposure apparatus used in the electron beam exposure method of the present embodiment has a sample table 4 using an electrostatic adsorption method, and a wafer 1 as a sample to be exposed is set on the sample table 4. (Mounted) and fixed by an electrostatic adsorption method.
[0016]
In this case, the wafer 1 of the present embodiment is characterized in that a resist film 2 is applied on the surface, and a conductive film 3 as an electrostatic shield film is deposited on the resist film 2. .
[0017]
The wafer 1 of the present embodiment is a wafer as a conductor made of a semiconductor substrate made of silicon used in the manufacturing process of a semiconductor integrated circuit device.
[0018]
The wafer 1 of the present embodiment is mounted on the sample stage 4 and the conductive film 3 on the wafer 1 is electrically connected to the ground (earth) 10 by the grounding needle 12. In this case, the grounding needle 12 is electrically connected to the pallet holder 8 installed around the sample stage 4, and the pallet holder 8 is electrically connected to the ground 10 and is grounded (0 V). It is in a state.
[0019]
In the sample stage 4 of the present embodiment, an electrode 6 is disposed on an insulator 5 made of ceramic or the like, and a dielectric 7 made of silicon carbide or the like is disposed on the electrode 6. For example, the electrode 6 is electrically connected to one side of the power source 9 of 300 V via the resistor 11, and the ground 10 is electrically connected to the other side of the power source 9.
[0020]
In the electron beam exposure method of this embodiment, a conductive film 3 serving as an electrostatic shield film is deposited on a resist film 2 applied on a wafer 1, and the sample stage 4 of the electron beam exposure apparatus is used. A process is performed in which the wafer 1 is set, the conductive film 3 is grounded, and the resist film 2 is exposed by an electron beam (electron beam).
[0021]
Next, after the resist film 2 is exposed, the conductive film 3 is removed, and then the resist film 2 is developed and baked in a lithography technique to form a patterned resist film 2.
[0022]
In this case, a resist film 2 is applied to the surface of the wafer 1 of the present embodiment, and a conductive film 3 as an electrostatic shield film is deposited on the resist film 2.
[0023]
FIG. 2 is a graph showing the relationship between the film thickness of the conductive film 3 made of a poly compound, for example, isothianaphthenediyl-sulfonate, and the surface resistance value of the conductive film 3. As is clear from FIG. 2, when the film thickness of the conductive film 3 increases, the surface resistance value of the conductive film 3 decreases. In this case, the conductive film 3 is a conductive film deposited on the resist film 2 using an aqueous solution containing 1.4 wt% of the polyisocyanate isothianaphthenediyl-sulfonate and the surfactant. Yes.
[0024]
As a result of the study by the present inventor, by setting the surface resistance value of the conductive film 3 to 1 × 10 ⁵ Ω / cm ² or less, the wafer 1 has a leakage current of about 10 μA from the sample stage 4 having the electrostatic adsorption method. Charging can be completely shielded against an electron beam (electron beam).
[0025]
As a result, according to the electron beam exposure method of the present embodiment, the alignment accuracy (accuracy) of about 0.05 μm can be achieved, so that highly accurate exposure can be performed.
[0026]
FIG. 3 is a plan view showing alignment accuracy when the electron beam exposure method of the present embodiment is used. FIG. 4 is a plan view showing alignment accuracy when a conventional electron beam exposure method is used. 3 and 4, 1 indicates a wafer, C (C ₁ C ₂ C ₃ ..., C ₃₄ ,..., C ₃₆ ,...) Indicates a chip, and M (M ₁ M ₂ M ₃ .. M ₃₄ , M ₃₆ , and M are the pattern error of the patterned resist film 2 after exposure (the pattern error of the patterned resist film 2 when compared with the design specification pattern). Shows the shape).
[0027]
As the conductive film 3 of the present embodiment, a conductive film deposited on the resist film 2 using an aqueous solution containing 1.4 wt% of the polyisocyanate isothianaphthenediyl-sulfonate and the surfactant is applied. By doing so, the conductive film 3 can be deposited on the resist film 2 by an easy manufacturing process such as a spin coating method. In addition, since the conductive film 3 can be removed using an aqueous solution after the resist film 2 is exposed, the conductive film 3 can be removed by an easy manufacturing process.
[0028]
In addition, as another aspect of the conductive film 3 of the present embodiment, a conductive poly compound can be used in addition to the conductive film made of the above-described poly compound isothianaphthenediyl-sulfonate.
[0029]
According to the electron beam exposure method of the present embodiment described above, the conductive film 3 serving as an electrostatic shield film is deposited on the resist film 2 applied on the wafer 1, and the electron beam exposure apparatus is used. The wafer 1 is set on the sample stage 4, the conductive film 3 is grounded, and the resist film 2 is exposed by an electron beam (electron beam), so that 10 μA from the sample stage 4 having the electrostatic adsorption method is obtained. It is possible to shield the charging of the wafer 1 due to a leakage current of a certain degree against the electron beam.
[0030]
In this case, in particular, by setting the surface resistance value of the conductive film 3 to 1 × 10 ⁵ Ω / cm ² or less, the wafer 1 is charged with a leakage current of about 10 μA from the sample stage 4 having the electrostatic adsorption method. Can be completely shielded against wires.
[0031]
Therefore, according to the electron beam exposure method of the present embodiment, the accuracy (alignment accuracy) of 0.05 μm can be achieved, so that highly accurate exposure can be performed.
[0032]
(Embodiment 2)
5 to 10 are schematic cross-sectional views showing manufacturing steps of the semiconductor integrated circuit device according to the second embodiment of the present invention. The manufacturing method of the semiconductor integrated circuit device of this embodiment uses the electron beam exposure method of the first embodiment described above. The method for manufacturing the semiconductor integrated circuit device of the present embodiment will be specifically described with reference to FIG.
[0033]
First, as shown in FIG. 5, a p-type semiconductor substrate (wafer) 13 made of, for example, single crystal silicon is prepared, and a selective region on the surface of the semiconductor substrate 13 is thermally oxidized to be LOCOS (Local Oxidation of Silicon). An element isolation field insulating film 14 made of a silicon oxide film having a structure is formed.
[0034]
Next, the surface of the semiconductor substrate 1 is subjected to thermal oxidation or the like to form a silicon oxide film (gate insulating film) 15, and a CVD (Chemical Vapor Deposition) method is used to form a silicon oxide film 15 on the silicon oxide film 15. A crystalline silicon film 16 is deposited. In this case, the polycrystalline silicon film 16 becomes a gate electrode.
[0035]
Next, a silicon oxide film 17 is formed on the semiconductor substrate 13 using the CVD method, a resist film 18 is applied on the silicon oxide film 17, and a conductive film is then formed on the resist film 18. 19 is formed.
[0036]
In this case, the conductive film 19 is the conductive film of the first embodiment described above, and a resist film is formed using an aqueous solution containing 1.4 wt% of the polyisocyanate isothianaphthenediyl-sulfonate and the surfactant. 18 is a conductive film deposited on 18. Further, by setting the surface resistance value of the conductive film 19 to 1 × 10 ⁵ Ω / cm ² or less, the semiconductor substrate 13 is charged with an electron beam (electron beam) due to a leakage current of about 10 μA from the sample stage 4 having the electrostatic adsorption method. The film thickness of the conductive film 19 is set to 150 nm or more.
[0037]
Next, using the electron beam exposure method of the first embodiment described above, the resist film 18 is exposed (drawn) with an electron beam (electron beam) to serve as an etching mask for forming a gate electrode pattern. Exposure for forming a pattern of the resist film 18 is performed. Note that the resist film 18a in FIG. 5 indicates the resist film 18 in the exposed region.
[0038]
Next, as shown in FIG. 6, the conductive film 19 is removed using an aqueous solution, and then the resist film 18 is developed and baked by lithography to form a patterned resist film 18.
[0039]
Thereafter, using the patterned resist film 18 as an etching mask, the silicon oxide film 17 and the polycrystalline silicon film 16 are patterned using a selective etching technique such as dry etching. A pattern is formed as a gate electrode.
[0040]
In this case, the pattern of the gate electrode formed of the polycrystalline silicon film 16 is formed with high accuracy by using the lithography technique and the selective etching technique using the exposure method of the first embodiment described above. Therefore, the gate electrode can be formed with high accuracy and fine processing.
[0041]
Next, as shown in FIG. 7, a silicon oxide film is deposited on the semiconductor substrate 13 using the CVD method, and then an unnecessary region of silicon oxide is used using a lithography technique and a selective etching technique. The film is removed, and a sidewall insulating film (sidewall spacer) 20 made of a silicon oxide film is formed on the sidewall of the polycrystalline silicon film 16 as the gate electrode.
[0042]
Thereafter, n-type impurities such as phosphorus are ion-implanted into the semiconductor substrate 13 to form n-type semiconductor regions 21 as a source and a drain.
[0043]
Next, as shown in FIG. 8, after removing the silicon oxide film 15 as the gate insulating film whose surface on the n-type semiconductor region 21 as the source and drain is exposed, on the semiconductor substrate 13. A silicon oxide film (insulating film) 22 is formed.
[0044]
Thereafter, the resist film 23 applied on the silicon oxide film 22 is exposed using the electron beam exposure method of the first embodiment described above, and then the resist film 23 is patterned.
[0045]
Next, through holes (connection holes) 24 are formed in selective regions of the silicon oxide film 22 using a selective etching technique such as dry etching using the resist film 23 as an etching mask.
[0046]
In this case, as the silicon oxide film 22, for example, after a silicon oxide film is formed by a CVD method, surface polishing is performed and the surface is flattened to form a flattened silicon oxide film 22. For the planarization treatment, a mode in which the surface of the silicon oxide film 22 is planarized by, for example, an etch back method or a CMP (Chemical Mechanical Polishing) method can be employed.
[0047]
Therefore, by forming the pattern of the through hole 24 using the lithography technique and the selective etching technique using the exposure method of the first embodiment described above, the pattern can be formed with high precision exposure. Therefore, the through hole 24 can be formed with high accuracy and fine processing.
[0048]
Next, as shown in FIG. 9, a wiring layer 25 made of, for example, a conductive polycrystalline silicon layer is formed on the semiconductor substrate 13.
[0049]
Thereafter, the resist film 26 applied on the wiring layer 25 is exposed using the electron beam exposure method of the first embodiment described above, and then the resist film 26 is patterned.
[0050]
Next, using the resist film 26 as an etching mask, the wiring layer 25 is patterned using a selective etching technique such as dry etching.
[0051]
In this case, the wiring layer 25 is formed, for example, by forming a conductive polycrystalline silicon layer by a CVD method and then polishing the surface to planarize the surface, thereby forming the planarized wiring layer 25. For the planarization treatment, a mode in which the surface of the wiring layer 25 is planarized by, for example, an etch back method or a CMP method can be employed.
[0052]
Further, as a pre-process for forming the wiring layer 25, a mode in which a conductive material such as a conductive polycrystalline silicon film or tungsten is embedded in the through hole 24 to form a plug in the through hole 24 is applied. can do.
[0053]
Therefore, by forming the pattern of the wiring layer 25 using the lithography technique and the selective etching technique using the exposure method of the first embodiment described above, the pattern can be formed with high-precision exposure. Therefore, the wiring layer 25 can be formed with high accuracy and fine processing.
[0054]
Next, as shown in FIG. 10, after forming an insulating film 27 as an interlayer insulating film made of, for example, a silicon oxide film on the semiconductor substrate 13, the electron beam exposure method of the first embodiment described above is used. Through holes are formed in selective regions of the insulating film 27 using the conventional lithography technique and selective etching technique.
[0055]
In this case, as the insulating film 27 as an interlayer insulating film, for example, after a silicon oxide film is formed by a CVD method, the surface is polished and the surface thereof is flattened to form the flattened insulating film 27. For the planarization treatment, a mode in which the surface of the insulating film 27 is planarized by, for example, an etch back method or a CMP method can be employed.
[0056]
The insulating film 27 is, for example, a PSG (Phospho Silicate Glass) film that is a silicon oxide film containing phosphorus, a BPSG (Boro Phospho Silicate Glass) film that is a silicon oxide film containing boron and phosphorus, or a spin coating method. An insulating film having silicon oxide such as an SOG (Spin On Glass) film that can be formed by the above method can be used.
[0057]
Thereafter, after forming a wiring layer 28 made of, for example, an aluminum layer on the semiconductor substrate 1, the wiring layer 28 is formed by using the lithography technique and the selective etching technique using the electron beam exposure method of the first embodiment described above. Patterning.
[0058]
In this case, the wiring layer 28 is formed by, for example, forming an aluminum layer by sputtering, then polishing the surface and planarizing the surface, thereby forming the planarized wiring layer 28. For the planarization treatment, a mode in which the surface of the wiring layer 28 is planarized by, for example, an etch back method or a CMP method can be employed.
[0059]
After that, the manufacturing process of the semiconductor integrated circuit device is completed by forming the multi-layer wiring layer and then forming the passivation film by repeating the manufacturing process of the interlayer insulating film and the wiring layer described above according to the design specifications. To do.
[0060]
According to the manufacturing method of the semiconductor integrated circuit device of the present embodiment described above, the gate electrode formed of the polycrystalline silicon film 16 using the lithography technique and the selective etching technique using the exposure method of the first embodiment described above. Since the patterns such as the through hole 24 and the wiring layer 25 are formed, the pattern can be formed with high-precision exposure, so that high-yield production can be performed with high-precision and fine processing.
[0061]
According to the manufacturing method of the semiconductor integrated circuit device of the present embodiment, the gate electrode and the through-hole formed of the polycrystalline silicon film 16 using the lithography technique and the selective etching technique using the exposure method of the first embodiment described above. By forming patterns such as holes 24, wiring layers 25, etc., it is possible to achieve a lithography technique with high alignment accuracy and easy microfabrication, and various types of semiconductor integrated circuit devices that are microfabricated bodies and By applying it to various manufacturing processes, microfabrication can be performed with high accuracy and easily.
[0062]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0063]
For example, the exposure apparatus used in the exposure method of the present invention can use various exposure apparatuses such as an X-ray exposure apparatus and an SR (synchrotron radiation) exposure apparatus in addition to the electron beam exposure apparatus.
[0064]
In the method of manufacturing a semiconductor integrated circuit device using the exposure method of the present invention, a MOSFET, a CMOSFET, a bipolar transistor, or a BiMOS or BiCMOS in which a MOSFET and a bipolar transistor are combined on a wafer such as a semiconductor substrate or an SOI (Silicon on Insulator) substrate. A semiconductor element having a combination of various semiconductor elements such as a structure can be formed, and a memory system or a logic system such as a DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) using the semiconductor elements. The present invention can be applied to various semiconductor integrated circuit device manufacturing methods.
[0065]
【The invention's effect】
Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0066]
(1). According to the exposure method of the present invention, a conductive film as an electrostatic shield film is deposited on a resist film coated on a wafer, and is placed on a sample stage of an exposure apparatus such as an electron beam exposure apparatus. By setting the wafer, grounding the conductive film, and exposing the resist film with an electron beam (electron beam) or the like, the wafer is charged by a leakage current of about 10 μA from a sample stage having an electrostatic adsorption method. It can be shielded against electron beams.
[0067]
In this case, in particular, by setting the surface resistance value of the conductive film to 1 × 10 ⁵ Ω / cm ² or less, the wafer is charged to the electron beam by a leakage current of about 10 μA from the sample stage having the electrostatic adsorption method. And can be completely shielded.
[0068]
Therefore, according to the exposure method of the present invention, the accuracy (alignment accuracy) of about 0.05 μm can be achieved, so that highly accurate exposure can be performed.
[0069]
(2). According to the method for manufacturing a semiconductor integrated circuit device of the present invention, a pattern such as a gate electrode, a through hole formed in an insulating film, a wiring layer is formed using a lithography technique and a selective etching technique using the exposure method of the present invention. By forming the pattern, the pattern can be formed with high-accuracy exposure, so that it is possible to manufacture a high manufacturing yield with high accuracy and fine processing.
[0070]
(3). According to the method for manufacturing a semiconductor integrated circuit device of the present invention, a pattern of a multi-gate electrode, a through-hole formed in an insulating film, a wiring layer, etc., using the lithography technique and the selective etching technique using the exposure method of the present invention. Can be applied to various types and various manufacturing processes of semiconductor integrated circuit devices, which are microfabricated bodies, by being able to achieve lithography technology that enables high precision and easy microfabrication. Fine processing can be easily performed with high accuracy.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view for explaining an electron beam exposure method according to a first embodiment of the present invention.
FIG. 2 is a graph showing the relationship between the film thickness of a conductive film made of a poly compound, isothianaphthenediyl-sulfonate, and the surface resistance value of the conductive film.
FIG. 3 is a plan view showing alignment accuracy when the electron beam exposure method according to Embodiment 1 of the present invention is used.
FIG. 4 is a plan view showing alignment accuracy when a conventional electron beam exposure method is used.
FIG. 5 is a schematic cross sectional view showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of the present invention;
6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention; FIG.
FIG. 7 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device which is Embodiment 2 of the present invention;
FIG. 8 is a schematic cross sectional view showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of the present invention;
FIG. 9 is a schematic cross sectional view showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of the present invention;
FIG. 10 is a schematic cross sectional view showing a manufacturing process of the semiconductor integrated circuit device which is Embodiment 2 of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Wafer 2 Resist film 3 Conductive film 4 Sample stand 5 Insulator 6 Electrode 7 Dielectric 8 Pallet holder 9 Power supply 10 Ground (earth)
11 Resistor 12 Grounding Needle 13 Semiconductor Substrate (Wafer)
14 Field insulating film 15 Silicon oxide film (gate insulating film)
16 Polycrystalline silicon film (gate electrode)
17 Silicon oxide film 18 Resist film 19 Conductive film 20 Side wall insulating film 21 Semiconductor region 22 Silicon oxide film 23 Resist film 24 Through hole 25 Wiring layer 26 Resist film 27 Insulating film 28 Wiring layers C ₁ C ₂ C ₃ C ₃₄ , C ₃₆ Chip M ₁ M ₂ M ₃ M ₃₄ , M ₃₆ shaped resist pattern error

Claims (3)

Forming a resist film on the wafer; forming a conductive film on the resist film; fixing the wafer having the conductive film to a sample stage of an exposure apparatus using an electrostatic adsorption method; A step of forming a pattern of a semiconductor integrated circuit device using a lithography technique and a selective etching technique using an exposure method including a step of grounding a conductive film and a step of exposing the resist film using an electron beam thereafter DOO have a, electrodes used in the electrostatic adsorption is a single electrode, the electrostatic adsorption method of manufacturing a semiconductor integrated circuit device according to claim scheme der Rukoto not energizing the wafer. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the resist film is subjected to development processing and baking processing after the conductive film is removed. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the conductive film is made of a material that can be removed by an aqueous solution.

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