JP3614946B2 - Memory buffer device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory buffer device for memory reading and memory writing in a computer.
[0002]
[Prior art]
In computers based on existing technology, memory operations are basically performed by reading data (load instruction execution) and writing data (store instruction execution) to an arbitrary memory address in units of one word, half word, or 1/4 word. . For this reason, a small-scale computer has a one-word memory register, and when executing a load instruction, the data read from the memory device is stored in this register, and the CPU (central processing unit) takes it in and stores it. In instruction execution, data to be written is temporarily stored in a register and written in a memory device.
For this reason, in the load instruction execution, the memory access time is reflected on the instruction execution time as it is for each CPU request, and in the store instruction execution, the time until the write data is stored in the register from the CPU is reflected in the instruction execution time. . However, when a load instruction or a store instruction is executed immediately after execution of the store instruction, the next memory operation is waited for the memory write time associated with execution of the previous store instruction.
[0003]
In a large-scale computer, a cache memory is installed, and load instructions and store instructions are executed through the cache memory. As a result, the CPU exchanges data in units of words with the cache memory, and the memory device exchanges data of a plurality of words (hereinafter referred to as data blocks) arranged at continuous memory addresses with the cache memory. I do. As a result, when the data requested by the load instruction exists in the cache memory (hereinafter referred to as a load cache hit), the load instruction is completed in a short time by a high-speed data response from the cache memory, and the store instruction In the case where a data block including data to be written exists in the cache memory (hereinafter referred to as a store cache hit), the store instruction can be completed by executing only the data write to the cache memory.
[0004]
When the load instruction is not a load cache hit (hereinafter referred to as a load cache miss), or when the store instruction is not a store cache hit (hereinafter referred to as a store cache miss), the memory device access time is the same as in a small computer. Is reflected in the instruction execution time or the memory operation immediately after.
[0005]
[Problems to be solved by the invention]
As described above, in the memory operation in the computer according to the prior art, the access time of the memory device is directly reflected in the instruction execution time for each load instruction in a small-scale computer, and for the memory write operation accompanying the store instruction execution Since execution of a load instruction or a store instruction that is continuous to this is awaited, there is a large problem of performance degradation due to execution time of a memory operation instruction. In addition, since the memory operation is performed in units of one word, the improvement of the memory throughput due to the memory operation over continuous words such as high-speed page access prepared in the DRAM device cannot be utilized.
In particular, in recent high operating frequency CPUs, there is a tendency for the difference between the instruction execution time executed only inside the CPU and the execution time of the memory operation instruction to increase, and this is the reason for the program execution despite the improvement of the CPU operating frequency. This is the reason why performance does not increase.
[0006]
On the other hand, in a large-scale computer, the cache memory is installed to fill the gap between the CPU operation and the memory operation. However, the chip size, chip cost, and power consumption by incorporating the cache memory in the same LSI as the CPU. The increase in device cost, the device volume, and the power consumption due to the increase of the cache memory or the outside of the CPU-LSI is a problem.
Further, with the improvement of the CPU operating frequency, the access time of the cache memory cannot follow this, and the number of clock cycles for executing the memory operation instruction is increased while the cache memory is installed.
[0007]
In view of the above, it has been desired to realize a memory buffer device that can reduce cost and power consumption and can improve program execution performance.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problem, a memory buffer device according to a first aspect of the present invention includes a load buffer unit for reading data from a memory device, and a store buffer unit for writing to the memory device. , A load data buffer unit having a plurality of words independently readable and writable registers for storing data for one memory block, and any one of the registers in response to a data read request from the central processing unit to the memory device Is returned to the central processing unit, and if there is no corresponding data in any register, the memory device continuously sends the final data of the same memory block from the memory address of the read request data. Load buffer control unit that reads data up to address and stores them sequentially in registers The store buffer unit has a store data buffer unit including a first-in first-out buffer for storing a plurality of words as data for one memory block, and a write request to the memory device from the central processing unit in the first-in first-out buffer. When the corresponding data exists, it is updated, and the storage position is the last, and when the data of the same memory block of the corresponding data exists, the corresponding data is stored at the last, and the data in the first-in first-out buffer is When the memory block is different from the memory block of the corresponding data, the storage block control unit writes all the data stored in the first-in first-out buffer to the memory device and stores the data at the head position of the first-in first-out buffer. It is characterized by this.
[0009]
Since the memory buffer device according to the first aspect of the present invention is configured in this way, the load buffer unit has corresponding data in any of the registers in response to a data read request from the central processing unit to the memory device. If so, return it to the central processing unit. On the other hand, if there is no corresponding data in any register, the data from the memory address of the read request data to the last address of the same memory block is read from the memory device, and these are sequentially stored in the register. To do.
In response to a write request from the central processing unit to the memory device, the store buffer unit updates the corresponding data if it exists in the first-in first-out buffer, and sets the storage position at the end.
If the data in the same memory block as the write request data exists in the first-in first-out buffer, the corresponding data is stored at the end thereof.
On the other hand, if the data in the first-in first-out buffer is a memory block different from the memory block of the corresponding data, all the data stored in the first-in first-out buffer is written to the memory device, and the corresponding data is stored at the head position of the first-in first-out buffer. To store.
[0010]
In order to solve the above-described problem, the memory buffer device of the second invention includes a load buffer unit for reading data from the memory device, and a store buffer unit for writing to the memory device. , A load data buffer unit having a plurality of words independently readable and writable registers for storing data for one memory block, and any one of the registers in response to a data read request from the central processing unit to the memory device Is returned to the central processing unit, and if the corresponding data does not exist in any register, the entire memory block including the memory address of the read request data is read from the memory device. It consists of a load buffer control unit that reads and stores them in registers in sequence. The store data buffer unit has a first-in first-out buffer that stores a plurality of words as data for one memory block, and the corresponding data exists in the first-in first-out buffer in response to a write request from the central processing unit to the memory device. If the data is stored in the first-in / first-out buffer, the data is stored at the tail and the data is stored in the first-in first-out buffer. When the memory block is different from the block, it is characterized by comprising a store buffer control unit for writing all the data stored in the first-in first-out buffer to the memory device and storing the corresponding data at the head position of the first-in first-out buffer. To do.
[0011]
Since the memory buffer device according to the second aspect of the present invention is configured as described above, the load buffer unit has corresponding data in any of the registers in response to a data read request from the central processing unit to the memory device. If so, return it to the central processing unit. On the other hand, if there is no corresponding data in any register, the entire memory block including the memory address of the read request data is read from the memory device, and these are sequentially stored in the register.
The operation of the store buffer unit is the same as in the first invention.
[0012]
In order to solve the above-described problem, the memory buffer device of the third invention is the memory buffer device of the first or second invention, wherein the corresponding data in response to a data write request from the central processing unit to the memory device, In the case where it exists in any of the registers in the load data buffer unit, a load buffer control unit for updating this data is provided.
[0013]
Since the third invention is configured as described above, when there is a data write request from the central processing unit to the memory device, when the corresponding data exists in any of the registers in the load data buffer unit, Each time, only the data in the load data buffer unit is updated without writing to the memory device.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Embodiment 1
[Constitution]
FIG. 1 is a block diagram showing Embodiment 1 of the memory buffer device of the present invention and Embodiment 2 described later.
The illustrated apparatus shows a load buffer unit 100 and a store buffer unit 200, a central processing unit (hereinafter referred to as a CPU) 300, and a memory device 400 that constitute a memory buffer device.
[0015]
The load buffer unit 100 mainly works when executing a load instruction (memory read instruction) from the CPU 300, and the store buffer unit 200 works when executing a store instruction (memory write instruction) from the CPU 300.
That is, the load buffer unit 100 includes a load data buffer unit 101 having a plurality of words independently readable and writable registers for storing data for one memory block, and a plurality of registers in response to a memory read request from the CPU 300. If the corresponding data exists in any of the registers, it is returned to the CPU 300. If no corresponding data exists in any register, the memory device 400 continuously reads the same memory from the memory address of the data requested to be read. The load buffer control unit 102 reads out data up to the last address of the block and stores them sequentially in a register.
[0016]
When executing a load instruction, the CPU 300 asserts a request signal to the load buffer unit 100 (outputs “1”), negates a read / write signal (outputs “0”), and further sets a predetermined memory address. The address is output as follows. In response to this, the load buffer unit 100 asserts an acknowledge signal and outputs the load data requested by the CPU 300 to the CPU 300. When data is read from the memory device 400 when the load instruction is executed, a memory request is asserted from the load buffer unit 100 to the memory device 400, a memory read / write signal is negated, and a predetermined memory address is obtained. The memory address is output as follows.
In response to this, the memory device 400 asserts a memory acknowledge signal and outputs read data requested by the load buffer unit 100 to the load buffer unit 100.
[0017]
The store buffer unit 200 includes a store data buffer unit 201 having a first-in first-out buffer that stores a plurality of words as data for one memory block, and a write request from the CPU 300 to the memory device 400 in the first-in first-out buffer. When the corresponding data exists, it is updated, and the storage position is the last, and when the data of the same memory block of the corresponding data exists, the corresponding data is stored at the last, and the data in the first-in first-out buffer is When the memory block is different from the memory block of the corresponding data, all the data stored in the first-in first-out buffer is written in the memory device 400, and the corresponding data is stored at the head position of the first-in first-out buffer; It has.
[0018]
When executing a store instruction, the CPU 300 asserts a request signal to the store buffer unit 200 (outputs “1”), asserts a read / write signal (outputs “1”), and writes data to be written, that is, Store data is output, and an address is output so that a predetermined memory address is obtained. In response to this, the store buffer unit 200 asserts an acknowledge signal and outputs it to the CPU 300. When data is written to the memory at the time of execution of the store instruction, the memory request is asserted from the store buffer unit 200 to the memory device 400, the memory read / write signal is asserted, and the write data is set to become the data to be written. And a memory address is output so that a predetermined memory address is obtained. In response to this, the memory device 400 asserts a memory acknowledge signal and outputs it to the load buffer unit 100.
[0019]
FIG. 2 is a configuration diagram of the load buffer unit 100.
The load buffer unit 100 includes the load data buffer unit 101 and the load buffer control unit 102 as described above.
In the first embodiment, the load data buffer unit 101 includes a four-word data register (LB0 to LB3), a load buffer input selector 101a, and a load buffer output selector 101b. In the present invention, the number of data words is as follows. The number of words is not limited to four, and an arbitrary number of one or more words can be taken.
[0020]
In the first and second embodiments, the load data buffer unit 101 can temporarily store four words of memory data. One word of data read from the memory device 400 or two to two of the data read continuously. Stores 4 words of data. When the data stored in the data registers LB0 to LB3 includes a copy of the data stored in the memory address specified by the address from the CPU 300 when the load instruction is executed from the CPU 300, the memory device Data is not read from 400, and one of the outputs of the four data registers LB0 to LB3 for storing data specified by the CPU 300 is selected by the load buffer output selector 101b and output to the CPU 300 as load data.
[0021]
In addition, when the store instruction is executed, when data is read from the same memory address as that of the store data and stored in the data registers LB0 to LB3, a new one is stored to maintain data consistency. Store data must also be stored in the corresponding register. In the present embodiment, this is hereinafter referred to as a store bypass operation. The load buffer input selector 101a selects either read data at the time of reading from the normal memory device 400 or store data from the CPU 300 at the time of store bypass operation, and outputs the selected data to the data registers LB0 to LB3.
[0022]
The load buffer control unit 102 has a function of inputting / outputting control signals to / from the CPU 300 and the memory device 400 and controlling the load data buffer unit 101. A store bypass signal, LB 0 to 3 sets, and a load address offset signal are output from the load buffer control unit 102 to the load data buffer unit 101. The store bypass signal is an input selection signal to the load buffer input selector 101a. When it is “0”, read data is selected, and when it is “1”, store data is selected and output to LB0-3. The LB0 to 3 set signals are data set signals to the data registers LB0 to LB3, respectively, and input data is newly stored at the rising edge of this signal. The lower two bits (hereinafter referred to as a small address) of the address from the CPU 300 serve as a selection signal to the load buffer output selector 101b, and selects one of the outputs of LB0 to LB3.
[0023]
FIG. 3 is a configuration diagram of the load buffer control unit 102.
4 and 5 are configuration diagrams of the load data buffer valid flag portion and the LB0 to 3 set signal generation portions in FIG. 3, respectively.
The load buffer control unit 102 inputs / outputs control signals to / from the CPU 300 and the memory device 400, and controls the load data buffer unit 101. The load address control unit 102a, a load data buffer valid flag (hereinafter referred to as V) (Denoted as a flag) unit 102b, LB0 to 3 set signal generation unit 102c, and a sequence control unit.
[0024]
That is, the load buffer control unit 102 shown in these drawings includes AND circuits 1 to 21, OR circuits 31 to 35, buffers 41 to 44, block address buffer 45, offset address buffer 46, tag register 51, and V0 register (V0). ~ V3 register (V3), memory request register 52, small address selector 61, V flag selector 62, small address decoder 71, offset address decoder 72, small address decoder 73, offset address counter 81, and comparator 91.
[0025]
In FIG. 3, A1 indicates an acknowledge, A2 indicates a large address (block address), A3 indicates a read / write, A4 indicates a request, and A5 indicates a small address. B1 is a memory block address, B2 is a memory offset address, B3 is a memory request, B4 is memory read / write, B5 is memory busy, B6 is store bypass, B7 is memory acknowledge, and B8 to B11 are LB0 set to LB3 set. Is shown.
[0026]
The memory address coincidence checking unit 102 a is configured by a tag register 51 and a comparator 91.
The tag register 51 is a register for temporarily storing a signal (large address) excluding the lower 2 bits of the address input from the CPU 300, and a memory device for data of 1 to 4 words stored in the load data buffer unit 101. The block address arranged on 400 is held. The comparator 91 is an Ex-NOR circuit, and compares the large address (block address) stored in the tag register 51 with the value excluding the lower 2 bits of the address input from the CPU 300, and the two match. Check for no. That is, it is checked whether or not a part or all (four words) of a copy of data arranged at a block address input from the CPU 300 at the time of execution of a load instruction or a store instruction is stored in the load data buffer unit 101. It is. Hereinafter, a case where the above inspection results match is referred to as a load data buffer hit, and a case where the result is not the case is referred to as a load data buffer miss.
[0027]
As shown in FIG. 4, the V flag unit 102 b includes V0 to 3 registers (V0 to 3), a small address selector 61, a small address decoder 71, AND circuits 3 to 6, and a V flag selector 62.
The V0 to 3 registers (V0 to V3) have V0 to 3 flags for indicating whether or not the contents of the copy of the memory data stored in the LB0 to LB3 of the load data buffer unit 101 are valid. This corresponds to the data register specified by the lower 2 bits (hereinafter referred to as the small address) of the address input from the CPU 300 when the load data hits, that is, one of LB0 to LB. When the V flag is “1”, this indicates that the contents of the data register are valid.
[0028]
On the other hand, if the corresponding V flag is “0”, the data requested by the CPU 300 is not stored in the data registers LB0 to 3 even when the load data hits, and the memory device 400 is accessed. Need to read data. The small address selector 61 selects a 2-bit selection signal for selecting a register in which the V flag is to be set from the V0 to 3 registers V0 to V3. When storing in LB0-3, the output of the offset address counter 81 (sequence control unit) is selected, and the small address input from the CPU 300 is selected during the store bypass operation. The small address decoder 71 decodes the output of the small address selector 61. The AND circuits 3 to 6 take logical products of the output of the small address decoder 71 (one of the four outputs is “1”) and the output of the OR circuit 31 of the sequence control unit (described later). Are connected to the set inputs of the V0-3 registers V0-V3, respectively.
[0029]
At the time when the output of the OR circuit 31 is asserted, one of the AND circuits 3 to 6 becomes “1”, and one of the corresponding V0 to 3 registers V0 to V3 becomes “1” at the rising edge of this signal. Set. The other three of the V0 to V3 registers V0 to V3 store the previous contents. The reset inputs of the V0 to 3 registers V0 to V3 are connected to the output of the AND circuit 9 of the sequence control unit (the set input of the memory request register 52: described later), and V0 to V0 when the output of the AND circuit 9 is asserted. The contents of 3 are all “0”.
The V flag selector 62 selects and outputs one of the four outputs of the V0-3 registers V0-V3, and uses the small address input from the CPU 300 as a selection signal. If the output of the V flag selector 63 is “1” at the time of the load buffer hit, it indicates that a copy of the memory data requested by the CPU 300 with the load instruction is stored in the corresponding load data buffer unit 101.
[0030]
As shown in FIG. 5, the LB0-3 set signal generation unit 102c includes an offset address decoder 72, a small address decoder 73, AND circuits 14-21, and OR circuits 32-35, and load data buffers LB0-3 LB0-3. A data set signal is generated.
[0031]
The offset address decoder 72 decodes the 2-bit output of the offset address counter 81 of the sequence control unit. The offset address counter 81 is the lower two bits of the memory address when reading data from the memory device 400. The offset address counter 81 is a position in the memory block where data is actually read from the memory device 400 (hereinafter referred to as the memory offset). ).
[0032]
The AND circuits 14 to 17 each perform a logical product of the output of the offset address decoder 72 (any one of the four outputs becomes “1”) and the AND circuit 11 (described later) of the sequence control unit. Therefore, a set signal for storing the read data read from the memory device 400 in the corresponding registers of the data registers LB0 to LB3 is generated.
[0033]
The small address decoder 73 decodes the 2-bit small address input from the CPU 300, and is one of the data registers LB0 to LB3 corresponding to the data write position (memory offset) in the memory block during the store bypass operation. To choose one.
[0034]
The AND circuits 18 to 21 each perform a logical product of the output of the small address decoder 73 (any one of the four outputs becomes “1”) and the AND circuit 13 (described later) of the sequence control unit. Therefore, a set signal for bypassing the store data input from the CPU 300 during the store bypass operation and storing it in the corresponding registers of the data registers LB0 to LB3 is generated.
The OR circuits 32 to 35 take the logical sum of the outputs of the AND circuits 14 to 17 and the AND circuits 18 to 21, respectively. The outputs of the OR circuits 32 to 35 are sent to the data registers LB0 to LB3 as LB0 to 3 set signals. Each is output.
[0035]
The sequence control unit performs input / output of control signals to / from the CPU 300 and the memory device 400, performs read operation control on the memory device 400, and controls operation of the load data buffer unit 101. The sequence circuits 1-2 shown in FIG. 7-13, memory request register 52, buffers 41-44, block address buffer 45, offset address buffer 46, OR circuit 31, and offset address counter 81.
[0036]
In the sequence control unit, first, the AND circuit 1 performs a logical product of the request signal from the CPU 300 and the inverted signal of the read / write signal to generate a read request signal. The read / write signal indicates read when “0” and write when “1”. Therefore, when the read request signal is “1”, it is recognized that the load instruction is executed from the CPU 300.
[0037]
In the AND circuit 2, the logical product of the request signal from the CPU 300, the read / write signal, and the output of the comparator 91 of the memory address match checking unit 102a (hereinafter, this output is referred to as a tag match signal) is obtained. Is generated. When the store bypass signal is asserted, a store bypass operation is performed. That is, the store bypass operation is performed because the write instruction and the block address match.
[0038]
The AND circuit 7 performs an AND operation between the output of the comparator 91 of the address match checking unit 102a and the valid signal that is the output of the V flag selector 62 of the V flag unit 102b. When the output of the AND circuit 7 is “1”, it indicates that a copy of the data in the memory device 400 arranged at the address input from the CPU 300 exists in the corresponding registers of the data registers LB0 to LB3. That is, the load data buffer hits and the V flag is “1”.
[0039]
The AND circuit 8 performs a logical product of the output of the AND circuit 7 and the output of the AND circuit 1 (read request signal). When the output of the AND circuit 8 is “1”, data reading from the memory device 400 is not performed, and this signal is output to the CPU 300 by the buffer 41 as a drive acknowledge signal. At this time, the load buffer output selector 101b in the load buffer unit 100 of FIG. 2 selects the data register output specified by the small address input from the CPU 300 from the data registers LB0 to LB3, and sends it to the CPU 300 as load data. Output.
[0040]
Here, the acknowledge signal and the request signal are in a handshake relationship. That is, the request signal is asserted by the CPU 300, and the memory buffer device operates. When this is completed, an acknowledge signal is asserted in the memory buffer device. The CPU 300 negates the request signal when the acknowledge signal is asserted. In the memory buffer device, the acknowledge signal is negated when the request signal is negated. In the state where the acknowledge signal is negated, the CPU 300 asserts the next memory request.
As described above, the memory request signal and the acknowledge signal are used to synchronize the operation for each data access of one word between the CPU 300 and the memory buffer device.
[0041]
In the AND circuit 9, the logical product of the inverted signal of the output of the AND circuit 7, the read request signal output from the AND circuit 1, and the inverted signal of the memory busy is obtained. This output indicates that the data that needs to be read by the load instruction from the CPU 300 does not exist in the load data buffer unit 101 and the memory device 400 is accessible at that time.
The memory busy signal is a signal common to the load buffer unit 100 and the store buffer unit 200. The memory request register 52 is set to “1” (hereinafter, set to “1”) when the output of the AND circuit 9 is asserted when either of them is accessing the memory device 400. That it is set is simply set, and that it is set to “0” is reset). In other words, since the load data buffer is missed, it is necessary to read out the data requested by the CPU 300 from the memory device 400, and the memory device 400 is activated by setting the memory request register 52.
[0042]
The output of the AND circuit 9 is further connected to the clock input of the tag register 51, the reset input of the V0-3 registers V0 to V3, and the load input of the offset address counter 81. The tag register 51 newly stores a large address input from the CPU 300 when the output of the AND circuit 9 is asserted, that is, when the memory request register 52 is set.
The output of the tag register 51 is driven by the block address buffer 45 while the M request signal output from the memory request register 52 is asserted, and is output to the memory device 400 as a memory block address. The V0-3 registers are all cleared when a new memory access to the memory device 400 is started, that is, when the output of the AND circuit 9 is asserted, and the contents thereof become “0”.
[0043]
The offset address counter 81 sets a 2-bit small address input from the CPU 300 when the output of the AND circuit 9 is asserted. The output of the offset address counter 81 is driven by the offset address buffer 46 and is output to the memory device 400 as a memory offset address. This signal is input to the offset address decoder 72, and becomes a selection signal for LB0 to LB3 when the read data from the memory device 400 is stored in the load data buffer unit 101. Further, this signal is input to the small address selector 61 and becomes a selection signal for the V0-3 registers V0-V3 when the V flag is set when read access to the memory device 400 is performed.
[0044]
The M request signal that is the output of the memory request register 52 is ANDed with the inverted signal of the memory acknowledge in the AND circuit 12, is driven by the buffer 42, and is output to the memory device 400 as a memory request signal. The memory acknowledge signal is a signal input from the memory device 400. When this signal is asserted, it indicates that a predetermined operation in the memory device 400 is completed. The memory request signal is a signal common to the load buffer unit 100 and the store buffer unit 200, and indicates that either of them requests access to the memory device 400.
[0045]
The memory request signal and the memory acknowledge signal have a handshake relationship. That is, the memory request signal is asserted in the memory buffer device (load buffer unit 100 or store buffer unit 200), and the memory device 400 operates. When this is completed, the memory device 400 asserts a memory acknowledge signal. In the memory buffer device, when the memory acknowledge signal is asserted, the memory request signal is negated. The memory device 400 negates the memory acknowledge signal when the memory request signal is negated. The memory buffer device asserts the next memory request in a state where the memory acknowledge signal is negated. As described above, the memory request signal and the memory acknowledge signal are used to synchronize operations for each data access of one word between the memory buffer device and the memory device 400. Therefore, the two signals are turned on and off every memory cycle.
[0046]
The inverted signal of the M request is driven by the buffer 43 and output to the memory device 400 as a memory read / write signal. The memory read / write signal is “0” while the M request signal is “1”. The M request signal is driven by the buffer 44 and asserts a memory busy signal. The memory read / write signal and the memory busy signal are not turned on / off every memory cycle, and are continuously driven while the M request signal is asserted. These are asserted for 1 to 4 memory cycles in order to make consecutive memory accesses in the memory block between the memory buffer device and the memory device 400.
[0047]
The M request signal is further connected to an input of the AND circuit 11 and a selection input of the small address selector 61. The AND circuit 11 performs an AND operation between the M request signal and the memory acknowledge signal. This output indicates that the read access operation in the memory device 400 is completed by asserting this signal as a read acknowledge signal. The small address selector 61 selects and sets any one of the V0 to V3 registers, selects the output of the offset address counter 81 at the time of read access to the memory device 400, and sets the store bypass. Sometimes a small address input from the CPU 300 is selected and output to the small address decoder 71. An M request signal is used as a selection signal for this purpose.
[0048]
The read acknowledge signal, which is the output of the AND circuit 11, is connected to the input of the AND circuit 10, the input of the OR circuit 31, the clock input of the offset address counter 81, and the inputs of the AND circuits 14-17. The AND circuit 10 performs a logical product of the read acknowledge signal and the output 3 of the offset address decoder 72 (asserted when the input signal is “11”). The output of the AND circuit 10 is a read signal, and by asserting this signal, read access is started from the data requested by the CPU 300 from the memory device 400 and the maximum memory address of the memory block, that is, the lower 2 bits of the memory address is “11”. Indicates that read access has been completed.
[0049]
The read signal is input to the reset input of the memory request register 52, and the memory request register 52 is reset when the signal rises. The output M request signal is negated.
In the OR circuit 31, the logical sum of the read acknowledge signal and the output of the AND circuit 13 is taken. The output of the OR circuit 31 is input to the AND circuits 3 to 6 of the V flag unit 102b, and becomes a timing signal for asserting the set input to the V0 to 3 registers V0 to V3.
[0050]
The read acknowledge signal that is the output of the AND circuit 11 is used as a V flag set timing signal when the memory device 400 is read-accessed. The offset address counter 81 is used to generate an offset address to be output to the memory device 400 and to count the number of cycles when memory access is continuously performed. In the first embodiment, in memory access, data arranged from the memory address in which a load buffer miss occurs to the maximum address of the memory block is continuously read-accessed and stored in the load data buffer unit 101.
[0051]
The AND circuit 13 takes a logical product of the store bypass signal and the acknowledge signal. The acknowledge signal at this time is driven and asserted by the store buffer unit 200 when the store instruction is executed. The output of the AND circuit 13 is connected to the input of the OR circuit 31 and the inputs of the AND circuits 18 to 21 of the LB0 to 3 set signal generation unit 102c. The OR circuit 31 is input as a V flag set timing signal during store bypass. The AND circuits 18 to 21 serve as timing signals for asserting LB0 to 3 set signals for bypassing store data input from the CPU 300 and storing in the load data buffer unit 101 during store bypass.
[0052]
FIG. 6 is a configuration diagram of the store buffer unit 200.
As described above, the store buffer unit 200 includes the store data buffer unit 201 and the store buffer control unit 202.
The store data buffer unit 201 includes a queue (FIFO: first-in first-out memory). In this embodiment, a 4-word data register (SB0-3), four small address registers (2 bits each: SB0-3A), and three data selectors (SB1-3B) are connected in series to store data The part of the queue that stores the lower 2 bits of the write destination memory address, that is, the small address, and the contents of the small address input from the CPU 300 and already stored in the small address registers SB0 to 3A. Although it is composed of matchers SB0 to 3C that perform comparison with the contents of the small address, in the present invention, the number of data words is not limited to four words, and it is possible to take an arbitrary number of one or more words. .
[0053]
When the large address input when executing the store instruction from the CPU 300, that is, the value excluding the lower 2 bits of the memory address, and the address of the write destination memory block of the data stored in the queue, that is, the memory block address are the same In this case, data is not written to the memory device 400, and new store data and an offset address in the write destination memory block (hereinafter simply referred to as an offset address), that is, input from the CPU 300 are input at the end of the queue. Write the contents of the small address.
[0054]
At this time, the data already stored in the queue and the offset address are shifted toward the head of the queue for one word. When both the memory block address and the offset address are equal to the large address and small address input from the CPU 300, that is, store data to the same memory address as the memory address given by the store instruction is already stored in the queue. If so, the data is overwritten with subsequent store data. That is, new store data for the same memory address is stored in the queue without actually being written to the memory device 400.
[0055]
The match check between the large address and the memory block address is performed by the store buffer control unit 202, and the match check between the small address and the memory offset address is performed by the matchers SB0 to 3C. When the match is confirmed in any of the matchers SB0 to 3C, the matchers SB0 to 3C corresponding to the matched store buffers SB (collectively referring to the data registers SB0 to 3 and the small address registers SB0 to 3A) are stored. Either is asserted.
When new data is stored in the queue, the data selectors SB0 to 3B select store data and small addresses input from the CPU 300 for the input to the store buffer SB, and other store buffers. For SB, the output of the next store buffer SB is selected and output.
[0056]
The store buffer control unit 202 inputs / outputs control signals to / from the CPU 300 and the memory device 400 and controls the store data buffer unit 201.
The store buffer control unit 202 outputs the SB0-3 clock signal and the SB1-3 set signal to the store data buffer unit 201, and the store data buffer unit 201 outputs the SB0-3 match signal to the store buffer control unit 202. Is output. The SB0-3 clock signals are clock signals for the data registers SB0-3 and small address registers SB0-3A. The data registers SB0 to SB3 and the small address registers SB0 to 3A store inputs at the rising edge of the clock signal. The SB1 to 3 set signals are selection signals for the data selectors SB1 to SB3. When “1”, the store data input from the CPU 300 and the small address are selected. When “0”, the subsequent signals connected in series are selected. Select the output of the register. The SB0-3 match signal is “1” when the matcher inputs match the output signals of the matchers SB0-3C.
[0057]
FIG. 7 is a configuration diagram of the store buffer control unit 202.
FIG. 8 is a configuration diagram of the store buffer signal generation unit 202b in FIG.
In these figures, the store buffer control unit 202 inputs / outputs control signals to / from the CPU 300 and the memory device 400 and controls the store data buffer unit 201. The memory address match check unit 202a, the store buffer signal The generation unit 202b and a sequence control unit are included.
[0058]
That is, the store buffer control unit 202 shown in these drawings includes AND circuits 1 to 18, OR circuits 31 to 40, buffers 41 to 43, block address buffer 44, tag register 51, memory request register 52, selectors 63 to 66, A write buffer tail decoder 74, a write buffer pointer 82, and a comparator 91 are provided.
In FIG. 7, A1 is a large address, A2 is an acknowledge, A3 is a request, A4 is a read / write, A5 to A8 are SB0 match to SB3 match, B1 is a memory block address, B2 is a memory read / write, B3 is a memory busy, B4 is a memory request, B5 is a memory acknowledge, B6 to B8 are SB1 set to SB3 set, and B9 to B12 are SB0 clock to SB3 clock.
[0059]
The memory address match checking unit 202a has the same configuration and operation as the memory address match check unit 102a of the load buffer control unit 102 shown in FIG. Description of is omitted.
[0060]
The store buffer signal generation unit 202b is a circuit that generates SB0-3 clocks and SB1-3 set signals. As shown in FIG. 8, the write buffer tail decoder 74, AND circuits 12-14, and OR circuits 35-40 , Selectors 63 to 66 and AND circuits 15 to 18.
The write buffer tail decoder 74 is a 2-4 decoder, and decodes a 2-bit input signal indicating the last position of the write data buffer queue composed of the store buffer SB counted by the write buffer pointer 82 of the sequence control unit. Therefore, the store buffer SB corresponding to one of the four outputs asserted is the tail of the queue.
[0061]
The AND circuits 12 to 14 generate SB1 to 3 set signals, and 1 to 3 outputs of the write buffer tail decoder 74 (asserted when the input is “01”, “10”, and “11”, respectively). The logical product with the output (described later) of the AND circuit 1 of the sequence control unit is obtained. Here, when there is a signal “1” among the outputs of the AND circuits 12 to 14, store data and small addresses input from the CPU 300 are selected in the data selectors SB 1 to 3 B of FIG. SB1 to SB3 and small address registers SB1 to 3A are input to corresponding registers.
[0062]
On the other hand, since the data register SB0 and the small address register SB0A are installed at the entrance of the queue, the subsequent registers are not connected to the input. Accordingly, when data is stored in the data register SB0 and the small address register SB0A, store data and a small address input from the CPU 300 are always input.
[0063]
The OR circuits 35 to 37 select generation of SB0 to 3 clock signals to be output to the store buffer SB when new data is stored in the queue and when the contents of the queue are shifted out and written to the memory device 400. This is the part that takes logic. When new data is stored in the queue, the clock signal is supplied to the store buffer SB connected before the register indicated by the value of the write buffer pointer 82, that is, in the head direction of the queue. Also, when the contents of the queue are shifted out and written to the memory device 400, only the data already stored in the queue is shifted in the head direction unless new data to be written from the outside is input from the CPU 300. To do. Therefore, also in this case, the clock signal is supplied to the store buffer SB connected before the register indicated by the value of the write buffer pointer 82, that is, in the head direction of the queue. By taking such logic in the OR circuits 35 to 37, invalid data is not stored in the queue even when the contents of the queue are written to the memory device 400.
[0064]
In the OR circuits 38 to 40, selection of SB0 to 3 clock signal generation in the case of executing a store instruction for the same memory address as the write memory address in the memory device 400 of data already stored in the queue is performed. In this case, in order to overwrite the queue contents, SB0-3 clock signals are generated in accordance with one to four signals asserted among the SB0-3 matches input from the store data buffer unit 201.
[0065]
That is, when only the store buffer SB0 is asserted, only the SB0 clock is generated, and when only the store buffer SB1 or both the store buffers SB0 and SB1 are asserted, the SB0 clock and the SB1 clock are generated. If only store buffer SB2, both store buffers SB2, SB1, or three store buffers SB2, SB1, and SB0 are asserted, three of SB0 clock, SB1 clock, and SB2 clock are generated and stored Only the buffer SB3, both the store buffers SB3 and SB2, the three store buffers SB3, SB2 and SB1, or the store buffer SB3, SB2, SB1 and the store buffer SB0 are all asserted when the SB0 clock is asserted. , SB1 clock, SB2 clock, and SB3 all clocks are generated.
[0066]
As a result, newly written data is stored at the tail end of the queue indicated by the write buffer tail signal (output of the write buffer pointer 82), and the original store data is overwritten on the subsequent store data.
The selectors 63 to 66 are selection circuits for signals generated through the two systems of SB0 to 3 clock generation selection circuits. When the output (described later) of the AND circuit 3 of the sequence control unit is “1”, that is, the queue When the store data stored in is overwritten, the outputs of the OR circuits 38 to 40 and the SB3 match signal are selected and output to the AND circuits 15 to 18. On the other hand, when the output of the AND circuit 3 is “0”, that is, when new store data is stored in the queue, or when the store data stored in the queue is sequentially written in the memory device 400, The 0 output of the write buffer tail decoder 74 and the OR circuits 35 to 37 are selected and input to the AND circuits 15 to 18. The AND circuits 15 to 18 AND the outputs of the selectors 63 to 66 and the output (described later) of the OR circuit 34 of the sequence control unit, and output SB0 to 3 clocks to be output to the store data buffer unit 201. Generate. The output of the OR circuit 34 is a signal that determines the assert timing of the clock supplied to the store buffer SB.
[0067]
The sequence control unit performs input / output of control signals to / from the CPU 300 and the memory device 400, controls writing operation to the memory device 400, and controls operation of the store data buffer unit. The sequence control unit includes AND circuits 1 to 11, OR circuits 31 to 34, a memory request register 52, buffers 41 to 43, a block address buffer 44, and a write buffer pointer 82 shown in FIG.
[0068]
In the sequence control unit, first, the AND circuit 1 calculates the logical product of the request signal from the CPU 300 and the read / write signal, and generates a write request signal. When the write request signal is “1”, it is recognized that the store instruction is executed from the CPU 300. In addition, the OR circuit 31 calculates the logical sum of all the SB0-3 match signals input from the store data buffer unit 201. The output of the OR circuit 31 is an offset address match signal, and the store data buffer unit 201 (queue) is newly written in the lower 2 bits of the memory address requested by the CPU 300, that is, the same address within the memory block as the small address. For example, this signal is asserted when store data for a memory offset address is already stored in the queue.
[0069]
The AND circuit 2 takes a logical product of the output of the comparator 91 of the memory address match checking unit 202a and the inverted signal of the offset address match output from the OR circuit 31. The output of the AND circuit 2 is that the tag match signal is “1”, that is, the contents of the memory block address stored in the tag register 51 and the contents of the large address input from the CPU 300 are the same, but the small address and the queue This means that the contents of the memory offset addresses stored in the small address registers SB0 to 3A do not match. That is, this is a case where a store instruction for writing to a new intra-block offset address of the same memory block as the store data stored in the queue is executed. In this case, the input store data and the contents of the small address are stored in the queue. The storage destination store buffer SB at this time is indicated by a write buffer tail signal that is an output of the write buffer pointer 82.
[0070]
The AND circuit 3 takes the logical product of the output of the comparator 91 of the memory address match checking unit 202a and the offset address match signal. The output of the AND circuit 3 is asserted as an address match signal when the address input from the CPU 300 matches the memory address stored in the tag register 51 and the queue. In this case, the store data already stored in the queue is overwritten, and the store data newly input from the CPU 300 is stored at the end of the queue specified by the write buffer tail signal.
[0071]
The AND circuit 4 takes a logical product of the inverted signal of the output of the comparator 91 of the memory address coincidence inspection unit 202a, the write request signal that is the output of the AND circuit 1, and the memory busy signal. The memory busy signal is a signal common to the load buffer unit 100 and the store buffer unit 200 as described in the load buffer unit 100.
[0072]
The AND circuit 5 calculates the logical product of the output of the AND circuit 1 and the output of the AND circuit 2, and outputs an enqueue signal. The AND circuit 6 calculates the logical product of the output of the AND circuit 1 and the output of the AND circuit 3, and outputs an overwrite signal. The output of the AND circuit 3 is used as a selection signal for the selectors 63 to 66 of the store buffer signal generation unit 202b. The enqueue signal is output to the OR circuit 34 and the OR circuit 32. The overwrite signal is input to the OR circuit 34. The OR circuit 34 takes a logical sum of these two signals and an output (described later) of the AND circuit 10, and outputs a shift timing signal.
[0073]
The shift timing signal is input to the AND circuits 15 to 18 of the store buffer signal generation unit 202b, and gives the assert timing of the SB0 to 3 clock signals. The shift timing signal is further output to the AND circuit 7. The AND circuit 7 calculates the logical product of the write request signal and the shift timing signal, is driven by the buffer 41, and outputs the result as an acknowledge signal to the CPU 300. The output of the AND circuit 4 is output to the set input (S input) of the memory request register 52 and the OR circuit 32. The memory request register 52 is set at the rising edge of the set input and asserts the M request signal. Similar to the M request signal of the load buffer control unit 102, the M request signal is an activation signal for performing write access to the memory device 400.
[0074]
The M request signal drives the output of the tag register 51 as an enable signal of the block address buffer 44, outputs the memory large address to the memory device 400, is driven by the buffer 42, and outputs the memory read / write signal to the memory device 400. Then, it is output to the AND circuit 11 and logically ANDed with the inverted signal of the memory acknowledge input from the memory device 400, driven by the buffer 43, and output to the memory device 400 as a memory request signal.
[0075]
The memory request signal and the memory acknowledge signal are handshake signals as described in the load buffer unit 100. The M request signal is further output to the AND circuit 10. The AND circuit 10 calculates the logical product of the M request signal and the memory acknowledge signal, and outputs a write acknowledge signal. The write acknowledge signal is a signal indicating that the operation for the request signal for the memory write access request output from the store buffer unit 200 is completed, and it is recognized that the memory operation is completed at the rising edge of this signal.
[0076]
The output of the AND circuit 10, that is, the write acknowledge signal is output to the OR circuit 34, the AND circuit 8, and the AND circuit 9. The OR circuit 34 generates a shift timing signal. When the write acknowledge signal is asserted and input to the OR circuit 34, it indicates that the write access to the memory device 400 is completed. The shift timing signal is asserted and output to the AND circuits 15 to 18 to give the assert timing of the SB0 to 3 clock signals. The shift timing signal is output to the AND circuit 7.
When the write acknowledge signal is asserted, the shift timing signal is asserted, and when the AND output with the write request is asserted in the AND circuit 7, the acknowledge signal for the execution of the store instruction accompanied with the writing to the memory device 400 Is asserted, driven by the buffer 41, and output to the CPU 300. The acknowledge signal in this case is asserted when the first word of the store data buffer (queue) is completely written to the memory device 400.
[0077]
The output of the AND circuit 10, ie, the write acknowledge signal, is ANDed with the output of the write buffer tail decoder 74, ie, the last access signal, in the AND circuit 8, and the AND circuit 9 performs the AND operation on the last access signal. The logical product with the inverted signal is taken. The output of the AND circuit 8 is a write to an old memory data block stored in a store data buffer (queue) to the memory device 400 (different from the write destination memory data block of data newly requested by the CPU 300). Asserted upon completion of the last memory access. The output of the AND circuit 9 is asserted when memory access other than the last of the memory write is completed. The output of the AND circuit 8 is a write-dan signal, and is output to the reset input of the memory request register 52 and the OR circuit 33. The output of the AND circuit 9 is output to the OR circuit 32.
[0078]
The memory request register 52 is reset when the reset input rises. When the memory request register 52 is reset, the M request signal is negated, thereby completing one to four memory writes to the memory device 400 and negating the memory busy signal. The OR circuit 32 takes the logical sum of the output of the AND circuit 4, that is, the set input to the memory request register 52, and the output of the AND circuit 9, and the output is an up input to the write buffer pointer 82. Connected to. The OR circuit 33 takes the logical sum of the output of the AND circuit 5, that is, the enqueue signal, and the output of the AND circuit 8, that is, the write-in signal, and the output is a down input to the write buffer pointer 82. Connected.
[0079]
The write buffer pointer 82 generates a 2-bit write buffer tail signal for indicating the tail end of the store data buffer (queue). The counting operation by the write buffer pointer 82 is shown below. Store data buffers are numbered in the order of 3, 2, 1, 0 from the head position (exit). Therefore, the queue structure entry (not necessarily the tail; the tail is the queue entry during operation) is zero. The tail of the queue usually indicates an SB to which data can be written next. Therefore, the write buffer pointer is updated when data is inserted (one number is decreased), and is prepared for the next data insertion, and is updated when data is written to the memory device 400 (one number is increased).
[0080]
[A. Initial state, ie immediately after power-on]
Since no data is written, it becomes 3.
[B. When executing a store instruction to the same memory block as the contents of the tag register]
(B-1. When the small address is the same as one of the small address registers SB0 to 3A): Since data is overwritten, there is no increase or decrease.
(B-2. When the small address is not the same as any of the small address registers SB0 to 3A): 1 is subtracted because data is inserted.
[0081]
[C. When executing a store instruction to a memory block different from the contents of the tag register]
{Circle around (1)} First, it is incremented by 1 (data insertion into the queue and shifting of the original queue content toward the head, ie, preparation of a pointer for shifting out the queue content of one word).
{Circle around (2)} A write access to the memory device 400 is performed, and is incremented by 1 each time a memory acknowledge is asserted (a pointer is prepared to shift out the queue contents. Write data to a new memory block is inserted). The increase continues until the pointer value becomes 3.
(3) When the value of the pointer is 3, when the memory acknowledge signal is asserted during memory write access, 1 is subtracted to 2, and the memory write access is completed. That is, all the write data to the previous memory block is written to the memory device 400, the write data to the new memory block advances to the head of the queue, and the pointer value becomes 2 in preparation for the insertion of the next data ( The second SB2 from the head of the queue is shown).
[0082]
In the above description, the output of the AND circuit 5, that is, the enqueue signal is asserted at b-1, the output of the AND circuit 4 is asserted at c- <1>, and the AND circuit 9 at c- <2>. And the output of the AND circuit 8, that is, the write-dan signal is asserted, and the up-input or down-input of the write buffer pointer 82 via the OR circuit 32 or the OR circuit 33. And the necessary counting operation is performed by the write buffer pointer 82.
[0083]
[Operation]
9 to 11 are explanatory diagrams showing the operation of the first embodiment. FIG. 9 shows the operation during loading, and FIGS. 10 and 11 show the operation during storage.
When executing the load instruction, the contents of the V flag (“1”) in the case where the contents of the tag register 51 of the load buffer unit 100 and the contents of the large address input from the CPU 300 match or do not match, and the large address matches. The operation differs depending on whether it is valid or invalid when “0”.
[0084]
When the store instruction is executed, the contents of the tag register 51 of the store buffer unit 200 and the contents of the large address input from the CPU 300 match or do not match, and these and the memory offset address stored in the queue and the CPU 300 input. The operation differs depending on whether the contents of the small addresses match or do not match. Furthermore, when the store instruction is executed, the operation is further different depending on whether the contents of the tag register 51 of the load buffer unit 100 and the contents of the large address input from the CPU 300 match or do not match. 9 to 11 show combinations and operations of these.
[0085]
12 and 13 are time charts at the time of execution of a load instruction in the first embodiment and a second embodiment to be described later.
FIG. 12 shows an operation in the case of a buffer hit. In this case, the memory device 400 is not read-accessed, and necessary data in the load data buffer unit 101 is selected and output to the CPU 300. In FIG. 12, the request signal and the acknowledge signal have a handshake relationship. The large address, small address, and read / write signal are correct values while the request signal is asserted. The load data is correct at the rising edge of the acknowledge signal.
[0086]
FIG. 13 shows an operation in the case of a buffer miss. In this case, the memory device 400 is read-accessed, and the data requested by the CPU 300 is output to the CPU 300 and stored in the load data buffer unit 101. Further, after the memory address at which the CPU 300 performs read access to the memory device 400, the memory device 400 continues to the last data of the memory block (consisting of four words in the first embodiment and the second embodiment described later). And stored in the corresponding register of the load data buffer unit 101. The assertion of the acknowledge signal to the CPU 300 and the output of the load data are determined when the data read from the memory device 400 is input in the first memory read access, that is, when the memory acknowledge signal is asserted in response to the assertion of the first memory request signal. .
[0087]
FIG. 13 shows an operation when the content of the small address is “00”, that is, when a load instruction is executed for data arranged at the beginning of the memory block. In this case, the read access is performed from the data arranged at the beginning of the memory block in which the load buffer is missed, and all the four word memory blocks are continuously read and sequentially stored in the corresponding registers of the load data buffer unit 101. . In FIG. 13, the request signal and the acknowledge signal have a handshake relationship. The large address, small address, and read / write signal are correct values while the request signal is asserted. Further, the memory block address, the memory offset address, and the memory read / write signal are correct values while the memory request signal is asserted. The memory read data has a correct value at the rise time of the memory acknowledge signal and at the rise time of the LB0 to 3 set signals. The load data is correct at the rising edge of the acknowledge signal.
[0088]
14 and 15 are time charts at the time of execution of a store instruction according to the first embodiment and the second embodiment to be described later.
FIG. 14 shows a case of a buffer hit. In this case, the write access to the memory device 400 is not performed, and only the write data is stored in the store data buffer (queue). In FIG. 14, the request signal and the acknowledge signal have a handshake relationship. The large address, small address, read / write signal, and store data are correct values while the request signal is asserted.
[0089]
FIG. 15 shows an operation in the case of a buffer miss. In this case, write access is continuously made to the memory device 400, and write data already stored in the queue is written to the memory block of the memory device 400. In addition, store data input from the CPU 300 is newly stored in the queue. The assertion of the acknowledge signal to the CPU 300 is determined when the data at the head of the queue is completely written to the memory device 400 by the first memory write access, that is, when the memory acknowledge signal is asserted in response to the assertion of the first memory request signal. In FIG. 15, the request signal and the acknowledge signal have a handshake relationship. The large address, small address, read / write signal, and store data are correct values while the request signal is asserted. Further, the memory block address, the memory offset address, the memory read / write signal, and the memory write data are correct values while the memory request signal is asserted and at the rising edge of the SB0-3 clocks.
[0090]
[effect]
As described above, in the first embodiment, the memory buffer device includes the load data buffer unit 101 of multiple words, the store data buffer unit 201 (queue) of multiple words, and the control units. For example, a memory buffer device can be configured with a small-scale circuit such that a separate memory unit for storing data is not required as compared with a cache memory. As a result, it is possible to secure an operation speed that can sufficiently follow the increase in the operating frequency of the CPU 300, and the LSI chip area including the CPU 300 and the memory buffer device of the present invention is configured by the CPU and the cache memory according to the prior art. This can be significantly reduced compared to an LSI that has a low cost and can reduce power consumption.
[0091]
In addition, when a buffer miss occurs during execution of a load instruction, a memory access operation for a plurality of words is performed from the memory device 400. Therefore, the access frequency of the CPU 300 to the memory device 400 can be reduced, and the memory throughput can be improved. Therefore, the program execution performance can be improved.
[0092]
Further, in the first embodiment, when a buffer miss occurs at the time of executing the load instruction, read access from the memory address to the last address of the same memory block is performed and stored in the load buffer unit 100. Therefore, there are the following effects.
By continuously accessing only the data that precedes the memory address where the error occurred (in the direction of increasing memory address), the entire block is always read for the execution of a program with high forward reference frequency, such as array operations. The memory access cycle can be reduced as compared with the case where it is started. That is, if there is a high probability that the memory reference is performed continuously from the target address of the immediately preceding memory reference or forward several words away (in the direction in which the memory address increases), the target address of the immediately preceding memory reference This is because data access in the backward direction (in the direction in which the memory address decreases) is rare, and these data are not unnecessarily read from the memory device 400.
[0093]
<< Embodiment 2 >>
[Constitution]
In the second embodiment, the overall configuration is the same as that shown in FIG. 1 and the configuration shown in FIG. Further, the store buffer unit is the same as the configuration shown in FIGS.
The present embodiment differs from the first embodiment in the configuration of the load buffer control unit, which is as follows.
[0094]
FIG. 16 is a configuration diagram of a load buffer control unit according to the second embodiment.
That is, the present embodiment is different from the load buffer control unit 102 of the first embodiment in that a memory access counter 83 is newly installed. Since the configuration other than this point is the same as that of the first embodiment, the corresponding parts are denoted by the same reference numerals and the description thereof is omitted.
[0095]
The difference between the second embodiment and the first embodiment is only the operation when a buffer miss occurs during execution of a load instruction. In such a case, in the first embodiment, an operation of continuously reading from the memory device 400 to the data at the last address of the memory block continuously from the memory address in which a miss occurs is stored in the corresponding register of the load data buffer unit 101. Went. In contrast, in the second embodiment, the data at the last address of the memory block continuously from the memory address where the miss occurred and the data at the memory address immediately before the memory address where the miss occurred from the data at the head address of the memory block. Until that is, that is, the entire data of one memory block is read and accessed from the memory device 400 and stored in the corresponding register of the load data buffer unit 101.
[0096]
For this purpose, two counters, an offset address counter 81 and a memory access counter 83, are installed as shown in FIG. The offset address counter 81 generates an offset address in the memory block to which read access is performed, and counts the number of access cycles for performing data read access for one memory block. The count clock input of the memory access counter 83 is the same signal as the count clock input of the offset address counter 81, and is the same as the read acknowledge signal of the load buffer control unit 102 shown in FIG.
[0097]
The load input of the memory access counter 83 is the same signal as the load input of the offset address counter 81 and is the same as the set input to the memory request register 52 of the load buffer control unit 102 shown in FIG. At this time, the memory access counter 83 is always loaded with “00”. The carry output of the memory access counter 83 is asserted when the 2-bit counter overflows, that is, when it becomes 4. As a result, it is recognized that data of four words, which are data for one memory block, have been continuously read from the memory device 400. This signal is a last access signal, ANDed with the read acknowledge signal by the AND circuit 10, and its output becomes a reset signal for the memory request register 52 to reset the memory request register 52. The last access signal has the same role as the load buffer control unit 102 of the first embodiment shown in FIG.
By installing the memory access counter 83, in the case of a buffer miss, the entire memory block in which the miss has occurred, that is, data access for four words is continuously performed on the memory device 400.
[0098]
FIGS. 17 to 19 are explanatory diagrams showing the operation of the second embodiment. FIG. 17 shows the operation during loading, and FIGS. 18 and 19 show the operation during storage.
The operation of the memory buffer device according to the second embodiment is different from the operation of the memory buffer device according to the first embodiment shown in FIGS.
In the second embodiment, in the case of a load buffer miss, the entire memory block (4 words) including the memory address that is always a miss is read from the memory device 400 and stored in the corresponding register of the load data buffer unit 101. In the memory access, the load V flag is always “1”. Therefore, when the contents of the tag register 51 of the load buffer unit 100 match the contents of the large address input from the CPU 300, a buffer hit is always caused. In this case, data from the corresponding register of the load data buffer unit 101 is transferred to the CPU 300. Output.
[0099]
On the other hand, if the contents of the tag register 51 and the contents of the large address input from the CPU 300 do not match, a buffer miss occurs, so that data corresponding to one memory block from the memory device 400 continues from the memory address in which the miss occurred. The first read data is output to the CPU 300, and the data (4 words) for one memory block is stored in the corresponding register of the load data buffer unit 101. The operation at the time of executing the store instruction is the same as the operation of the memory buffer device of the first embodiment shown in FIGS.
[0100]
Further, the timing of each signal at the time of execution of the load instruction and the execution of the store instruction in the second embodiment is the same as the state shown in FIGS. However, in the second embodiment, even if the content of the small address is any value from “00” to “11”, the read access is performed from the data arranged at the beginning of the memory block in which the load buffer miss occurs. All four word memory blocks are successively read and sequentially stored in the corresponding registers of the load data buffer.
[0101]
[effect]
As described above, in the second embodiment, similarly to the first embodiment, it is possible to reduce the cost and reduce the power consumption, and when a buffer miss occurs when the load instruction is executed, Since the read access of the data of the entire memory block including the memory address having the miss is performed and stored in the load buffer unit 100, the following effects are obtained.
By continuously accessing the entire memory block including the memory address that caused the miss, for example, for the execution of a program having a high forward reference frequency and a backward reference frequency such as operations using a stack, the entire block is By constantly reading, the total number of buffer misses can be reduced. That is, the memory reference is the same level of memory access to the front (memory address increasing direction) and backward (memory address decreasing direction) that are consecutive or several words away from the target address of the immediately preceding memory reference. When there is a probability, the memory throughput can be maximized by continuously accessing from the memory device 400 data of the maximum number of words that can be continuously accessed and stored in the buffer at a time.
[0102]
【The invention's effect】
As described above, according to the memory buffer device of the first aspect of the present invention, the load data buffer unit having a register of a plurality of words, the store data buffer unit having a first-in first-out buffer of a plurality of words, and these control units are configured. Therefore, for example, a memory buffer device can be configured with a small-scale circuit such that a separate memory unit for storing data is not required as compared with a cache memory. As a result, it is possible to ensure an operation speed that can sufficiently follow the increase in the operating frequency of the CPU, and the LSI chip area including the CPU and the memory buffer device of the present invention is configured by the CPU and the cache memory according to the prior art. This can be significantly reduced compared to an LSI that has a low cost and can reduce power consumption.
[0103]
In addition, when a buffer miss occurs during the execution of the load instruction, the memory access operation of a plurality of words is performed from the memory device, so that the access frequency of the CPU to the memory device can be reduced, and the memory throughput can be improved. Therefore, it can contribute to the improvement of the program execution performance.
[0104]
Furthermore, when a buffer miss occurs during execution of a load instruction, read access from the memory address to the last address of the same memory block is performed and stored in the load buffer unit. effective.
By continuously accessing only the data that precedes the memory address where the error occurred (in the direction of increasing memory address), the entire block is always read for the execution of a program with high forward reference frequency, such as array operations. The memory access cycle can be reduced as compared with the case where it is started.
[0105]
According to the memory buffer device of the second invention, similarly to the first invention, the load data buffer unit having a register of a plurality of words, the store data buffer unit having a first-in first-out buffer of a plurality of words, and these control units are constituted. Therefore, there are the same effects as the first invention. Further, when a buffer miss occurs at the time of executing the load instruction, the data read access of the entire memory block including the memory address in which the miss occurred is performed and stored in the load buffer unit. effective. In other words, by continuously accessing the entire memory block including the memory address in which a mistake has occurred, for example, for a program execution in which the forward reference frequency and backward reference frequency are as high as operations using a stack, The total number of buffer misses can be reduced by always reading the whole.
[0106]
According to the memory buffer device of the third invention, in response to a data write request from the central processing unit, if the corresponding data exists in any of the registers in the load data buffer unit, this data is updated. Therefore, in such a case, it is not necessary to access the memory device, and therefore the program execution performance can be improved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing first and second embodiments of a memory buffer device of the present invention.
FIG. 2 is a configuration diagram of a load buffer unit of the memory buffer device of the present invention.
FIG. 3 is a configuration diagram of a load buffer control unit according to the first embodiment of the memory buffer device of the present invention;
FIG. 4 is a configuration diagram of a load data buffer valid flag unit in the first embodiment of the memory buffer device of the present invention;
FIG. 5 is a configuration diagram of an LB0 to 3 set signal generation unit in the first embodiment of the memory buffer device of the present invention;
FIG. 6 is a configuration diagram of a store buffer unit in the first embodiment of the memory buffer device of the present invention;
FIG. 7 is a configuration diagram of a store buffer control unit in the first embodiment of the memory buffer device of the present invention;
FIG. 8 is a configuration diagram of a store buffer signal generation unit in the first embodiment of the memory buffer device of the present invention;
FIG. 9 is an explanatory diagram of an operation (when loading) in the first embodiment of the memory buffer device of the present invention;
FIG. 10 is an explanatory diagram (part 1) of an operation (during storage) in the first embodiment of the memory buffer device of the present invention;
FIG. 11 is an explanatory diagram (part 2) of the operation (during storage) in the first embodiment of the memory buffer device of the present invention;
FIG. 12 is a time chart (buffer hit) when a load instruction is executed in the memory buffer device of the present invention;
FIG. 13 is a time chart (buffer miss) when a load instruction is executed in the memory buffer device of the present invention.
FIG. 14 is a time chart (buffer hit) when a store instruction is executed in the memory buffer device of the present invention.
FIG. 15 is a time chart (buffer miss) when a store instruction is executed in the memory buffer device of the present invention;
FIG. 16 is a configuration diagram of a load buffer control unit in the second embodiment of the memory buffer device of the present invention;
FIG. 17 is an explanatory diagram of an operation (when loading) in the second embodiment of the memory buffer device of the present invention;
FIG. 18 is an explanatory diagram (part 1) of an operation (during storage) in the second embodiment of the memory buffer device of the present invention;
FIG. 19 is an explanatory diagram (part 2) of the operation (during storage) in the second embodiment of the memory buffer device of the present invention;
[Explanation of symbols]
100 Load buffer section
101 Load data buffer
102 Load buffer control unit
200 Store buffer
201 Store data buffer
202 Store buffer control unit

Claims (3)

A load buffer unit for reading data from the memory device, and a store buffer unit for writing to the memory device,
The load buffer unit
A load data buffer unit having a plurality of independently read / write registers for storing data for one memory block;
In response to a data read request from the central processing unit to the memory device, if the corresponding data exists in any of the registers, return it to the central processing unit,
If no corresponding data exists in any register, data from the memory device to the last address of the same memory block is read continuously from the memory address of the data of the read request, and these are sequentially stored in the register. The load buffer control unit
The store buffer unit
A store data buffer unit having a first-in first-out buffer for storing a plurality of words as data for one memory block;
In response to a write request from the central processing unit to the memory device, if the corresponding data exists in the first-in first-out buffer, it is updated, and the storage position is the last, and the same memory block of the corresponding data is stored. If data exists, store the data at the end,
When the data in the first-in first-out buffer is a memory block different from the memory block of the corresponding data, all the data stored in the first-in first-out buffer is written to the memory device and the corresponding data is stored in the first-in first-out buffer. A memory buffer device comprising: a store buffer control unit storing at a head position. A load buffer unit for reading data from the memory device, and a store buffer unit for writing to the memory device,
The load buffer unit
A load data buffer unit having a plurality of independently read / write registers for storing data for one memory block;
In response to a data read request from the central processing unit to the memory device, if the corresponding data exists in any of the registers, return it to the central processing unit,
When there is no corresponding data in any register, the load buffer control unit reads out the entire memory block data including the memory address of the data of the read request from the memory device, and stores them sequentially in the register And consist of
The store buffer unit
A store data buffer unit having a first-in first-out buffer for storing a plurality of words as data for one memory block;
In response to a write request from the central processing unit to the memory device, if the corresponding data exists in the first-in first-out buffer, it is updated, and the storage position is the last, and the same memory block of the corresponding data is stored. If data exists, store the data at the end,
When the data in the first-in first-out buffer is a memory block different from the memory block of the corresponding data, all the data stored in the first-in first-out buffer is written to the memory device and the corresponding data is stored in the first-in first-out buffer. A memory buffer device comprising: a store buffer control unit storing at a head position. The memory buffer device according to claim 1 or 2,
In response to a data write request from the central processing unit to the memory device, when the corresponding data exists in any of the registers in the load data buffer unit, a load buffer control unit is provided for updating the data. A memory buffer device.

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