JP3607505B2 - Digital image correction device - Google Patents

Description

また、水平ライン数ｍが５２５ラインのとき、垂直走査周期をｎ分割、たとえば２５６分割したときの間隔に相当する周期ａは、下式（２）で示される。
【００５７】

この周期ａをｎ倍、たとえば２５６倍したときの周期ｂは、下式（３）となる。
【００５８】

したがって、下式（４）に示すように、周期ｂの逆数をとることによって、垂直走査周期ｆｖが求まる。
【００５９】

このように、上記式（４）で求まる垂直走査周波数ｆｖは、ＶＧＡ入力に対応する垂直走査周波数（５９．９４０Ｈｚ）と同一であり、ゆえに、上記した方法によって垂直走査周期をｎ分割することにより、垂直走査周期をｎ分割したときの間隔に相当するタイミング信号が得られる。
【００６０】
上記コンパレータ２３_{１ −２} から出力されるタイミング信号はカウンタ２３_２ に供給され、このカウンタ２３_２ によりｎ回（たとえば、２５６回）カウントされることによって、２５６分割された垂直走査同期が再生される。
【００６１】
そして、このカウンタ２３_２ の計数値がコンパレータ２３_３ に供給されることにより、上記計数値は、第１のコンパレータ２３_{３ −１} および第２のコンパレータ２３_{３ −２} において、調整ポイント位置ＰＡの位置データまたは調整ポイント位置ＰＢの位置データと比較される。
【００６２】
この比較の結果、位置データとカウンタ２３_２ の計数値とが一致するタイミングで、第１のコンパレータ２３_{３ −１} または第２のコンパレータ２３_{３ −２} より、ラッチ回路２３_４ に対してタイミング信号が出力される。
【００６３】
これにより、第１のラッチ回路２３_{４ −１} および第２のラッチ回路２３_{４ −２} において、各タイミングでの、上記水平ラインカウンタ２１の計数値（水平ラインカウント値）が保持される。
【００６４】
こうして、第１のラッチ回路２３_{４ −１} および第２のラッチ回路２３_{４ −２} により水平ラインカウント値がラッチされると、領域・係数演算回路２３_５によって、それぞれにラッチされた水平ラインカウント値と上記水平ラインカウンタ２１の水平ラインカウント値とにもとづいて、垂直走査方向の水平走査位置に対応した領域・係数データの算出が行われる。
【００６５】
以上のようにして、垂直同期信号と水平同期信号とから、垂直走査方向の水平走査位置に対応する領域・係数データを得ることができる。なお、この領域・係数データの算出方法の詳細については、たとえば特願平８−９８４２６号を参照されたい。
【００６６】
上記したように、ディジタル画像補正装置において、アナログ要素を排除でき、アナログ要素に対するディジタルノイズ対策を不要にできるようにしている。すなわち、垂直走査方向の水平走査位置を検出する手段として、垂直偏向電流を検出するのではなく、垂直同期信号と水平同期信号とから演算によって垂直走査方向の水平走査位置に対応した領域・係数データを算出するようにしている。これにより、アナログ要素を用いることなく、ディジタル画像補正装置をすべてディジタル回路により構成できるようになる。したがって、集積化する際の、ＬＳＩ面積の増大やアナログ要素にありがちな製造過程における性能ばらつきが発生するといった問題を回避することが可能となるものである。
なお、この発明は上記した実施の一形態に限定されるものではなく、発明の要旨を変えない範囲において、種々変形実施可能なことは勿論である。
【００６７】
【発明の効果】
以上、詳述したようにこの発明によれば、アナログ要素を用いることなく、すべてディジタル回路により構成でき、集積化にとって好適なディジタル画像補正装置を提供できる。
【図面の簡単な説明】
【図１】この発明の実施の一形態にかかる、マルチスキャン・カラーＣＲＴモニタの概略構成を示すブロック図。
【図２】同じく、上記カラーＣＲＴモニタに用いられるディジタル画像補正装置における、領域・係数データ演算部の構成例を示すブロック図。
【図３】従来技術とその問題点を説明するために示す、マルチスキャン・カラーＣＲＴモニタの概略ブロック図。
【符号の説明】
１１…カラーＣＲＴ
１２…ビデオアンプ
１３…垂直偏向ヨーク
１４…垂直偏向回路
１５…垂直画像補正回路
１６…インターフェース部
２１…水平ラインカウンタ
２２…垂直周期検出回路
２３…領域・係数データ演算部
２３_１ …１／ｎ回路
２３_{１ −１} …カウンタ
２３_{１ −２} …コンパレータ
２３_{１ −３} …クリア回路
２３_２ …カウンタ
２３_３ …コンパレータ
２３_{３ −１} …第１のコンパレータ
２３_{３ −２} …第２のコンパレータ
２３_４ …ラッチ回路
２３_{４ −１} …第１のラッチ回路
２３_{４ −２} …第２のラッチ回路
２３_５ …領域・係数演算回路
２４…補間演算回路
２５_１ ２５_ｎ …ＤＡＣ
２６…ＤＲＡＭ
２７…クロック発生回路
２８…タイミング発生回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital image correction apparatus, and in particular, a color image display apparatus having a plurality of display modes having different scanning frequencies, such as a multi-system TV using a color CRT and a multi-scan (or multi-sync) CRT monitor. It is used in a so-called color display.
[0002]
[Prior art]
As is well known, in a color image display device having a plurality of display modes, a deviation of convergence (beam convergence deviation due to a difference in distance from each cathode electrode of RGB to a CRT phosphor screen scanning point) is different for each display mode. The amount of distortion and the amount of various distortions of the image are different. This is because the scanning frequency in each display mode is different. Therefore, when performing convergence correction and various image distortion corrections, in order to automatically perform appropriate correction for each display mode, the position of the screen (vertical scanning) used as a reference for correcting the image using some means. It is necessary to detect the horizontal scanning position).
[0003]
As means for detecting the horizontal scanning position in the vertical scanning direction, for example, a digital image correcting apparatus as shown in FIG. 3 is known (see Japanese Patent Application No. Hei 8-98426). That is, FIG. 3 shows a schematic configuration of a conventional multi-scan color CRT monitor provided with a vertical deflection digital image correction apparatus. In the case of this color CRT monitor, for example, a video amplifier 102 for amplifying video signals is connected to the color CRT 101. A vertical deflection yoke 103 and a vertical convergence deflection yoke 104 are attached to the color CRT 101, respectively.
[0004]
A vertical deflection circuit 105 is connected to the vertical deflection yoke 103, and a vertical deflection signal is supplied through the vertical deflection circuit 105.
An interface unit 106 is connected to the vertical deflection circuit 105. The interface unit 106 can designate a plurality of adjustment point positions in the vertical scanning direction on the display screen of the color CRT 101, and can set a digital signal corresponding to a vertical deflection current corresponding to the adjustment point positions. It is possible.
[0005]
On the other hand, a digital image correction device 200 is connected to the vertical convergence deflection yoke 104, and an analog image correction signal for correcting convergence correction and image distortion in the vertical scanning direction is supplied from the digital image correction device 200. It has become so.
[0006]
In the digital image correction apparatus 200, for example, the vertical deflection current detection circuit 201 detects the vertical deflection current flowing through the vertical deflection yoke 103. The vertical deflection current (analog value) detected by the vertical deflection current detection circuit 201 is converted into a digital signal by an ADC (Analog to Digital Converter) 202.
[0007]
After that, the digital signal analog / digital converted by the ADC 202 is sent to the comparator 203, and the comparator 203 compares it with the reference value (position data of the adjustment point position) from the interface unit 106.
[0008]
Then, at a timing at which the reference value and the digital signal have a predetermined relationship, a vertical value obtained by counting a count value from the horizontal line counter 204 (a horizontal synchronization signal defining the horizontal scanning period of the color CRT 101 is obtained. The latch circuit 205 latches the horizontal line count value corresponding to the horizontal scanning position in the scanning direction.
[0009]
Next, based on the count value latched by the latch circuit 205 and the count value from the horizontal line counter 204, based on the image adjustment data supplied from the EEPROM (Electrically Erasable and Programmable Read Only Memory) 212, the area / coefficient The arithmetic circuit 206 calculates area / coefficient data (vertical adjustment area corresponding to the horizontal line count value and image correction coefficient in the area) corresponding to the horizontal scanning position in the vertical scanning direction.
[0010]
Further, the interpolation / calculation circuit 207 obtains the area / coefficient data calculated by the area / coefficient calculation circuit 206, the count value from the horizontal line counter 204, and the image adjustment data from the DRAM (Dynamic Random Access Memory) 213. Based on the interpolation calculation, image correction data is calculated.
[0011]
Then, this image correction data (digital value) is converted into a DAC (Digital to Analog Converter) 208.₁  Then, the signal is converted into an analog signal (analog image correction signal) and then output to the vertical convergence deflection yoke 104.
[0012]
The adjustment data input unit 211 is used to input image adjustment data to be written into the EEPROM 212.
DAC208₂  ~ 208_n  Is for converting the image correction data calculated by the interpolation calculation circuit 207 into an analog image correction signal and supplying it to other correction circuits other than the vertical convergence deflection yoke 104.
[0013]
The clock generation circuit 214 generates a clock signal having a frequency, for example, 256 times that of the horizontal synchronization signal, and supplies it to the region / coefficient operation circuit 206 and the interpolation operation circuit 207 as an operation control signal. It has become.
[0014]
According to the digital image correction apparatus having such a configuration, the capacity of the image adjustment data holding memory (EEPROM 212, DRAM 213) necessary for performing image correction in the vertical scanning direction on the display screen of the color CRT 101 can be reduced as much as possible. By increasing the number of adjustment point positions in the vertical scanning direction on the display screen, it is possible to easily improve the accuracy of image correction.
[0015]
However, in the case of the digital image correction apparatus described above, the ADC 202 that is an analog element exists, and therefore, when this is integrated in a digital / analog mixed LSI (Large Scale Integrated circuit), the LSI area is increased by adding an ADC core. In addition, there are concerns about an increase in the number of input / output terminals for ADC, a countermeasure against digital noise against ADC is required, and there is a problem that performance variations that are often caused by analog elements are likely to occur.
[0016]
[Problems to be solved by the invention]
As described above, conventionally, it is possible to improve the image correction accuracy by reducing the capacity of the image adjustment data holding memory as much as possible and increasing the adjustment point position. In addition, since a digital circuit and an analog circuit are mixedly mounted, there is a problem that it is not suitable for integration.
[0017]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital image correction apparatus that can be constructed entirely of digital circuits without using analog elements and that is suitable for integration.
[0018]
[Means for Solving the Problems]
According to one aspect of the present invention,A horizontal line counter that counts a horizontal synchronization signal that defines a horizontal scanning period of a CRT (Cathode Ray Tube) and outputs a count value corresponding to a horizontal scanning position in the vertical scanning direction;Counted by the horizontal line counter based on a vertical synchronization signal defining the vertical scanning period of the CRT.A vertical cycle detection circuit for detecting the number of horizontal lines for each vertical scanning cycle and a timing signal corresponding to an interval when the vertical scanning cycle is divided into n are output based on the number of horizontal lines detected by the vertical cycle detection circuit. A 1 / n circuit, a counting circuit that performs a counting operation according to a timing signal from the 1 / n circuit, and compares the count value of the counting circuit with a reference value;The count value matches the reference valueA comparison circuit that outputs a timing signal at the time, a holding circuit that holds the count value of the horizontal line counter in accordance with the timing signal from the comparison circuit, a count value held by the holding circuit, and the horizontal line counter Based on the count value, an area / coefficient operation circuit that calculates the area / coefficient data corresponding to the horizontal scanning position in the vertical scanning direction, and the area / coefficient data and image adjustment data calculated by the area / coefficient operation circuit A generation circuit that generates image correction data corresponding to a horizontal scanning position in the vertical scanning direction and a conversion circuit that performs digital / analog conversion on the image correction data generated by the generation circuit and outputs the converted data. Digital image correction deviceWill be provided.
[0019]
According to the above configuration,Analog elements can be eliminated, and digital noise countermeasures for analog elements can be made unnecessary. As a result, problems such as an increase in LSI area and performance variations in the manufacturing process can be avoided.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an example in which a vertical deflection digital image correction apparatus according to an embodiment of the present invention is applied to a multi-scan color CRT monitor.
[0021]
In the case of this color CRT monitor, for example, a video amplifier 12 for video signal amplification is connected to the color CRT 11. A vertical deflection yoke 13 is attached to the color CRT 11.
[0022]
A vertical deflection circuit 14 is connected to the vertical deflection yoke 13, and a vertical deflection signal is supplied to the vertical deflection yoke 13 via the vertical deflection circuit 14.
[0023]
The vertical deflection circuit 14 is supplied with the vertical deflection signal from a control system circuit (not shown) and various image correction signals via the vertical image correction circuit 15. Yes.
[0024]
A digital image correction device 20 is connected to the vertical image correction circuit 15, and an analog image correction signal for correcting image distortion in the vertical scanning direction is supplied from the digital image correction device 20. .
[0025]
The digital image correction device 20 calculates area / coefficient data corresponding to the horizontal scanning position in the vertical scanning direction from the vertical synchronizing signal that defines the horizontal scanning period of the color CRT 11 and the horizontal synchronizing signal that defines the horizontal scanning period. Thus, the horizontal scanning position in the vertical scanning direction is detected. For example, the horizontal line counter 21, the vertical cycle detection circuit 22, the region / coefficient data calculation unit 23, and the interpolation calculation circuit (generation circuit) 24 are used. , DAC (conversion circuit) 25₁  ~ 25_n  , A DRAM (memory circuit) 26, a clock generation circuit 27, and a timing generation circuit 28.
[0026]
That is, in the digital image correction apparatus 20, the horizontal line counter 21 counts a horizontal synchronization signal that defines a horizontal scanning period of the color CRT 11 and is supplied from a horizontal circuit (not shown), and performs a vertical scanning direction. A count value (horizontal line count value) corresponding to the horizontal scanning position is output.
[0027]
The horizontal line counter 21 is reset by a vertical synchronization signal that is supplied from a vertical circuit (not shown) and defines the vertical scanning period of the color CRT 11.
[0028]
The vertical cycle detection circuit 22 detects the number of horizontal lines for each vertical scanning cycle counted by the horizontal line counter 21 based on the vertical synchronization signal.
[0029]
The region / coefficient data calculation unit 23 is for calculating region / coefficient data corresponding to the horizontal scanning position in the vertical scanning direction.₁  Counter (counting circuit) 23₂  , Comparator (comparison circuit) 23₃  , Latch circuit (holding circuit) 23₄  And area / coefficient operation circuit 23₅  It is made up of.
[0030]
1 / n circuit 23₁  Is to output a timing signal corresponding to the interval when the vertical scanning period is divided into n based on the number of horizontal lines detected by the vertical period detection circuit 22.
[0031]
Counter 23₂  1 / n circuit 23₁  The counting operation is performed using the timing signal from as a clock input.
Comparator 23₃  The reference value (position data of the adjustment point position) set in advance during the adjustment process by the interface unit 16 and the counter 23₂  And a timing signal is output when the comparison result has a predetermined relationship.
[0032]
Latch circuit 23₄  Is the comparator 23₃The horizontal line count value of the horizontal line counter 21 is held in accordance with the timing signal from. Area / coefficient operation circuit 23₅  The latch circuit 23₄  The area / coefficient data corresponding to a plurality of (for example, m) horizontal scanning positions in the vertical scanning direction is calculated on the basis of the horizontal line count value held in step 1 and the horizontal line count value of the horizontal line counter 21. is there.
[0033]
The details of the region / coefficient data calculation unit 23 will be described later.
The interpolation calculation circuit 24 is connected to the area / coefficient calculation circuit 23.₅  The vertical scanning direction is based on the area / coefficient data corresponding to the horizontal scanning position in the vertical scanning direction calculated in the above and the image adjustment data set in advance by the interface unit 16 during the adjustment process and read from the DRAM 26. The image correction data corresponding to the horizontal scanning position is generated.
[0034]
In the interpolation calculation circuit 24, when the horizontal scanning position in the vertical scanning direction is the adjustment point position, the image adjustment data corresponding to the position data of the adjustment point position is used as the image correction data, and the horizontal scanning position in the vertical scanning direction is used. If the scanning position is not the adjustment point position (between the adjustment point positions), an interpolation operation is performed based on the region / coefficient data and the image adjustment data, and the result corresponds to the horizontal scanning position in the vertical scanning direction. The image correction data is output in real time.
[0035]
DAC25₁  ~ 25_n  Is for D / A (digital / analog) conversion of the image correction data generated by the interpolation calculation circuit 24 and outputs the result to the vertical image correction circuit 15. This DAC25₁  ~ 25_n  Are prepared for each type of image distortion (for example, vertical linearity distortion, barrel shape, trapezoidal distortion, arcuate shape, parallelogram distortion, etc.) generated on the display screen of the color CRT 11.
[0036]
The DRAM 26 stores, for example, image adjustment data corresponding to at least two different adjustment point positions for correcting image distortion in the vertical scanning direction, and position data of the adjustment point positions. Volatile semiconductor memory.
[0037]
The clock generation circuit 27 generates a clock signal having a frequency several times (for example, 256 times) the horizontal synchronizing signal and supplies it as an operation control signal in the digital image correction apparatus 20.
[0038]
The timing generation circuit 28 generates a timing signal necessary for controlling the digital image correction device 20 based on the clock signal from the clock generation circuit 27.
[0039]
The interface unit 16 designates, for example, a plurality of adjustment point positions in the vertical scanning direction on the display screen of the color CRT 11, or sets at least two different adjustment point positions among the adjustment point positions. Image adjustment data corresponding to the corresponding vertical deflection current can be set.
[0040]
Here, an outline of the operation of the digital image correction apparatus 20 having the above-described configuration will be described.
Here, a plurality of (for example, n) adjustment point positions are provided in the vertical scanning direction on the display screen of the color CRT 11, and among the n adjustment point positions, the first adjustment point position from the upper side is P1. The second adjustment point position is referred to as P2, and hereinafter the nth adjustment point position is also referred to as Pn.
[0041]
In the adjustment process of the color CRT monitor, for example, when distortion correction of an image in the vertical scanning direction is performed, first, using the interface unit 16, at least two different adjustment point positions PA and PB (PA and PB are P1 to Pn). The image adjustment data for any of the above is set and held inside.
[0042]
In this adjustment process, the interface unit 16 is used to designate position data of at least two different adjustment point positions PA and PB and hold them inside.
[0043]
Prior to the normal operation of the color CRT monitor, the image adjustment data held in the interface unit 16 is transferred to and stored in the DRAM 26 and an internal register (not shown) of the interpolation calculation circuit 24. Further, the position data held in the interface unit 16 is transferred to and stored in an internal register (not shown) of the digital image correction apparatus 20.
[0044]
During normal operation of the color CRT monitor, image distortion correction in the vertical scanning direction is performed by changing the horizontal scanning position for each horizontal scanning.
For example, first, based on the position data of at least two different adjustment point positions PA and PB specified via the interface unit 16, the region / coefficient calculation circuit 23 is used.₅  The area / coefficient data corresponding to the horizontal scanning position in the vertical scanning direction is obtained.
[0045]
When the area / coefficient data is the adjustment point positions PA and PB, the interpolation calculation circuit 24 uses the image adjustment data and the area / coefficient data to correct the horizontal scanning position in the vertical scanning direction. Ask for.
[0046]
If the area / coefficient data is between the adjustment point positions PA and PB, the interpolation calculation circuit 24 performs an interpolation calculation based on the area / coefficient data and the image adjustment data to obtain image correction data.
[0047]
In this way, image correction data is generated in real time corresponding to the horizontal scanning period, and the DAC 25₁  ~ 25_n  After obtaining an analog image correction signal that changes in the horizontal scanning direction by D / A conversion at, image distortion correction in the vertical scanning direction is performed via the vertical image correction circuit 15.
[0048]
In this way, in the digital image correction apparatus 20, by specifying at least two different adjustment point positions PA and PB on the display screen of the color CRT 11, vertical scanning on the display screen is performed without using an ADC. It is possible to obtain analog image correction signals for all horizontal scanning positions in the direction.
[0049]
FIG. 2 shows a configuration example of the region / coefficient data calculation unit 23 in the digital image correction apparatus 20 having the above-described configuration. Here, a case will be described in which area / coefficient data corresponding to the horizontal scanning position in the vertical scanning direction is obtained based on position data of at least two different adjustment point positions PA and PB.
[0050]
1 / n circuit 23₁  For example, the counter 23 that performs a counting operation by the clock signal of the clock generation circuit 27 (a clock signal nfh having a frequency n times that of the horizontal synchronizing signal)._1  -1  And this counter 23_1  -1  And the number of horizontal lines detected by the vertical period detection circuit 22 are compared with each other at a certain timing (counter 23_1  -1  ) And a timing signal corresponding to an interval when the vertical scanning period is divided into n at the counter 23.₂  Comparator 23 to output to_1  -2  And this comparator 23_1  -2  In response to the timing signal from the counter 23,_1  -1  Clear circuit 23 for generating a timing signal for clearing (resetting) the counting operation_1  -3  It consists of and.
[0051]
Comparator 23₃  At least the first comparator 23_3  -1  And the second comparator 23_3  -2  And the position data of at least two different adjustment point positions PA and PB specified by the interface unit 16 and the counter 23₂  Are compared with each other, and the position data and the counter 23 are compared.₂  A timing signal is output by detecting the timing at which the count value matches.
[0052]
Latch circuit 23₄  Are at least the first latch circuit 23._4  -1  And the second latch circuit 23_4  -2  And each of the first comparators 23._3  -1  And the second comparator 23_3  -2  The count value of the horizontal line counter 21 is held by the timing signal output from the.
[0053]
In such a configuration, for example, vertical scanning in a display mode in which a horizontal scanning frequency fh corresponding to a VGA (Video Graphics Array) input is 31.469 KHz, a vertical scanning frequency fv is 59.940 Hz, and the number of horizontal lines m is 525 lines. When calculating the area / coefficient data corresponding to the horizontal scanning position in the direction, first, the vertical cycle detection circuit 22 detects the number of horizontal lines (525 lines) for each vertical scanning cycle, and the 1 / n circuit 23.₁  Comparator 23 constituting_1  -2  To be supplied.
[0054]
Also, a clock signal 256fh having a frequency n times (for example, 256 times) the horizontal scanning frequency is generated by the clock generation circuit 27, and the 1 / n circuit 23₁  Counter 23 constituting_1  -1  To be supplied.
[0055]
Thus, the counter 23_1  -1  And the comparator 23 at a timing when the count value coincides with the number of horizontal lines detected by the vertical period detection circuit 22._1  -2  Therefore, a timing signal corresponding to the interval when the vertical scanning period is divided into 256 is output.
[0056]
Here, the cycle of the clock signal 256fh having a frequency n times, for example, 256 times the horizontal scanning frequency fh is expressed by the following equation (1).

Further, when the number m of horizontal lines is 525 lines, a period a corresponding to an interval when the vertical scanning period is divided into n, for example, 256, is expressed by the following expression (2).
[0057]

The period b when the period a is multiplied by n, for example, 256 times, is expressed by the following expression (3).
[0058]

Therefore, as shown in the following expression (4), the vertical scanning period fv is obtained by taking the reciprocal of the period b.
[0059]

As described above, the vertical scanning frequency fv obtained by the above equation (4) is the same as the vertical scanning frequency (59.940 Hz) corresponding to the VGA input. A timing signal corresponding to the interval when the vertical scanning period is divided into n is obtained.
[0060]
The comparator 23_1  -2  The timing signal output from the counter 23₂  This counter 23₂  Is counted n times (for example, 256 times) to reproduce the 256 divided vertical scanning synchronization.
[0061]
And this counter 23₂  Is the comparator 23₃  The count value is supplied to the first comparator 23._3  -1  And the second comparator 23_3  -2  Are compared with the position data of the adjustment point position PA or the position data of the adjustment point position PB.
[0062]
As a result of this comparison, the position data and the counter 23₂  At the timing when the count value of the first comparator 23 coincides,_3  -1  Alternatively, the second comparator 23_3  -2  Therefore, the latch circuit 23₄  A timing signal is output.
[0063]
Thus, the first latch circuit 23_4  -1  And the second latch circuit 23_4  -2  The count value (horizontal line count value) of the horizontal line counter 21 at each timing is held.
[0064]
Thus, the first latch circuit 23_4  -1  And the second latch circuit 23_4  -2  When the horizontal line count value is latched by the area / coefficient operation circuit 23,₅Thus, the area / coefficient data corresponding to the horizontal scanning position in the vertical scanning direction is calculated based on the latched horizontal line count value and the horizontal line count value of the horizontal line counter 21.
[0065]
As described above, the area / coefficient data corresponding to the horizontal scanning position in the vertical scanning direction can be obtained from the vertical synchronizing signal and the horizontal synchronizing signal. Refer to Japanese Patent Application No. Hei 8-98426 for details of the calculation method of the region / coefficient data.
[0066]
As described above, in the digital image correction apparatus, analog elements can be eliminated, and digital noise countermeasures for analog elements can be eliminated. That is, as means for detecting the horizontal scanning position in the vertical scanning direction, instead of detecting the vertical deflection current, the region / coefficient data corresponding to the horizontal scanning position in the vertical scanning direction is calculated from the vertical synchronization signal and the horizontal synchronization signal. Is calculated. As a result, the digital image correction apparatus can be configured entirely by digital circuits without using analog elements. Therefore, it is possible to avoid problems such as an increase in LSI area and performance variations in the manufacturing process that are often found in analog elements during integration.
Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.
[0067]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a digital image correction apparatus that can be constituted entirely by digital circuits without using analog elements and is suitable for integration.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a multi-scan color CRT monitor according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration example of a region / coefficient data calculation unit in the digital image correction apparatus used for the color CRT monitor.
FIG. 3 is a schematic block diagram of a multi-scan color CRT monitor for explaining the related art and its problems.
[Explanation of symbols]
11 ... Color CRT
12 ... Video amplifier
13 ... Vertical deflection yoke
14: Vertical deflection circuit
15: Vertical image correction circuit
16 ... Interface part
21 ... Horizontal line counter
22: Vertical cycle detection circuit
23 ... Area / coefficient data calculation section
23₁  ... 1 / n circuit
23_1  -1  …counter
23_1  -2  …comparator
23_1  -3  ... Clear circuit
23₂  …counter
23₃  …comparator
23_3  -1  ... First comparator
23_3  -2  ... Second comparator
23₄  ... Latch circuit
23_4  -1  ... First latch circuit
23_4  -2  ... Second latch circuit
23₅  ... Region / coefficient operation circuit
24. Interpolation calculation circuit
25₁    25_n  ... DAC
26 ... DRAM
27. Clock generation circuit
28. Timing generation circuit

Claims (10)

A horizontal line counter that counts a horizontal synchronization signal that defines a horizontal scanning period of a CRT (Cathode Ray Tube) and outputs a count value corresponding to a horizontal scanning position in the vertical scanning direction;
A vertical period detection circuit for detecting the number of horizontal lines for each vertical scanning period counted by the horizontal line counter based on a vertical synchronization signal defining a vertical scanning period of the CRT ;
A 1 / n circuit that outputs a timing signal corresponding to an interval when the vertical scanning period is divided into n based on the number of horizontal lines detected by the vertical period detecting circuit;
A counting circuit that performs a counting operation in accordance with a timing signal from the 1 / n circuit;
A comparison circuit that compares the count value of the count circuit with a reference value and outputs a timing signal when the count value and the reference value match ;
A holding circuit for holding a count value of the horizontal line counter in response to a timing signal from the comparison circuit;
An area / coefficient operation circuit that calculates area / coefficient data corresponding to the horizontal scanning position in the vertical scanning direction based on the count value held by the holding circuit and the count value of the horizontal line counter;
A generation circuit that generates image correction data corresponding to the horizontal scanning position in the vertical scanning direction based on the region / coefficient data and image adjustment data calculated by the region / coefficient arithmetic circuit;
A digital image correction apparatus, comprising: a conversion circuit that performs digital / analog conversion on the image correction data generated by the generation circuit and outputs the result. The digital image correction apparatus according to claim 1, further comprising a memory circuit that stores the image adjustment data and the reference value. The digital image correction apparatus according to claim 2, wherein the image adjustment data and the reference value are preset by an interface unit. The horizontal line counter, a digital image correction apparatus according to claim 1, characterized in that it is reset by the front Kishide straight synchronization signal. The 1 / n circuit compares a counter for counting a clock signal having a frequency n times the horizontal synchronizing signal, and the number of horizontal lines detected by the vertical period detecting circuit and the count value of the counter, the When the count value matches the number of horizontal lines, the comparator outputs a timing signal corresponding to the interval when the vertical scanning period is divided into n, and the counting operation of the counter is cleared by the timing signal from this comparator. The digital image correction apparatus according to claim 1, further comprising: a clear circuit that performs the above-described operation. The digital image correction apparatus according to claim 1, wherein the comparison circuit includes at least a first comparator and a second comparator. In the first comparator and the second comparator, position data of two different adjustment point positions among the plurality of adjustment point positions in the vertical scanning direction on the display screen of the CRT is stored in the first comparator and the second comparator. The digital image correction apparatus according to claim 6 , wherein the digital image correction apparatus is supplied as a reference value. The digital image correction apparatus according to claim 1, wherein the holding circuit includes at least a first latch circuit and a second latch circuit. The area / coefficient calculation circuit is configured to perform a remaining operation based on image adjustment data corresponding to position data of at least two adjustment point positions among a plurality of adjustment point positions in the vertical scanning direction on the display screen of the CRT. 2. The digital image correction apparatus according to claim 1, wherein image adjustment data corresponding to the position data of the adjustment point position is calculated and output as the area / coefficient data. When the horizontal scanning position in the vertical scanning direction is the adjustment point position, the generation circuit uses the image adjustment data corresponding to the position data of the adjustment point position as the image correction data and the vertical scanning If the horizontal scanning position in the direction is not the adjustment point position, an interpolation operation is performed based on the area / coefficient data and the image adjustment data, and the result is an image corresponding to the horizontal scanning position in the vertical scanning direction. The digital image correction apparatus according to claim 1, wherein the digital image correction apparatus outputs the correction data.

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