JPH09284589A - Digital image correction device and color image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the memory capacity, to easily design a large scale integration circuit for the device and to reduce the cost by entering a small number of adjustment points so as to set lots of correction points through arithmetic operation and generating correction data for each horizontal scanning. SOLUTION: A horizontal scanning position in the vertical direction is detected based on a current of a vertical deflection yoke 12 in the adjustment process. Thus, as to at least two adjustment point positions in the vertical direction, image adjustment data for each correction item with respect to the horizontal scanning are entered. An interpolation arithmetic circuit 29 calculates adjustment data for remaining image adjustment points and the data are stored in an erasure/rewritable read only EEPROM 27. Furthermore, the adjustment data are also stored in a DRAM 28. Even when number of the adjustment points is small, since lots of correction points are set, the memory capacity is reduced and since correction data are generated for each horizontal scanning, the device is easily formed to be a large scale integration circuit and the cost is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image correction device, and more particularly to a device for generating an image correction signal in a vertical direction of a display screen using a color CRT (cathode ray tube), and a multi-scan monitor device. It is used for a color image display device having a plurality of display modes, such as a multi-system color television receiver.

[0002]

2. Description of the Related Art In a color CRT monitor device, RG
A digital image correction device is used to perform correction (convergence correction) of beam convergence deviation due to a difference in distance from each cathode electrode of B to the scanning point of the CRT phosphor screen.

As a multi-scan color CRT monitor, a horizontal scanning frequency is, for example, 24 to 69H.
z, and a vertical scanning frequency of, for example, 50 to 152 Hz.

FIG. 6 shows a vertical deflection system digital image correction device in a conventional color CRT monitor device. In FIG. 6, 10 is a video amplifier for amplifying a video signal,
Reference numeral 11 is a color CRT, 12 is a vertical deflection yoke attached to the CRT, 13 is a vertical convergence deflection yoke attached to the CRT, 14 is a vertical deflection circuit for supplying a vertical deflection signal to the vertical deflection yoke 12. Reference numeral 50 is a digital image correction device.

In the digital image correction apparatus 50, 51 is a vertical deflection current detection circuit for detecting a vertical deflection current flowing in the vertical deflection yoke 12, and 52 is a vertical deflection current detection output detected by the vertical deflection current detection circuit 51. ADC for converting (analog signal) to digital signal
(Analog-digital conversion circuit), 53 is the ADC 5
2 is a decoder circuit that decodes the digital signal output from 2 to generate a zone address corresponding to the CRT display screen position.

These vertical deflection current detection circuits 51, AD
The C52 and the decoder circuit 53 correspond to the vertical deflection yoke 12
A zone address generation circuit 54 for generating a zone address representing the CRT display screen position corresponding to the value of the vertical deflection current flowing in the.

55 is a memory for holding image adjustment data,
Reference numeral 56 is an adjustment data input section for inputting image adjustment data to be written in the memory 55, and 57 is various kinds of converters including the vertical convergence deflection yoke 13 by converting the image adjustment data read from the memory 55 into an analog signal. It is a DAC (digital-analog conversion circuit) supplied to the image correction unit.

Next, the operation of the digital image correction apparatus 50 having the above configuration will be described. During the normal operation of the color CRT monitor device employing the digital image correction device 50, the image adjustment data of each correction item is held in the memory 55, and the zone address generation circuit 54 is always operated.

Thus, the vertical deflection yoke current is detected, the analog amount is converted into a digital signal, and the digital signal is decoded to generate a zone address representing a display screen position corresponding to the value of the vertical deflection current. Further, the image adjustment data corresponding to the zone address is read from the memory 55 and converted into an analog signal by the DAC 57 to obtain various image correction signals.

However, in the above-described conventional digital image correction apparatus 50, the more correction points are set, the more the memory 5 becomes.
The capacity of 5 increases and the cost of the digital image correction device 50 also increases, and conversely, if the number of correction points is reduced, the accuracy of correction deteriorates.

Japanese Patent Laid-Open No. 5-176335 discloses a technique for storing correction data for each display mode in a multi-scan display device, but it requires a large memory capacity.

Further, Japanese Patent Laid-Open No. 7-20809 discloses that
In a multi-scan display device, a technique for reading convergence correction data at a fixed time interval regardless of a scanning frequency of a video signal input is disclosed.However, since interpolation is not performed, the number of adjustment points is very large, and Requires memory capacity.

Further, in Japanese Patent Laid-Open No. 5-7367, in a color CRT display device having a plurality of display modes, n points of correction data in a certain reference display mode are prepared, and interpolation data is created based on the correction data. In other display modes, a technique is disclosed in which correction data is recalculated corresponding to the reference point position on the display screen that differs for each mode, and then interpolation data is created. Moreover, since a large number of interpolation data are held in the memory in advance, a large memory capacity is required.

[0014]

As described above, in the conventional digital image correction apparatus, as the number of correction points increases, the memory capacity for holding the image adjustment data increases and the cost of the digital image correction apparatus also increases. On the contrary, if the number of correction points is reduced, there is a problem that the correction accuracy deteriorates.

The present invention has been made to solve the above-mentioned problems, and the memory capacity for holding image adjustment data necessary for performing image correction in the vertical direction on a color CRT display screen is reduced as much as possible. An object of the present invention is to provide a digital image correction device capable of improving the image correction accuracy by increasing the number of correction points in the vertical direction on the screen.

[0016]

A digital image correction apparatus according to the present invention includes a vertical deflection current detection circuit for detecting and outputting an analog amount of a vertical deflection current flowing in a vertical deflection yoke of a CRT which is an object of image correction. An analog-digital conversion circuit that converts an analog signal input from the vertical deflection current detection circuit into a digital signal and outputs the digital signal, and a digital signal input from the analog-digital conversion circuit and a reference digital signal input having a preset reference value. And a horizontal line that counts the horizontal synchronizing signal that defines the horizontal scanning cycle of the CRT and detects the horizontal scanning position in the vertical scanning direction, and a comparator that detects the timing when the magnitudes of both inputs have a predetermined relationship. A counter and the count value of the horizontal line counter based on the detection output of the comparator. A latch circuit for loading, a memory for holding image adjustment data at a plurality of vertical adjustment point positions on the display screen of the CRT, including a horizontal scanning position corresponding to the count value latched by the latch circuit; Vertical adjustment area at the horizontal scanning position corresponding to the count value of the line counter, area / coefficient calculation circuit for calculating image correction coefficient in the vertical direction, and image adjustment data held in the memory for the plurality of adjustment point positions Output, and for horizontal scanning positions other than the plurality of adjustment point positions, interpolation calculation is performed based on the vertical adjustment area / coefficient data obtained by the area / coefficient calculation circuit and the image adjustment data held in the memory, An interpolation calculation circuit that outputs image correction data and an analog calculation of the digital output data of the interpolation calculation circuit. Characterized by comprising a digital-to-analog conversion circuit for converting the image correction signal.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a digital image correction device of a vertical deflection system in a multi-scan color CRT monitor device according to a first embodiment of the digital image correction device of the present invention.

In FIG. 1, 10 is a video amplifier for amplifying a video signal, 11 is a color CRT, and 12 is the CRT.
Vertical deflection yoke attached to the
A vertical convergence deflection yoke attached to T, 14 is a vertical deflection circuit for supplying a vertical deflection signal to the vertical deflection yoke 12, and 20 is a digital image correction device.

In the digital image correction apparatus 20, 21 is a vertical deflection current detection circuit for detecting a vertical deflection current flowing in the vertical deflection yoke 12, and 22 is a vertical deflection current detection output detected by the vertical deflection current detection circuit 21. ADC that converts (analog current) to digital signal
(Analog-digital conversion circuit).

A comparator 23 compares a digital signal output from the ADC 22 with a preset reference value, and detects a timing (in this example, a coincident timing) when the magnitudes of both inputs have a predetermined relationship. Is a horizontal line counter for counting the period (horizontal period) of the horizontal scanning signal output from a horizontal circuit (not shown).

Reference numeral 25 is a latch circuit for taking in the output value (horizontal line count value) of the horizontal line counter 24 based on the detection output of the comparator 23, and 26 is based on the horizontal line count value and the output value of the latch circuit 25. The vertical adjustment area corresponding to the horizontal line count value (horizontal scanning position) and the area for calculating the image correction coefficient.
It is a coefficient calculation circuit.

Reference numeral 27 denotes a non-volatile memory (for example, an electrically erasable / rewritable read-only memory; EEPROM) that holds image adjustment data of the monitor device, and 27a inputs image adjustment data to be written in the EEPROM memory 27. The adjustment data input unit 28 is a high-speed volatile semiconductor memory (for example, a dynamic random access memory; DRA) that captures and stores the adjustment data of the EEPROM 27 prior to the normal operation of the monitor device.
M).

Reference numeral 29 denotes an interpolation calculation based on the horizontal line count value, the vertical adjustment area / coefficient value obtained by the area / coefficient calculation circuit 26 and the image adjustment data read from the DRAM 28, and the horizontal line count value. It is an interpolation calculation circuit that generates image-Japanese data corresponding to (horizontal scanning position).

Reference numeral 301 denotes one or a plurality of DACs (digital-analog conversion circuit) for converting the digital signal output of the interpolation calculation circuit 29 into an analog image correction signal and supplying it to one or a plurality of convergence deflection yokes 13. 302 to 30n are the interpolation calculation circuits 2 respectively.
9 is a DAC which converts the digital signal output of 9 into an analog image correction signal and supplies it to a correction circuit other than the vertical convergence deflection yoke.

Reference numeral 31 is a clock generating circuit for generating a clock signal having a frequency of, for example, 256 times that of the horizontal synchronizing signal. The clock signal is supplied to the area / coefficient calculating circuit 26 and the interpolation calculating circuit 29 as an operation control signal. Is supplied as.

An interface unit 32 is capable of selectively designating a plurality of adjustment point positions in the vertical direction on the display screen and outputting a digital signal corresponding to a vertical deflection current value corresponding to the adjustment point positions. Have a configuration.

Next, a method of using the digital image correcting apparatus having the above-described structure and an outline of its operation will be described with reference to FIG.
A brief description will be given with reference to the display screen and the operation waveforms shown in FIG.

First, a plurality of (n) pixels are arranged in the vertical direction on the display screen of the monitor device which employs the digital image correction device 20.
Individual adjustment points are provided, and the first point from the upper side of the plurality of adjustment points in the vertical direction is P
The first and second points are called P2, and similarly, the nth point is called Pn.

Then, in the process of adjusting the monitor device,
Adjusting the image display characteristics, each of the correction items (dynamic convergence, vertical focus, color gain, white balance, horizontal phase, etc.) corresponding to horizontal scanning at at least two adjustment point positions in the vertical direction designated by the interface unit 32. Image adjustment data EEP
It is held in the ROM 27.

In this adjustment step, the horizontal scanning position in the vertical direction is detected based on the magnitude of the vertical deflection yoke current, the image adjustment data is input for the two adjustment point positions, and the remaining image adjustment points are calculated. The adjustment data is obtained in accordance with and stored in the EEPROM 27. In this case, the number of adjustment data is the number of correction items xn
It is.

Then, prior to the normal operation of the monitor device, the adjustment data of the EEPROM 27 is fetched and stored in the DRAM 28. During normal operation of the monitor device, the digital image correction device 20 generates an image correction signal that changes in the vertical direction, and by using this, correction is performed in each horizontal scan.

At this time, the digital image correction device 20
The horizontal scanning at the adjustment point is corrected based on the vertical adjustment data, and the remaining horizontal scanning calculates the vertical adjustment area and the correction coefficient based on the vertical adjustment data. It is obtained in real time and is corrected for each horizontal scan based on this correction data.

Digital image correction device 2 as described above
According to 0, the required number of adjustment data is the number of correction items × n
Since many correction points can be set even if there are few adjustment points, the capacities of the memories 28 and 29 can be reduced. In addition, since the correction data is generated for each horizontal scan, the digital image correction device 20 can be easily integrated into an LSI. Therefore, the cost of the digital image correction device 20 can be reduced.

Moreover, even if the vertical amplitude (size) and position (position) of the display screen designated by the interface unit 32 change, the image correction automatically changes in the vertical direction in response to these changes. Since it is possible to generate signals, multi-scan support is fully possible.

Next, an example of the data interpolation method in the digital image correction apparatus 20 having the above-mentioned configuration will be described in detail with reference to FIG. (A) First, the operation in the adjustment process of the monitor device will be described.

The vertical deflection current detection circuit 21 converts the deflection yoke current flowing in the vertical deflection yoke 12 into, for example, a voltage by the vertical deflection current supplied from the vertical deflection circuit 14.
The ADC 22 samples this voltage once in each horizontal scanning period within a fixed period of the vertical cycle (or performs sampling several times to obtain an average value), thereby obtaining a vertical deflection current value (physical value of the display screen). The value corresponding to the position) is output as a digital signal.

Here, as shown in FIG. 3, a certain two points (P) in the output (voltage waveform) obtained by detecting the vertical deflection current.
A, PB) is defined as corresponding to a certain physical position in the vertical direction on the display screen.

For example, PA is 3/1 from the upper end on the display screen.
Assuming that PB corresponds to the position of 0 and PB corresponds to the center position of the display screen, the detected value of the vertical deflection current is always constant in various display modes of the monitor device (modes in which the screen size, screen position, etc. are different). It corresponds to a physical position in the vertical direction on the display screen.

When the vertical scanning line comes to the central position in the vertical direction on the display screen in one display mode, and the detected value (voltage value) of the vertical deflection current becomes xV (volt), another display mode. However, when the vertical scanning line comes to the center position in the vertical direction on the display screen, the detected value (voltage value) of the vertical deflection current becomes x.
V.

The two points (PA, PB) are
Since it suffices that it is within the operating range of the ADC 22, even if the minimum value IVMIN and the maximum value IVMAX of the vertical deflection current are outside the operating range of the ADC 22, the digital image correction apparatus 20 does not malfunction.

The ADC 22 converts the detection output (analog signal) of the vertical deflection current detection circuit 21 into a digital signal and supplies it to the first input terminal of the comparator 23.
In this case, the conversion accuracy of the ADC 22 is 2 points (P
As long as there is linearity between A and PB), the ADC 22
To reduce the cost by reducing the number of conversion bits of
Alternatively, it is possible to increase the full-scale voltage applied to the ADC 22 to further improve the conversion accuracy.

On the other hand, the microcomputer of the interface unit 32 or the like selects and designates two adjustment point positions corresponding to the above two points (PA, PB) in the vertical direction on the display screen, and designates these adjustment point positions (PA, PB). A value corresponding to the corresponding deflection current value is set, and two digital signals corresponding to the set values of the two adjustment point positions (PA, PB) are sequentially supplied to the second input terminal of the comparator 23.

The above two adjustment point positions (P
A, PB), for example, when the adjustment point n = 9,
A point P3 (= PA) at a position 3/10 from the upper end in the vertical direction on the display screen and a point P5 (= PB) at the center are designated.

For example, in the display mode of 600 dots in the horizontal direction and 480 dots in the vertical direction corresponding to VGA input, the adjustment point position PA corresponds to the approximately 144th line of the horizontal scanning, and the adjustment point position PB corresponds to the approximately 240th line of the horizontal scanning. Equivalent to.

The horizontal line counter 24 is a CRT.
Is reset by a vertical synchronization signal defining the vertical scanning period of the CRT, and by counting the horizontal synchronization signal defining the horizontal scanning period of the CRT, the position on the time axis in the vertical scanning period (from the top in the vertical direction on the display screen) Is output.

When the digital value of the first input terminal crosses (matches) the digital value of the second input terminal, the comparator 23 changes the output logic level. Then, the latch circuit 25 fetches the output value of the horizontal line counter 24 according to the change of the output of the comparator 23. As a result, the latch circuit 25 sequentially latches the two horizontal line count values corresponding to the two adjustment point positions (PA, PB).

When the horizontal line count values corresponding to the two adjustment point positions (PA, PB) are obtained as described above, the horizontal line count values of the remaining other adjustment points can be calculated easily based on this. You can ask.

Further, based on the horizontal line count value corresponding to the above-mentioned two adjustment point positions (PA, PB), the relationship between the horizontal line count value and the vertical adjustment area / image correction coefficient as shown in FIG. The vertical adjustment area / image correction coefficient of the remaining adjustment points can be easily obtained by the area / correction calculation circuit 29.

In this way, the adjustment data of each adjustment point position is prepared and stored in the EEPROM 27,
Prior to the normal operation of the monitor device, the EEPROM 2 is controlled by the microcomputer of the user interface unit.
The image adjustment data of No. 7 is fetched and stored in the DRAM 28.

Next, an example of the relationship between the horizontal line count value, the vertical adjustment area of the display screen and the image correction coefficient will be described in detail with reference to FIG. First, with respect to the vertical area, the area to be scanned before the adjustment point P1 on the display screen is the adjustment area 0, the area to be scanned before P2 is the adjustment area 0, and the area to be scanned after P2 and before P3 is the adjustment area 1.
The part to be scanned after Pn-1 and before Pn is the adjustment area (n-
2), a portion scanned after Pn is also called an adjustment area (n-2).

The number of areas from the adjustment area 0 to the adjustment area (n-2) can be represented by log ₂ (n-1) bits. For example, when the adjustment point n = 9, the adjustment area is 0 to 7, and the number of areas can be represented by log ₂ (9-1) = 3 bits. Further, the bit precision m of the correction coefficient can be freely selected, and in this example, m = 8.

The relationship between the horizontal line count value and the vertical adjustment area / correction coefficient shown in FIG. 4 is expressed by the following equations (1) to (3).
Obey. When HL ≦ P1: X = 000.00000000 (1) REG = 000 COEF = 00000000 When P1 <HL <P9: X = 8 * (HL-P1) / (P9-P1)… (2) REG = 000 〜 111 COEF = 00000000 to 11111111 When HL ≧ P9: X = 111.11111111 (3) REG = 111 COEF = 11111111 where HL = horizontal line count value X = data indicating area (3 bits) and coefficient (8 bits) REG = area (3 bits) = integer part of X COEF = coefficient (8 bits) = fractional part of X

The image correction signal is calculated according to the following equation (4). OUT = D (REG) * (11111111-COEF) + D (REG + 1) * (COEF) (4) where OUT = image correction signal D (1) = P1 adjustment data D (2) = P2 Adjustment data D (n) = Pn adjustment data.

(B) Next, the operation of the monitor device during normal operation will be described. The horizontal line counter 24
It is reset by the vertical synchronizing signal and counts the horizontal synchronizing signal to output a value corresponding to the position on the time axis (the distance from the upper end in the vertical direction on the display screen) in the vertical scanning period.

When the horizontal scanning position corresponding to the output value of the horizontal line counter 24 is a vertical adjustment point, the area / coefficient calculation circuit 26 and the interpolation calculation circuit 29 obtain the adjustment data of the corresponding adjustment point position. Output. On the other hand, when the horizontal scanning position is not the adjustment point in the vertical direction, the vertical adjustment area and the image correction coefficient are calculated based on the adjustment data in the vertical direction, and further interpolation calculation is performed to obtain the image correction data in real time. And output to.

In this way, the adjustment data or the correction data extracted in real time corresponding to the vertical deflection scanning is DA-converted by the DACs 301 to 30n to generate an image correction signal which changes in the vertical direction, and this is used. The correction in each horizontal scan is performed by.

That is, by setting two vertical adjustment points on the display screen as described above, it becomes possible to generate appropriate image correction signals for all positions in the vertical direction on the display screen. In this case, the image correction signal in each vertical adjustment area follows the relationship shown in FIG.

That is, the horizontal scanning image correction signal (REG = 000, COEF = 00000000) before the adjustment point P1 uses the adjustment data of P1. The horizontal scanning image correction signals (REG = 000, COEF = 00000000 to 11111111) after P1 and before P2 are
The correction data interpolated between the P1 adjustment data and the P2 adjustment data is used.

The horizontal scanning image correction signals (REG = 111, COEF = 00000000 to 11111111) from Pn-1 to Pn are Pn-
The correction data interpolated with the adjustment data of 1 and the adjustment data of Pn is used.

Image correction signal for horizontal scanning after Pn (REG =
111, COEF = 11111111) uses Pn adjustment data. In the above embodiment, the comparator 23
Is a comparator in which a digital signal output from the ADC is input to the first input terminal, and reference digital signals having reference values set for two adjustment point positions are sequentially input to the second input terminal. However, the present invention is not limited to this, and may be changed as shown in FIG. 5, for example.

In the comparator shown in FIG. 5, there are two sets of comparators (first comparator 231 and second comparator 231).
Of the digital signal from the ADC 22 and the reference set for the positions of the two adjustment points corresponding to the first input terminal and the second input terminal of the first comparator 231. One of the two reference digital signals having a value is input, and the digital signal from the ADC 22 and the two adjustment points are provided corresponding to the first input terminal and the second input terminal of the second comparator 232. The other of the two reference digital signals having the reference value set for the position is input.

The detection output of the first comparator 231 causes the first latch circuit 251 to latch the horizontal line count value, and the detection output of the second comparator 232 causes the second latch circuit 252 to receive the horizontal line count value. Latch and each latch output is the area / coefficient calculation circuit 2
I am typing in 6.

[0063]

As described above, according to the present invention, the memory capacity for holding the image adjustment data necessary for performing the image correction in the vertical direction on the color CRT display screen is reduced as much as possible, and the vertical display on the display screen is reduced. It is possible to provide a digital image correction apparatus capable of improving the image correction accuracy by increasing the number of directional correction points.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital image correction device of a vertical deflection system in a multi-scan CRT monitor device according to a first embodiment of a digital image correction device of the present invention.

FIG. 2 is a diagram showing adjustment point positions on a display screen of the monitor device in FIG.

3 is a diagram showing an example of a correspondence relationship between a vertical deflection current detection value in a digital image correction device and an adjustment point position on a monitor display screen in an adjustment process of the monitor device in FIG.

FIG. 4 is a diagram showing an example of a correspondence relationship between a count value of a horizontal line counter and a vertical area / correction coefficient on a monitor display screen for explaining a data interpolation method in the digital image correction apparatus in FIG.

FIG. 5 is a block diagram showing a modified example of the comparator in FIG.

FIG. 6 is a block diagram showing a vertical deflection system digital image correction device in a conventional color CRT monitor device.

[Explanation of symbols]

 10 ... Video amplifier, 11 ... CRT, 12 ... Vertical deflection yoke, 13 ... Vertical convergence deflection yoke, 14 ... Vertical deflection circuit, 20 ... Digital image correction device, 21 ... Vertical deflection current detection circuit, 22 ... ADC, 23 ... Comparator , 24 ... Horizontal line counter, 25 ... Latch circuit, 26 ... Area / coefficient arithmetic circuit, 27 ... Non-volatile memory, 27a ... Adjustment data input section, 28 ... DRAM, 29 ... Interpolation arithmetic circuit, 301-30n ... DAC, 31 ... Clock generator circuit, 32 ... Interface unit.

Claims (9)

[Claims] 1. A vertical deflection current detection circuit for detecting and outputting an analog amount of a vertical deflection current flowing through a vertical deflection yoke of a CRT which is an object of image correction, and a digital analog signal inputted from the vertical deflection current detection circuit. An analog-digital conversion circuit for converting into a signal and outputting the same, a digital signal output from the analog-digital conversion circuit and a reference digital signal having a preset reference value are input, both inputs are compared, and the magnitude of both inputs is compared. And a horizontal line counter that counts a horizontal synchronizing signal that defines a horizontal scanning cycle of the CRT and detects a horizontal scanning position in the vertical scanning direction, and a detection output of the comparator. A latch circuit for fetching the count value of the horizontal line counter based on A memory for holding image adjustment data at a plurality of vertical adjustment point positions on the display screen of the CRT including a horizontal scanning position corresponding to the count value latched in the horizontal line counter; and a horizontal line corresponding to the count value of the horizontal line counter. Vertical adjustment area at scanning position, area / coefficient calculation circuit for calculating image correction coefficient in vertical direction, and image adjustment data held in the memory for the plurality of adjustment point positions, and the plurality of adjustment points are output. For horizontal scanning positions other than the position, an interpolation calculation circuit for performing an interpolation calculation based on the vertical adjustment area / coefficient data obtained by the area / coefficient calculation circuit and the image adjustment data held in the memory, and outputting image correction data And a digitizer for converting the digital output data of the interpolation calculation circuit into an analog image correction signal. Digital image correction apparatus characterized by comprising an analog conversion circuit. 2. The non-volatile memory that holds the image adjustment data, and the adjustment data of the non-volatile memory that is stored in the memory prior to normal operation of the display device including the CRT. 2. The digital image correction apparatus according to claim 1, further comprising: a volatile semiconductor memory whose stored data is read by the interpolation calculation circuit during the normal operation of. 3. The area / coefficient operation circuit is the CRT.
On the basis of the image adjustment data given to the non-volatile memory for at least two adjustment point positions of the plurality of vertical adjustment point positions on the display screen,
2. The digital image correction apparatus according to claim 1, wherein the image adjustment data at the remaining adjustment point positions other than the two adjustment point positions are calculated. 4. The comparator inputs a digital signal output from the analog-digital conversion circuit to a first input end, and outputs a reference digital signal having a reference value set for the two adjustment point positions to a first reference signal. The digital image correction apparatus according to claim 3, wherein the input is sequentially input to the two input terminals. 5. The comparator has a first comparator and a second comparator, and the first comparator receives a digital signal output from the analog-digital conversion circuit at a first input end, 2 with reference values set for two adjustment point positions
One of the two reference digital signals is input to the second input terminal, the second comparator inputs the digital signal output from the analog-digital conversion circuit to the first input terminal, and the two adjustment points 4. The digital image correction apparatus according to claim 3, wherein the other of the two reference digital signals having the reference value set for the position is input to the second input end. 6. The digital image correction apparatus according to claim 4, wherein the comparator detects a timing when the magnitudes of both inputs match. 7. The horizontal line counter is the CRT.
Is reset by a vertical synchronization signal that defines the vertical scanning cycle of the CRT, and the horizontal synchronization signal that defines the horizontal scanning cycle of the CRT is counted to detect a horizontal scanning position with the upper end in the vertical direction on the display screen as a reference. The digital image correction apparatus according to claim 1, wherein the digital image correction apparatus is a digital image correction apparatus. 8. A color CRT to which an image display signal is applied.
A vertical deflection yoke attached to the color CRT; a vertical deflection circuit that supplies a vertical deflection signal to the vertical deflection yoke; a vertical convergence deflection yoke attached to the color CRT; A vertical deflection current detection circuit that detects and outputs an analog amount of deflection current, an analog-digital conversion circuit that converts an analog signal input from the vertical deflection current detection circuit into a digital signal and outputs the digital signal, and an analog-digital conversion circuit A comparator for inputting an output digital signal and a reference digital signal having a preset reference value, comparing both inputs, and detecting a timing at which the magnitudes of both inputs have a predetermined relationship, and the horizontal of the color CRT. Counts the horizontal sync signal that defines the scanning cycle, and A horizontal line counter for detecting a horizontal scanning position; a latch circuit for taking in the count value of the horizontal line counter based on the detection output of the comparator; and a horizontal scanning position corresponding to the count value latched by the latch circuit. A memory for holding image adjustment data at a plurality of vertical adjustment point positions on a color CRT display screen, and a horizontal adjustment area and a vertical image correction coefficient at a horizontal scanning position corresponding to the count value of the horizontal line counter. A region / coefficient calculation circuit which is obtained by calculation; and image adjustment data held in the memory for the plurality of adjustment point positions, and the region / coefficient calculation circuit for horizontal scanning positions other than the plurality of adjustment point positions. Vertical adjustment area / coefficient data obtained by An interpolation calculation circuit for performing interpolation calculation based on image adjustment data and outputting image correction data, and a digital-analog conversion circuit for converting digital output data of the interpolation calculation circuit into an analog image correction signal are provided. A color image display device characterized in that a current supplied to the vertical convergence deflection yoke is controlled by using an output signal of a circuit. 9. A function of outputting a digital signal corresponding to vertical deflection current values corresponding to a plurality of adjustment point positions in the vertical direction on the display screen of the color CRT, and an amplitude in the vertical direction on the display screen of the color CRT. 9. The color image display device according to claim 8, further comprising an interface unit having a function of outputting a signal designating a position.