JP3602042B2 - Asynchronous packet data multiplexing circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an improvement in an apparatus having a function of multiplexing and transferring packet data input asynchronously on a plurality of channels.
[0002]
[Prior art]
When multiplexing packet data input by a plurality of channels, circuits using the same number of memory ICs as the number of channels of the input packet data are generally used. It is required to reduce the number of parts used in the apparatus for reduction. In order to respond to this request, for example, as disclosed in Japanese Patent Application Laid-Open No. 04-196654, the number of parts is reduced by using a single memory as a unit that performs multiplex processing on asynchronous data generation and transfer units of a plurality of channels. Has been proposed. In the technique disclosed in this prior art document, a plurality of asynchronous input data are received by an asynchronous generation / transfer unit (memory), and the data is transmitted using one memory in an asynchronous data multiplexing unit via a TDM (time division control) bus. Are multiplexed.
[0003]
[Problems to be solved by the invention]
However, this technique has a problem in that a memory is provided for each channel in order to take in asynchronous data at a stage preceding the multiplexing unit, and data is temporarily stored, so that the number of input channels IC increases.
[0004]
A main object of the present invention is to provide an asynchronous packet data multiplexing circuit capable of realizing a function of multiplexing asynchronous packet data input through a plurality of channels and outputting one line with a small circuit.
[0005]
[Means for Solving the Problems]
According to the present invention, in an asynchronous packet data multiplexing apparatus for multiplexing and outputting N (N is an integer of 2 or more) asynchronous packet data of N channels, the asynchronous packet data of N channels is provided on the write control side. Means for retiming the N-channel asynchronous packet data by an internal clock, and time-division multiplexing of N write channel selection signals corresponding to each of the N-channel asynchronous packet data, and after retiming with the highest rate among the N channels Write channel selection signal generating means for outputting the multiplexed signal at a period in which all channels can be selected during one packet data length of the asynchronous packet data of the asynchronous packet data; A first multiplexing means for multiplexing and outputting in a permutation specified by a selection signal; For each of the packet data, a memory write signal is output when a channel to which a write ready signal generated at a signal change point due to the input of the next packet data as a timing coincides with a channel specified by the write channel selection signal. A memory write signal generating means, provided for each of the channels, wherein a channel designated by the write channel select signal matches a channel of the own channel and counts an address on condition that the memory write signal is input; N write address counting means for up-outputting, and first decoding means for decoding the write channel selection signal and designating a write area of a memory. Determined based on the write area information provided by the write control side corresponding to each channel. N read channel selection signals including read area information are time-division multiplexed, and all of the N channels are selected during one packet data length of asynchronous packet data after retiming with the highest rate. Read channel selection signal generating means for outputting the multiplexed signal at a possible cycle, and a read ready signal generated corresponding to each channel triggered by a change in an enable signal indicating an active period of asynchronous packet data after the retiming Read address counting means for counting up and outputting an address on condition that the channel of the read channel select signal matches the channel of the read channel select signal, and a second decode for designating a read area based on the read channel select signal and the write area information Means and two ports for writing and reading In a write operation to the memory, the asynchronous packet information after the retiming is written in accordance with a write address from a head of an area designated by the write area on condition that a memory write signal is input. In the writing and reading operation to the memory, an asynchronous packet data multiplexing device comprising a memory for reading data from a head of an area designated by the reading area in accordance with a write address can be obtained.
[0006]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below. The asynchronous packet data multiplexing circuit shown in FIG. 1 has a circuit configuration when the input packet data is 4ch, and includes retiming units 20-1 to -4, a multiplexer unit 30, a write control unit 40, a dual port memory unit 50, and a read control unit. Unit 60, internal clock generation unit 70, data 302-1-1 to -4-1 obtained by retiming input asynchronous data 300-1 to 300-4 by an internal clock, and enable 302-1-2 to -4-2. , Clocks 302-1-3 to -4-3, data selected by the multiplexer section 30, data 303 output to the dual port memory section, a selection signal 345 output from the write control section to the multiplexer section, Write address signal 344-1, -2, write signal 346 to dual port memory, read Address signal 306-1～-2 to be output from the control section to the dual-port memory unit, composed of the read signal 306-3.
[0007]
FIG. 2 shows the configuration of the write control unit 40 shown in FIG. 2, the write channel selection signal generator 41, the write address counters 42-1 to 4 for each channel, the multiplexer 43, the write ready registers 44-1 to 4-4 for each channel, Write signal generator 45, write channel selection signal 345, write address signal 402 for each channel, lower 12 bits signal 344-2, upper 3 bits 344-1 of selected memory address, write ready signal 406 for each channel, memory It comprises a write signal 346, an internal clock signal 310, retiming clock signals 302-1-3 to -4-3, and retiming enable signals 302-1-2 to -4-2.
[0008]
FIG. 3 shows the read control unit 60 of FIG. 3, a read channel selection signal generator 61, a read ready register 62, a decoder 63, an address counter enable generator 64, a memory address counter 65, a multiplexed data enable, a clock generator 66, and a memory read signal generator 67, read channel selection signal 601, read ready signal 602 for each channel, upper 3 bits 306-1 and lower 12 bits 306-2 of memory read address, multiplexed data enable, clock signal 308, memory read signal 306-3, internal It comprises a clock signal 310 and retiming enable signals 302-1-2 to -4-2.
[0009]
Hereinafter, the operation of the embodiment of the present invention will be described with reference to the drawings and the timing chart. That is, the operation of the embodiment of the asynchronous packet data multiplexing circuit according to the present invention will be described with reference to FIGS.
[0010]
Each of the input packet data is asynchronous input packet data, and includes input data, an input clock, and input enables 300-1 to 300-4. The input data is retimed by the retiming units 20-1 to 20-4 using the input clock and the internal clock 310 output from the internal clock generation unit 70, and is synchronized with the internal clock.
[0011]
After the data 302-1-1 to -1-4 retimed by the internal clock are input to the multiplexer unit 30, one of four channels is selected by the write channel selection signal 345 output from the write control unit 40, and The data is output to the port memory unit 50.
[0012]
Writing to the dual port memory unit 50 is permitted by the memory write signal 346 output from the write control unit 40, and the multiplexer unit starts from the top of the area indicated by the write area information 344-1 output from the decode unit 46. According to the count-up address output from 43, the asynchronous packet data of the CH is written. Here, the write control unit 40 will be described with reference to the timing charts of FIGS.
[0013]
Referring to FIG. 2, the write channel selection signal generator 41 generates a write channel selection signal 345 at a fixed period by the internal clock 310 as shown in FIG. The signals are input to the registers 44-1 to -44-4 and the memory write signal generator 45. As shown in FIG. 5, the write channel selection signal needs to have such a rate that all the channels can be selected between the change points of the fastest data among the retiming data to be input.
[0014]
As shown in FIG. 5, the write ready registers 44-1 to 4-4 output the write ready signals 406 of the corresponding channels at the falling edges of the retiming clocks 302-1-3 to -4-3 indicating the data change points of the respective channels. Set to Hi. The write ready signal 345 is set to Lo when the write channel selection signal selects the corresponding channel and the memory write signal generator 45 outputs the memory write signal.
[0015]
The memory write signal generator 45 generates a write signal 346 when the write ready 406 of the channel specified by the write channel selection signal 345 is Hi.
[0016]
In the memory write counter units 42-1 to 4-4 of each channel, the address counter of the corresponding channel counts up according to the channel specified by the write channel selection signal and the memory write signal.
[0017]
The multiplexer 43 outputs the output signal 402 of the write counter selected by the write channel selection signal 345 as the lower 12 bits of the write address of the memory.
[0018]
The decoding section 46 decodes the write channel selection signal 345 and outputs the upper 3-bit signal 344-1 of the write address designating the write area of the dual port memory.
[0019]
The memory area of the dual port memory will be described with reference to FIG. In the memory area of the dual port memory unit 50, two areas are prepared for each channel as shown in FIG. An example of the operation of accessing the memory will be described. For the channel 1, first, packet data is written to the CH1-1 area, and when writing of one packet data is completed, writing is next performed to the CH1-2 area. The packet data written in the CH1-1 area is read by the read control unit 60 based on the status information on the write received from the write control side while writing in the CH1-2 area.
[0020]
The read control unit 60 of FIG. 1 periodically and repeatedly performs a read check on each area of the dual port memory 50 in packet units using a timing signal generated from an internal clock signal. And multiplexed data is output by simultaneously generating an enable and a clock signal 308 synchronized with the data. The detailed operation will be described with reference to FIGS.
[0021]
In FIG. 3, the read channel selection signal generation unit 61 stores the memory within the shortest enable time of the retiming packet enable inputted as shown in FIG. 6 (the time when the retiming enable is Hi in FIG. 6). A read channel selection signal 601 is generated at a rate at which all packet data of all channels written in the area can be read. Note that the read channel selection signal 601 needs to specify a read area in the later-described decoding unit 63, so the write control side outputs the read channel selection signal 601 based on status information on write area information.
[0022]
The read ready register 62 detects the fall of the retimed enable signals 301-1-2 to -4-2 of each channel, and detects the falling of the read ready signals 602 output to the address counter enable generation unit 64. The read ready signal of the channel is changed from Lo to Hi. That is, when the retiming enable falls, the writing of the memory is guaranteed as described above, and by defining the reading rate as described above, the memory overflow can be prevented.
[0023]
The address counter enable generator 64 generates a read enable signal 607 on condition that the read ready signal 602 of each channel matches the read channel selection signal 601, and the memory read address counter 65, the multiplexed data enable, and the clock generator 66. , And the memory read signal generation unit 67.
[0024]
In the memory read address counter section 65, the address signal 306-2 output to the memory during the period when the read enable signal 607 is Hi is counted up by the internal clock 310.
[0025]
When the input read enable signal 607 becomes Hi, the memory read signal generator 67 outputs the memory read signal 306-3 synchronized with the address counter to the dual port memory 50 as a read permission signal.
[0026]
The multiplexed data enable / clock generator 66 generates a multiplexed data enable / clock signal 308 based on the input read enable signal 607 and the internal clock 310, and outputs a signal obtained by multiplexing a plurality of input asynchronous packet data. I do.
[0027]
【The invention's effect】
As described above, according to the present application, a circuit with a small number of components is provided by realizing the function of multiplexing a plurality of asynchronous packet data with one memory and a control circuit regardless of the number of input channels. . It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately modified within the scope of the technical idea of the present invention.
[Brief description of the drawings]
FIG. 1 is a block diagram of an asynchronous packet data multiplexing circuit. FIG. 2 is a block diagram of a write control unit. FIG. 3 is a block diagram of a read control unit. FIG. 4 is a memory area diagram. FIG. Read timing chart [Explanation of symbols]
20-1 to 4-4 Retiming unit 30 Multiplexer unit 40 Write control unit 41 Write channel selection signal generation unit 42-1 to 4 Memory write counter 43 Multiplexer units 44-1 to 4-4 Write ready register 45 Memory write signal generation unit 46 Decode unit 50 Dual port memory unit 60 Read control unit 61 Read channel selection signal generation unit 62 Read ready register 63 Decode unit 64 Address counter enable generation unit 65 Memory read address counter unit 66 Multiplexed data enable, clock generation unit 67 Memory read signal generation unit 300-1-4 Input data 302-1-1 to 302-4-1 Retimed input data 302-1-2 to 302-4-2 Retimed input enable 302-1-3 to 302-4-3 Rita Immed input clock 303 Multiplexed input data 306-1 Read area information 306-2 Read address 306-3 Memory read signal 307 Multiplexed data signal 308 Multiplexed data enable, clock 310 Internal clock 344-1 Write area information 344 -2 Address information 345 Write channel selection signal 346 Memory write signal

Claims (1)

In an asynchronous packet data multiplexing device for multiplexing and outputting asynchronous packet data of N (N is an integer of 2 or more) channels, the write control side transmits the asynchronous packet data of N channels and input enable to an internal clock. Re-timing means, and N write channel selection signals corresponding to each of the N-channel asynchronous packet data are time-division multiplexed, and the highest-rate asynchronous packet data among the re-timed N channels. Writing channel selection signal generating means for outputting the multiplexed signal at a period in which all channels can be selected during one packet data length of the packet data length; First multiplexing means for multiplexing and outputting in a permutation designated by When the channel on which the write-ready signal generated based on the signal change point due to the input of the next packet data for each of the asynchronous packet data of the channel is dependent matches the channel specified by the write channel selection signal, the memory write signal And a memory write signal generating means for outputting a signal corresponding to each of the channels, wherein a channel designated by the write channel select signal matches a channel of the own channel, and provided that the memory write signal is inputted. N write address counting means for counting up and outputting an address; and first decoding means for decoding the write channel selection signal and designating a write area of a memory. Write area information corresponding to each channel of packet data and given from the write control side N read channel selection signals including read area information determined based on the time division multiplexing, and select all of the N channels during one packet data length of asynchronous packet data after retiming with the highest rate among the N channels A read channel selection signal generating means for outputting the multiplexed signal at a period that can be performed, and a change in an enable signal indicating an active period of the asynchronous packet data after the retiming is generated as a trigger for each channel. Read address counting means for counting up and outputting an address on condition that the channel of the read ready signal matches the channel of the read channel selection signal; and a read area specifying the read area based on the read channel selection signal and the write area information. 2 decoding means for writing and reading A dual-port memory having two ports, wherein in a write operation to the memory, the re-timing after the retiming is performed according to a write address from a head of an area specified by the write area on condition that a memory write signal is input. An asynchronous packet data multiplexing apparatus for writing asynchronous packet information and reading data from a memory according to a read address from a head of an area designated by the read area in a read operation to the memory.

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