JP3593737B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a plurality of functional circuits that operate with an external operation signal supplied from an external terminal.
[0002]
[Prior art]
FIG. 3 shows a circuit configuration diagram of an example of a conventional semiconductor integrated circuit. A conventional semiconductor integrated circuit 11 has a first function circuit 12 and a second function circuit 13 which operate inside according to different operation signals.
[0003]
A DC power supply 14 is connected to a terminal T ₁₁ of the semiconductor integrated circuit 11, and the semiconductor integrated circuit 11 is connected to the first functional circuit 12 and the first functional circuit 12 by a DC voltage V _CC supplied from the DC power supply 14 via the terminal T ₁₁ . The internal circuit including the second functional circuit 13 is driven.
First functional circuit 12 is connected to the terminal _{T 11} and the terminal _{T 12,} and generates an output signal in response to the DC voltage _{V CC} supplied from the terminal _{T 11.}
[0004]
The second functional circuit 13 sends a signal to the constant current source 15 that generates a driving fixed current from the DC voltage V _CC supplied to the terminal T ₁₁ , an input circuit 16 of an I ² L (Integrated Injection Logic) gate, and a signal to the input circuit 16. It comprised of input transistor _{Q 11} supplies.
[0005]
Based input transistor Q ₁₁ is another internal circuit of the semiconductor integrated circuit 11 (e.g., oscillation circuit) is connected to the input transistor Q ₁₁ is made of NPN transistors, internal operation supplied from other internal circuitry A signal (for example, a clock) turns on when it is high and turns off when it is low, and supplies a signal whose internal operation is inverted to the input circuit 16.
[0006]
Input circuit 16 is made of a PNP transistor _Q 12, NPN transistors _{Q 13,} constitute a so-called ^{I 2} L gate on the wafer. Input circuit 16 is supplied to other internal circuits further inverts the internal operation signal inverted by the input transistor Q _11.
[0007]
Also, a collector connected to the semiconductor integrated circuit 11, the input transistor Q ₁₁ to the external terminal T _13, operates the second function circuit 13 by external operation signal by supplying an external operation signal from the outside to the external terminal T ₁₃ The configuration is such that it can be performed.
[0008]
FIG. 4 shows an operation waveform diagram of the conventional semiconductor integrated circuit 11. FIG. 4 (A) external operation signal waveforms applied to the terminal T _12, FIG. 4 (B) internal operation signal waveforms applied to the second function circuit 13 in the semiconductor integrated circuit 11, FIG. 4 (C ) input operation of the input circuit 16 at the time of circuit operation by the internal operation signal is a signal waveform, FIG. 4 (D) output signal waveform of the input circuit 16 at the time of circuit operation by the internal operation signal, FIG. 4 (E) are terminal T ₁₃ 4 (F) shows an output signal waveform of the input circuit 16 when the circuit is operated by the external operation signal.
[0009]
The first functional circuit 12 operates by the signal shown in FIG. 4A and generates an output signal (not shown).
A signal as shown in FIG. 4B is supplied to the second function circuit 13 from an oscillator or the like in the semiconductor integrated circuit 11 at the time of operation by an internal signal. Signal shown in FIG. 4 (B) is inverted by the input transistors Q _11, is a signal shown in FIG. 4 (C), it is supplied to the input circuit 16.
[0010]
The input circuit 16 inverts the signal shown in FIG. 4C and outputs it as a signal as shown in FIG.
Also, when operating the operation signal of the second function circuit 13 from the outside, such as supply to the second function circuit 13 of the internal operation signal is cut, as shown to the terminal T ₁₃ in FIG. 4 (E) Supply signal. The input circuit 16 inverts the signal of FIG. 4E and outputs the inverted signal as shown in FIG.
[0011]
Thus, when operating by the first functional circuit 12 and an external operation signal a second function circuit 13 of a conventional semiconductor integrated circuit 11, another function, the external terminal T _12, T ₁₃ for each function circuit each Had been provided.
[0012]
[Problems to be solved by the invention]
However, in the conventional semiconductor integrated circuit, in order to operate the first function circuit 12 and the second function circuit 13 having different functions by operation signals from the outside, it is necessary to input an operation signal from the outside for each circuit. Since the external terminals are provided, the number of external terminals of the semiconductor integrated circuit increases, which leads to a problem that the device becomes larger.
[0013]
The present invention has been made in view of the above points, and has as its object to provide a semiconductor integrated circuit that can reduce the number of external terminals while maintaining operation by an external operation signal.
[0014]
[Means for Solving the Problems]
The present invention relates to a semiconductor integrated circuit having a plurality of built-in functional circuits to which a pulse-like operation signal supplied from the outside is supplied, wherein the operation signal is supplied, and the operation signal is output by the voltage. Operating signal supply control means for selectively supplying to at least one of the plurality of function circuits according to the plurality of function circuits, and each of the plurality of function circuits has a preset voltage range operable by the operation signal. And when the voltage of the operation signal is within a preset operable voltage range when the operation signal is selectively supplied by the operation signal supply control means, the voltage of the operation signal is preset. It does not operate when it is out of the operable voltage range .
[0015]
[Action]
According to the present invention, when a voltage range in which a plurality of functional circuits can be operated by an operation signal is set in advance, and the operation signal is selectively supplied by operation signal supply control means, the operation signal It operates when the voltage of is in operable voltage range set in advance, with the configuration that does not work when it is outside the operating voltage range which the voltage is set in advance of the operation signal, among the plurality of functional circuits A desired functional circuit can be selectively operated. Therefore, a terminal for supplying an operation signal can be shared by a plurality of functional circuits.
[0016]
【Example】
FIG. 1 shows a circuit configuration diagram of an embodiment of the semiconductor integrated circuit of the present invention.
The semiconductor integrated circuit 1 of the present embodiment first functional circuit 2 for performing a predetermined process on the input signal, the second function circuit 3 for inverting the input signal, an external operation to be supplied to the external terminal T ₂ An operation signal supply control circuit 4 for controlling the supply of an external operation signal to the second function circuit 3 according to the signal.
[0017]
A DC power supply 5 is connected to a terminal T1 of the semiconductor integrated circuit 1, and the semiconductor integrated circuit 1 is driven by a DC voltage VCC supplied from the DC power supply 5.
The first functional circuit 2 is supplied with a clock from an oscillation circuit or the like in the semiconductor integrated circuit 1 or a clock supplied from an external terminal T2 of the semiconductor integrated circuit 1, and the first functional circuit 2 receives the supplied clock. Performs an operation specific to the first functional circuit 2 such as frequency conversion in accordance with. At this time, the first functional circuit 2 is configured so that, for example, the clock input transistor saturates at Vcc or higher and does not operate at Vcc or higher , and the low level of the clock is 0 and the high level is V1 (V1 <Vcc ).
[0018]
The second functional circuit 3 inputs an input circuit 6 constituting an I ² L (Integrated Injection Logic) gate, a constant current source 7 for supplying a drive current to the input circuit 6, and a clock from an internal oscillator of the semiconductor integrated circuit 1. composed of input transistor _{Q 1.}
The input circuit 6 includes a driving current injection transistor Q ₂ formed as a lateral PNP transistor on a semiconductor substrate, and an output transistor Q ₃ formed as a vertical NPN transistor on a semiconductor substrate, and forms an I ² L gate. I have.
[0019]
The constant current source 7 is connected to the terminal T _1, the DC voltage V _CC supplied from the DC power source 5 is applied to the terminal T _1, and generates a constant current to drive the input circuit 6 from the DC voltage V _CC, It is supplied to the emitter of the transistor Q ₂ of the input circuit 6.
Input transistor Q ₁ is constructed from NPN transistor, the emitter is grounded, and the collector connected to the base of the transistor Q ₃ to be the input of the input circuit 6 is supplied from the oscillator or the like of an internal circuit of the semiconductor integrated circuit 1 to the base A clock is supplied.
[0020]
The operation signal supply control circuit 4 corresponds to an operation signal control means in the claims, and includes PNP transistors Q ₄ and Q ₅ , an NPN transistor Q ₆ , a resistor R _1, and an input terminal T ₂ to which an external clock is input. The DC power supply 5 is connected between the second functional circuit 3 and the DC voltage _VCC . It is connected to the terminal T _1, when the clock external clock supplied to the input terminal T ₂ is inverted by the DC voltage V _CC or higher supplies an external clock to a second functional circuit 3, the following DC voltage V _CC When the clock is inverted in level, no external clock is supplied to the second function circuit 3.
[0021]
PNP transistor _{Q 4} of the operation signal supply control circuit 4 is an emitter connected to the terminal _{T 2,} the collector and base connected to the terminal _{T 1,} also, the PNP transistor _{Q 5} is connected emitter to the terminal _{T 2,} the base is is connected to the terminal T _1, the collector is grounded through a resistor R _1, further, NPN transistor Q ₆ is a base connected to the collector and the connection point of the resistors R ₁ of the transistor Q _5, the emitter is grounded, a collector It is connected to the base of the transistor Q ₃ constituting the input circuit 6 of the second functional circuit 6.
[0022]
The emitter of the operation signal supply control circuit 4 external clock supplied to the terminal T ₂ In becomes high / low in the DC voltage V _CC is less than the level when the transistor Q _4, Q ₅ - reverse voltage is applied between the base, transistors Q _4, Q ₅ is turned off, the base of the transistor Q ₆ becomes a low level, the transistor Q ₆ is turned off, the input of the second functional circuit 3 is held at the high level, the external clock is not supplied.
[0023]
Further, when the external clock to be the terminal T ₂ supply is high / low in the DC voltage V _CC is greater than the level, when the external clock becomes a low level in the DC voltage V _CC is the transistor Q _4, Q ₅ an emitter - base reverse voltage is applied between the transistors Q _4, Q ₅ is turned off, the base of the transistor Q ₆ goes low, the transistor Q ₆ is turned off, the input of the second functional circuit 3 and the high level Become.
[0024]
The emitter of the transistor _Q 4, _{Q 5} when the external clock supplied to the terminal _{T 2} is at the high level by the DC voltage _{V CC} is greater than the voltage _(V CC + V _f) - forward voltage between the base applied is the result in, the transistor Q _4, Q ₅ is turned on, the base of the transistor Q ₆ becomes high, the transistor Q ₆ is turned on, the input of the second functional circuit 3 becomes low.
[0025]
By this way the external clock low level is supplied to the external terminal _{T 2} is 0, the high level of the clock _{V 1 (V 1 <V CC} ), a clock as a high / low at a voltage less than the voltage _{V CC} Operates the first functional circuit 2 which operates on the first function circuit. At this time, since the external clock is equal to or lower than the voltage V _CC , the operation signal supply control circuit 4 is turned off, the input of the second function circuit 3 becomes constant at a high level, and no clock is input. Operation 3 is stopped.
[0026]
The first function circuit 2 operates in the following clock voltage V _CC by the low level external clock supplied to the external terminal T ₂ is to V _CC, clock high level is V _{CC +} V _f is not work Instead, the operation signal supply control circuit 4 is turned on, a clock is input to the second function circuit 3, and the second function circuit 3 can be operated.
[0027]
FIG. 2 shows an operation waveform diagram of one embodiment of the present invention. 2 (A) is an external clock waveform supplied to the external terminal T ₂ when operating a first function circuit 2, (B) is the second function circuit 3 during the operation of the first function circuit 2 input signal waveform, (C) shows a waveform of the external clock supplied to the external terminal T ₂ when operating a second function 3, (D) the base waveform of the transistor Q ₆ during the operation of the second function 3 shows the (E) is the second function 3 collector waveform of the transistor Q ₆ during the operation of, (F) and the second output signal waveform of the functional circuit 3 during the operation of the second functional circuit 3.
[0028]
Low level 0 V, as shown in FIG. 2 (A) when operating the first function circuit 2 supplies a clock of a high level _{V 1} [V] _(V 1 _{<V CC)} to the external terminal _{T 2} As a result, a clock lower than the voltage _VCC can be supplied to the first functional circuit 2, and the first functional circuit 2 can be operated. At this time, the transistors Q ₄ and Q ₅ of the operation signal supply control circuit 4 are turned off, and the base of the transistor Q ₆ is at a low level, so that the second functional circuit 2 supplies a clock as shown in FIG. Is not supplied, the input of the second functional circuit 2 is fixed at a high level as shown in FIG. 2B, and the second functional circuit 2 does not operate.
[0029]
Low level _{V CC} [V] as shown in FIG. 2 (C) when operating the second functional circuit 2 supplies a clock of a high level _V 2 _{(V 2> V CC)} to the external terminal _{T 2.} When the high-level external terminal T ₂ supplies a DC voltage V _CC or more clock turned on in response to the transistor Q _4, Q ₅ is a clock signal of the operation signal supply control circuit 4, the base of the signal waveform of the transistor Q ₆ It changes according to the clock. Transistor Q ₆ is turned on when the clock is high, to off when low, the collector of the transistor Q ₆ is changed as shown in FIG. 2 (E). As described above, a signal corresponding to the external clock is supplied to the second functional circuit 3, and the second functional circuit 3 can be similarly operated by using the internal clock.
[0030]
At this time, since the first functional circuit 2 is supplied with a clock that is inverted in a level range (V _{CC to} V _CC + V _f ) larger than the DC voltage V _CC , the first functional circuit 3 does not operate.
According to this embodiment, the range of levels that reverses depending on whether the same external terminal T ₂ to supply the external clock to the first function circuit 2, to operate the one of the second functional circuit 3 The low-level range (0 to V _CC ), but the high-level range (V _{CC to} V _CC + V _f ) enables selective operation.
[0031]
Therefore, the number of external terminals of the semiconductor integrated circuit 1 can be reduced, and the size of the package can be reduced.
In this embodiment, the case where the operations of the two functional circuits are shared has been described. However, the present invention is not limited to this, and it is needless to say that a plurality of functional circuits can be handled by setting a plurality of ranges. .
[0032]
【The invention's effect】
As described above, according to the present invention, when a voltage range in which a plurality of functional circuits can be operated by an operation signal is set in advance, and the operation signal is selectively supplied by operation signal supply control means, In addition, by operating when the voltage of the operation signal is within a preset operable voltage range, and not operating when the voltage of the operation signal is outside the preset operable voltage range , a plurality of Since a desired one of the functional circuits can be selectively operated, a terminal for supplying an operation signal can be shared by a plurality of functional circuits, and thus the number of external terminals of the semiconductor integrated circuit can be reduced. Therefore, there is a feature that the size can be reduced while improving the function.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of the present invention.
FIG. 2 is an operation waveform diagram of one embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of a conventional example.
FIG. 4 is an operation waveform diagram of a conventional example.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor integrated circuit 2 first function circuit 3 second function circuit 4 operation signal supply control circuit 5 DC power supply T ₁ , T ₂ input terminal

Claims (2)

In a semiconductor integrated circuit in which a plurality of functional circuits to which a pulse-like operation signal supplied from the outside is supplied ,
The operation signal is supplied, the operation signal, the operation, comprising an operation signal supply control means for selectively supplying the operation to at least one of the plurality of functional circuits according to the voltage,
In each of the plurality of functional circuits, a voltage range operable by the operation signal is set in advance, and the operation signal is selectively supplied when the operation signal is selectively supplied by the operation signal supply control unit. The semiconductor device operates when the voltage of the operation signal is within a preset operable voltage range, and does not operate when the voltage of the operation signal is out of the preset operable voltage range. Integrated circuit. In a semiconductor integrated circuit in which a first function circuit and a second function circuit that operate in response to a pulse-like operation signal supplied from the outside are provided,
A DC voltage is supplied from the outside and the operation signal is supplied. When the operation signal is smaller than the DC voltage, the operation signal is supplied to the first function circuit, and the operation signal is An operation signal supply control unit that supplies the operation signal to both the first functional circuit and the second functional circuit when the voltage is higher than the voltage;
The first functional circuit is configured to stop operating when the voltage of the operation signal is higher than the DC voltage, and to operate when the voltage of the operation signal is lower than the DC voltage,
The second function circuit is configured to operate when the operation signal is supplied from the operation signal supply control unit and to stop operation when the operation signal is not supplied from the operation signal supply control unit. A semiconductor integrated circuit characterized by being performed.

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