JP3592272B2 - Integrated circuit device and ink jet recording device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an integrated circuit device.as well asInkjet recording equipmentIn placeIn particular, a central processing unit that performs initialization based on an external reset signal, and an integrated circuit device mounted with a plurality of circuit blocks,as well asInk jet recording device equipped with the integrated circuit deviceIn placeRelated.
[0002]
[Prior art]
Conventionally, instead of general-purpose ICs such as CPUs (Central Processing Units) and memories, application-specific integrated circuits (hereinafter abbreviated as “ASICs”) for realizing functions optimal for specific applications have been developed. ing.
[0003]
In recent years, with the development of semiconductor integrated circuit technology, the operation speed, degree of integration, and scale of such ASICs have evolved to higher levels, and the individual circuits constituting the ASIC have also changed from single functions to composite functions. Evolving.
[0004]
2. Description of the Related Art Conventionally, in an ASIC, at least three circuits, namely, a CPU, a peripheral logic circuit, and a special-purpose logic circuit, have been independently designed for high integration, high speed, and large scale. On the other hand, recently, with the establishment of a one-chip type semiconductor integrated technology in which all functions are incorporated in the same chip, higher integration is possible. In the ASIC, the CPU, the peripheral logic circuit, and the special-purpose logic circuit are each integrated on one semiconductor wafer by the semiconductor integrated technology for realizing the one-chip form.
[0005]
In such a highly integrated semiconductor integrated circuit, an external input signal is also sampled by an external clock signal and taken in. Further, the internal circuit operates using a clock signal input from the outside as a synchronization signal.
[0006]
[Problems to be solved by the invention]
In the conventional ASIC with high integration as described above, a plurality of circuits mounted on a semiconductor wafer are synchronized with each other by a clock signal from the outside, but each circuit functions independently. It was only.
[0007]
In other words, the circuit operation is clock-synchronized, but the reset operation (initialization operation) when the power of each circuit is turned on is performed independently by each circuit, so there is a slight difference in reset timing between the circuits. As a result, there is a problem that the operation of the ASIC becomes unstable.
[0008]
This will be described with reference to FIG. 11 showing a block configuration of a conventional ASIC.
[0009]
Reference numeral 101 denotes an ASIC. Inside the ASIC 101, a CPU (Central Processing Unit) 102, a peripheral logic circuit 103, and a special-purpose logic circuit 104 are provided. The peripheral logic circuit 103 includes a memory (not shown) built in the ASIC 101, a program ROM (not shown) provided outside the ASIC 101, and transmission and reception of data between the CPU 102 and the special-purpose logic circuit 104. Control. The specific use logic circuit 104 is a logic circuit that is set by a user in order to optimize the ASIC 101 for a specific control device on which the ASIC 101 is mounted.
[0010]
Reference numeral 105 denotes a clock signal supplied from the outside to the ASIC 101, and is used to synchronize the internal circuit of the ASIC 101. Reference numeral 106 denotes a reset signal supplied from the outside to the ASIC 101. Reference numeral 107 denotes an inverter circuit inside the ASIC 101 for logically inverting the reset signal 106.
[0011]
In such a conventional ASIC 101, when a reset signal 106 is input for a predetermined time due to a rise of a power supply, an internal reset signal 108 obtained by inverting the reset signal 106 is supplied to each reset terminal of the CPU 102, the peripheral logic circuit 103, and the specific use logic circuit 104. Is input to Each of the CPU 102, the peripheral logic circuit 103, and the special purpose logic circuit 104 is initialized by the input of the internal reset signal 108.
[0012]
However, in the CPU 102, the peripheral logic circuit 103, and the special-purpose logic circuit 104, there is a difference in the rise of the voltage after the start of power supply, so that the reset timing of each circuit is slightly different. Therefore, in some cases, the reset timing of the CPU 102 may be later than the reset timing of the peripheral logic circuit 103 or the special-purpose logic circuit 104. In this case, there is a problem that the ASIC 101 cannot expect stable operation.
[0013]
The present invention has been made in view of such a problem, and has an integrated circuit device that controls initialization timing of each circuit to an appropriate timing when each of a plurality of circuits constituting an ASIC is initialized.as well asInkjet recording equipmentPlaceThe purpose is to provide.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, according to the invention described in claim 1,A central processing unit, a special purpose logic circuit, and a peripheral logic circuit bus-connected between the special purpose logic circuit and the central processing unit,Based on external reset signalThe central processing unit, the special purpose logic circuit, and the peripheral logic circuitPerform initializationOne-chip configurationAn integrated circuit device,The peripheral logic circuit controls data transmission performed between an externally provided program ROM and the special-purpose logic circuit and the central processing unit, and the special-purpose logic circuit and the peripheral logic circuit respectivelyCompletion signal output means for outputting an initialization completion signal to the central processing unit when the initialization is completedHas, The central processing unitIs the special purpose logic circuit and the peripheral logic circuitBased on the initialization completion signal output from each ofFor the specific purpose logic circuit and the peripheral logic circuitAllow actionRuiNavel signalOutEnable signal output means forWhen an initialization completion signal is not output for at least one of the completion signal output means of the specific use logic circuit and the peripheral logic circuit for a predetermined time, the output of the enable signal is changed to change the output of the enable signal. Re-initialization means for causing the logic circuit and the peripheral logic circuit to perform initialization again;An integrated circuit device having the following is provided.
[0015]
Claim6According to the invention described above, the recording head is used.Recording operationControlA central processing unit, a special purpose logic circuit, and a peripheral logic circuit bus-connected between the special purpose logic circuit and the central processing unit.Integrated circuit deviceAnd a reset signal generation circuit for generating a reset signalAn inkjet recording apparatus equipped with, wherein the integrated circuit device,SaidCentral processing unit that performs initialization based on the reset signalAnd peripheral logic circuits and special purpose logic circuitsHaving the aboveThe peripheral logic circuit and the special purpose logic circuit are each based on the reset signal.Initialization completedLaterCompletion signal output means for outputting an initialization completion signal to the central processing unit, wherein the central processing unitIsAnd saidPeripheral logic circuit and said special purpose logic circuitBased on the initialization completion signal output from each of the completion signal output means,Each of the peripheral logic circuit and the special purpose logic circuitmotionstartThe enable signal for permittingPeripheral logic circuit and the special purpose logic circuitOutput enable signal output meansAnd when at least one of the completion signal output means of the peripheral logic circuit and the specific use logic circuit does not output an initialization completion signal for a predetermined time, the output of the enable signal is changed to Re-initialization means for causing the logic circuit and the special-purpose logic circuit to restart initialization.An ink jet recording apparatus characterized by having:
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
FIG. 1 is a perspective view of a printer equipped with an integrated circuit device according to the present invention. The printer is an ink jet printer.
[0021]
A recording head 1005 is mounted on a carriage 1004 and can reciprocate in a longitudinal direction along a shaft 1003.
[0022]
The ink ejected from the recording head 1005 reaches the recording material 1002 whose recording surface is regulated by the platen 1001 at a minute interval from the recording head 1005, and forms an image thereon.
[0023]
An ejection signal corresponding to image data is supplied to the print head 1005 via a flexible cable 1019. Reference numeral 1014 denotes a carriage motor for scanning the carriage 1004 along the shaft 1003. Reference numeral 1013 denotes a wire for transmitting the driving force of the carriage motor 1014 to the carriage 1004. Reference numeral 1018 denotes a transport motor coupled to the platen roller 1001 to transport the recording material 1002.
[0024]
The resolution of the recording head 1005 is 600 DPI. The recording head 1005 has 128 recording elements arranged by an ink jet method. The recording element includes a driving unit and a nozzle. In the driving unit, the ink can be heated by a heater. The ink causes film boiling due to this heating, and a pressure change occurs due to the growth or shrinkage of bubbles due to the film boiling, whereby the ink is ejected from the nozzles.
[0025]
(First Embodiment)
FIG. 2 is a block diagram showing the configuration of the first embodiment in the integrated circuit device according to the present invention.
[0026]
Reference numeral 1 denotes an ASIC (Application Specific Integrated Circuit). Reference numeral 2 denotes a circuit block provided inside the ASIC 1, which is a CPU (Central Processing Unit).
[0027]
Reference numeral 3 denotes a circuit block provided inside the ASIC 1, which is a peripheral logic circuit. The peripheral logic circuit 3 sends and receives data between the CPU 2 and a memory (not shown) built in the ASIC 1, a program ROM (not shown) provided outside the ASIC 1, and the specific use logic circuit 4. Logic circuit.
[0028]
Reference numeral 4 denotes a circuit block provided inside the ASIC 1, which is a specific use logic circuit. The specific-purpose logic circuit 4 processes print data received from a host computer 46 (FIG. 3) described later. For example, compressed print data is expanded on a memory, and data rearrangement is performed at high speed according to the arrangement of recording elements.
[0029]
The special-purpose logic circuit 4 generates a control signal for the carriage motor 1014. This control signal is output to the drive circuit of the carriage motor 1014. This control signal is, for example, a signal for controlling the rotation direction and rotation speed of the carriage motor 1014. Based on the control signal, the carriage 1004 on which the recording head 1005 is mounted performs a reciprocating operation smoothly.
[0030]
Further, the special purpose logic circuit 4 generates a plurality of control signals for controlling the recording head 1005. The control signal controls, for example, a drive time and a drive cycle of a print element in the print head 1005. The printing element is appropriately driven by this control signal. The control signal sent to the print head 1005 is output with good timing according to the operation of the carriage 1004. The control signal also includes an initialization signal for initializing a control circuit built in the print head 1005. The circuit scale of the specific use logic circuit 4 is, for example, about several hundred thousand gates.
[0031]
15a and 15b are data buses used for data transmission / reception among the CPU 2, the peripheral logic circuit 3, and the special purpose logic circuit 4.
[0032]
The spatial arrangement of the entity of the ASIC 1 shown in FIG. 2 will be described. The electrical distance between the specific logic circuit 4 and the CPU 2 (for example, the one related to the wiring length) is the electrical distance between the peripheral logic circuit 3 and the CPU 2. Greater than. That is, the specific logic circuit 4 may be disposed farther away from the CPU 2 than the peripheral logic circuit 3. As a result, when arranging in the ASIC, the degree of freedom of the layout of the specific logic circuit 4 is increased.
[0033]
Reference numeral 5 denotes a clock signal supplied from the outside to the ASIC 1, and is used to synchronize the internal circuit of the ASIC 1. Reference numeral 6 denotes a reset signal supplied from the outside to the ASIC 1, and is used to initialize the CPU 2 inside the ASIC 1. This reset signal 6 is High active.
[0034]
Reference numeral 7 denotes an inverter circuit inside the ASIC 1 for logically inverting the reset signal 6. Reference numeral 8 denotes an inverted signal of the reset signal 6, which is an internal reset signal transmitted to each of the logic circuits 3 and 4 inside the ASIC 1.
[0035]
9a, 9b and 9c are flip-flop circuits (hereinafter referred to as "F / F circuits"). The F / F circuit 9a is a circuit for synchronizing the clock of the reset signal 6, and the F / F circuits 9b and 9c are circuits for synchronizing the output signals of the inversion AND circuits 10a and 10b, which will be described later. . The output signal of the F / F circuit 9a is sent from the inverting terminal of the F / F circuit 9a to the reset terminal of the CPU 2. The output signals of the F / F circuits 9b and 9c are sent from the inverting terminals of the F / F circuits 9b and 9c to the peripheral logic circuit 3 and the ENB terminals of the special purpose logic circuit 4, respectively.
[0036]
Reference numeral 11 denotes an initialization completion signal output from the peripheral logic circuit 3 when the initialization in the peripheral logic circuit 3 is completed. Reference numeral 12 denotes an initialization completion signal output from the specific use logic circuit 4 when the initialization in the specific use logic circuit 4 is completed.
[0037]
Reference numeral 13 denotes a logical product circuit, which calculates a logical product of the initialization completion signal 11 and the initialization completion signal 12, and outputs the result to the CPU 2 as an initialization completion notification signal 14. Upon receiving the initialization completion notification signal 14, the CPU 2 outputs an enable signal 19 to the AND circuits 10a and 10b.
[0038]
Inverted AND circuits 10a and 10b perform inverted AND of the internal reset signal 8 and the enable signal 19 from the CPU 2 and send them to the F / F circuits 9b and 9c, respectively.
[0039]
Reference numerals 21a and 21b denote enable signals for bringing the peripheral logic circuit 3 and the special-purpose logic circuit 4 into an operation permission state. When the enable signal 21a is output from the F / F circuit 9b to the peripheral logic circuit 3, the peripheral logic circuit 3 enters an operation permission state. Similarly, when the enable signal 21b is output from the F / F circuit 9c to the special-purpose logic circuit 4, the special-purpose logic circuit 4 enters an operation permission state.
[0040]
As described above, when the CPU 2 outputs the enable permission signal 19 based on the initialization completion signals 11 and 12 from the peripheral logic circuit 3 and the specific use logic circuit 4, if the reset signal 6 is at a high level, The enable signals 21a and 21b are sent to the peripheral logic circuit 3 and the specific-purpose logic circuit 4, respectively, and the peripheral logic circuit 3 and the specific-purpose logic circuit 4 enter an operation permission state.
[0041]
Next, the operation of the ASIC 1 having such a configuration will be described. First, when power is supplied to the ASIC 1 from a power supply unit 33 (see FIG. 3) described later, a reset IC 39 (see FIG. 3) described later monitors the power supply voltage, and a predetermined time (for example, 100 mS) from the start of power supply. A reset signal 6 that is at a high level (hereinafter referred to as “H level”) for a while is generated and output to the ASIC 1.
[0042]
When the reset signal 6 is input to the ASIC 1 from the reset IC 39, the F / F circuit 9a performs clock synchronization with the reset signal 6. The reset signal synchronized with the clock is input to the reset terminal of the CPU 2, and the CPU 2 is initialized.
[0043]
The peripheral logic circuit 3 and the special-purpose logic circuit 4 initialize based on the clock signal 5 before the high-level enable signals 21a and 21b are input to the respective ENB terminals. When completing the initialization, the peripheral logic circuit 3 and the special-purpose logic circuit 4 output an initialization completion signal 11 and an initialization completion signal 12 to the AND circuit 13, respectively. When both the initialization completion signal 11 and the initialization completion signal 12 are input, the AND circuit 13 outputs an initialization completion notification signal 14 to the CPU 2. When receiving the initialization completion notification signal 14, the CPU 2 outputs an enable signal 19 to the AND circuits 10a and 10b.
[0044]
On the other hand, the reset signal 6 supplied from the reset IC 39 is inverted by the inverter circuit 7 to become the internal reset signal 8, which is sent to the inverted AND circuits 10a and 10b.
[0045]
In the AND circuits 10a and 10b, when the enable permission signal 19 is received from the CPU 2 and the internal reset signal 8 is at a low level (hereinafter referred to as "L level"), that is, when the reset signal 6 is at an H level. , H level signals to the F / F circuits 9b and 9c, respectively.
[0046]
The F / F circuits 9b and 9c receiving these H-level signals synchronize the H-level enable signals 21a and 21b with the clock signal 5 and then turn on the ENB terminals of the peripheral logic circuit 3 and the special-purpose logic circuit 4 respectively. To each. As a result, the peripheral logic circuit 3 and the special-purpose logic circuit 4 enter an operation permission state.
[0047]
If there is no input of the initialization completion notification signal 14 within the specified time, the CPU 2 outputs the enable permission signal 19 for a certain period of time, whereby the peripheral logic circuit 3 and the specific use logic circuit 4 are initialized again. Try to make
[0048]
As described above, when the CPU 2 confirms that the initialization has been completed in the peripheral logic circuit 3 and the specific-purpose logic circuit 4, the CPU 2 outputs the enable permission signal 19 and operates the peripheral logic circuit 3 and the specific-purpose logic circuit 4. Move to the permission state.
[0049]
At this time, the special-purpose logic circuit 4 outputs a signal for initialization to the control circuit of the printhead 1005, and outputs a signal for initialization to a drive circuit for driving each motor.
[0050]
Next, a case where the ASIC 1 is mounted on a printer will be described.
[0051]
FIG. 3 is a block diagram illustrating a configuration of the printer 31 on which the ASIC 1 is mounted.
[0052]
Reference numeral 32 denotes a wiring board on which an electric circuit for driving and controlling the printer 31 is mounted. The ASIC 1 is mounted on the wiring board 32. A power supply unit 33 supplies power to an electric circuit on the wiring board 32 and supplies power to each drive unit (not shown) via the electric circuit.
[0053]
Reference numeral 34 denotes an AC cable for supplying commercial power to the power supply unit 33. An operation panel unit 35 is used when a user operates the printer 31. Reference numeral 36 denotes a memory unit mounted on the wiring board 32, which temporarily stores information sent from the ASIC 1 and supplies storage information to the ASIC 1.
[0054]
A drive circuit 37 controls the operation of each drive portion (not shown) in the printer 31. The drive circuit 37 has a drive circuit for the carriage motor 1014 and the transport motor 1018. The drive circuit 37 drives the carriage motor 1014 and the transport motor 1018 based on a control signal from the ASIC 1.
[0055]
Reference numeral 38 denotes an I / F connector. The printer 31 receives print data from the host computer 46 which is an external device of the printer 31 via the I / F connector 38. Further, the printer 31 sends setting information and the like of the printer 31 to the host computer 46 via the I / F connector 38.
[0056]
A reset IC 39 monitors a power supply voltage supplied from the power supply unit 33, and outputs a reset signal 6 which becomes H level for a predetermined time (for example, 100 ms) from the start of power supply. The predetermined time is set to a time required until the internal circuit of the ASIC 1 reaches a sufficiently operable state.
[0057]
Reference numeral 40 denotes a clock generation circuit which generates a clock signal 5 for operating the ASIC 1 at predetermined time intervals. An operation bus 41 connects the operation panel unit 35 and the ASIC 1 and sends information from the operation panel unit 35 to the ASIC 1. Information from the ASIC 1 is sent to the operation panel unit 35 via the operation bus 41 and displayed.
[0058]
A memory bus 42 connects the memory unit 36 to the ASIC 1 and is used for writing information from the ASIC 1 to the memory unit 36 and reading information from the memory unit 36 to the ASIC 1.
[0059]
A DC line 43 connects the power supply unit 33 to the ASIC 1, the reset IC 39, etc., and supplies DC power. The DC line 43 includes a power supply line for a logic circuit for operating the ASIC 1 and the like, and a power supply line for a drive circuit for operating the drive circuit 37. Note that the voltage of the drive circuit power supply line is higher than the voltage of the logic circuit power supply line.
[0060]
A drive bus 44 connects the ASIC 1 and the drive circuit 37, and is used to transmit a drive signal from the ASIC 1 to the drive circuit 37.
[0061]
An I / F bus 45 connects the ASIC 1 and the I / F connector 38, and is used for transmitting print data created by the host computer 46 to the ASIC 1 and transmitting information from the printer 31 to the host computer 46. .
[0062]
An I / F cable 47 connects the host computer 46 and the printer 31.
[0063]
Reference numeral 48 denotes a recording head. 49 is a flexible cable. 50 is a control circuit of the recording head 48, and 51 is a driving circuit of the recording head 48. A control signal for driving the recording head 48 is sent from the ASIC 1 to the control circuit 50 of the recording head 48 via the flexible cable 49.
[0064]
When an initialization signal is sent from the ASIC 1 to the control circuit 50 in the recording head 48, the control circuit 50 in the recording head 48 is initialized.
[0065]
Next, the operation of the printer 31 will be described.
[0066]
The printer 31 is used by inserting an AC cable 34 into a commercial power outlet. First, when the AC cable 34 is inserted into a power outlet, the power supply unit 33 converts AC (commercial power) into DC power supply voltages (logic circuit power supply voltage and drive circuit power supply voltage) required by the printer 31 and converts them into a DC line. 43.
[0067]
The DC line 43 is connected to the ASIC 1 and the reset IC 39, and the ASIC 1 and the reset IC 39 are driven. Here, the reset IC 39 constantly monitors the supply voltage of the DC line 43 and, when detecting that the power is supplied, outputs the reset signal 6 which becomes H level for a predetermined time (for example, 100 mS) from the time of the detection, to the ASIC 1. Output to
[0068]
This predetermined time is set to the time required until the internal circuit of the ASIC 1 reaches a sufficiently operable state, as described above. The operation in the ASIC 1 supplied with the reset signal 6 is as described with reference to FIG.
[0069]
Thus, in the ASIC 1 according to the first embodiment, when each of the plurality of circuits 2, 3, and 4 constituting the ASIC 1 is initialized, the initialization timing of each circuit can be controlled to an appropriate timing.
[0070]
(Second embodiment)
FIG. 4 is a block diagram illustrating a configuration of the ASIC according to the second embodiment. Since the configuration of the second embodiment is basically the same as that of the first embodiment shown in FIG. 2, the same components will be denoted by the same reference characters and description thereof will be omitted. In the description of the second embodiment, the configuration of the printer shown in FIG. 3 is used.
[0071]
In the second embodiment, the reset signal 6a externally supplied to the ASIC 1a is Low active. The reset signal 6a is at a low level (hereinafter referred to as "L level") only for a predetermined time (for example, 100 mS) from the start of power supply. In addition, the inverter circuit 7 in the first embodiment is deleted, and AND circuits 20a and 20b are provided instead of the AND circuits 10a and 10b, respectively.
[0072]
In the ASIC 1a to which the reset signal 6a has been input, the F / F circuit 9a performs clock synchronization with the reset signal 6. In the second embodiment, the clock-synchronized signal is input from the non-inverting output terminal of the F / F circuit 9a to the reset terminal of the CPU 2, and the CPU 2 is initialized.
[0073]
On the other hand, the peripheral logic circuit 3 and the special-purpose logic circuit 4 are initialized based on the clock signal 5 and output initialization completion signals 11 and 12 to the AND circuit 13, respectively. As a result, the AND circuit 13 outputs an initialization completion notification signal 14 to the CPU 2.
[0074]
As a result, the CPU 2 outputs the enable permission signal 19 to the AND circuits 20a and 20b. The logical product circuits 20a and 20b take the logical product of the enable signal 19 and the reset signal 6a and output the logical product to the F / F circuits 9b and 9c.
[0075]
The F / F circuit 9b outputs an enable signal 21a to the ENB terminal of the peripheral logic circuit 3, and the F / F circuit 9c outputs an enable signal 21b to the ENB terminal of the specific use logic circuit 4. The peripheral logic circuit 3 and the special-purpose logic circuit 4 receive the enable signals 21a and 21b, respectively, and enter the operation permission state.
[0076]
At this time, the specific-purpose logic circuit 4 outputs a signal for initialization to the control circuit 50 of the recording head 48, and outputs a signal for initialization to the drive circuit 37 for driving each motor.
[0077]
FIG. 5 is a timing chart showing an initialization operation performed by the ASIC 1a according to the second embodiment shown in FIG.
[0078]
In FIG. 5, CLK is a clock signal 5 input to the ASIC 1a. PS is a voltage waveform of the power supplied from the power supply unit 33 shown in FIG. 3 to the ASIC 1a.
[0079]
S6 is the waveform of the reset signal 6a. For a short time after the power supply voltage rises, the operation of each circuit block of the ASIC 1a becomes unstable, and the normal operation of the ASIC 1a is not guaranteed. Therefore, the reset IC 39 monitors the power supply voltage (voltage waveform PS), and after a lapse of a predetermined time from detecting that the power supply voltage has exceeded the prescribed voltage, resets the reset signal 6a (waveform S6) from the L level. Change to H level.
[0080]
S19 is a waveform of the enable permission signal 19. S11 is a waveform of the initialization completion signal 11 output from the peripheral logic circuit 3. S12 is a waveform of the initialization completion signal 12 output from the specific use logic circuit 4. S14 is the waveform of the initialization completion notification signal 14 output from the AND circuit 13. S21 is a waveform of the enable signals 21a and 21b.
[0081]
Next, the temporal transition of the signal waveform in FIG. 5 will be described.
[0082]
When power is supplied from the power supply unit 33 shown in FIG. 3 to the ASIC 1a and the reset IC 39, the reset IC 39 changes the reset signal 6a (S6) to the L level until the power supply voltage becomes equal to or higher than the specified voltage and a predetermined time has elapsed. Keep in state.
[0083]
The elapse of the predetermined time is measured by a counter in the reset IC 39, and the operation of the counter is asynchronous with the clock signal 5 (CLK) applied to the ASIC 1a.
[0084]
The peripheral logic circuit 3 and the special-purpose logic circuit 4 perform initialization based on the clock signal 5 (CLK) while the reset signal 6a (S6) is at the L level, and after the initialization is completed, the initialization completion signal 11 (S11). ) And the initialization completion signal 12 (S12) are changed from L level to H level.
[0085]
The AND circuit 13 receiving the initialization completion signal 11 (S11) and the initialization completion signal 12 (S12) performs a logical product operation, sets the initialization completion notification signal 14 (S14) to the H level, and outputs the signal to the CPU 2. As a result, the CPU 2 recognizes that the peripheral logic circuit 3 and the special-purpose logic circuit 4 have been normally initialized.
[0086]
Thereafter, the CPU 2 confirms that the reset signal 6a (S6) is at the H level, and sets the enable permission signal 19 (S19) to the H level. As a result, the outputs of the AND circuits 20a and 20b change from L level to H level, and the clock-synchronized enable signals 21a and 21b (S21) change to H level, respectively. As a result, the peripheral logic circuit 3 and the special-purpose logic circuit 4 enter an operation permission state.
[0087]
The process in which the peripheral logic circuit 3 and the special-purpose logic circuit 4 enter the operation permission state has been described above with reference to FIG. 5, but another initialization operation will be described with reference to FIG.
[0088]
FIG. 6 is a timing chart illustrating another initialization operation performed by the ASIC 1a according to the second embodiment.
[0089]
When the CPU 2 receives the initialization completion notification signal 14 (S14), the CPU 2 changes the enable permission signal 19 (S19) from L level to H level. Thereafter, when the reset signal 6a (S6) changes from the L level to the H level, the AND circuits 20a and 20b output an H level signal, and the F / F circuits 9b and 9c output the enable signals 21a and 21b (S21). Change from L level to H level. As a result, the peripheral logic circuit 3 and the special-purpose logic circuit 4 enter an operation permission state.
[0090]
That is, as shown in FIGS. 5 and 6, the timing when the reset signal 6a (S6) changes from the L level to the H level before and after the timing when the enable permission signal 19 (S19) changes from the L level to the H level. Even so, the CPU 2 can reliably put the peripheral logic circuit 3 and the special-purpose logic circuit 4 into the operation permission state. That is, the CPU 2 can reliably cause the peripheral logic circuit 3 and the special-purpose logic circuit 4 to perform the operation after the initialization without depending on the timing of the reset signal 6a (S6).
[0091]
It should be noted that the initialization completion signal 11 (S11) and the initialization completion signal 12 (S12) may not shift from the L level to the H level even after a predetermined time has elapsed. In this case, since the peripheral logic circuit 3 and the special-purpose logic circuit 4 cannot be set to the operation permission state, the CPU 2 attempts to initialize the peripheral logic circuit 3 and the special-purpose logic circuit 4 again.
[0092]
FIG. 7 is a timing chart showing the operation of the ASIC 1a when the peripheral logic circuit 3 and the special-purpose logic circuit 4 are initialized again in the second embodiment.
[0093]
In FIG. 7, when the power supply voltage PS rises, the reset signal 6a (S6) shifts to the H level after maintaining the L level for a predetermined time. Here, if the initialization completion signal 12 (S12) does not change from the L level to the H level, and therefore the initialization completion notification signal 14 (S14) does not shift from the L level to the H level, the CPU 2 sets the enable permission signal 19 (S12). (S19) is changed from L level to H level once. Then, after a predetermined time (after three clocks of the clock signal 5 (CLK) are generated), the level is returned from the H level to the L level.
[0094]
Accordingly, the enable signals 21a and 21b (S21) shift from the L level to the H level, and shift from the H level to the L level after a predetermined time (after three clocks). When the enable signals 21a and 21b (S21) change from the H level to the L level, the peripheral logic circuit 3 and the special-purpose logic circuit 4 restart initialization, and the initialization completion signal 11 (S11) and the initialization completion signal. 12 (S12) becomes L level.
[0095]
When the initialization is started, in the peripheral logic circuit 3, a clock means (not shown) in the ASIC 1a samples the clock signal 5 and starts counting. Similarly, the special-purpose logic circuit 4 samples the clock signal 5 and starts counting. Then, when the count reaches a predetermined count value, the peripheral logic circuit 3 changes the initialization completion signal 11 (S11) from L level to H level. Similarly, when the count number reaches a predetermined count value, the special-purpose logic circuit 4 also changes the initialization completion signal 12 (S12) from L level to H level.
[0096]
Thus, if the peripheral logic circuit 3 and the special-purpose logic circuit 4 have not completed initialization, the CPU 2 can cause the peripheral logic circuit 3 and the special-purpose logic circuit 4 to execute the initialization again, so that the ASIC 1a Can realize a reliable operation.
[0097]
(Third embodiment)
FIG. 8 is a block diagram showing a configuration of the ASIC according to the third embodiment. Since the configuration of the third embodiment is basically the same as that of the second embodiment shown in FIG. 4, the same components are denoted by the same reference numerals and description thereof will be omitted.
[0098]
In the ASIC 1b according to the third embodiment, the AND circuits 20a and 20b and the F / F circuit 9c according to the second embodiment are deleted, and an F / F circuit 9d is newly added. The F / F circuit 9d outputs a synchronized reset signal 22, which is a signal obtained by synchronizing the reset signal 6a with a clock, to the peripheral logic circuit 3 and the special-purpose logic circuit 4. An enable signal 19 from the CPU 2 is input to the F / F circuit 9b, and the F / F circuit 9b outputs an enable signal 21 to each of the ENB terminals of the peripheral logic circuit 3 and the special purpose logic circuit 4.
[0099]
FIG. 9 is a timing chart showing an initialization operation performed by the ASIC 1b according to the third embodiment shown in FIG. In the figure, the same reference numerals as those in the timing chart of the second embodiment shown in FIG. 5 denote the same signals, and a description thereof will be omitted.
[0100]
This timing chart shows each signal waveform when the initialization completion signal 12 (S12) output from the specific use logic circuit 4 in the third embodiment does not shift from the L level to the H level even after a predetermined time has elapsed. Is shown.
[0101]
As in the second embodiment, when the power supply voltage PS rises, the reset signal 6a (S6) shifts to the H level after maintaining the L level for a predetermined time. When the reset signal 6a (S6) shifts to the H level, the synchronization reset signal 22 (S22) shifts from the L level to the H level.
[0102]
If the initialization completion signal 12 (S12) does not change from the L level to the H level and the initialization completion notification signal 14 (S14) does not change from the L level to the H level, the CPU 2 sets the enable permission signal 19 (S19). Is temporarily shifted from the L level to the H level, and is returned from the H level to the L level after a predetermined time.
[0103]
Thus, the enable signal 21 (S21) output from the F / F circuit 9b temporarily shifts from the L level to the H level, and shifts from the H level to the L level after a predetermined time. When the enable signal 21 (S21) returns to the L level, the peripheral logic circuit 3 and the special-purpose logic circuit 4 start initialization, and the initialization completion signal 11 (S11) and the initialization completion signal 12 (S12) are at the L level. become.
[0104]
Thereafter, when it can be considered that the initialization has been completed in the peripheral logic circuit 3 and the specific-purpose logic circuit 4 after a predetermined period of time, respectively, the initialization completion signal 11 (S11) and the initialization completion signal 12 (S12) become L level. To H level.
[0105]
As a result, the initialization completion notification signal 14 (S14) shifts from the L level to the H level, and the CPU 2 is notified that the peripheral logic circuit 3 and the specific-purpose logic circuit 4 have completed the initialization. Upon receiving this, the CPU 2 sets the enable permission signal 19 (S19) to the H level.
[0106]
The F / F circuit 9b that has received the enable permission signal 19 (S19) that has become the H level transfers the enable signal 21 (S21) obtained by synchronizing the enable permission signal 19 (S19) with the clock to the peripheral logic circuit 3 and the specific application. It outputs to each ENB terminal of the logic circuit 4.
[0107]
Each of the peripheral logic circuit 3 and the specific-purpose logic circuit 4 receiving the enable signal 21 (S21) confirms the H level of the synchronization reset signal 22 (S22) and shifts to the operation permission state.
[0108]
As described above, the CPU 2 confirms the completion of the initialization of the peripheral logic circuit 3 and the specific-purpose logic circuit 4, and further confirms that the reset signal 6a (S6) is at the H level. Further, the operation after initialization can be reliably performed by the specific-purpose logic circuit 4.
[0109]
(Fourth embodiment)
FIG. 10 is a block diagram showing a configuration of an ASIC according to the fourth embodiment. Since the configuration of the fourth embodiment is basically the same as that of the second embodiment shown in FIG. 4, the same components are denoted by the same reference numerals and description thereof will be omitted.
[0110]
In the ASIC 1c according to the fourth embodiment, the AND circuit 13 according to the second embodiment is deleted, and the CPU 2 has two ports for inputting the initialization completion signal 11 and the initialization completion signal 12. ing.
[0111]
The CPU 2 performs a logical product operation of the initialization completion signal 11 and the initialization completion signal 12 input to these two ports, and confirms the completion of the initialization of the peripheral logic circuit 3 and the specific use logic circuit 4.
[0112]
Except for the above points, the operation of the fourth embodiment is the same as that of the second embodiment.
[0113]
(Other embodiments)
In the first to fourth embodiments, an ASIC (integrated circuit device) as a control circuit of a printer has been described. In the ASIC, there is one specific-purpose logic circuit. May be provided.
[0114]
In the first to fourth embodiments, the specific-purpose logic circuit 4 processes the print data and controls the recording head 48. However, the present invention is not limited thereto. 4 may control communication with the host computer.
[0115]
In the first to fourth embodiments, after receiving the enable signal 21a, the specific-purpose logic circuit 4 outputs a signal for initialization to the control circuit of the recording head 48 and the drive circuit of each motor. However, the output timing of this signal is not limited to the timing after receiving the enable signal 21a. The specific-purpose logic circuit 4 may output an initialization signal to the control circuit of the recording head 48 or the drive circuit of each motor, for example, in accordance with an instruction sent from the CPU 2 at a predetermined timing. Alternatively, the specific-purpose logic circuit 4 may output an initialization signal to the control circuit of the recording head 48 or the drive circuit of each motor after outputting the initialization completion signal 12.
[0116]
In the first to fourth embodiments, the AND circuit 13 that receives the initialization completion signal from the peripheral logic circuit 3 and the specific-purpose logic circuit 4 has two input terminals. Is not limited to two. For example, when the ASIC includes a CPU, a peripheral logic circuit, and two special-purpose logic circuits, the AND circuit has three input terminals for calculating the logical product of three initialization completion signals. To
[0117]
Further, in the first to fourth embodiments, the case where the initialization completion signal 11 shifts from the L level to the H level before the initialization completion signal 12 has been described as an example (FIGS. 5 to 7, 9), the order of the transition is not limited to this, and the initialization completion signal 12 may transition from the L level to the H level before the initialization completion signal 11.
[0118]
Further, in the first to fourth embodiments, the system is such that the heater is heated in the recording head 48 to discharge the ink. However, the recording head 48 may be constituted by a piezo element instead. . In addition, although the number of recording elements (nozzles) of the recording head 48 is 128, the number is not limited thereto, and may be, for example, 256. Further, the resolution of the recording head 48 is 600 DPI, but is not limited to this, and may be, for example, 1200 DPI.
[0119]
Further, in the first to fourth embodiments, a serial type in which a carriage reciprocates to perform recording is described as an example of a printer. However, the present invention is not limited to this. A printer using a full-line type recording head having a length corresponding to the width of the maximum recording medium may be used.
[0120]
Further, the program code itself of software for realizing the functions of the above-described embodiments may constitute the present invention, and a storage medium storing the program code may constitute the present invention.
[0121]
In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.
[0122]
As a storage medium for supplying the program code, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, nonvolatile memory card, ROM, or the like is used. Can be.
[0123]
When the computer executes the readout program code, not only the functions of the above-described embodiments are realized, but also the OS or the like running on the computer is actually executed based on the instructions of the program code. It goes without saying that the present invention includes a case where some or all of the processing is performed and the functions of the above-described embodiments are realized by the processing.
[0124]
Further, after the program code read from the storage medium is written into a memory provided on a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It is needless to say that the present invention includes a case where a CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.
[0125]
【The invention's effect】
As described in detail above, claim 1OrClaim6According to the described invention,A central processing unit, a special purpose logic circuit, and a peripheral logic circuit bus-connected between the special purpose logic circuit and the central processing unit,Based on external reset signalThe central processing unit, the special purpose logic circuit, and the peripheral logic circuitPerform initializationOne-chip configurationIn an integrated circuit device,The peripheral logic circuit controls data transmission performed between an externally provided program ROM and the special-purpose logic circuit and the central processing unit, and the special-purpose logic circuit and the peripheral logic circuit respectivelyOutputting an initialization completion signal to the central processing unit when the initialization is completed;IsBased on each of the initialization completion signals input,For special purpose logic circuits and the peripheral logic circuitsAllow actionRuiNavel signalOutPower.The central processing unit changes the output of the enable signal when at least one of the special-purpose logic circuit and the peripheral logic circuit does not output an initialization completion signal for a predetermined time, thereby changing the output of the enable signal. The circuit and the peripheral logic circuit are initialized again.
[0126]
This allowsIn a one-chip integrated circuit device composed of a central processing unit, a special-purpose logic circuit, and a peripheral logic circuit, each of the constituent circuits (devices) immediately after the start of power supply has a different input voltage rise and the like. Even if the reset timing in the constituent circuits (devices) is shifted, only after the central processing unit confirms that the initialization in the special purpose logic circuit and the peripheral logic circuit has been completed, the special purpose logic circuit and the peripheral logic Since the operation permission signal is output to the circuit, the initialization timing of each constituent circuit (device) can be controlled to an appropriate timing. Further, even if the initialization for the specific-purpose logic circuit and the peripheral logic circuit fails for some reason, the central processing unit causes the specific-purpose logic circuit and the peripheral logic circuit to be initialized again. Can be started in a correct order.
[Brief description of the drawings]
FIG. 1 is a perspective view of a printer equipped with an integrated circuit device according to the present invention.
FIG. 2 is a block diagram showing a configuration of a first embodiment of the integrated circuit device according to the present invention.
FIG. 3 is a block diagram illustrating a configuration of a printer equipped with an ASIC.
FIG. 4 is a block diagram illustrating a configuration of an ASIC according to a second embodiment.
FIG. 5 is a timing chart showing an initialization operation performed by the ASIC according to the second embodiment shown in FIG.
FIG. 6 is a timing chart illustrating another initialization operation performed by the ASIC according to the second embodiment.
FIG. 7 is a timing chart illustrating an operation of the ASIC when the peripheral logic circuit and the specific-purpose logic circuit are initialized again in the second embodiment.
FIG. 8 is a block diagram illustrating a configuration of an ASIC according to a third embodiment.
FIG. 9 is a timing chart showing an initialization operation performed by the ASIC according to the third embodiment shown in FIG.
FIG. 10 is a block diagram illustrating a configuration of an ASIC according to a fourth embodiment.
FIG. 11 is a block diagram showing a configuration of a conventional ASIC.
[Explanation of symbols]
1 ASIC (integrated circuit device)
2 CPU (central processing unit, enable signal output means, initialization means)
3. Peripheral logic circuit (circuit block, completion signal output means)
4 Special-purpose logic circuit (circuit block, completion signal output means)
5 Clock signal
6 Reset signal
7 Inverter circuit
8 Internal reset signal
9a, 9b, 9c Flip-flop circuit (F / F circuit)
10a, 10b inverted AND circuit
11 Initialization completion signal
12 Initialization completion signal
13 AND circuit (logical operation means)
14 Initialization completion notification signal
15a, 15b data bus
19 Enable permission signal
21a, 21b enable signal
31 Printer (inkjet recording device)
32 Wiring board
33 power supply unit
34 AC cable
35 Operation panel unit
36 memory units
37 Drive Circuit
38 I / F connector
39 Reset IC
40 Clock generation circuit
41 Operation bus
42 Memory Bus
43 DC line
44 Drive bus
45 I / F bus
46 Host computer
47 I / F cable
48 recording head
49 Flexible cable
50 control circuit
51 Drive circuit
1014 Carriage motor
1018 Transport motor

Claims (8)

A central processing unit, a special-purpose logic circuit, and a peripheral logic circuit connected to the central processing unit by a bus between the special-purpose logic circuit and the central processing unit; A one-chip integrated circuit device for performing initialization of a logic circuit and the peripheral logic circuit ,
The peripheral logic circuit controls an externally provided program ROM and the special-purpose logic circuit, and data transmission performed between the central processing unit,
The specific-purpose logic circuit and the peripheral logic circuit each have a completion signal output unit that outputs an initialization completion signal to the central processing unit when initialization is completed,
The central processing unit, the specific application on the basis of the logic circuit and the initialization completion signal output from each of the peripheral logic circuit, allow to Louis enable the operation to the specific application logic circuit and the peripheral logic circuit an enable signal output means for output the signal, if the initialization completion signal from at least one of the completion signal output means of the specific application logic circuit and the peripheral logic circuit is not output for a predetermined time, the enable An integrated circuit device comprising re-initializing means for changing the output of a signal to cause the special-purpose logic circuit and the peripheral logic circuit to perform initialization again . A logical operation is performed on the initialization completion signal output from each of the completion signal output means included in the specific use logic circuit and the peripheral logic circuit, and a result of the logical operation is output to the central processing unit. 2. The integrated circuit device according to claim 1, further comprising a logical operation unit. The enable signal output means, said application specific logic circuits and if all the completion signal output unit of the peripheral logic circuit outputs an initialization completion signal, the said enable signal application specific logic circuits and the peripheral logic circuit 2. The integrated circuit device according to claim 1, wherein the integrated circuit device outputs the data. The re-initialization means, after outputting the enable signal, stops the output after a second predetermined time, thereby causing the special-purpose logic circuit and the peripheral logic circuit to start re-initialization. The integrated circuit device according to claim 1, wherein The integrated circuit device is an integrated circuit device according to any one of claims 1 to 4, characterized in that it is installed in the printer. An integrated circuit device including a central processing unit, a special purpose logic circuit, and a peripheral logic circuit connected to the central processing unit by a bus for controlling a printing operation using a print head And a reset signal generating circuit for generating a reset signal, the inkjet recording apparatus,
The integrated circuit device, and a special purpose logic circuit and central processing unit and the peripheral logic circuit for performing each initialized based on the reset signal,
The peripheral logic circuit and the special-purpose logic circuit each include a completion signal output unit that outputs an initialization completion signal to the central processing unit after initialization based on the reset signal is completed,
The central processing unit on the basis of the peripheral logic circuit and each initialization completion signal output from the completion signal output means of the specific application logic, the operation start of each of the peripheral logic circuit and said application specific logic circuits From at least one of the peripheral logic circuit and the specific use logic circuit, and an enable signal output means for outputting an enable signal for permitting to the peripheral logic circuit and the special use logic circuit. When the initialization completion signal is not output for a predetermined time, re-initialization means for changing the output of the enable signal to cause the peripheral logic circuit and the specific-purpose logic circuit to restart initialization again. An inkjet recording apparatus characterized by the above-mentioned. The recording head has a control circuit,
7. The ink jet recording apparatus according to claim 6, wherein the specific use logic circuit outputs a signal for initializing the control circuit to the control circuit. A driving circuit for performing the recording operation ;
The ink jet recording apparatus according to claim 6, wherein the specific use logic circuit outputs a signal for initializing the drive circuit to the drive circuit.

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