JP3591453B2 - Oscillator, display data processing device, matrix type display device, oscillation signal generation method, and display data processing method - Google Patents

Description

となる。ここで発振周波数ｆＯＳＣ４は、

となる。但しＴｎ＝Ｃ×Ｖ／Ｉｎ、Ｔｐ＝Ｃ×Ｖ／Ｉｐであり、ＭＯＳバッファ１のディレイ値は除いている。
【００７９】
上式（１）、（２）、（４）から明らかなように、発振周波数ｆＯＳＣ４は、電流値Ｉ２により任意に調整できる。そしてこの電流値Ｉ２は、バイアス調整回路１７により調整される。またデューティ比Ｄ４はＤ４＝Ｉｎ／（Ｉｎ＋Ｉｐ）であるため、上式（３）から明らかなように、トランジスタのサイズ比等を変更することで任意に設定できる。
【００８０】
（実施例５）
実施例５も、電流源及びバイアス回路の具体的構成の例を示すものであり、図７にその回路構成を示す。上記実施例４と異なるのは、Ｐ型ＭＯＳトランジスタ２６、Ｎ型ＭＯＳトランジスタ２７を新たに設けると共に、Ｐ型ＭＯＳトランジスタ１１のゲート電極への電圧印加を、バイアス端子１３ではなく、バイアス端子１３’（第３のバイアス端子）により行っている点である。そしてＰ型ＭＯＳトランジスタ２６（第９トランジスタ）は、ゲート電極及びソース領域がバイアス端子１３’に接続され、またＮ型ＭＯＳトランジスタ２７（第１０トランジスタ）は、ゲート電極がバイアス端子１４に接続されると共にドレイン領域がバイアス端子１３’に接続される。
【００８１】
トランジスタ２６、２７のベータ値をβｐ３、βｎ３とすると、カレントミラーにより以下の式が成り立つ。
【００８２】

上式（５）、（６）から明らかなように、上記実施例４と同様に、発振周波数ｆＯＳＣ５は、バイアス調整回路１７からの電流値Ｉ２により任意に調整できる。またデューティ比Ｄ５も、上式（７）から明らかなように、トランジスタのサイズ比等を変更することで任意に設定できる。
【００８３】
なお実施例５の構成は実施例４に比べて以下の点で有利である。即ち図６の実施例４では、上式（３）から明らかなようにトランジスタ２４、２５のトランジスタサイズを調整すること等でデューティ比が調整される。ところが端子１５にバイアス調整回路１７が接続されること等に起因して、トランジスタ２４、２５のドレイン・ソース領域間に印加される電圧は小さい。従ってトランジスタ２４、２５を飽和領域にて動作させるためには、トランジスタ２４、２５に許容されるトランジスタサイズはある程度制限される。実施例４ではこのような制限のもとで、トランジスタ２４、２５のトランジスタサイズにより更にデューティ比も調整しなければならないため、設計が難しい。これに対して実施例５では、上式（７）から明らかなようにトランジスタ２６、２７のトランジスタサイズを調整することでデューティ比を調整できる。従ってトランジスタ２４、２５のトランジスタサイズをデューティ比の設定とは無関係に調整できるため、設計が容易となる。この設計の容易性の差は、電源電圧が低電圧化された場合に更に顕著となる。
【００８４】
なお実施例４、５ではバイアス調整回路１７は端子１５の位置に挿入されているが、本発明はこれに限らず、端子８１６、８１７、８１８のいずれの位置に挿入しても構わない。
【００８５】
（実施例６）
実施例６はバイアス調整回路の具体的例を示すものである。バイアス調整回路としては例えば図８（Ａ）〜（Ｄ）に示すもの等が考えられる。
【００８６】
図８（Ａ）に示すバイアス調整回路は可変抵抗２８から成り、周波数選択信号１８で抵抗値を変更することで発振周波数を調整する。
【００８７】
図８（Ｂ）に示すバイアス調整回路は抵抗２９、３０及びこれらの各々に接続されるスイッチ３１、３２を含み、スイッチ３１、３２を周波数選択信号１８で選択することによって発振周波数を調整する。
【００８８】
図８（Ｃ）に示すバイアス調整回路は、抵抗２９、３０及びこれらの各々に接続されるフューズ３３、３４を含み、フューズ３３、３４を周波数選択信号１８で選択することによって発振周波数を調整できる。
【００８９】
図８（Ｄ）に示すバイアス調整回路は、抵抗２９、３０及びこれらの各々に接続されるＭＯＳトランジスタ３５、３６を含み、ＭＯＳトランジスタ３５、３６のゲート電極に周波数選択信号１８である制御信号３７、３８を送ることによって発振周波数を調整できる。
【００９０】
なお、図８（Ｂ）〜（Ｄ）では、抵抗が２個の例を挙げているが複数であっても構わない。
【００９１】
また抵抗は、ＭＯＳトランジスタで作ることも可能である。この場合、例えば図８（Ｂ）では、スイッチ３１、３２をＭＯＳトランジスタにより構成し、ＭＯＳトランジスタのオン抵抗により抵抗２９、３０の抵抗値を代用させることもできる。
【００９２】
なお電流源１１、１２の電流値Ｉｎ、Ｉｐを調整することにより、もしくは図６、図７の端子１５を流れる電流値又は端子１５における電圧値を調整することにより、本発明を、ＶＣＯ（ＶＯＬＴＡＧＥ ＣＯＮＴＲＯＬＥＤ ＯＳＣＩＬＬＡＴＯＲ）に適用することも可能である。例えば、本発明をＶＣＯとして使用し、これに周知の位相比較回路、フィルターを付加することで、ＰＬＬ（ＰＨＡＳＥ ＬＯＣＫＫＥＤ ＬＯＯＰ）回路を構成できる。この場合、次のような用途が考えられる。例えば液晶パネル等において、複数の表示データ処理装置を用意し、これらの複数の表示データ処理装置からの表示データを切り替えて使用し、液晶パネル上に表示画面を表示する。この時、各々の表示データ処理装置に内蔵される発振装置は異なる周波数で発振するため、各表示データ処理装置のフレーム信号の周波数も７０〜１３０Ｈｚの範囲（仕様の範囲）でばらつく。従って複数の表示データ処理装置からの表示データを切り替えて使用するためには、これらのフレーム信号を同期させる必要がある。そこで、このような場合に、外部（他の表示データ処理装置）からの外部フレーム信号と、ＶＣＯの出力により作られる内部フレーム信号とを位相比較回路に入力し、位相比較を行う。そして位相比較回路の出力を、フィルターによって適正な電圧及び電流に変換しＶＣＯに入力する。これにより、１の表示データ処理装置と他の表示データ処理装置との間で、フレーム信号を同期させることが可能となる。この結果、複数の表示データ処理装置からの表示データを切り替えて使用するような場合に、表示画像の乱れ等をなくすことができる。
【００９３】
（実施例７）
以下に説明する実施例７〜１２は表示データ処理装置に関する実施例である。
【００９４】
図９に実施例７の表示データ処理装置の構成を示す。実施例７は、第１メモリ（画像表示メモリ）３５３、第２メモリ（画像表示パターン発生器）３５５、格納手段（ラインメモリ）３５７、第１、第２等価回路３５４、３５６を含む。実施例７の特徴は以下の通りである。即ち第１信号３７１は第１メモリ３５３、第１等価回路３５４に入力されており、第１信号３７１が有効レベル（例えばＬレベル）になると第１メモリ３５３の読み出し動作が行われ第１データ３７９が出力される。この時の読み出しアドレスはアドレス信号３７７により決められる。ここで第１等価回路３５４は、第１信号３７１に基づいて第２信号３７２を出力するものであり、第１メモリ３５３から読み出される第１データ３７９が確定した時点又はそれ以降に第２信号３７２を有効レベル（例えばＬレベル）にする。第２信号３７２は第２メモリ３５５、第２等価回路３５６に入力されており、第２信号３７２が有効レベルになると第２メモリ３５５の読み出し動作が行われ第２データ３８０が出力される。この時、第２メモリ３５５の読み出しは、第１データ３７９に基づいて行われる。また第２等価回路３５６は、第２信号３７２に基づいて第３信号３７３を出力するものであり、第２メモリ３５５から読み出される第２データ３８０が確定した時点又はそれ以降に第３信号３７３を有効レベル（例えばＬレベル）にする。第３信号３７３が有効レベルになると、格納手段３５７への第２データ３８０の書き込み動作が行われる。この時の格納アドレスは例えばアドレス信号３７７により決められる。
【００９５】
実施例７では上記のように、第１、第２、第３信号３７１、３７２、３７３が有効レベルとなると、第１、第２メモリ３５３、３５５の読み出し動作並びに格納手段３５７の書き込み動作が行われる。これに加えて例えば、第１、第２、第３信号３７１、３７２、３７３が非有効レベル（例えばＨレベル）になった場合に、第１、第２メモリ３５３、３５５、格納手段３５７の中の少なくとも１つがプリチャージ動作するようにしてもよい。このようにすれば第１、第２メモリ３５３、３５５、格納手段３５７に読み出し動作・プリチャージ動作のいずれを行わせるかの選択を、第１信号３７１等の信号レベルを制御するだけで実現でき、回路制御を簡易化できる。また読み出し期間・プリチャージ期間の設定を、第１信号３７１等のデューティ比を制御するだけで実現できる。特に、上記実施例１〜６で説明したデューティ比の調整が可能な発振装置を用いた場合には次のような利点がある。即ち第１信号３７１を実施例１〜６の発振装置の出力により生成し、発振装置によりデューティ比を調整することで、読み出し期間・プリチャージ期間の設定を自由に調整できるという利点がある。
【００９６】
なおデータの読み出しに必要な時間（読み出しのアクセスタイム）とプリチャージに必要な時間（プリチャージのアクセスタイム）との関係は、読み出しのアクセスタイムを１００とすると、一般にプリチャージのアクセスタイムは５〜４０程度となる（好ましくは１０〜３０程度）。このため第１信号３７１は、５〜４０％程度のデューティ比の波形とすることが望ましい。
【００９７】
次に実施例７の動作を、図１０に示すタイミングチャート図を用いて説明する。まず第１信号３７１をＬレベル（有効レベル）にする（図１０のＡ参照）。この時、アドレス信号３７７は、第１信号３７１がＬレベルになる前に確定させておく（Ｂ参照）。なお図１０に示すＣＫはクロック信号であり、このＣＫは例えば実施例１〜６で説明したような発振装置により生成する。第１信号３７１はこのクロック信号ＣＫを反転した信号となっている。
【００９８】
第１信号３７１がＬレベルになると第１メモリ３５３からのデータ読み出しが行われ、所定のディレイ期間経過後に第１データ３７９が確定する（Ｃ参照）。この時、第１等価回路３５４の出力である第２信号３７２は、第１データ３７９の確定と同時又はそれよりも少し遅れてＬレベルとなる（Ｄ参照）。第２信号３７２は第２メモリ３５５に入力されており、第２信号３７２がＬレベルになると、第１データ３７９をアドレス信号とするデータ読み出しが第２メモリ３５５において行われる。そして所定のディレイ期間経過後に第２データ３８０が確定する（Ｅ参照）。第２信号３７２は第２等価回路３５６にも入力されており、第２等価回路３５６の出力である第３信号３７３は、第２データ３８０の確定と同時又はそれよりも少し遅れてＬレベルとなる（Ｆ参照）。第３信号３７３がＬレベルになると、第２データ３８０が格納手段３５７に書き込まれる。
【００９９】
第１信号３７１がＨレベルになると（Ｇ参照）、第１メモリ３５３はプリチャージ動作に移行する。そして実施例７では第１信号３７１がＨレベルになると、第２、第３信号３７２、３７３もＨレベルになり（Ｈ、Ｉ参照）、これにより第２メモリ３５５、格納手段３５７もプリチャージ動作に移行する。但し、第１、第２メモリ３５３、３５５、格納手段３５７がプリチャージ動作を有しないものである場合はプリチャージ動作させる必要はない。例えば格納手段３５７が、Ｄフィリップフロップ等を含むラッチ回路等により構成される場合には、格納手段３５７をプリチャージ動作させる必要はなく、第３信号３７３をＨレベルにする必要はない。なお、この場合、第３信号３７３は、格納手段（ラッチ回路）３５７に第２データ３８０をラッチさせるための取り込み信号の役割を果たすことになる。
【０１００】
以上のように実施例７によれば、第１、第２等価回路を設けることで、データの読み出し・プリチャージ動作等のタイミング調整を自己制御的に行うことができる。従って従来例のようにタイミング調整のための種々の制御信号を生成する必要も無く、また、クロック信号の１周期で無駄無く読み出し・プリチャージ動作を行うことができるため、回路規模及び消費電力を大幅に削減できる。
【０１０１】
（実施例８）
図１１に実施例８の表示データ処理装置の構成を示す。上記実施例７との相違は、第３等価回路３５８、選択回路３５２が新たに設けられている点である。第３等価回路３５８は、第３信号３７３に基づいて第４信号３７６を出力するものであり、格納手段３５７に第２データ３８０が書き込まれた時点又はそれ以降に第４信号３７６を有効レベルにする。選択回路３５２は、入力された第４信号３７６、クロック信号ＣＫ３７０とに基づいて第１信号３７１を生成し、これを第１メモリ３５３、第１等価回路３５４に出力する。より具体的には第４信号３７６が有効レベルになった場合に、第１信号を非有効レベル（例えばＨレベル）にする。これにより、望ましくは第２信号３７２、第３信号３７３も非有効レベルになる。第１、第２、第３信号３７１、３７２、３７３が非有効レベルになると、第１、第２メモリ３５３、３５５、格納手段３５７がプリチャージ動作に移行する。
【０１０２】
図１２には実施例８の動作を説明するためのタイミングチャート図が示される。図１０に示す実施例７と異なるのは、格納手段３５７へのデータ書き込みが完了すると第４信号３７６がＬレベルになり（図１２のＪ参照）、これにより第１〜第３信号３７１〜３７３がＨレベルになり（Ｋ、Ｌ、Ｍ参照）、第１、第２メモリ３５３、３５５等がプリチャージ動作に移行する点である。
【０１０３】
格納手段３５７に第２データ３８０が書き込まれてしまえば、その後は第１データ３７９、第２データ３８０はどのようなデータに変化しても構わない。一方、メモリ等においては、消費電力の節減及び動作の高速化のために、データを読み出した後、なるべく早くプリチャージ動作に移行させることが望ましい。実施例８によれば、格納手段３５７へデータが書き込まれた時点又はそれ以降に第４信号３７６が有効レベルにされる。これにより第１〜第３信号３７１〜３７３を非有効レベルにし、第１、第２メモリ３５３、３５５、格納手段３５７をプリチャージ動作に移行させることができるため、消費電力の大幅な節減、動作の高速化等が可能となる。このように実施例８によれば、読み出し動作のみならず、プリチャージ動作についても自己制御できる。
【０１０４】
（実施例９）
図１３に実施例９の表示データ処理装置の構成を示す。上記実施例８との相違は、選択回路３５２が、第２等価回路３５６と第３等価回路３５８との間にある点である。これにより、格納手段３５７に第２データ３８０が書き込まれた時点で（又はそれよりも遅く）、第３等価回路３５８の出力である第４信号３７６が有効レベルになり、選択回路３５２の出力である第３’信号３７４が非有効レベルになる。これにより格納手段３５７はプリチャージ動作に移行する。即ち、格納手段３５７へデータが書き込まれた時点で、第１、第２メモリ３５３、３５５が第１、第２信号３７１、３７２によってプリチャージされるよりも前に、自己的に書き込み動作を終了する。これにより格納手段３５７のプリチャージ動作への移行を速めることができ、消費電力の低減、動作の高速化を図れる。
【０１０５】
なお選択回路３５２は、図１１、図１３に示した場所に限らず種々の場所に配置できる。即ち選択回路３５２は、図１３のＡ、Ｂ、Ｃで示す場所の少なくとも１カ所に配置でき、２カ所に配置したり３カ所に配置したりすることもできる。そしてＡ、Ｂ、Ｃの全ての場所に配置する構成は、回路規模の面では不利であるが、低消費電力、高速動作の点では有利となる。
【０１０６】
また上記実施例７〜９では、含まれるメモリが２個の場合を例にとり説明したが、本発明はこれに限らず、表示データ処理装置が３個以上の複数のメモリを有する場合も本発明の範囲に含まれる。図１４には、例えば実施例８（図１１参照）においてＮ個のメモリを含む場合の構成例が示される。図１４でＮ、Ｋは整数であり、１＜Ｋ≦Ｎとなっている。実施例７、９及び下記する実施例１０〜１２において、メモリをＮ個含ませる場合も、図１４と同様の構成となる。
【０１０７】
（実施例１０）
実施例１０は、本発明に係る表示データ処理装置の更なる具体例を示すものであり、図１５にその構成が示される。
【０１０８】
表示データ処理装置の代表例である文字パターン発生器付きの表示データ処理装置に本発明を適用した場合を説明する。ここで表示データＲＡＭ（表示データメモリ）５５・ＣＧＲＯＭ（文字パターン発生回路）５９・ドライバ回路６３は、各々、実施例７〜９の第１メモリ・第２メモリ・格納手段に相当するものである。
【０１０９】
ここで表示データＲＡＭ５５は、マイクロコントローラ及びプロセッサー等から送られる１画面分の文字コード信号を記憶する。ＣＧＲＯＭ５９は、この文字コード信号に対応した文字パターンを発生する。ドライバ回路（信号駆動回路）６３は、文字パターン信号を１水平期間中に時分割記憶するラッチ機能を有する。そして、この表示データ処理装置を用いて、ドライバー回路６３により駆動される複数の信号電極と、走査駆動回路により順次走査される複数の走査電極とが交差するドットマトリックスパネルに対して文字パターン等を表示する。
【０１１０】
例えばドットマトリックスパネルにＮ×Ｍの文字を表示し、１文字の構成がｎ×ｍドットである場合を考える。１文字の中の１画素行（１ドットライン）分のデータが、表示データＲＡＭ５５からＣＧＲＯＭ５９を介してドライバー回路６３へと転送される一連の動作の期間を１Ｃ（１キャラクタ）とする。またＣＧＲＯＭ５９のデータ出力をｎビットとする。するとＮ×１Ｃの期間が１ドットライン期間（１Ｈ）となり、Ｍ×ｍ×Ｎ×１Ｃの期間が１フレーム期間（１ＦＲ）となる。
【０１１１】
マイクロコントローラ及びプロセッサー等からの表示データＲＡＭ５５に対する表示データの書き込みは、書き込み用データ信号８３と、アドレス信号４９（書き込み用アドレス信号８４をアドレスデコーダ６４によりアドレスデコードしたもの）とに基づいて行われる。
【０１１２】
発振装置５０より出力されたクロック信号７０は、タイミング発生回路５１に入力される。タイミング発生回路５１は必要な制御信号であるＲＡＭ用アドレス信号７７、ＣＧＲＯＭ用アドレス信号７８を発生する。表示データＲＡＭ５５は１種のフレームメモリーであって文字（表示）コードが格納されている。ＣＧＲＯＭ５９には表示データＲＡＭ５５の文字コードに対応する文字パターンデータ（表示データ）が格納されている。ドライバー回路６３はＣＧＲＯＭ５９から出力される文字パターンデータ８２をラッチし、かつ蓄積する。そしてその蓄積された文字パターンデータに応じた液晶駆動電圧を液晶パネルに送り、これにより液晶パネルへ表示画面が表示される。
【０１１３】
図１６には、従来の手法（図３７（Ａ）参照）で表示データ処理装置を構成したものが比較例として示される。
【０１１４】
実施例１０（図１５参照）と比較例との相違点は、実施例１０では、アドレスデコーダ５３、表示データＲＡＭ５５、アドレスデコーダ５７、ＣＧＲＯＭ５９、アドレスデコーダ６１の各々に対応して、ダミー回路である等価回路５４、５６、５８、６０、６２が設けられている点である。
【０１１５】
また比較例では、タイミング発生回路２５１が、アドレスデコーダ２５３、表示データＲＡＭ２５５、アドレスデコーダ２５７、ＣＧＲＯＭ２５９、アドレスデコーダ２６１に対して読み出し及びプリチャージのための信号２７０、２７４、２７５を発生している。これに対して、実施例１０ではこれらを発生しない。即ち実施例１０では、発振装置５０より出力されたクロック信号７０がＲＳラッチ回路５２に入力され、このＲＳラッチ回路５２の出力７１が、アドレスデコーダ５３の等価回路５４に入力される。そして等価回路５４の出力７２は、等価回路５６、５８、６０、６２を経由してプリチャージ信号７６となり、このプリチャージ信号７６はＲＳラッチ回路５２にフィードバックされている。
【０１１６】
次に実施例１０における表示データの読み出し動作について説明する。
【０１１７】
表示データＲＡＭ５５のアドレス信号７７は、発振装置５０から出力されるクロック信号７０に基づきタイミング発生回路５１により生成され、表示データＲＡＭ用のアドレスデコーダ５３に入力される。更にクロック信号７０は、ＲＳラッチ回路５２を経て読み出し信号７１としてアドレスデコーダ５３及び等価回路５４に入力される。そして読み出し信号７２、アドレス信号７９が、等価回路５４、アドレスデコーダ５３から同時に出力される（７９よりも７２を遅くしてもよい）。ここで読み出し信号７１はＬレベルで有効レベル（アクティブ）となり、クロック信号７０がＬレベルの時に読み出し信号７１もＬレベルになる。
【０１１８】
表示データＲＡＭ５５は、アドレスデコードされたアドレス信号７９の状態に応じて読み出し信号７２によってアドレスセットされる。ここで読み出し信号７２はアドレスデコードに要する時間分だけ読み出し信号７１よりも遅れている。読み出し信号７２がＬレベルになると、文字コード信号８０とＣＧＲＯＭ用読み出し信号７３とが同時に出力される（８０よりも７３を遅くしてもよい）。
【０１１９】
ＣＧＲＯＭ用のアドレスデコーダ５７は、文字コード信号８０及びアドレス信号７８の状態に応じたアドレスデコードを行い、アドレス信号８１をＣＧＲＯＭ５９に出力する。ここで読み出し信号７４は、アドレス信号８１と同時に出力されており（８１よりも７４を遅くしてもよい）、アドレスデコードに要する時間分だけ読み出し信号７３よりも遅れている。次に、読み出し信号７４により文字パターンデータ８２、読み出し信号７５が同時に出力される（８２よりも７５を遅くしてもよい）。
【０１２０】
ドライバー回路用のアドレスデコーダ６１は、アドレス信号７７の状態に応じたアドレスデコードを行い、変換アドレス信号（取り込み信号）４８をドライバー回路６３に出力する。これによりドライバー回路６３をアドレスセットするとともに文字パターンデータ８２をドライバ回路６３にラッチし蓄積する。ここでプリチャージ信号７６と変換アドレス信号４８とは同時に出力されている（４８よりも７６を遅くしてもよい）。
【０１２１】
プリチャージ信号７６はＲＳラッチ回路５２にフィードバックされる。そしてアドレスデコーダ５３、表示データＲＡＭ５５、アドレスデコーダ５７、ＣＧＲＯＭ５９、アドレスデコーダ６１等を次々にプリチャージする。従ってこの場合には、信号７１、７２、７３、７４、７５はプリチャージ信号となる。こうして読み出し動作及びプリチャージ動作を繰り返すことで、表示データが読み出される。
【０１２２】
図１７に実施例１０の動作を説明するためのタイミングチャート図を示す。
【０１２３】
クロック信号７０をＣＫとし、表示データＲＡＭ５５の読み出し及びプリチャージ信号となる信号７１をＥＩＲＡＭとし、アドレス信号７７をＡＲＡＭとしている。ＣＧＲＯＭ５９のアドレス信号となる文字コード信号８０をＡＲＯＭとし、ＣＧＲＯＭ５９の読み出し及びプリチャージ信号となる信号７３をＥＩＲＯＭとしている。ドライバー回路６３のアドレス信号７７をＡＲＡＴとし、ドライバ回路６３の書き込み及びプリチャージ信号となる信号７５をＥＩＬＡＴとし、入力データとなる文字パターンデータ８２をＤＬＡＴとしている。またドライバー回路６３に蓄積された信号の波形をＤＤＲＶとしている。ここでＥＩＲＡＭがＬレベルになると読み出し動作となり、Ｈレベルになるとプリチャージ動作となる。またＥＩＲＯＭ、ＥＩＬＡＴがＨレベルになると読み出し動作となり、Ｌレベルになるとプリチャージ動作となる。タイミング発生回路５１はＥＩＲＡＭ、ＥＩＲＯＭ、ＥＩＬＡＴを発生しておらず、各々の回路が自己制御で動作する。このため、タイミング発生回路５１は、アドレス信号ＡＲＡＭ（７７、７８）、ＡＬＡＴ（７７）を同じタイミングで発生するのみとなる。
【０１２４】
なお図１８には比較例のタイミングチャート図が示される。図１７と図１８を比較すれば理解されるように、比較例で必要な高い周波数のクロックが実施例１０では必要なく、従って実施例１０によれば消費電力を低減できる。また実施例１０では、ＥＩＲＯＭ、ＥＩＬＡＴ等をタイミング発生回路５１で生成する必要がないため、回路規模の削減、動作の高速化を図れる。
【０１２５】
次に、アドレスデコーダ５３、５７、６１、表示データＲＡＭ５５、ＣＧＲＯＭ５９及び等価回路５４、５８、６０、６２の詳細な回路構成の一例について説明する。まず図１９にアドレスデコーダ５３及びその等価回路５４の具体例を示す。
【０１２６】
ＭＯＳトランジスタ８７〜９０は直列ＲＯＭを構成する。そしてデータ無し（例えばデータ”０”）に対応するトランジスタはドレイン領域とソース領域とをショートさせ、データ有り（例えばデータ”１”）に対応するトランジスタはショートさせない。ショートするか否かの切り替えは、マスクＲＯＭと同様に、メタル切り替え方式、イオン注入プログラム方式（フィールド切り替え）等で実現できる。ＭＯＳトランジスタ８５により直列ＲＯＭからのデータ読み出しが制御され、ＭＯＳインバータ９９により直列ＲＯＭからの信号が増幅される。ＭＯＳトランジスタ９５、９６はそれぞれプリチャージ用、電位固定用である。アドレスデコーダ５３の等価回路５４は、アドレスデコーダ５３の１アドレスライン（７９の中の１ライン）分のＲＯＭと同等に構成されており、相違するのはＭＯＳトランジスタ９１〜９４が読み出し信号７１によって制御されている点である。
【０１２７】
アドレス信号７７の状態に応じてアドレスラインのいずれか（７９のいずれか）が選択され、これによりアドレス信号７７がアドレスデコードされる。次にＥＩＲＡＭ７１がＬレベルになると、アドレスデコードされた信号が変換アドレス信号７９として表示データＲＡＭ５５へと出力される。それと同時にアドレスデコーダの等価回路５４は、表示データＲＡＭ５５の読み出し信号７２を出力する。この時、アドレスラインの中でディレイ値が最も大きいラインに接続されるトランジスタと少なくとも同数のトランジスタがライン７０１に接続されている。これにより読み出し信号７２が、変換アドレス信号７９と同時又はこれよりも遅く出力されることが保証される。
【０１２８】
次に表示データＲＡＭ５５及び等価回路５６の詳細な回路構成について図２０を用いて説明する。
【０１２９】
ＭＯＳインバータ１０５、１０６、データ書き込み用のＭＯＳトランジスタ１０９、１１０、データ読み出し用のＭＯＳトランジスタ１０７、１０８により１ｂｉｔのＲＡＭセル１２５を構成する。ＲＡＭの出力セル１２６は、プリチャージ用、電位固定用のＭＯＳトランジスタ１１６、１１８、及びデータ信号１１４の増幅用のＭＯＳインバータ１２０、１２２を含む。
【０１３０】
ＭＯＳトランジスタ１１３は、ＲＡＭセル１２５内のＭＯＳトランジスタ１０８と等価であり、ＭＯＳトランジスタ１１１、１１２はそれぞれ、ＲＡＭセル１２５内のＭＯＳトランジスタ１０７、１０８と等価である。またＭＯＳトランジスタ１１７、１１９、ＭＯＳインバータ１２１、１２３は、ＲＡＭの出力セル１２６と等価となっている。等価回路５６は、これらのトランジスタ１１１、１１２、１１３、１１７、１１９、ＭＯＳインバータ１２１、１２３を含んで構成される。アドレスデコーダ５３、等価回路５４から同時に出力されるアドレス信号７９、読み出し信号７２が、表示データＲＡＭ５５、等価回路５６に同時に入力され、これによりＥＩＲＯＭ７３、ＡＲＯＭ（文字コード信号）８０が同時に出力される。このようにＥＩＲＯＭ７３は、表示データＲＡＭ５５の等価回路５６によって自己的にタイミング調整される。
【０１３１】
ここでデータ信号８３、アドレス信号４９は表示データＲＡＭへの書き込み用である。なお本実施例１０ではデュアルポートＲＡＭを使用しているため、読み出し動作と書き込み動作は独立してオペレーションできる。
【０１３２】
次にアドレスデコーダ５７、ＣＧＲＯＭ５９及び等価回路５８、６０の詳細な回路構成について図２１を用いて説明する。
【０１３３】
ＲＯＭセル１３９はＭＯＳトランジスタ１３８を含む。ＭＯＳトランジスタ１３０、１３１はそれぞれプリチャージ用、電位固定用であり、ＭＯＳインバータ１３２、１３３はデータ信号の増幅用であり、これらによりＣＧＲＯＭ５９の出力セルが構成される。ＭＯＳトランジスタ１４７は読み出し制御用である。
【０１３４】
ＣＧＲＯＭ５９用のアドレスデコーダ５７はＭＯＳトランジスタ１５０、１５１、１５４を含み、その基本構成は、表示データＲＡＭ用のアドレスデコーダ５３（図１９参照）と同様である。
【０１３５】
ＭＯＳトランジスタ１５２、１５３、１５５はアドレスデコーダ５７内のＭＯＳトランジスタ１５０、１５１、１５４と等価であり、等価回路５８はこれらのＭＯＳトランジスタ１５２、１５３、１５５を含んで構成される。
【０１３６】
ＭＯＳトランジスタ１４６はＭＯＳトランジスタ１４７と等価であり、ＭＯＳトランジスタ１４０、１４１はＲＯＭセル１３９、１５７内のＭＯＳトランジスタ１３８、１５６と等価である。またＭＯＳトランジスタ１３４、１３５、ＭＯＳインバータ１３６、１３７は、ＣＧＲＯＭ５９の出力セル内のＭＯＳトランジスタ１３０、１３１、ＭＯＳインバータ１３２、１３３と等価である。等価回路６０は、これらのＭＯＳトランジスタ１４６、１４０、１４１、１３４、１３５、ＭＯＳインバータ１３６、１３７を含んで構成される。
【０１３７】
表示データＲＡＭ５５及びその等価回路５６から同時に出力されるＡＲＯＭ（文字コード信号）８０及びＥＩＲＯＭ７３が、ＣＧＲＯＭ用のアドレスデコーダ５７及びその等価回路５８に同時に入力され、ＣＧＲＯＭ５９及びその等価回路６０を経由して、ＤＬＡＴ（文字パターンデータ）８２及びＥＩＬＡＴ７５が同時に出力される。即ちＥＩＬＡＴ７５は、アドレスデコーダ５７用の等価回路５８及びＣＧＲＯＭ５９用の等価回路６０によって自己的にタイミング調整される。
【０１３８】
次にアドレスデコーダ６１及びその等価回路６２の詳細な回路構成について図２２を用いて説明する。
【０１３９】
ＭＯＳトランジスタ１６２〜１６５は直列ＲＯＭを構成する。ＭＯＳトランジスタ１６０により直列ＲＯＭからのデータ読み出しが制御され、ＭＯＳインバータ１７４により直列ＲＯＭからの信号が増幅される。ＭＯＳトランジスタ１７０、１７１はそれぞれプリチャージ用、電位固定用である。等価回路６２は、アドレスデコーダ６１内の１アドレスライン分のＲＯＭと同等に構成されており、相違するのはＭＯＳトランジスタ１６６〜１６９が読み出し信号７５によって制御されている点である。
【０１４０】
アドレス信号７７の状態に応じてアドレスラインのいずれか（４８のいずれか）が選択され、これによりアドレス信号７７がアドレスデコードされる。次にＥＩＬＡＴ７５がＨレベルになると、アドレスデコードされた信号が変換アドレス信号４８としてドライバー回路６３へと出力される。そしてこの変換アドレス信号（取り込み信号に相当）４８に基づき、すでに出力されているＤＬＡＴ（文字パターンデータ）８２がドライバー回路６３にラッチし蓄積される。それと同時に等価回路６２はＲＳラッチ回路５２へとＲＳ７６を出力する。即ちＲＳ７６は等価回路６２によって自己的にタイミング調整される。
【０１４１】
次にＲＳラッチ回路５２の具体的構成について図２３を用いて説明する。
【０１４２】
ＲＳラッチ回路５２は、ＮＡＮＤ１８０、１８１、１８２、ＭＯＳインバータ１８３を含む。クロック信号ＣＫ７０及びプリチャージ信号ＲＳ７６は共にＨレベルで有効レベル（アクティブ）になる。即ちＣＫ７０がＨレベルになるとＥＩＲＡＭ７１はＬレベルになり、表示データＲＡＭ５５からドライバー回路６３へと送るデータの読み出し動作を行う。そしてその読み出し動作の終了を示す信号であるＲＳ７６がＨレベルになると、ＥＩＲＡＭ７１はＨレベルになり、プリチャージ動作が開始される。
【０１４３】
なお実施例１０では、等価回路が５個ある場合（５４、５６、５８、６０、６２）の構成を説明したが、アドレスデコーダ、メモリ等の数を増やし等価回路を６個以上設けた構成としても構わない。またアドレスデコーダ及びメモリーと、等価回路とは、出力を同時にするとして主に上記説明を行ったが、等価回路の出力がアドレスデコーダ及びメモリーの出力よりも遅くなるようにしてもよい。即ち、製造バラツキ等考慮して、等価回路の出力がアドレスデコーダ及びメモリーの出力より遅くなるように、ある程度のマージンをもたせた等価回路の設計及び設定を行うことが好ましい。
【０１４４】
以上のように本実施例によれば、クロック信号ＣＫ７０の１周期の期間（１Ｃの期間）に１水平ドットラインの中の１文字分の表示データの読み出しが行われる。このようにデータの読み出しからラッチまでの１連のオペレーションの制御を、クロック信号ＣＫ７０だけで行うことができる。これは各回路に等価回路を設け、制御信号となる読み出し信号の遅延時間が、データ読み出しの遅延時間と同等になるように等価回路を構成することで実現される。これにより、各回路のアクセスタイムを考慮したタイミング信号を発生させる必要がなくなり、高い周波数のクロック信号（読み出し信号の３〜５倍）を使用する必要が無くなる。ＣＭＯＳ回路の消費電流ＩＤＤは、周波数ｆ、電圧Ｖ、負荷容量Ｃとすると、ＩＤＤ＝ｆ×Ｖ×Ｃとなる。従ってクロック周波数の低減により、消費電流を１／３〜１／５に低減できる。このように本実施例によれば、制御回路を削減でき、且つこの回路の削減及び発振周波数の低減により消費電流の低減を実現できる。
【０１４５】
また等価回路を設けることで読み出し及びプリチャージ動作等のタイミングを自己制御できるため、発振装置からのクロック信号の１周期で、無駄なく、読み出し及びプリチャージ動作を制御でき、装置の低消費電力化及び高速動作化を実現できる。
【０１４６】
（実施例１１）
実施例１１はドライバ回路の具体的な構成を示す実施例であり、図２４にその構成が示される。
【０１４７】
図２４に示すように、ドライバ回路（以下、信号駆動回路と呼ぶ）６３は、駆動部４１５、ラインメモリ４１６、４１７を含む。駆動部４１５は駆動回路４１５−ａ、４１５−ｂ、４１５−１〜４１５−ｎ／５を含み、ラインメモリ４１６はラッチ回路４１６−ａ、４１６−ｂ、４１６−１〜４１６−ｎ／５を含み、ラインメモリ４１７は第２ラッチ回路４１７−ａ、４１７−ｂ、第１ラッチ回路４１７−１〜４１７−ｎ／５を含む。信号駆動回路６３の出力は、マトリックスパネル４５３上の信号電極ＳＡ１〜ＳＡ５、Ｓ１〜Ｓｎ、ＳＢ１〜ＳＢ５に出力される。マトリックスパネル４５３上には、液晶素子等の表示画素がマトリックス状に配置されるとともに、複数の信号電極ＳＡ１〜ＳＡ５、Ｓ１〜Ｓｎ、ＳＢ１〜ＳＢ５及び走査電極Ｃｓ１、Ｃ１〜Ｃｍ、Ｃｓ２が交差して配置される。ここでＳ１〜Ｓｎ、Ｃ１〜Ｃｍは文字表示用であり、ＳＡ１〜ＳＡ５、ＳＢ１〜ＳＢ５、Ｃｓ１、Ｃｓ２はアイコン表示用である。図２５には、実施例１１によりマトリックスパネル４５３上に表示される表示画面の一例が示される。表示画面上には、文字１２２０及びアイコン１２２２〜１２３０が表示されている。そして表示画面の上側にあるアイコン表示領域には通話マークアイコン１２２２、電話マークアイコン１２２４が表示され、左右側にあるアイコン表示領域には電池のバッテリー残量を示すインジケーターアイコン１２２６、１２２８が表示されている。また表示画面の下側にあるアイコン表示領域には電池マークアイコン１２３０が表示されている。このように実施例１１によれば、表示画面の上下及び左右にアイコンを表示できる。
【０１４８】
駆動部４１５は、信号電極ＳＡ１〜ＳＡ５、Ｓ１〜Ｓｎ、ＳＢ１〜ＳＢ５を駆動するための信号を生成するものであり、これにより図２５に示すような文字及びアイコンの表示が可能となる。ここで駆動回路４１５−ａ、４１５−ｂはアイコン表示用であり、駆動回路４１５−１〜４１５−ｎ／５は文字表示用である。ラインメモリ４１６は、ラインメモリ４１７からのデータをラッチパルスＬＰ４１１によりラッチするものであり、ラッチされたデータは１水平期間毎に駆動部４１５に転送される。ここでラッチ回路４１６−ａ、４１６−ｂはアイコン表示用であり、ラッチ回路４１６−１〜４１６−ｎ／５は文字表示用である。ラインメモリ４１７は、ＣＧＲＯＭ５９から出力されるＤＬＡＴ８２を、取り込み信号４８（４８−ａ、４８−ｂ、４８−１〜４８−ｎ／５）に基づいて時分割に格納するものである。ここで第２ラッチ回路４１７−ａ、４１７−ｂ、取り込み信号４８−ａ、４８−ｂはアイコン表示用であり、第１ラッチ回路４１７−１〜４１７−ｎ／５、４８−１〜４８−ｎ／５は文字表示用である。
【０１４９】
ＣＧＲＯＭ５９は、文字パターンデータのみならずアイコンパターンデータも発生する。そして発生した文字パターンデータ、アイコンパターンデータは、ＣＧＲＯＭ５９に含まれるマルチプレクサ４１２によりマルチプレクスされ、文字パターンデータ、アイコンパターンデータが時系列に並んだ信号であるＤＬＡＴ８２が生成される。そしてＤＬＡＴ８２に含まれる文字パターンデータは、取り込み信号４８−１〜４８−ｎ／５により第１ラッチ回路４１７−１〜４１７−ｎ／５に順次格納される。一方、ＤＬＡＴ８２に含まれるアイコンパターンデータは、取り込み信号４８−ａ〜４８−ｂにより第２ラッチ回路４１７−ａ、４１７−ｂに格納される。これにより第１ラッチ回路４１７−１〜４１７−ｎ／５に対応する信号電極Ｓ１〜Ｓｎ上に文字が表示されると共に、第２ラッチ回路４１７−ａ、４１７−ｂに対応する信号電極ＳＡ１〜ＳＡ５、ＳＢ１〜ＳＢ５上にアイコンが表示される。
【０１５０】
また例えば所定のアイコンパターンデータがＤＬＡＴ８２として出力されている時に、取り込み信号４８−ａ、４８−ｂを同時に発生すれば、図２５に示すように同一アイコン（インジケーターアイコン１２２６、１２２８）を２つの異なる領域に同時に表示できる。また、アイコンパターンデータがＤＬＡＴ８２として出力されている時に、例えば取り込み信号４８−２を発生すれば、文字表示領域へアイコン表示することも可能となる。このように本実施例によれば、マトリックスパネル４５３上の任意の領域へ文字及びアイコンを表示できる。これによりマトリックスパネル上への、より複雑で高度な画像表示が可能となる。また本実施例によれば、文字あるいはアイコンの移動を行うこともできる。この文字等の移動も取り込み信号４８の発生タイミングを制御することにより可能となる。このような文字等の移動が可能となると、例えば携帯電話において、ダイヤルボタンを押す毎に前に押した番号の文字を表示パネルにおいて左側に移動する等の処理が可能となる。
【０１５１】
さて取り込み信号４８を発生するアドレスデコーダ６１は、図２４に示すようにデコーダ回路４１０（４１０−ａ、４１０ー１〜４１０−ｎ／５、４１０−ｂ）及び等価回路６２を含む。取り込み信号４８（４８−ａ、４８ー１〜４８−ｎ／５、４８−ｂ）の発生タイミングは、デコーダ回路４１０におけるＲＯＭプログラミングの設定等により制御できる。デコーダ回路４１０−ａは１アドレスライン分の直列ＲＯＭ及び出力セルに相当するものであり、例えば図２２のＭＯＳトランジスタ１６０〜１６５、１７０、１７１及びＭＯＳインバータ１７４を含むものである。デコーダ回路４１０ー１〜４１０−ｎ／５、４１０−ｂも同様である。従ってＲＯＭプログラミングの設定により、即ちどのＭＯＳトランジスタのドレイン及びソース領域をショートするかを設定することにより、取り込み信号（変換アドレス信号）４８の発生タイミング（有効となるタイミング）を制御できる。ＡＬＡＴ７７は、例えば（００００）、（０００１）・・・・（１１１１）というように順次インクリメントされ、デコーダ回路４１０−ａはこのＡＬＡＴ７７をデコードする。そしてＡＬＡＴ７７が所定値になった時にデコーダ回路４１０−ａが選択され取り込み信号４８−ａが発生し、これによりその時にＤＬＡＴ８２として出力されているデータが第２ラッチ回路４１７−ａに格納される。例えばＡＬＡＴ７７が所定値の時に、デコーダ回路４１０−ａ、４１０ーｂの両方を選択し、取り込み信号４８−ａ、４８ーｂの両方を発生するようにすれば、図２５のように同一のアイコン（インジケーターアイコン１２２６、１２２８）を異なる場所に表示できる。
【０１５２】
また等価回路６２は、図２２において説明したように、デコーダ回路と同様の回路構成となっており、取り込み信号４８が発生される（有効になる）のとほぼ同時（又は遅く）にＲＳ７６を有効にする。これにより少なくともラインメモリ４１７にデータが書き込まれた時点又はそれ以降にＲＳ７６を有効にし、表示データＲＡＭ、ＣＧＲＯＭ等をプリチャージ動作に移行させることが可能となる。
【０１５３】
なお実施例１１では、ラインメモリ４１７等に格納されるデータ（ＤＬＡＴ８２に含まれるデータ）として文字パターンデータとアイコンパターンデータの２種類のデータを考えた。しかしながら本発明はこれに限らず、ラインメモリ４１７に第１〜第Ｌ（Ｌは整数）の種類のデータを格納するようにしてもよい。この場合には、ラインメモリ４１７は第１〜第Ｌのラッチ回路を含むことになる。但し、第１〜第Ｌラッチ回路の回路構成はお互いに同じものであっても構わない。
【０１５４】
（実施例１２）
実施例１２は、表示データ処理装置に含まれる等価回路を用いて発振信号を生成する実施例であり、図２６にその構成を示す。
【０１５５】
等価回路２１は、実施例７（図９参照）の等価回路３５４及び３５６、実施例８及び実施例９（図１１及び図１３参照）の等価回路３５４、３５６及び３５８、実施例１０（図１５参照）の等価回路５４、５６、５８、６０及び６２に相当するものである。そして図２６に示すように等価回路２１の出力、例えば実施例７の第３信号３７３、実施例８の第４信号３７６等を第１信号として帰還し、自己発振ループを形成する。これにより等価回路２１による信号ディレイ等を利用した発振が可能となる。
【０１５６】
この時、図２６に示すように、発振周波数、デューティ比の少なくとも一方を制御できる制御手段９００を設けることが望ましい。このようにすれば例えば等価回路２１のディレイ値等が製造プロセスのバラツキ等に依存して変動し、得られる発振周波数数が変動した場合において、発振周波数を、発振装置に要求される周波数に近づけることが可能となる。またデューティ比を制御して、表示データ処理装置内のメモリ等を適正に動作させることが可能となる。
【０１５７】
図２７には、等価回路２１の出力を遅延回路２０を介して等価回路２１の入力に帰還して、リングオシレータを形成した場合の構成例が示される。この場合には、遅延回路２０が制御手段９００に相当し、遅延回路２０における信号ディレイを調整することで発振周波数等を制御できる。ここで遅延回路２０は、波形整形用のインバータ、バッファ等で代用することもできる。図２８には、実施例７の回路において、遅延回路２０を設けると共に自己発振ループを形成し、リングオシレータを形成した場合の例が示される。
【０１５８】
従来のリングオシレータを１０Ｋ〜５００ＫＨｚ程度の低い周波数で発振させようとすると、回路規模もしくは素子数が非常に大きくなり実用に適さないという問題があった。しかしながら実施例１２によれば、等価回路のディレイを利用しているため、回路規模をそれほど大きくすることなく、このような低い周波数での発振が可能になる。
【０１５９】
図２９には、本実施例と実施例１とを組み合わせて発振周波数及びデューティ比の両方を制御する場合の構成例が示される。図２９と図１を比較すれば理解されるように、この構成では、実施例１のＭＯＳバッファ３０１の出力に等価回路２１が付加される。この時、ＭＯＳバッファ３０１と等価回路２１とによりバッファ手段が構成される。但しＭＯＳバッファ３０１については必ずしも設ける必要はない。
【０１６０】
図３０には、本実施例と実施例３とを組み合わせて発振周波数及びデューティ比の両方を制御する場合の構成例が示される。ここで例えば等価回路２１の遅延時間をｔ（２１）とし、電流源１１、１２の値をそれぞれＩｎ、Ｉｐとする。すると発振周波数ｆＯＳＣ１２は、
ｆＯＳＣ１２＝１／｛Ｔｎ＋Ｔｐ＋ｔ（２１）｝
となる。但しＴｎ＝Ｃ×Ｖ／Ｉｎ、Ｔｐ＝Ｃ×Ｖ／Ｉｐであり、ＭＯＳバッファ１のディレイ値は除いている。よって電流源１１、１２の電流値Ｉｎ、Ｉｐを調整することによって、発振周波数ｆＯＳＣ１２を自由に調整及び設定できる。
【０１６１】
以上説明した実施例１２によると、実施例１〜６の発振装置と実施例７〜１１の表示データ処理装置の双方の利点を得ることができる。そして表示データ処理装置内に含まれる回路（メモリ等）に対して動作時間を無駄なく割り当てることができると共に、これらの回路の有するディレイ値等を用いて発振装置の発振周波数を決めることができる。これにより製造プロセスの変動に影響されにくく、また低消費電力で高速動作が可能な表示データ処理装置を提供できる。
【０１６２】
なお、本発明は上記実施例１〜実施例１２に限定されるものではなく、本発明の要旨の範囲内で種々の変形実施が可能である。
【０１６３】
例えば実施例１の充電手段、放電手段の具体的構成は実施例２〜６で説明したものに限らない。また図４ではバイアス回路、バイアス調整回路を設けたが、これらを設けなくてもよく、またバイアス回路、バイアス調整回路の構成も実施例４〜６で説明したものに限らない。
【０１６４】
また表示データ処理装置に含まれるメモリも、表示データＲＡＭ、ＣＧＲＯＭ等に限らず、各種のメモリを考えることができる。またメモリ間等に他の回路を挿入した場合も本発明の均等な範囲に含まれる。また格納手段は、少なくともデータを格納できるものであれば、ラッチ回路、メモリ等、種々のものを採用できる。更にアドレスデコーダも実施例１０等で説明した構成に限られるものではない。
【０１６５】
また実施例１〜６の発振装置を実施例７〜１２に組み合わせると、低消費電力化、回路の小規模化等の観点で特に効果があるが、実施例７〜１２に組み合わせる発振装置は実施例１〜６に示すものに限られるものではない。即ち、発振信号のデューティ比、あるいは発振周波数を制御できる発振装置であれば、実施例７〜１２との組み合わせにより低消費電力化等を図ることができる。例えば図３１に示す構成の発振装置では、ＭＯＳバッファ３０１の出力に基づき選択回路３０２により充電手段３０７、放電手段３０８のいずれかを選択し、ＭＯＳバッファ３０１の入力に対する充放電を行う。これにより発振信号の発振周波数、デューティ比を自由に調整できる。また例えば図３２（Ａ）、（Ｂ）、図３３（Ａ）、（Ｂ）に示すように、高周波の発振信号が出力される発振装置７００と、波形整形回路７１０、７２０とを組み合わせることでも、デューティ比の調整は可能である。ここで図３２（Ａ）の波形整形回路７１０は、インバータ７１２〜７１５及びＡＮＤ回路７１６を含む。そして図３２（Ｂ）に示すように、発振装置７００からの発振信号Ｅ（発振周期ＴＯＳＣ）と、これを遅延させた信号Ｆ（ディレイ値Ｔｄｅｌａｙ）とをＡＮＤ回路７１６に入力することで、信号Ｇを得ることができる。この時のデューティ比Ｄは、
Ｄ＝（ＴＯＳＣ−Ｔｄｅｌａｙ）／ＴＯＳＣ
となる。従ってＴｄｅｌａｙを制御することでデューティ比を調整できる。
【０１６６】
また図３３（Ａ）の波形整形回路７２０は、Ｄフィリップフロップ７２２、７２４及びＡＮＤ回路７２６を含む。そして、Ｄフィリップフロップ７２２、７２４のクロック端子には発振装置７００からの発振信号Ｅが入力され、Ｄフィリップフロップ７２２、７２４の出力をＡＮＤ回路７２６に入力することで、信号Ｈを得ることができる。図３３（Ｂ）から明らかなように、デューティ比を２５パーセントとするためには信号Ｈの２倍の周波数を有する発振信号Ｅが必要とされ、デューティ比を１２．５パーセントとするためには信号Ｈの４倍の周波数を有する発振信号Ｅが必要とされる。以上のように波形整形回路を設ける構成とすると、消費電力の点では実施例１〜６の発振装置よりも不利となるが、実施例７〜１２と組み合わせることで、メモリ、タイミング発生回路等における消費電力を低減できる。これにより装置全体としては消費電力の低減を図れる。
【０１６７】
また本発明は、少なくとも複数の表示データ処理用メモリを有するものであれば、単純マトリックス型の液晶表示装置のみならずアクティブマトリックス型液晶表示装置等にも適用でき、また液晶素子以外の表示素子を用いた表示装置にも適用できる。
【０１６８】
【発明の効果】
以上説明したように本発明によれば、発振信号の発振周波数、デューティ比をフレキシブルに簡易に正確に調整でき、低消費電力化、回路規模の削減等が図れる。
【０１６９】
また本発明によれば、読み出し動作を自己的に制御でき、各種タイミング信号を発生する必要がなくなるため、低消費電力化、回路規模の削減等が可能となる。
【０１７０】
また本発明によれば、読み出し動作のみならずプリチャージ動作も自己的に制御でき、クロック信号の１周期で、無駄なく、読み出し動作及びプリチャージ動作を制御できる。
【０１７１】
また本発明によれば、例えば文字、アイコン等を所望の配置で例えばマトリックスパネル等に表示でき、複雑な画像表示を簡易に実現できる。
【０１７２】
また本発明によれば、発振装置のデューティ比を制御するだけで、読み出し時間、プリチャージ時間を制御でき、データ処理に必要な最低周波数の発振クロック信号で表示データ処理装置を動作させることができる。
【０１７３】
また本発明によれば、表示処理装置内に含まれる回路に対して動作時間を無駄なく割り当てることができ、これらの回路の有するディレイ値等を用いて発振装置の発振周波数を決めることができる。これにより製造プロセスの変動に影響されにくい表示データ処理装置を提供できる。
【図面の簡単な説明】
【図１】実施例１の発振装置の構成を示す図である。
【図２】実施例１の動作を示す波形図である。
【図３】実施例２の発振装置の構成を示す図である。
【図４】実施例３の発振装置の構成を示す図である。
【図５】実施例３の動作を示す波形図である。
【図６】電流源及びバイアス回路の具体的構成を示す図である。
【図７】電流源及びバイアス回路の具体的構成を示す図である。
【図８】図８（Ａ）〜（Ｄ）は、バイアス調整回路の具体的構成を示す図である
【図９】実施例７の表示データ処理装置の構成を示す図である。
【図１０】実施例７の動作を示すタイミングチャート図である。
【図１１】実施例８の表示データ処理装置の構成を示す図である。
【図１２】実施例８の動作を示すタイミングチャート図である。
【図１３】実施例９の表示データ処理装置の構成を示す図である。
【図１４】表示データ処理装置がＮ個のメモリを含む場合の構成の例を示す図である。
【図１５】実施例１０の表示データ処理装置の構成を示す図である。
【図１６】従来の手法で表示データ処理装置を構成した比較例を示す図である。
【図１７】実施例１０の動作を示すタイミングチャート図である。
【図１８】比較例の動作を示すタイミングチャート図である。
【図１９】表示データＲＡＭ用のアドレスデコーダ及びその等価回路の構成の一例を示す図である。
【図２０】表示データＲＡＭ及びその等価回路の構成の一例を示す図である。
【図２１】ＣＧＲＯＭ用のアドレスデコーダ、ＣＧＲＯＭ及びその等価回路の構成の一例を示す図である。
【図２２】ドライバ回路用のアドレスデコーダ及びその等価回路の構成の一例を示す図である。
【図２３】ＲＳラッチ回路の構成の一例を示す図である。
【図２４】実施例１１（ドライバ回路の具体例）の構成を示す図である。
【図２５】マトリックスパネル上に表示される表示画面の一例である。
【図２６】表示データ処理装置に含まれる等価回路を用いて発振信号を生成する実施例１１の構成を示す図である。
【図２７】実施例１１によりリングオシレータを形成する場合の構成例を示す図である。
【図２８】実施例７との組み合わせでリングオシレータを形成する場合の構成例を示す図である。
【図２９】実施例１との組み合わせで発振周波数及びデューティ比を制御する場合の構成例を示す図である。
【図３０】実施例３との組み合わせで発振周波数及びデューティ比を制御する場合の構成例を示す図である。
【図３１】発振周波数及びデューティ比の調整が可能な発振装置の構成例を示す図である。
【図３２】図３２（Ａ）は波形整形回路を用いた発振装置の構成の例を示す図であり、図３２（Ｂ）はそのタイミングチャート図である。
【図３３】図３３（Ａ）は波形整形回路を用いた発振装置の構成の他の例を示す図であり、図３３（Ｂ）はそのタイミングチャート図である。
【図３４】従来のＣＲ発振回路の構成を示す図である。
【図３５】従来のリングオシレータの構成を示す図である。
【図３６】発振信号のデューティ比を可変できるＣＲ発振回路の構成を示す図である。
【図３７】図３７（Ａ）は従来の表示データ処理装置の構成例であり、図３７（Ｂ）はそのタイミングチャート図である。
【符号の説明】
１、１３３、１３７ ＭＯＳバッファ
２、９９、１００、１０１、１０２、１０５、１０６、１２０、１２１、１２２、１２３、１２４、１３２、１３６、１４２、１４９、１７４、１７５、１７６、１７７、１８３、２００、２０１、２０２、２０３、２０７、２０８、２０９、２１０ ＭＯＳインバータ
３、１１、２２、２４、２６、８５、８６、８７、８８、８９、９０、９１、９２、９３、９４、１０８、１０７、１１１、１１２、１１３、１３０、１３１、１３４、１３５、１４３、１４４、１４５、１７０、１７１、１７２、１７３ Ｐ型ＭＯＳトランジスタ
４、１２、２３、２５、２７、９５、９６、９７、９８、１０９、１１０、１１６、１１７、１１８、１１９、１３８、１４０、１４１、１４６、１４７、１４８、１５０、１５１、１５２、１５３、１５４、１５５、１５６、１６０、１６１、１６２、１６３、１６４、１６５、１６６、１６７、１６８、１６９ 第２Ｎ型ＭＯＳトランジスタ
５、２０４ キャパシタ
６ 発振出力
７、８、２９、３０、２０５ 抵抗
９ 高電位側電源
１０ 低電位側電源
１１、１２ 電流源
１３、１４ バイアス端子
１５ 端子
１６ バイアス回路
１７ バイアス調整回路
１８ 周波数選択信号
２０ 遅延回路
２１ 等価回路
２８ 可変抵抗
３１、３２ スイッチ
３３、３４ フューズ
３５、３６ ＭＯＳトランジスタ
３７、３８ 制御信号
５０ 発振装置
５１ タイミング発生回路
５２ ＲＳラッチ回路
５３ 表示データＲＡＭ用のアドレスデコーダ
５４ 表示データＲＡＭ用のアドレスデコーダの等価回路
５５ 表示データＲＡＭ（表示データメモリ）
５６ 表示データＲＡＭの等価回路
５７ ＣＧＲＯＭ用のアドレスデコーダ
５８ ＣＧＲＯＭ用のアドレスデコーダの等価回路
５９ ＣＧＲＯＭ（文字パターン発生回路）
６０ ＣＧＲＯＭの等価回路
６１ ドライバー回路用のアドレスデコーダ
６２ ドライバー回路用のアドレスデコーダの等価回路
６３ ドライバー回路
６４ 書き込み用のアドレスデコーダ
７０ 発振クロック
１２５ ＲＡＭセル
１２６ ＲＡＭ出力セル
１３９ ＲＯＭセル
１８０、１８１ １８２ ＮＡＮＤ
２０６ 発振出力
２５０ 発振装置
２５１ タイミング発生回路
３０１ ＭＯＳバッファ
３０２ 選択手段
３０３ 波形整形手段
３０５ 帰還手段
３０６ 発振クロック
３１０ 充電手段
３１２ 第１電流制御手段
３１４ 第１スイッチング手段
３２０ 放電手段
３２２ 第２電流制御手段
３２４ 第２スイッチング手段
３５２ 選択回路
３５３ 第１メモリ（画像表示メモリ）
３５４ 第１等価回路
３５５ 第２メモリ（画像表示パターン発生器）
３５６ 第２等価回路
３５７ 格納手段（ラインメモリ）
３５８ 第３等価回路
３７０ クロック信号ＣＫ
３７１ 第１信号
３７２ 第２信号
３７３ 第３信号
３７６ 第４信号
３７７ アドレス信号
３７９ 第１データ
３８０ 第２データ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an oscillation device and a display data processing device, and more particularly to an oscillation device and a display data processing device capable of low power consumption operation.
[0002]
BACKGROUND ART AND PROBLEMS TO BE SOLVED BY THE INVENTION
A conventional oscillator will be described. FIG. 34 shows a configuration of a CR oscillation circuit as a typical example of a conventional oscillation device. The inverters 200, 201, 202, and 203 are serially connected, and a capacitor 204 is connected between the output of the inverter 201 and the input of the inverter 200. A resistor 205 is connected between the output of the inverter 202 and the input of the inverter 200. The inverter 203 is for waveform shaping. As is well known, the oscillation frequency of the CR oscillation circuit is fOSC = 1 / (2.2 × C × R) where a capacitor value is C and a resistance value is R. However, the delay values of the inverters 200, 201, and 202 are excluded.
[0003]
FIG. 35 shows a configuration of a ring oscillator as a typical example of a conventional oscillation device. The inverters 207, 208, 209, and 210 are serially connected, and the output of the inverter 209 is fed back to the input of the inverter 207. The inverter 210 is for waveform shaping. As is well known, assuming that the delay value of each inverter is t (207), t (208), and t (209), fOSC = 1 / ｛2 × [t (207) + t (208) + t (209)].
[0004]
However, the CR oscillation circuit and the ring oscillator have the following problems.
[0005]
First, the duty ratio of the oscillation signal is around 50%, and this duty ratio cannot be adjusted flexibly.
[0006]
In a matrix display device or the like, which is a main application of the display data processing device, the frequency of one frame display is called a frame frequency, and the specification of the frame frequency is generally in a range of 70 to 130 Hz. Therefore, in order to satisfy this specification, the accuracy of the oscillation frequency of the CR oscillation circuit needs to be within a range of ± 30%. However, when capacitors and resistors are manufactured on a semiconductor substrate, the values of these capacitors and resistors vary from 10 to 30%. Therefore, it has been practically impossible to simultaneously manufacture a capacitor and a resistor on a semiconductor substrate and secure an accurate oscillation frequency. For this reason, the resistance of the CR oscillation circuit used in the display data processing device is almost always an external component.
[0007]
The oscillation frequency of the clock required for the matrix display device or the like is about 10K to 500KHz. However, if such a low frequency is oscillated by the ring oscillator, the circuit scale and the number of elements become very large. For this reason, the ring oscillator cannot be practically used for an oscillation device such as a matrix display device.
[0008]
On the other hand, a CR oscillation circuit having a configuration shown in FIG. 36 is known as a CR oscillation circuit capable of varying the duty ratio of an oscillation signal. This CR oscillation circuit has a configuration in which a resistor 211 and a diode 212 are added to the configuration shown in FIG. In this circuit, the duty ratio can be controlled by adjusting the resistance ratio of the resistors 205 and 211. However, this CR oscillation circuit has the following problems. First, the diode 212 has a parasitic resistance and a parasitic capacitance, and a leak current occurs in the diode 212 at the time of reverse bias. These parasitic resistances, parasitic capacitances, and leak currents have a large adverse effect on the generation and maintenance of the oscillation signal, the accuracy of the oscillation frequency, and the like. Second, it is difficult to form a diode having good characteristics on the same semiconductor substrate as other circuits such as the inverter 200, and if it is formed, the manufacturing cost increases. Third, in this CR oscillation circuit, a current source cannot be used instead of the resistors 205 and 211 as a means for changing the duty ratio. Fourth, there is a problem that the inverter 202 required for polarity inversion and the diode 212 required for switching between charging and discharging cannot be shared.
[0009]
As described above, the conventional oscillation device has various problems.
[0010]
Next, a conventional display data processing device will be described. FIG. 37A shows an example of a configuration of a conventional display data processing device. The display data device includes a plurality of memories for processing display data. Here, the first and second memories 504 and 506 and the storage means 508 respectively correspond to, for example, an image display memory, an image display pattern generator (CGROM, CGRAM, etc.), and a line memory. The timing generation circuit 502 outputs the first and second addresses 512 and 514 and the first, second and third signals 516, 518 and 520 to them. The first and second signals 516 and 518 serve as read signals of the first and second memories 504 and 506, and the third signal 520 serves as a write signal to the storage means 508. The clock signal CK510 is supplied from the oscillation device 500 to the timing generation circuit 502, and the timing generation circuit 502 generates various signals as shown in FIG. 37B based on the CK510. In this display data processing device, an address of the second memory 506 is generated based on the first data 522 and the like output from the first memory 504, and the second data 524 output from the second memory 506 is stored in the storage unit. 508 is the write data.
[0011]
As shown in FIG. 37B, when the first signal 516 becomes L level (see the point F in FIG. 37B), the read operation of the first memory 504 is started, and the first data 522 is read. Since the address of the second memory 506 is generated based on the first data 522, the second signal 518 needs to fall at least one clock later than the first signal 516 (see point G). Then, when the second signal 518 becomes L level, the second data 524 is output from the second memory 506. Since the storage unit 508 stores the second data 524, it is necessary to make the third signal 520 fall at least one clock later than the second signal 518 (see point H). Then, the timing generation circuit 502 raises the first to third signals 516 to 520 to the H level when the data writing to the storage means 508 is completed.
[0012]
As described above, in the conventional display data processing device, the timing generation circuit 502 must generate signals at various timings in consideration of the access times of the first and second memories and the storage unit. Therefore, as is apparent from FIG. 37B, a clock signal CK having a frequency three to five times the frequency of the first to third signals is required to generate the first to third signals and the like. Will hinder low power consumption.
[0013]
On the other hand, it is also possible to generate signals at various timings as shown in FIG. 37B by using a delay circuit or the like based on clock signals having the same frequency as the first to third signals. However, it is extremely difficult to generate these signals in consideration of the access time of the first and second memories and the storage unit, and the like, in view of manufacturing variations and the like. Therefore, a display data processing device capable of adjusting the timing between these first and second memories, storage means, and the like in a self-controlled manner is desired.
[0014]
An object of the present invention is to solve the above-described problems, and an object of the present invention is to provide an oscillation device and a display data processing device capable of reducing power consumption and circuit scale.
[0015]
Another object of the present invention is to provide an oscillation device that can easily and accurately adjust the oscillation frequency and duty ratio of an oscillation signal.
[0016]
It is another object of the present invention to provide a display data processing device having a plurality of memories, which can adjust the timing between these memories and the like in a self-controlled manner.
[0017]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the present invention is an oscillation device including a buffer unit, a feedback unit for returning an output of the buffer unit to an input, and a charging unit and a discharging unit connected to an input of the buffer unit. hand,
A first switching unit that is turned on / off based on an output of the buffer unit; and a first current control unit that controls a current that flows into an input of the buffer unit via the first switching unit. Including
A second switching unit that is turned on / off based on an output of the buffer unit; and a second current control unit that controls a current flowing from an input of the buffer unit via the second switching unit. It is characterized by including.
[0018]
According to the present invention, when the first switching means is turned on based on the output of the buffer means, the current controlled by the first current control means flows into the input of the buffer means, and the charging operation is performed. On the other hand, when the second switching means is turned on based on the output of the buffer means, the current controlled by the second current control means flows from the input of the buffer means, and the discharging operation is performed. An oscillation waveform is generated by repeating charging and discharging in this manner. At this time, by controlling the current by the first and second current control means, the oscillation frequency and the duty ratio of the oscillation signal can be adjusted.
[0019]
Also, in the present invention, the first and second switching means are first and second transistors of first and second conductivity types, respectively, wherein an output of the buffer means is connected to a gate electrode. The second current control means is a first and a second resistor.
[0020]
According to the present invention, the oscillation frequency and the duty ratio of the oscillation signal can be adjusted by adjusting the resistance values of the first and second resistors.
[0021]
Also, in the present invention, the first and second switching means are first and second transistors of first and second conductivity types in which an output of the buffer means is connected to a gate electrode. The current control means is a first and a second current source.
[0022]
According to the present invention, the oscillation frequency and the duty ratio of the oscillation signal can be adjusted by controlling the current flowing through the first and second current sources.
[0023]
Further, according to the present invention, the first current source includes a third transistor of a first conductivity type, and the second current source includes a fourth transistor of a second conductivity type.
First and second bias terminals connected to the gate electrodes of the third and fourth transistors, and the first and second currents are controlled by controlling a bias voltage to the first and second bias terminals. And a bias circuit for controlling at least a current ratio of the first and second currents flowing through the source.
[0024]
According to the present invention, by controlling the bias voltage to the first and second bias terminals, it is possible to control the current ratio of the first and second currents, thereby controlling the ratio between the charging time and the discharging time, The duty ratio of the oscillation signal can be adjusted.
[0025]
Further, the invention is characterized in that it includes means for controlling the magnitude of the first and second current values.
[0026]
According to the present invention, the oscillation frequency and the like can be adjusted by controlling the magnitudes of the first and second currents.
[0027]
The present invention also provides a bias circuit comprising: a first conductivity type fifth transistor having a gate electrode connected to the first bias terminal and a drain region connected to the second bias terminal; and a gate electrode and a drain region. A sixth transistor of a first conductivity type connected to the first bias terminal; a seventh transistor of a second conductivity type having a gate electrode and a drain region connected to the second bias terminal; An eighth transistor of a second conductivity type connected to the second bias terminal and having a drain region connected to the first bias terminal.
[0028]
According to the present invention, the same voltage is applied to the gate electrodes of the third, fifth, and sixth transistors. The same voltage is applied to the fourth, seventh, and eighth gate electrodes. Therefore, the current flowing through the fifth transistor (or the sixth transistor) can be copied to the third transistor and the current flowing through the seventh transistor (or the eighth transistor) can be copied to the fourth transistor by the current mirror. This makes it possible to adjust the oscillation frequency and the duty ratio of the oscillation signal based on the current flowing through the fifth and seventh transistors (or the sixth and eighth transistors), the beta value (transistor size) of the transistors, and the like. Become.
[0029]
Further, according to the present invention, a third bias terminal is connected to the gate electrode of the third transistor instead of the first bias terminal,
A ninth transistor of a first conductivity type having a gate electrode and a drain region connected to the third bias terminal; a gate electrode connected to the second bias terminal; and a drain region connected to the third bias terminal. And a tenth transistor of the second conductivity type.
[0030]
According to the present invention, the duty ratio can be adjusted using the beta value (transistor size) or the like of the third, fourth, ninth, and tenth transistors, so that the design becomes easy.
[0031]
The present invention is also a display data processing device including N (N is an integer) memories for processing display data,
A first memory for reading data when the first signal becomes a valid level;
A first equivalent circuit that outputs a second signal based on the first signal, wherein the first equivalent circuit sets the second signal to an effective level at least when data read from the first memory is determined or thereafter;
A K-th memory for reading data based on an output result of the (K-1) -th memory when a K-th signal (1 <K ≦ N, K is an integer) becomes an effective level;
A circuit for outputting a (K + 1) -th signal based on the K-th signal, wherein a K-th equivalent for setting the (K + 1) -th signal to an effective level at least when data read from the K-th memory is determined or thereafter Circuit and
And storing means for writing data read from the N-th memory when the (N + 1) -th signal output from the N-th equivalent circuit becomes a valid level.
[0032]
According to the present invention, when the first signal becomes valid, data is read from the first memory, and the read data is output to the second memory. At this time, the first equivalent circuit enables the second signal at the same time as or after reading data from the first memory. When the second signal becomes valid, the second memory reads data based on the output result of the first memory. In this way, data is read one after another, read data from the N-th memory is stored in the storage means, and display data is generated based on the stored data.
[0033]
Further, the present invention is characterized in that at least one of the first to N-th memories and storage means performs a precharge operation when the first to (N + 1) -th signals are at an invalid level.
[0034]
According to the present invention, when the first to Nth memories and the storage means have a precharge operation, when the first to (N + 1) th signals become ineffective levels, these are shifted to the precharge operation. Can be done.
[0035]
The present invention is also a circuit for outputting a (N + 2) -th signal based on the (N + 1) -th signal. The circuit outputs the (N + 2) -th signal at least at the time when the read data is written to the storage means or thereafter. An (N + 1) th equivalent circuit for providing an effective level;
When the (N + 2) th signal becomes a valid level, at least one of the first to (N + 1) th signals is set to a non-valid level, and at least one of the first to Nth memories and storage means is precharged. Means for selecting an operation.
[0036]
According to the present invention, when the (N + 2) th signal is set to the effective level by the (N + 1) th equivalent circuit, at least one of the first to Nth memories and the storage means can be shifted to the precharge operation. As described above, according to the present invention, the timing of transition to the precharge operation can be controlled by itself.
[0037]
The present invention also provides a decoder for generating a converted address signal from an address signal input to at least one of the first to Nth memories and storage means;
Based on any one of the first to (N + 1) th signals, any of the first to Nth memories and the storage means may be replaced with first 'to (N + 1) th signals instead of first to (N + 1) th signals. N + 1) 'signal output circuit, and an equivalent circuit for a decoder for setting the first' to (N + 1) 'signals to an effective level at or after the conversion address signal output from the decoder means is determined. And characterized in that:
[0038]
According to the present invention, it is possible to convert the address signals input to the first to Nth memories and the storage means. Then, the first to N-th memories and the storage means perform a read operation or the like at the time when the conversion address signal is determined or thereafter, so that an appropriate read operation can be performed.
[0039]
Further, according to the present invention, the storage means includes first to L-th storage means for taking in first to L-th (L is an integer) types of read data,
A capture signal for storing the read data from the N-th memory in the storage means in a time-division manner every horizontal period is generated, and the first to L-th types of read data are stored in the first to L-th It is characterized by including a capture signal control means for controlling the generation timing of the capture signal so as to be captured by the storage means.
[0040]
According to the present invention, the read data includes character pattern data (first type of read data), icon pattern data (second type of read data), and the like, each of which controls the generation timing of a capture signal. By doing so, it can be stored in the first and second storage means. Thus, when the present invention is applied to, for example, a matrix type display device, characters, icons, and the like can be displayed at an arbitrary position on the matrix panel.
[0041]
Further, the present invention is characterized in that the capture signal control means generates a conversion address signal from an address signal input to the storage means, and comprises a decoder means for using the conversion address signal as the capture signal.
[0042]
According to the present invention, the conversion address signal generated by the decoder can be used as a capture signal, and the data is loaded into the storage based on the capture signal. Thus, for example, when a decoder means capable of ROM programming is used, a capture signal can be generated at an arbitrary timing by changing the ROM programming.
[0043]
Further, the invention is characterized in that the plurality of memories include means for storing a code signal of an image display pattern, and means for generating an image display pattern based on the code signal.
[0044]
According to the present invention, for example, a character code signal or the like can be stored in the first memory, and character pattern data corresponding to the character code signal can be stored in the second memory. Thus, for example, characters and the like can be easily arranged on the matrix panel.
[0045]
Further, the invention includes an oscillation device that outputs an oscillation signal for generating the first signal, and the oscillation device includes a unit that controls a duty ratio of the oscillation signal.
[0046]
According to the present invention, by controlling the duty ratio of the oscillation signal, it becomes possible to adjust the read time, the precharge time, etc. of the first to Nth memories and the storage means.
[0047]
Further, according to the present invention, the oscillation device includes buffer means, feedback means for feeding back an output of the buffer means to an input, and charging means and discharging means connected to the input of the buffer means,
A first switching unit that is turned on / off based on an output of the buffer unit; and a first current control unit that controls a current that flows into an input of the buffer unit via the first switching unit. Including
A second switching unit that is turned on / off based on an output of the buffer unit; and a second current control unit that controls a current flowing from an input of the buffer unit via the second switching unit. It is characterized by including.
[0048]
According to the present invention, the duty ratio of the oscillation signal can be controlled by controlling the charge / discharge current by the first and second current control means, whereby the read time of the first to Nth memories, the storage means, the precharge time Etc. can be adjusted.
[0049]
Further, the present invention is characterized in that one of the (N + 1) th signal and the (N + 2) th signal is fed back as the first signal to form a self-oscillation loop.
[0050]
According to the present invention, oscillation using a signal delay or the like of an equivalent circuit becomes possible, and power consumption can be reduced.
[0051]
Further, the invention is characterized in that it includes means for controlling at least one of an oscillation frequency and a duty ratio in the self-oscillation loop.
[0052]
According to the present invention, it is possible to make the oscillation frequency, the duty ratio, and the like close to desired values, for example, when the delay value of the equivalent circuit fluctuates depending on variations in the manufacturing process.
[0053]
Also, the present invention provides a buffer means including the first to Nth equivalent circuits or the first to (N + 1) th equivalent circuits, a feedback means for feeding back an output of the buffer means to an input, and an input to the buffer means. Including connected charging means and discharging means,
A first switching unit that is turned on / off based on an output of the buffer unit; and a first current control unit that controls a current that flows into an input of the buffer unit via the first switching unit. Including
A second switching unit that is turned on / off based on an output of the buffer unit; and a second current control unit that controls a current flowing from an input of the buffer unit via the second switching unit. It is characterized by including.
[0054]
According to the present invention, when the delay value of the equivalent circuit fluctuates depending on the variation in the manufacturing process, the current is controlled by the first and second current control means, so that the oscillation frequency, the duty ratio, and the like are desired. Can be approached.
[0055]
Further, the matrix type display device according to the present invention is the display data processing device, a matrix panel in which display pixels are arranged in a matrix and a plurality of signal electrodes and scanning electrodes are arranged to intersect, A signal drive circuit that applies a drive voltage to the signal electrode, and a scan drive circuit that applies a drive voltage to the scan electrode of the matrix panel,
A driving voltage of at least the signal driving circuit is generated based on data stored in the storage unit of the display data processing device.
[0056]
According to the present invention, it is possible to obtain a matrix type display device that can operate at high speed with low power consumption.
[0057]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0058]
(Example 1)
Embodiments 1 to 6 are embodiments relating to the oscillation device.
[0059]
FIG. 1 shows the configuration of the oscillation device according to the first embodiment of the present invention.
[0060]
Feedback means 305 is provided between the input A and the output B of the MOS buffer 301. A charging means 310 and a discharging means 320 are commonly connected to an input A of the MOS buffer 301. The output B of the MOS buffer 301 is input to the charging means 310 and the discharging means 320. However, in this case, a waveform shaping unit 303 including an inverter, a buffer, and the like may be provided.
[0061]
The charging unit 310 includes a first current control unit 312 and a first switching unit 314. The first switching means 314 turns on / off based on the output B of the MOS buffer 301, and the first current control means 312 controls the charging current flowing into the input A of the MOS buffer 301 via the first switching means 314. It controls I1. The discharging means 320 includes a second current control means 322 and a second switching means 324. The second switching means 324 turns on / off based on the output B of the MOS buffer 301, and the second current control means 322 controls the discharge current flowing out of the input A of the MOS buffer 301 via the second switching means 324. It controls I2.
[0062]
Next, the operation of the first embodiment will be described. FIG. 2 shows a waveform diagram of the input A and the output B of the MOS buffer 301. Here, the threshold voltage of the MOS buffer 301 is (1/2) × VDD. Then, when the input A of the MOS buffer 301 exceeds (１ ／) × VDD (see H in FIG. 2), the output B of the MOS buffer 301 rises from the L level to the H level (see I), and the feedback means 305 And the input A of the MOS buffer 301 becomes {(1/2) × VDD + VDD} (see J). At this time, since the output B is at the H level, the second switching means 324 in the discharging means 320 is selected and turned on, and the current is discharged from the input A of the MOS buffer 301. As a result, the potential of the input A gradually decreases (see K). When the input A falls slightly below the threshold voltage (1/2) × VDD (see L), the output of the MOS buffer 301 falls to L level (see M). As a result, the potential of the input A is lowered to {(1/2) × VDD−VDD} by the feedback means 305 (see N). At this time, since the output B is at the L level, the first switching means 314 in the charging means 310 is selected and turned on, and the input A of the MOS buffer 301 is charged with current. As a result, the potential of the input A gradually increases (see P). By repeating charging and discharging as described above, an oscillation signal such as the output B in FIG. 2 can be obtained. Note that the MOS buffer 301 only needs to function at least as a buffer means, and does not necessarily need to be configured by MOS transistors.
[0063]
As is clear from FIG. 2, according to the present embodiment, an oscillation signal (oscillation waveform) having an arbitrary frequency and duty ratio can be obtained. Adjustment of the frequency / duty ratio is realized by controlling the current values of I1 and I2 by the first and second current control means 312 and 322. For example, if control is performed so that I2> I1, an oscillation signal as shown in FIG. 2 is obtained. According to the present embodiment, there is no need to consider the parasitic resistance, parasitic capacitance, and the like of the diode in the conventional example shown in FIG. 36, and an oscillation signal with high accuracy and small process variation can be obtained. Further, the first and second switching means 314 and 324 can have both functions of a polarity inversion means (corresponding to the inverter 202 in FIG. 36) and a charge / discharge switching means (corresponding to the diode 212 in FIG. 36). Therefore, the number of circuit elements can be reduced and the accuracy of the oscillation frequency / duty ratio can be improved.
[0064]
(Example 2)
The second embodiment shows a specific configuration of the charging unit and the discharging unit, and FIG. 3 shows a circuit configuration thereof. The resistors 7 and 8 in FIG. 3 correspond to the first and second current control means 312 and 322 in FIG. 1, and the P-type MOS transistor 3 and the N-type MOS transistor 4 correspond to the first and second switching means 314 and 324, respectively. Is equivalent to
[0065]
The input A of the MOS buffer 1 is connected to the drain regions of the P-type MOS transistor 3 and the N-type MOS transistor 4, and to the capacitor 5. The output B of the MOS buffer 1 is connected to the gate electrodes of the P-type MOS transistor 3 and the N-type MOS transistor 4, and to the capacitor 5. The source regions of the P-type MOS transistor 3 and the N-type MOS transistor 4 are connected to one terminal of the resistors 7 and 8, respectively. The other terminals of the resistors 7 and 8 are connected to a high-potential power supply VDD9 and a low-potential power supply VSS (GND) 10, respectively. The MOS inverter 2 is for waveform shaping.
[0066]
The operation will now be described. First, when the input potential of the MOS buffer 1 slightly exceeds the threshold voltage (1/2) × VDD, the output B of the MOS buffer 1 rises to the H level, and the capacitance coupling via the capacitor 5 causes the output of the MOS buffer 1 to change. The potential of the input A is {VDD + (1/2) × VDD}. Then, the P-type MOS transistor 3 turns off and the N-type MOS transistor 4 turns on. Here, it is assumed that the resistances of the resistors 7 and 8 are sufficiently larger than the ON resistances of the P-type MOS transistor 3 and the N-type MOS transistor 4, the resistances of the resistors 7 and 8 are Rp and Rn, and the capacitance of the capacitor 5 is C. I do. Then, the potential of the input A of the MOS buffer 1 decreases (discharges) in the time of Tn = C × Rn.
[0067]
Next, when the input potential of the MOS buffer 1 becomes lower than the threshold voltage (1/2) × VDD, the P-type MOS transistor 3 is turned on, and the potential of the input A of the MOS buffer 1 becomes Tn = C × Rp Go up (charge) in time.
[0068]
Therefore, the oscillation frequency fOSC2 and the duty ratio D2 in the second embodiment are fOSC2 = 1 / (Tn + Tp) and D2 = Rn / (Rn + Rp), respectively. However, the delay value of the MOS buffer 1 is excluded.
[0069]
In FIG. 3, the transistors 3 and 4 are connected to the input A of the MOS buffer 1. On the contrary, the resistors 7 and 8 are connected to the input A of the MOS buffer 1 and the transistors 3 and 4 are connected. It may be configured to be connected to the power supplies 9 and 10.
[0070]
(Example 3)
The third embodiment shows another example of the specific configuration of the charging unit and the discharging unit, and FIG. 4 shows the circuit configuration. The difference from the second embodiment is that the current control means is changed from the resistors 7 and 8 to the current sources 11 and 12. That is, charging and discharging of the current from the input A of the MOS buffer 1 are performed by the current sources 11 and 12.
[0071]
FIG. 5 shows a waveform diagram of the input A and the output B of the MOS buffer 1. The difference from FIG. 2 is that the potential of the input A changes linearly during charging and discharging (see K ′ and P ′ in FIG. 5). When the potential of the input A changes linearly in this way, even when fluctuations in the manufacturing process, noise, etc. occur, variations in the oscillation frequency and duty ratio can be reduced as compared with the case of FIG. The duty ratio can be obtained. The other operations are the same as those in the first and second embodiments, and the description is omitted.
[0072]
The oscillation frequency fOSC3 and the duty ratio D3 of the oscillation device according to the third embodiment are fOSC3 = 1 / (Tn + Tp) and D3 = In / (In + Ip), where the current values flowing through the current sources 11 and 12 are In and Ip, respectively. . However, Tn = C × V / In and Tp = C × V / Ip, and the delay value of the MOS buffer 1 is excluded. Therefore, according to the third embodiment, the duty ratio of the oscillation signal can be easily adjusted by the ratio of In and Ip.
[0073]
When a current source is used as the current control means, it is desirable to provide a bias circuit 16 and a bias adjustment circuit 17 as shown in FIG. Here, the bias circuit 16 supplies a bias signal to the current sources 11 and 12 via the bias terminals 13 and 14. The bias adjustment circuit 17 supplies a bias adjustment signal to the bias circuit 16 via the terminal 15. By using the bias circuit 16 and the bias adjustment circuit 17, the oscillation frequency and the duty ratio can be freely adjusted.
[0074]
In FIG. 4, the transistors 3 and 4 are connected to the input A of the MOS buffer 1. On the contrary, the current sources 11 and 12 are connected to the input A of the MOS buffer 1 and the transistors 3 and 4 are connected. It may be configured to be connected to the power supplies 9 and 10. However, in order to improve the performance of the current source, the configuration of FIG. 4 is more preferable.
[0075]
(Example 4)
Embodiment 4 shows an example of a specific configuration of the current source and the bias circuit, and FIG. 6 shows the circuit configuration.
[0076]
In the fourth embodiment, the P-type MOS transistor 11 (third transistor) and the N-type MOS transistor 12 (fourth transistor) serve as the current sources 11 and 12. The P-type MOS transistor 22 (fifth transistor) has a gate electrode connected to the bias terminal 13 (first bias terminal) and a drain region connected to the bias terminal 14 (second bias terminal). The gate electrode and the drain region of the P-type MOS transistor 24 (sixth transistor) are connected to the bias terminal 13. The gate electrode and the drain region of the N-type MOS transistor 23 (seventh transistor) are connected to the bias terminal 14. The N-type MOS transistor 25 (eighth transistor) has a gate electrode connected to the bias terminal 14 and a drain region connected to the bias terminal 13.
[0077]
Here, the beta values of the transistors 11 and 12 are βpp and βnn. Also, the beta values of the transistors 22, 23, 24, and 25 are βp2, βn2, βp1, and βn1, respectively. Then, the current flowing in transistors 11, 22, and 24 divided by the beta value of each transistor is equal by the current mirror, and the current flowing in transistors 12, 23, and 25 divided by the beta value of each transistor is Equal by the current mirror. Therefore, the following equation holds.
[0078]

It becomes. Here, the oscillation frequency fOSC4 is

It becomes. However, Tn = C × V / In and Tp = C × V / Ip, and the delay value of the MOS buffer 1 is excluded.
[0079]
As is clear from the above equations (1), (2) and (4), the oscillation frequency fOSC4 can be arbitrarily adjusted by the current value I2. This current value I2 is adjusted by the bias adjustment circuit 17. Also, since the duty ratio D4 is D4 = In / (In + Ip), it can be arbitrarily set by changing the transistor size ratio or the like as is apparent from the above equation (3).
[0080]
(Example 5)
Embodiment 5 also shows an example of a specific configuration of the current source and the bias circuit, and FIG. 7 shows the circuit configuration. The difference from the fourth embodiment is that a P-type MOS transistor 26 and an N-type MOS transistor 27 are newly provided, and a voltage is applied to the gate electrode of the P-type MOS transistor 11 instead of the bias terminal 13 instead of the bias terminal 13 ′. (Third bias terminal). The gate electrode and the source region of the P-type MOS transistor 26 (ninth transistor) are connected to the bias terminal 13 ′, and the gate electrode of the N-type MOS transistor 27 (tenth transistor) is connected to the bias terminal 14. At the same time, the drain region is connected to the bias terminal 13 '.
[0081]
Assuming that the beta values of the transistors 26 and 27 are βp3 and βn3, the following equation is established by the current mirror.
[0082]

As is clear from the above equations (5) and (6), the oscillation frequency fOSC5 can be arbitrarily adjusted by the current value I2 from the bias adjustment circuit 17, as in the fourth embodiment. Also, the duty ratio D5 can be arbitrarily set by changing the size ratio of the transistor and the like, as is apparent from the above equation (7).
[0083]
The configuration of the fifth embodiment is more advantageous than the fourth embodiment in the following points. That is, in the fourth embodiment shown in FIG. 6, the duty ratio is adjusted by adjusting the transistor sizes of the transistors 24 and 25, as is apparent from the above equation (3). However, the voltage applied between the drain and source regions of the transistors 24 and 25 is small due to the connection of the bias adjustment circuit 17 to the terminal 15. Therefore, in order to operate the transistors 24 and 25 in the saturation region, the transistor size allowed for the transistors 24 and 25 is limited to some extent. In the fourth embodiment, under such restrictions, the duty ratio must be further adjusted according to the transistor sizes of the transistors 24 and 25, and thus the design is difficult. On the other hand, in the fifth embodiment, the duty ratio can be adjusted by adjusting the transistor sizes of the transistors 26 and 27 as is apparent from the above equation (7). Therefore, the transistor size of the transistors 24 and 25 can be adjusted irrespective of the setting of the duty ratio, which facilitates the design. This difference in ease of design becomes even more remarkable when the power supply voltage is reduced.
[0084]
In the fourth and fifth embodiments, the bias adjustment circuit 17 is inserted at the position of the terminal 15, but the present invention is not limited to this, and may be inserted at any position of the terminals 816, 817, and 818.
[0085]
(Example 6)
Embodiment 6 shows a specific example of the bias adjustment circuit. As the bias adjustment circuit, for example, those shown in FIGS. 8A to 8D can be considered.
[0086]
The bias adjustment circuit shown in FIG. 8A includes a variable resistor 28, and adjusts the oscillation frequency by changing the resistance value with the frequency selection signal 18.
[0087]
The bias adjustment circuit shown in FIG. 8B includes resistors 29 and 30 and switches 31 and 32 connected to each of them, and adjusts the oscillation frequency by selecting the switches 31 and 32 with the frequency selection signal 18.
[0088]
The bias adjustment circuit shown in FIG. 8C includes resistors 29 and 30 and fuses 33 and 34 connected to each of them, and the oscillation frequency can be adjusted by selecting the fuses 33 and 34 with the frequency selection signal 18. .
[0089]
The bias adjustment circuit shown in FIG. 8D includes resistors 29 and 30 and MOS transistors 35 and 36 connected to the resistors 29 and 30, respectively. A control signal 37 which is the frequency selection signal 18 is provided to the gate electrodes of the MOS transistors 35 and 36. , 38, the oscillation frequency can be adjusted.
[0090]
Although FIGS. 8B to 8D show an example in which two resistors are provided, a plurality of resistors may be used.
[0091]
Further, the resistor can be made of a MOS transistor. In this case, for example, in FIG. 8B, the switches 31 and 32 may be configured by MOS transistors, and the resistances of the resistors 29 and 30 may be substituted by the ON resistance of the MOS transistors.
[0092]
The present invention can be implemented by adjusting the current values In and Ip of the current sources 11 and 12 or by adjusting the current value flowing through the terminal 15 in FIGS. 6 and 7 or the voltage value at the terminal 15. It is also possible to apply to CONTROLLED OSCILLATOR. For example, a PLL (PHASE LOCKED LOOP) circuit can be configured by using the present invention as a VCO and adding a well-known phase comparison circuit and filter to the VCO. In this case, the following applications can be considered. For example, in a liquid crystal panel or the like, a plurality of display data processing devices are prepared, and display data from these plurality of display data processing devices is switched and used to display a display screen on the liquid crystal panel. At this time, since the oscillating devices built in each display data processing device oscillate at different frequencies, the frequency of the frame signal of each display data processing device also varies in a range of 70 to 130 Hz (specification range). Therefore, in order to switch and use display data from a plurality of display data processing devices, it is necessary to synchronize these frame signals. Therefore, in such a case, an external frame signal from the outside (another display data processing device) and an internal frame signal generated by the output of the VCO are input to a phase comparison circuit to perform phase comparison. Then, the output of the phase comparison circuit is converted into an appropriate voltage and current by a filter and input to the VCO. This makes it possible to synchronize the frame signal between one display data processing device and another display data processing device. As a result, in a case where display data from a plurality of display data processing devices are switched and used, it is possible to eliminate disturbance of a display image and the like.
[0093]
(Example 7)
Embodiments 7 to 12 described below are embodiments relating to a display data processing device.
[0094]
FIG. 9 shows the configuration of the display data processing device of the seventh embodiment. The seventh embodiment includes a first memory (image display memory) 353, a second memory (image display pattern generator) 355, a storage unit (line memory) 357, and first and second equivalent circuits 354 and 356. The features of the seventh embodiment are as follows. That is, the first signal 371 is input to the first memory 353 and the first equivalent circuit 354. When the first signal 371 becomes a valid level (for example, L level), the read operation of the first memory 353 is performed, and the first data 379 is obtained. Is output. The read address at this time is determined by the address signal 377. Here, the first equivalent circuit 354 outputs the second signal 372 based on the first signal 371, and the second signal 372 is read when the first data 379 read from the first memory 353 is determined or thereafter. Is set to an effective level (for example, L level). The second signal 372 is input to the second memory 355 and the second equivalent circuit 356. When the second signal 372 becomes a valid level, the read operation of the second memory 355 is performed and the second data 380 is output. At this time, reading of the second memory 355 is performed based on the first data 379. The second equivalent circuit 356 outputs the third signal 373 based on the second signal 372, and outputs the third signal 373 at the time when the second data 380 read from the second memory 355 is determined or thereafter. Set to an effective level (for example, L level). When the third signal 373 becomes a valid level, an operation of writing the second data 380 to the storage unit 357 is performed. The storage address at this time is determined by, for example, an address signal 377.
[0095]
In the seventh embodiment, as described above, when the first, second, and third signals 371, 372, and 373 are at the valid level, the read operation of the first and second memories 353 and 355 and the write operation of the storage unit 357 are performed. Is In addition to this, for example, when the first, second, and third signals 371, 372, and 373 have become ineffective levels (for example, H level), the first and second memories 353 and 355 and the storage means 357 May perform a precharge operation. In this way, selection of which of the read operation and the precharge operation is performed by the first and second memories 353 and 355 and the storage means 357 can be realized only by controlling the signal level of the first signal 371 and the like. Thus, circuit control can be simplified. The setting of the readout period and the precharge period can be realized only by controlling the duty ratio of the first signal 371 and the like. In particular, the following advantages are obtained when the oscillation device capable of adjusting the duty ratio described in the first to sixth embodiments is used. That is, the first signal 371 is generated from the output of the oscillation device of the first to sixth embodiments, and the duty ratio is adjusted by the oscillation device, whereby there is an advantage that the setting of the readout period and the precharge period can be freely adjusted.
[0096]
Note that the relationship between the time required for reading data (read access time) and the time required for precharge (precharge access time) is, assuming that the read access time is 100, the precharge access time is generally 5 About 40 (preferably about 10 to 30). Therefore, it is desirable that the first signal 371 has a waveform having a duty ratio of about 5 to 40%.
[0097]
Next, the operation of the seventh embodiment will be described with reference to a timing chart shown in FIG. First, the first signal 371 is set to L level (effective level) (see A in FIG. 10). At this time, the address signal 377 is determined before the first signal 371 becomes L level (see B). Note that CK shown in FIG. 10 is a clock signal, and this CK is generated by, for example, the oscillation device described in the first to sixth embodiments. The first signal 371 is a signal obtained by inverting the clock signal CK.
[0098]
When the first signal 371 becomes L level, data reading from the first memory 353 is performed, and the first data 379 is determined after a predetermined delay period has elapsed (see C). At this time, the second signal 372, which is the output of the first equivalent circuit 354, goes to the L level simultaneously with the determination of the first data 379 or slightly later (see D). The second signal 372 is input to the second memory 355, and when the second signal 372 becomes L level, data reading using the first data 379 as an address signal is performed in the second memory 355. Then, after the elapse of a predetermined delay period, the second data 380 is determined (see E). The second signal 372 is also input to the second equivalent circuit 356, and the third signal 373, which is the output of the second equivalent circuit 356, changes to the L level at the same time as the determination of the second data 380 or slightly later. (See F). When the third signal 373 becomes L level, the second data 380 is written to the storage unit 357.
[0099]
When the first signal 371 becomes H level (see G), the first memory 353 shifts to a precharge operation. In the seventh embodiment, when the first signal 371 becomes H level, the second and third signals 372 and 373 also become H level (see H and I), whereby the second memory 355 and the storage means 357 also perform the precharge operation. Move to However, if the first and second memories 353 and 355 and the storage means 357 do not have a precharge operation, it is not necessary to perform a precharge operation. For example, when the storage unit 357 is configured by a latch circuit including a D flip-flop or the like, it is not necessary to perform a precharge operation on the storage unit 357, and it is not necessary to set the third signal 373 to the H level. In this case, the third signal 373 plays a role of a capture signal for causing the storage means (latch circuit) 357 to latch the second data 380.
[0100]
As described above, according to the seventh embodiment, by providing the first and second equivalent circuits, it is possible to self-control the timing adjustment of the data readout / precharge operation and the like. Therefore, unlike the conventional example, there is no need to generate various control signals for timing adjustment, and the read / precharge operation can be performed without waste in one cycle of the clock signal. Can be significantly reduced.
[0101]
(Example 8)
FIG. 11 shows the configuration of the display data processing device of the eighth embodiment. The difference from the seventh embodiment is that a third equivalent circuit 358 and a selection circuit 352 are newly provided. The third equivalent circuit 358 outputs the fourth signal 376 based on the third signal 373, and sets the fourth signal 376 to an effective level at the time when the second data 380 is written to the storage unit 357 or thereafter. I do. The selection circuit 352 generates a first signal 371 based on the input fourth signal 376 and clock signal CK370, and outputs this to the first memory 353 and the first equivalent circuit 354. More specifically, when the fourth signal 376 becomes a valid level, the first signal is set to a non-valid level (for example, H level). Thereby, desirably, the second signal 372 and the third signal 373 also become ineffective levels. When the first, second, and third signals 371, 372, and 373 go to an invalid level, the first and second memories 353 and 355 and the storage unit 357 shift to a precharge operation.
[0102]
FIG. 12 is a timing chart for explaining the operation of the eighth embodiment. The fourth embodiment is different from the seventh embodiment shown in FIG. 10 in that the fourth signal 376 becomes L level when data writing to the storage means 357 is completed (see J in FIG. 12), whereby the first to third signals 371 to 373 are obtained. Becomes H level (see K, L, M), and the first and second memories 353, 355 and the like shift to the precharge operation.
[0103]
Once the second data 380 has been written to the storage unit 357, the first data 379 and the second data 380 may be changed to any data. On the other hand, in a memory or the like, it is desirable to shift to a precharge operation as soon as possible after reading data in order to reduce power consumption and speed up the operation. According to the eighth embodiment, the fourth signal 376 is set to the effective level at the time when data is written to the storage unit 357 or thereafter. As a result, the first to third signals 371 to 373 can be set to the non-effective level, and the first and second memories 353 and 355 and the storage means 357 can be shifted to the precharge operation. Can be speeded up. As described above, according to the eighth embodiment, not only the read operation but also the precharge operation can be self-controlled.
[0104]
(Example 9)
FIG. 13 shows the configuration of the display data processing device according to the ninth embodiment. The difference from the eighth embodiment is that the selection circuit 352 is located between the second equivalent circuit 356 and the third equivalent circuit 358. As a result, when the second data 380 is written to the storage unit 357 (or later), the fourth signal 376 output from the third equivalent circuit 358 becomes a valid level. A certain third 'signal 374 becomes an invalid level. Thereby, the storage unit 357 shifts to the precharge operation. That is, when data is written to the storage unit 357, the write operation is completed before the first and second memories 353 and 355 are precharged by the first and second signals 371 and 372. I do. This makes it possible to speed up the transition of the storage unit 357 to the precharge operation, thereby reducing power consumption and speeding up the operation.
[0105]
Note that the selection circuit 352 can be arranged not only in the places shown in FIGS. 11 and 13 but also in various places. That is, the selection circuit 352 can be disposed at at least one of the locations indicated by A, B, and C in FIG. 13, and can be disposed at two or three locations. The arrangement at all the locations A, B, and C is disadvantageous in terms of circuit scale, but is advantageous in terms of low power consumption and high-speed operation.
[0106]
In the above-described embodiments 7 to 9, the case where two memories are included has been described as an example. However, the present invention is not limited to this, and the present invention is not limited to the case where the display data processing apparatus has three or more memories. Included in the range. FIG. 14 shows a configuration example in the case of including the N memories in the eighth embodiment (see FIG. 11), for example. In FIG. 14, N and K are integers, and 1 <K ≦ N. In the seventh and ninth embodiments and the following tenth to twelfth embodiments, even when N memories are included, the configuration is similar to that of FIG.
[0107]
(Example 10)
Embodiment 10 Embodiment 10 shows a further specific example of the display data processing device according to the present invention, and the configuration is shown in FIG.
[0108]
A case where the present invention is applied to a display data processing device with a character pattern generator, which is a typical example of a display data processing device, will be described. Here, the display data RAM (display data memory) 55, the CGROM (character pattern generation circuit) 59, and the driver circuit 63 correspond to the first memory, the second memory, and the storage means of the seventh to ninth embodiments, respectively. .
[0109]
Here, the display data RAM 55 stores one screen of character code signals sent from the microcontroller, the processor, and the like. The CGROM 59 generates a character pattern corresponding to the character code signal. The driver circuit (signal drive circuit) 63 has a latch function of time-divisionally storing a character pattern signal during one horizontal period. Using this display data processing device, a character pattern or the like is formed on a dot matrix panel where a plurality of signal electrodes driven by the driver circuit 63 and a plurality of scanning electrodes sequentially scanned by the scanning drive circuit intersect. indicate.
[0110]
For example, consider a case where N × M characters are displayed on a dot matrix panel and one character is composed of n × m dots. A period of a series of operations in which data for one pixel row (one dot line) in one character is transferred from the display data RAM 55 to the driver circuit 63 via the CGROM 59 is defined as 1C (one character). The data output of the CGROM 59 is n bits. Then, the period of N × 1C becomes one dot line period (1H), and the period of M × m × N × 1C becomes one frame period (1FR).
[0111]
The writing of display data from the microcontroller, the processor, and the like to the display data RAM 55 is performed based on the write data signal 83 and the address signal 49 (the address decode of the write address signal 84 by the address decoder 64).
[0112]
The clock signal 70 output from the oscillation device 50 is input to the timing generation circuit 51. The timing generation circuit 51 generates a RAM address signal 77 and a CGROM address signal 78 which are necessary control signals. The display data RAM 55 is one type of frame memory and stores character (display) codes. The CGROM 59 stores character pattern data (display data) corresponding to the character code of the display data RAM 55. Driver circuit 63 latches and accumulates character pattern data 82 output from CGROM 59. Then, a liquid crystal driving voltage corresponding to the stored character pattern data is sent to the liquid crystal panel, whereby a display screen is displayed on the liquid crystal panel.
[0113]
FIG. 16 shows, as a comparative example, a display data processing device configured by a conventional method (see FIG. 37A).
[0114]
The difference between the tenth embodiment (see FIG. 15) and the comparative example is that in the tenth embodiment, a dummy circuit is provided corresponding to each of the address decoder 53, the display data RAM 55, the address decoder 57, the CGROM 59, and the address decoder 61. The point is that the equivalent circuits 54, 56, 58, 60, 62 are provided.
[0115]
In the comparative example, the timing generation circuit 251 generates signals 270, 274, and 275 for reading and precharging the address decoder 253, the display data RAM 255, the address decoder 257, the CGROM 259, and the address decoder 261. On the other hand, in the tenth embodiment, these are not generated. That is, in the tenth embodiment, the clock signal 70 output from the oscillation device 50 is input to the RS latch circuit 52, and the output 71 of the RS latch circuit 52 is input to the equivalent circuit 54 of the address decoder 53. The output 72 of the equivalent circuit 54 becomes a precharge signal 76 via the equivalent circuits 56, 58, 60, 62, and the precharge signal 76 is fed back to the RS latch circuit 52.
[0116]
Next, a read operation of display data in the tenth embodiment will be described.
[0117]
The address signal 77 of the display data RAM 55 is generated by the timing generation circuit 51 based on the clock signal 70 output from the oscillation device 50, and is input to the address decoder 53 for the display data RAM. Further, the clock signal 70 is input to the address decoder 53 and the equivalent circuit 54 as a read signal 71 via the RS latch circuit 52. Then, the read signal 72 and the address signal 79 are simultaneously output from the equivalent circuit 54 and the address decoder 53 (72 may be slower than 79). Here, the read signal 71 becomes an effective level (active) at L level, and when the clock signal 70 is at L level, the read signal 71 also becomes L level.
[0118]
The address of the display data RAM 55 is set by the read signal 72 in accordance with the state of the address signal 79 whose address has been decoded. Here, the read signal 72 is behind the read signal 71 by the time required for address decoding. When the read signal 72 goes low, the character code signal 80 and the CGROM read signal 73 are output simultaneously (73 may be slower than 80).
[0119]
The CGROM address decoder 57 performs address decoding according to the state of the character code signal 80 and the address signal 78, and outputs an address signal 81 to the CGROM 59. Here, the read signal 74 is output at the same time as the address signal 81 (74 may be later than 81), and is delayed from the read signal 73 by the time required for address decoding. Next, the character pattern data 82 and the read signal 75 are output simultaneously by the read signal 74 (75 may be made slower than 82).
[0120]
The driver circuit address decoder 61 performs address decoding according to the state of the address signal 77 and outputs a converted address signal (capture signal) 48 to the driver circuit 63. As a result, the address of the driver circuit 63 is set, and the character pattern data 82 is latched and stored in the driver circuit 63. Here, the precharge signal 76 and the converted address signal 48 are output at the same time (76 may be slower than 48).
[0121]
The precharge signal 76 is fed back to the RS latch circuit 52. Then, the address decoder 53, the display data RAM 55, the address decoder 57, the CGROM 59, the address decoder 61 and the like are precharged one after another. Therefore, in this case, the signals 71, 72, 73, 74, and 75 are precharge signals. By repeating the read operation and the precharge operation in this way, display data is read.
[0122]
FIG. 17 is a timing chart for explaining the operation of the tenth embodiment.
[0123]
The clock signal 70 is CK, the signal 71 serving as a read and precharge signal for the display data RAM 55 is EIRAM, and the address signal 77 is ARAM. A character code signal 80 serving as an address signal of the CGROM 59 is an AROM, and a signal 73 serving as a read and precharge signal of the CGROM 59 is an EIROM. The address signal 77 of the driver circuit 63 is ARAT, the signal 75 of the driver circuit 63 as a write and precharge signal is EILAT, and the character pattern data 82 as input data is DLAT. The waveform of the signal stored in the driver circuit 63 is DDRV. Here, the read operation is performed when the EIRAM goes low, and the precharge operation is performed when the EIRAM goes high. When EIROM and EILAT are at H level, a read operation is performed, and when EIROM and EILAT are at L level, a precharge operation is performed. The timing generation circuit 51 does not generate EIRAM, EIROM, and EILAT, and each circuit operates under its own control. Therefore, the timing generation circuit 51 only generates the address signals ARAM (77, 78) and ALAT (77) at the same timing.
[0124]
FIG. 18 is a timing chart of a comparative example. As can be understood by comparing FIGS. 17 and 18, a high-frequency clock required in the comparative example is not required in the tenth embodiment, and therefore the power consumption can be reduced according to the tenth embodiment. In the tenth embodiment, since the timing generator 51 does not need to generate the EIROM, the EILAT, and the like, the circuit scale can be reduced and the operation can be performed at a higher speed.
[0125]
Next, an example of a detailed circuit configuration of the address decoders 53, 57, 61, the display data RAM 55, the CGROM 59, and the equivalent circuits 54, 58, 60, 62 will be described. First, FIG. 19 shows a specific example of the address decoder 53 and its equivalent circuit 54.
[0126]
MOS transistors 87 to 90 form a serial ROM. The transistor corresponding to no data (for example, data “0”) short-circuits the drain region and the source region, and the transistor corresponding to data (for example, data “1”) does not short-circuit. Switching of whether or not to short-circuit can be realized by a metal switching method, an ion implantation program method (field switching), or the like, similarly to the mask ROM. The data read from the serial ROM is controlled by the MOS transistor 85, and the signal from the serial ROM is amplified by the MOS inverter 99. The MOS transistors 95 and 96 are for precharging and potential fixing, respectively. The equivalent circuit 54 of the address decoder 53 is configured to be equivalent to a ROM for one address line (one of 79 lines) of the address decoder 53, except that the MOS transistors 91 to 94 are controlled by the read signal 71. That is the point.
[0127]
One of the address lines (any of 79) is selected according to the state of the address signal 77, whereby the address signal 77 is decoded. Next, when the EIRAM 71 goes to the L level, an address-decoded signal is output to the display data RAM 55 as a converted address signal 79. At the same time, the equivalent circuit 54 of the address decoder outputs a read signal 72 of the display data RAM 55. At this time, at least as many transistors as the transistors connected to the line having the largest delay value among the address lines are connected to the line 701. This ensures that the read signal 72 is output at the same time as or later than the translated address signal 79.
[0128]
Next, a detailed circuit configuration of the display data RAM 55 and the equivalent circuit 56 will be described with reference to FIG.
[0129]
The MOS inverters 105 and 106, the MOS transistors 109 and 110 for writing data, and the MOS transistors 107 and 108 for reading data constitute a 1-bit RAM cell 125. The output cell 126 of the RAM includes MOS transistors 116 and 118 for precharging and fixing the potential, and MOS inverters 120 and 122 for amplifying the data signal 114.
[0130]
MOS transistor 113 is equivalent to MOS transistor 108 in RAM cell 125, and MOS transistors 111 and 112 are equivalent to MOS transistors 107 and 108 in RAM cell 125, respectively. The MOS transistors 117 and 119 and the MOS inverters 121 and 123 are equivalent to the output cell 126 of the RAM. The equivalent circuit 56 includes these transistors 111, 112, 113, 117, 119 and MOS inverters 121, 123. An address signal 79 and a read signal 72 simultaneously output from the address decoder 53 and the equivalent circuit 54 are simultaneously input to the display data RAM 55 and the equivalent circuit 56, whereby an EIROM 73 and an AROM (character code signal) 80 are simultaneously output. As described above, the timing of the EIROM 73 is adjusted by the equivalent circuit 56 of the display data RAM 55 by itself.
[0131]
Here, the data signal 83 and the address signal 49 are for writing to the display data RAM. Since the tenth embodiment uses a dual port RAM, the read operation and the write operation can be operated independently.
[0132]
Next, a detailed circuit configuration of the address decoder 57, the CGROM 59, and the equivalent circuits 58 and 60 will be described with reference to FIG.
[0133]
ROM cell 139 includes a MOS transistor 138. MOS transistors 130 and 131 are for precharging and potential fixing, respectively, and MOS inverters 132 and 133 are for amplifying data signals, and these constitute an output cell of the CGROM 59. The MOS transistor 147 is for reading control.
[0134]
The address decoder 57 for the CGROM 59 includes MOS transistors 150, 151 and 154, and its basic configuration is the same as that of the address decoder 53 for the display data RAM (see FIG. 19).
[0135]
MOS transistors 152, 153, and 155 are equivalent to MOS transistors 150, 151, and 154 in address decoder 57, and equivalent circuit 58 is configured to include these MOS transistors 152, 153, and 155.
[0136]
The MOS transistor 146 is equivalent to the MOS transistor 147, and the MOS transistors 140 and 141 are equivalent to the MOS transistors 138 and 156 in the ROM cells 139 and 157. The MOS transistors 134 and 135 and the MOS inverters 136 and 137 are equivalent to the MOS transistors 130 and 131 and the MOS inverters 132 and 133 in the output cell of the CGROM 59. The equivalent circuit 60 includes these MOS transistors 146, 140, 141, 134, 135 and MOS inverters 136, 137.
[0137]
An AROM (character code signal) 80 and an EIROM 73 simultaneously output from the display data RAM 55 and its equivalent circuit 56 are simultaneously input to the CGROM address decoder 57 and its equivalent circuit 58, and are passed through the CGROM 59 and its equivalent circuit 60. , DLAT (character pattern data) 82 and EILAT 75 are output simultaneously. That is, the timing of the EILAT 75 is self-adjusted by the equivalent circuit 58 for the address decoder 57 and the equivalent circuit 60 for the CGROM 59.
[0138]
Next, a detailed circuit configuration of the address decoder 61 and its equivalent circuit 62 will be described with reference to FIG.
[0139]
MOS transistors 162 to 165 form a serial ROM. The data read from the serial ROM is controlled by the MOS transistor 160, and the signal from the serial ROM is amplified by the MOS inverter 174. The MOS transistors 170 and 171 are for precharging and for fixing the potential, respectively. The equivalent circuit 62 has the same configuration as the ROM for one address line in the address decoder 61, and differs in that the MOS transistors 166 to 169 are controlled by the read signal 75.
[0140]
One of the address lines (any of 48) is selected according to the state of the address signal 77, whereby the address signal 77 is decoded. Next, when the EILAT 75 becomes the H level, the address decoded signal is output to the driver circuit 63 as the converted address signal 48. Then, based on the converted address signal (corresponding to a capture signal) 48, the already output DLAT (character pattern data) 82 is latched and accumulated in the driver circuit 63. At the same time, the equivalent circuit 62 outputs RS76 to the RS latch circuit 52. That is, the timing of the RS 76 is self-adjusted by the equivalent circuit 62.
[0141]
Next, a specific configuration of the RS latch circuit 52 will be described with reference to FIG.
[0142]
The RS latch circuit 52 includes NANDs 180, 181, 182, and a MOS inverter 183. The clock signal CK70 and the precharge signal RS76 are both at the H level and become effective levels (active). That is, when the CK 70 goes high, the EIRAM 71 goes low, and a read operation of data sent from the display data RAM 55 to the driver circuit 63 is performed. When RS76, which is a signal indicating the end of the read operation, goes high, the EIRAM 71 goes high, and the precharge operation is started.
[0143]
In the tenth embodiment, the configuration in the case where there are five equivalent circuits (54, 56, 58, 60, 62) has been described. However, the number of address decoders, memories, and the like is increased to provide six or more equivalent circuits. No problem. Although the above description has been made mainly on the assumption that the address decoder and the memory and the equivalent circuit output simultaneously, the output of the equivalent circuit may be slower than the output of the address decoder and the memory. That is, it is preferable to design and set an equivalent circuit with a certain margin so that the output of the equivalent circuit is slower than the output of the address decoder and the memory in consideration of manufacturing variations.
[0144]
As described above, according to the present embodiment, the display data of one character in one horizontal dot line is read in one cycle period (1C period) of the clock signal CK70. In this manner, a series of operations from data reading to latching can be controlled only by the clock signal CK70. This is realized by providing an equivalent circuit in each circuit and configuring the equivalent circuit so that the delay time of a read signal serving as a control signal is equal to the delay time of data reading. This eliminates the need to generate a timing signal considering the access time of each circuit, and eliminates the need to use a high-frequency clock signal (3 to 5 times the read signal). Assuming that the current consumption IDD of the CMOS circuit is f, voltage V, and load capacitance C, IDD = f × V × C. Therefore, the current consumption can be reduced to 1/3 to 1/5 by reducing the clock frequency. As described above, according to the present embodiment, it is possible to reduce the number of control circuits, and to reduce current consumption by reducing the number of circuits and the oscillation frequency.
[0145]
In addition, by providing an equivalent circuit, the timing of the read and precharge operations can be self-controlled, so that the read and precharge operations can be controlled without waste in one cycle of the clock signal from the oscillation device, and the power consumption of the device can be reduced. And high-speed operation can be realized.
[0146]
(Example 11)
Embodiment 11 is an embodiment showing a specific configuration of the driver circuit, and FIG. 24 shows the configuration.
[0147]
As shown in FIG. 24, the driver circuit (hereinafter, referred to as a signal driving circuit) 63 includes a driving unit 415 and line memories 416 and 417. The drive unit 415 includes drive circuits 415-a, 415-b, 415-1 to 415-n / 5, and the line memory 416 includes latch circuits 416-a, 416-b, 416-1 to 416-n / 5. The line memory 417 includes second latch circuits 417-a and 417-b and first latch circuits 417-1 to 417-n / 5. The output of the signal drive circuit 63 is output to the signal electrodes SA1 to SA5, S1 to Sn, and SB1 to SB5 on the matrix panel 453. On the matrix panel 453, display pixels such as liquid crystal elements are arranged in a matrix, and a plurality of signal electrodes SA1 to SA5, S1 to Sn, SB1 to SB5 and scanning electrodes Cs1, C1 to Cm, Cs2 intersect. Placed. Here, S1 to Sn and C1 to Cm are for character display, and SA1 to SA5, SB1 to SB5, Cs1, and Cs2 are for icon display. FIG. 25 illustrates an example of a display screen displayed on the matrix panel 453 according to the eleventh embodiment. Characters 1220 and icons 1222 to 1230 are displayed on the display screen. A call mark icon 1222 and a telephone mark icon 1224 are displayed in an icon display area on the upper side of the display screen, and indicator icons 1226 and 1228 indicating the remaining battery power are displayed in the icon display areas on the left and right sides. I have. A battery mark icon 1230 is displayed in an icon display area below the display screen. As described above, according to the eleventh embodiment, icons can be displayed at the top, bottom, left, and right of the display screen.
[0148]
The drive section 415 generates signals for driving the signal electrodes SA1 to SA5, S1 to Sn, and SB1 to SB5, and thereby enables display of characters and icons as shown in FIG. Here, the driving circuits 415-a and 415-b are for displaying icons, and the driving circuits 415-1 to 415-n / 5 are for displaying characters. The line memory 416 latches data from the line memory 417 by a latch pulse LP411, and the latched data is transferred to the drive unit 415 every horizontal period. Here, the latch circuits 416-a and 416-b are for displaying icons, and the latch circuits 416-1 to 416-n / 5 are for displaying characters. The line memory 417 stores the DLAT 82 output from the CGROM 59 in a time-division manner based on the capture signal 48 (48-a, 48-b, 48-1 to 48-n / 5). Here, the second latch circuits 417-a and 417-b and the capture signals 48-a and 48-b are for displaying icons, and the first latch circuits 417-1 to 417-n / 5 and 48-1 to 48-. n / 5 is for character display.
[0149]
The CGROM 59 generates not only character pattern data but also icon pattern data. The generated character pattern data and icon pattern data are multiplexed by the multiplexer 412 included in the CGROM 59 to generate a DLAT 82 which is a signal in which the character pattern data and the icon pattern data are arranged in time series. The character pattern data included in the DLAT 82 is sequentially stored in the first latch circuits 417-1 to 417-n / 5 according to the fetch signals 48-1 to 48-n / 5. On the other hand, the icon pattern data included in the DLAT 82 is stored in the second latch circuits 417-a and 417-b in response to the capture signals 48-a to 48-b. Thus, characters are displayed on the signal electrodes S1 to Sn corresponding to the first latch circuits 417-1 to 417-n / 5, and the signal electrodes SA1 to SA4 corresponding to the second latch circuits 417-a and 417-b. Icons are displayed on SA5, SB1 to SB5.
[0150]
Further, for example, if the capture signals 48-a and 48-b are generated simultaneously when predetermined icon pattern data is output as the DLAT 82, the same icon (indicator icons 1226 and 1228) is displayed in two different positions as shown in FIG. Can be displayed simultaneously in the area. When the icon pattern data is output as the DLAT 82, for example, if the capture signal 48-2 is generated, the icon can be displayed in the character display area. As described above, according to this embodiment, characters and icons can be displayed in an arbitrary area on the matrix panel 453. This enables more complex and advanced image display on the matrix panel. Further, according to the present embodiment, it is possible to move a character or an icon. This movement of characters and the like is also possible by controlling the generation timing of the capture signal 48. When such movement of characters and the like becomes possible, for example, in a mobile phone, it is possible to perform processing such as moving the character of the previously pressed number to the left on the display panel every time a dial button is pressed.
[0151]
The address decoder 61 that generates the capture signal 48 includes a decoder circuit 410 (410-a, 410-1 to 410-n / 5, 410-b) and an equivalent circuit 62 as shown in FIG. The generation timing of the capture signal 48 (48-a, 48-1 to 48-n / 5, 48-b) can be controlled by setting ROM programming in the decoder circuit 410 or the like. The decoder circuit 410-a corresponds to a serial ROM and an output cell for one address line, and includes, for example, the MOS transistors 160 to 165, 170, 171 and the MOS inverter 174 shown in FIG. The same applies to the decoder circuits 410-1 to 410-n / 5 and 410-b. Therefore, the generation timing (valid timing) of the capture signal (conversion address signal) 48 can be controlled by setting the ROM programming, that is, by setting the drain and source regions of the MOS transistors to be short-circuited. The ALAT 77 is sequentially incremented, for example, to (0000), (0001),... (1111), and the decoder circuit 410-a decodes the ALAT 77. Then, when the ALAT 77 becomes a predetermined value, the decoder circuit 410-a is selected, and the capture signal 48-a is generated, whereby the data output as the DLAT 82 at that time is stored in the second latch circuit 417-a. For example, when the ALAT 77 has a predetermined value, by selecting both the decoder circuits 410-a and 410-b and generating both the capture signals 48-a and 48-b, the same icon as shown in FIG. (Indicator icons 1226, 1228) can be displayed at different locations.
[0152]
The equivalent circuit 62 has the same circuit configuration as the decoder circuit, as described with reference to FIG. 22, and enables the RS 76 almost simultaneously (or later) when the capture signal 48 is generated (valid). To As a result, it becomes possible to enable the RS 76 at least at the time when data is written to the line memory 417 or thereafter, and shift the display data RAM, CGROM, and the like to the precharge operation.
[0153]
In the eleventh embodiment, two types of data, that is, character pattern data and icon pattern data are considered as data stored in the line memory 417 and the like (data included in the DLAT 82). However, the present invention is not limited to this, and the first to L-th (L is an integer) types of data may be stored in the line memory 417. In this case, the line memory 417 includes first to L-th latch circuits. However, the circuit configurations of the first to L-th latch circuits may be the same as each other.
[0154]
(Example 12)
The twelfth embodiment is an embodiment in which an oscillation signal is generated using an equivalent circuit included in the display data processing device, and FIG. 26 shows the configuration.
[0155]
The equivalent circuit 21 includes the equivalent circuits 354 and 356 of the seventh embodiment (see FIG. 9), the equivalent circuits 354, 356 and 358 of the eighth and ninth embodiments (see FIGS. 11 and 13), and the tenth embodiment (see FIG. 15). ), Equivalent to the equivalent circuits 54, 56, 58, 60 and 62 of FIG. Then, as shown in FIG. 26, the output of the equivalent circuit 21, for example, the third signal 373 of the seventh embodiment, the fourth signal 376 of the eighth embodiment, and the like are fed back as the first signal to form a self-oscillation loop. This enables oscillation using a signal delay or the like by the equivalent circuit 21.
[0156]
At this time, as shown in FIG. 26, it is desirable to provide control means 900 that can control at least one of the oscillation frequency and the duty ratio. In this way, for example, when the delay value or the like of the equivalent circuit 21 fluctuates depending on the variation of the manufacturing process or the like and the number of obtained oscillation frequencies fluctuates, the oscillation frequency is made closer to the frequency required for the oscillation device. It becomes possible. In addition, it is possible to control the duty ratio and appropriately operate the memory and the like in the display data processing device.
[0157]
FIG. 27 shows a configuration example in which the output of the equivalent circuit 21 is fed back to the input of the equivalent circuit 21 via the delay circuit 20 to form a ring oscillator. In this case, the delay circuit 20 corresponds to the control unit 900, and the oscillation frequency and the like can be controlled by adjusting the signal delay in the delay circuit 20. Here, the delay circuit 20 can be replaced by a waveform shaping inverter, a buffer, or the like. FIG. 28 shows an example in which a delay circuit 20 is provided and a self-oscillation loop is formed to form a ring oscillator in the circuit of the seventh embodiment.
[0158]
If a conventional ring oscillator is to be oscillated at a low frequency of about 10 K to 500 KHz, there is a problem that the circuit scale or the number of elements becomes very large and is not suitable for practical use. However, according to the twelfth embodiment, since the delay of the equivalent circuit is used, it is possible to oscillate at such a low frequency without increasing the circuit scale so much.
[0159]
FIG. 29 illustrates a configuration example in which both the oscillation frequency and the duty ratio are controlled by combining this embodiment and the first embodiment. As can be understood by comparing FIG. 29 and FIG. 1, in this configuration, the equivalent circuit 21 is added to the output of the MOS buffer 301 of the first embodiment. At this time, the buffer means is constituted by the MOS buffer 301 and the equivalent circuit 21. However, the MOS buffer 301 need not always be provided.
[0160]
FIG. 30 illustrates a configuration example in which both the oscillation frequency and the duty ratio are controlled by combining the present embodiment and the third embodiment. Here, for example, it is assumed that the delay time of the equivalent circuit 21 is t (21), and the values of the current sources 11 and 12 are In and Ip, respectively. Then, the oscillation frequency fOSC12 becomes
fOSC12 = 1 / {Tn + Tp + t (21)}
It becomes. However, Tn = C × V / In and Tp = C × V / Ip, and the delay value of the MOS buffer 1 is excluded. Therefore, by adjusting the current values In and Ip of the current sources 11 and 12, the oscillation frequency fOSC12 can be freely adjusted and set.
[0161]
According to the twelfth embodiment described above, the advantages of both the oscillation devices of the first to sixth embodiments and the display data processing devices of the seventh to eleventh embodiments can be obtained. The operation time can be allocated to circuits (memory and the like) included in the display data processing device without waste, and the oscillation frequency of the oscillation device can be determined using the delay value or the like of these circuits. This makes it possible to provide a display data processing device that is less affected by variations in the manufacturing process and that can operate at high speed with low power consumption.
[0162]
The present invention is not limited to the above-described first to twelfth embodiments, and various modifications can be made within the scope of the present invention.
[0163]
For example, the specific configurations of the charging unit and the discharging unit according to the first embodiment are not limited to those described in the second to sixth embodiments. Although the bias circuit and the bias adjustment circuit are provided in FIG. 4, these may not be provided, and the configurations of the bias circuit and the bias adjustment circuit are not limited to those described in the fourth to sixth embodiments.
[0164]
Further, the memory included in the display data processing device is not limited to the display data RAM, the CGROM, or the like, and various memories can be considered. The case where another circuit is inserted between memories or the like is also included in the equivalent range of the present invention. As the storage means, various devices such as a latch circuit and a memory can be adopted as long as they can store at least data. Further, the address decoder is not limited to the configuration described in the tenth embodiment or the like.
[0165]
Combining the oscillating devices of the first to sixth embodiments with the seventh to twelfth embodiments is particularly effective in terms of low power consumption and downsizing of the circuit. It is not limited to those shown in Examples 1 to 6. That is, as long as the oscillation device can control the duty ratio or the oscillation frequency of the oscillation signal, low power consumption can be achieved by combining with the seventh to twelfth embodiments. For example, in the oscillation device having the configuration shown in FIG. 31, the selection circuit 302 selects one of the charging unit 307 and the discharging unit 308 based on the output of the MOS buffer 301, and charges and discharges the input of the MOS buffer 301. Thereby, the oscillation frequency and the duty ratio of the oscillation signal can be freely adjusted. For example, as shown in FIGS. 32A, 32B, 33A, and 33B, an oscillator 700 that outputs a high-frequency oscillation signal and waveform shaping circuits 710 and 720 may be combined. The duty ratio can be adjusted. Here, the waveform shaping circuit 710 in FIG. 32A includes inverters 712 to 715 and an AND circuit 716. Then, as shown in FIG. 32B, an oscillation signal E (oscillation period TOSC) from the oscillation device 700 and a signal F (delay value Tdelay) obtained by delaying the oscillation signal E are input to an AND circuit 716, whereby a signal is inputted. G can be obtained. The duty ratio D at this time is
D = (TOSC−Tdelay) / TOSC
It becomes. Therefore, the duty ratio can be adjusted by controlling Tdelay.
[0166]
The waveform shaping circuit 720 of FIG. 33A includes D flip-flops 722 and 724 and an AND circuit 726. The oscillation signal E from the oscillation device 700 is input to the clock terminals of the D flip-flops 722 and 724, and the signal H can be obtained by inputting the outputs of the D flip-flops 722 and 724 to the AND circuit 726. . As is clear from FIG. 33B, an oscillation signal E having a frequency twice as high as that of the signal H is required to make the duty ratio 25%, and to make the duty ratio 12.5%. An oscillation signal E having a frequency four times that of the signal H is required. The configuration in which the waveform shaping circuit is provided as described above is disadvantageous in terms of power consumption as compared with the oscillating devices of the first to sixth embodiments. Power consumption can be reduced. As a result, the power consumption of the entire apparatus can be reduced.
[0167]
The present invention can be applied not only to a simple matrix type liquid crystal display device but also to an active matrix type liquid crystal display device as long as it has at least a plurality of display data processing memories. The present invention can be applied to the used display device.
[0168]
【The invention's effect】
As described above, according to the present invention, the oscillation frequency and duty ratio of an oscillation signal can be adjusted flexibly, easily, and accurately, and power consumption can be reduced and the circuit size can be reduced.
[0169]
Further, according to the present invention, the read operation can be controlled by itself and there is no need to generate various timing signals, so that power consumption can be reduced and the circuit size can be reduced.
[0170]
According to the invention, not only the read operation but also the precharge operation can be controlled by itself, and the read operation and the precharge operation can be controlled without waste in one cycle of the clock signal.
[0171]
Further, according to the present invention, for example, characters, icons, and the like can be displayed in a desired arrangement on, for example, a matrix panel, and a complicated image display can be easily realized.
[0172]
According to the invention, the read time and the precharge time can be controlled only by controlling the duty ratio of the oscillation device, and the display data processing device can be operated with the oscillation clock signal of the lowest frequency required for data processing. .
[0173]
Further, according to the present invention, the operation time can be efficiently allocated to the circuits included in the display processing device, and the oscillation frequency of the oscillation device can be determined using the delay value or the like of these circuits. This makes it possible to provide a display data processing device that is not easily affected by fluctuations in the manufacturing process.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of an oscillation device according to a first embodiment.
FIG. 2 is a waveform chart showing an operation of the first embodiment.
FIG. 3 is a diagram illustrating a configuration of an oscillation device according to a second embodiment.
FIG. 4 is a diagram illustrating a configuration of an oscillation device according to a third embodiment.
FIG. 5 is a waveform chart showing the operation of the third embodiment.
FIG. 6 is a diagram showing a specific configuration of a current source and a bias circuit.
FIG. 7 is a diagram showing a specific configuration of a current source and a bias circuit.
FIGS. 8A to 8D are diagrams illustrating a specific configuration of a bias adjustment circuit;
FIG. 9 is a diagram illustrating a configuration of a display data processing device according to a seventh embodiment.
FIG. 10 is a timing chart illustrating the operation of the seventh embodiment.
FIG. 11 is a diagram illustrating a configuration of a display data processing device according to an eighth embodiment.
FIG. 12 is a timing chart illustrating the operation of the eighth embodiment.
FIG. 13 is a diagram illustrating a configuration of a display data processing device according to a ninth embodiment.
FIG. 14 is a diagram illustrating an example of a configuration when the display data processing device includes N memories.
FIG. 15 is a diagram illustrating a configuration of a display data processing device according to a tenth embodiment.
FIG. 16 is a diagram showing a comparative example in which a display data processing device is configured by a conventional method.
FIG. 17 is a timing chart illustrating the operation of the tenth embodiment.
FIG. 18 is a timing chart illustrating the operation of the comparative example.
FIG. 19 is a diagram illustrating an example of a configuration of an address decoder for a display data RAM and an equivalent circuit thereof.
FIG. 20 is a diagram illustrating an example of a configuration of a display data RAM and an equivalent circuit thereof.
FIG. 21 is a diagram illustrating an example of a configuration of an address decoder for a CGROM, a CGROM, and an equivalent circuit thereof.
FIG. 22 is a diagram illustrating an example of a configuration of an address decoder for a driver circuit and an equivalent circuit thereof.
FIG. 23 is a diagram illustrating an example of a configuration of an RS latch circuit.
FIG. 24 is a diagram illustrating a configuration of an eleventh embodiment (specific example of a driver circuit).
FIG. 25 is an example of a display screen displayed on a matrix panel.
FIG. 26 is a diagram illustrating a configuration of an eleventh embodiment in which an oscillation signal is generated using an equivalent circuit included in a display data processing device.
FIG. 27 is a diagram illustrating a configuration example when a ring oscillator is formed according to the eleventh embodiment.
FIG. 28 is a diagram illustrating a configuration example when a ring oscillator is formed in combination with the seventh embodiment.
FIG. 29 is a diagram illustrating a configuration example in a case where an oscillation frequency and a duty ratio are controlled in combination with the first embodiment.
FIG. 30 is a diagram illustrating a configuration example in a case where an oscillation frequency and a duty ratio are controlled in combination with the third embodiment.
FIG. 31 is a diagram illustrating a configuration example of an oscillation device capable of adjusting an oscillation frequency and a duty ratio.
FIG. 32A is a diagram illustrating an example of a configuration of an oscillation device using a waveform shaping circuit, and FIG. 32B is a timing chart thereof.
FIG. 33A is a diagram showing another example of the configuration of the oscillator using the waveform shaping circuit, and FIG. 33B is a timing chart thereof.
FIG. 34 is a diagram showing a configuration of a conventional CR oscillation circuit.
FIG. 35 is a diagram showing a configuration of a conventional ring oscillator.
FIG. 36 is a diagram showing a configuration of a CR oscillation circuit capable of changing a duty ratio of an oscillation signal.
FIG. 37A is a configuration example of a conventional display data processing device, and FIG. 37B is a timing chart thereof.
[Explanation of symbols]
1,133,137 MOS buffer
2, 99, 100, 101, 102, 105, 106, 120, 121, 122, 123, 124, 132, 136, 142, 149, 174, 175, 176, 177, 183, 200, 201, 202, 203, 207, 208, 209, 210 MOS inverter
3, 11, 22, 24, 26, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 108, 107, 111, 112, 113, 130, 131, 134, 135, 143, 144, 145, 170, 171, 172, 173 P-type MOS transistor
4, 12, 23, 25, 27, 95, 96, 97, 98, 109, 110, 116, 117, 118, 119, 138, 140, 141, 146, 147, 148, 150, 151, 152, 153, 154, 155, 156, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169 Second N-type MOS transistor
5,204 capacitors
6 Oscillation output
7, 8, 29, 30, 205 resistance
9 High potential side power supply
10 Low potential side power supply
11, 12 Current source
13, 14 Bias terminal
15 terminals
16 bias circuit
17 Bias adjustment circuit
18 Frequency selection signal
20 Delay circuit
21 Equivalent circuit
28 Variable resistance
31, 32 switch
33, 34 fuse
35, 36 MOS transistor
37, 38 control signal
50 Oscillator
51 Timing generation circuit
52 RS latch circuit
53 Address Decoder for Display Data RAM
54 Equivalent circuit of address decoder for display data RAM
55 Display data RAM (Display data memory)
56 Equivalent circuit of display data RAM
57 Address decoder for CGROM
58 Equivalent circuit of address decoder for CGROM
59 CGROM (Character pattern generation circuit)
60 CGROM equivalent circuit
61 Address decoder for driver circuit
62 Equivalent circuit of address decoder for driver circuit
63 Driver circuit
64 Write Address Decoder
70 Oscillation clock
125 RAM cells
126 RAM output cell
139 ROM cell
180, 181 182 NAND
206 Oscillation output
250 oscillator
251 Timing generation circuit
301 MOS buffer
302 Selection means
303 Waveform shaping means
305 Return means
306 oscillation clock
310 charging means
312 First current control means
314 First switching means
320 discharging means
322 Second current control means
324 Second switching means
352 selection circuit
353 First memory (image display memory)
354 first equivalent circuit
355 second memory (image display pattern generator)
356 Second equivalent circuit
357 storage means (line memory)
358 3rd equivalent circuit
370 Clock signal CK
371 1st signal
372 Second signal
373 Third signal
376 4th signal
377 address signal
379 First data
380 Second data

Claims (21)

An oscillating device including buffer means, feedback means for feeding back the output of the buffer means to the input, charging means and discharging means connected to the input of the buffer means, and N (N) A display data processing device comprising:
A first switching unit that is turned on / off based on an output of the buffer unit, and a first current that controls a current flowing into an input of the buffer unit via the first switching unit; Control means,
A second switching unit that is turned on and off based on an output of the buffer unit, and a second current that controls a current flowing from an input of the buffer unit via the second switching unit. and a control means only including,
The display data processing device,
A first memory for reading data when a first signal generated by an oscillation signal from the oscillation device becomes an effective level;
A first equivalent circuit that outputs a second signal based on the first signal, wherein the first equivalent circuit sets the second signal to an effective level at least when data read from the first memory is determined or thereafter;
A K-th memory for performing data reading based on an output result of the (K-1) -th memory when a K-th signal (1 <K ≦ N, K is an integer) becomes an effective level;
A circuit for outputting a (K + 1) th signal based on the Kth signal, wherein a Kth equivalent for setting the (K + 1) th signal to a valid level at least at a time when data read from the Kth memory is determined or thereafter. Circuit and
A display data processing device , comprising: storage means for writing data read from the N-th memory when the (N + 1) -th signal output from the N-th equivalent circuit becomes a valid level . In claim 1,
The first and second switching means are first and second transistors of first and second conductivity types, respectively, wherein the output of the buffer means is connected to a gate electrode, and the first and second current control means are respectively provided. There display data processing device, wherein the first, the second resistor. In claim 1,
The first and second switching means are first and second transistors of first and second conductivity types, wherein the output of the buffer means is connected to a gate electrode, and the first and second current control means are the first and second current control means. 1. A display data processing device, which is a second current source. In claim 3,
The first current source comprises a third transistor of a first conductivity type, the second current source comprises a fourth transistor of a second conductivity type,
First and second bias terminals connected to the gate electrodes of the third and fourth transistors, and the first and second currents are controlled by controlling a bias voltage to the first and second bias terminals. A display data processing device , comprising: a bias circuit for controlling at least a current ratio of first and second currents flowing through a source. In claim 4,
A display data processing device comprising means for controlling the magnitude of the first and second currents. In any one of claims 4 and 5,
The bias circuit is
A fifth transistor of a first conductivity type having a gate electrode connected to the first bias terminal and a drain region connected to the second bias terminal; and a gate electrode and a drain region connected to the first bias terminal. A sixth transistor of a first conductivity type, a seventh transistor of a second conductivity type having a gate electrode and a drain region connected to the second bias terminal, and a drain region having a gate electrode connected to the second bias terminal. There display data processing device, characterized in that it comprises an eighth transistor of the second conductivity type connected to said first bias terminal. In claim 6,
Connecting a third bias terminal to the gate electrode of the third transistor instead of the first bias terminal;
A ninth transistor of a first conductivity type having a gate electrode and a drain region connected to the third bias terminal; a gate electrode connected to the second bias terminal; and a drain region connected to the third bias terminal. A display data processing device , comprising: a tenth transistor of a second conductivity type. In any one of claims 1 to 7,
A display data processing apparatus, wherein at least one of the first to N-th memories and storage means performs a precharge operation when the first to (N + 1) -th signals are at an invalid level. In claim 8,
A circuit for outputting an (N + 2) th signal based on the (N + 1) th signal, wherein the (N + 2) th signal is set to a valid level at least at or after the time when the read data is written to the storage means; (N + 1) equivalent circuit;
When the (N + 2) th signal becomes a valid level, at least one of the first to (N + 1) th signals is set to a non-valid level, and at least one of the first to Nth memories and storage means is precharged. Means for selecting an operation. In any one of claims 1 to 9,
The display data processing device according to claim 1, wherein when the first signal goes to an ineffective level, the second to Nth signals go to an ineffective level. In any one of claims 1 to 10,
A display data processing device, wherein the first to Nth equivalent circuits are constituted by MOS transistors equivalent to MOS transistors forming ROM cells or RAM cells of the first to Nth memories. In any one of claims 1 to 11,
Decoder means for generating a converted address signal from an address signal inputted to at least one of the first to Nth memories and storage means;
Based on any one of the first to (N + 1) th signals, any one of the first to Nth memories and the storage means may be replaced with the first to (N + 1) th signals which are replaced by the first to (N + 1) th signals. N + 1) 'signal, and a decoder equivalent circuit for setting the first' to (N + 1) 'signals to an effective level at or after the conversion address signal output from the decoder means is determined. And a display data processing device. In any one of claims 1 to 12,
The storage means comprises first to L-th storage means for capturing first to L-th (L is an integer) types of read data;
A fetch signal for storing the read data from the N-th memory in the storage means in a time-divisional manner every one horizontal period is generated, and the first to L-th types of read data are stored in the first to L-th memories. A display data processing device, comprising: a capture signal control means for controlling the generation timing of the capture signal so as to be captured by a storage means. In claim 13,
The display data processing apparatus according to claim 1, wherein said capture signal control means generates a conversion address signal from an address signal, and comprises decoder means using the conversion address signal as the capture signal. In any one of claims 1 to 14,
A display data processing apparatus, wherein the plurality of memories include means for storing a code signal of an image display pattern, and means for generating an image display pattern based on the code signal. In any one of claims 1 to 15,
A display data processing device, wherein a read time and a precharge time are adjusted by controlling a duty ratio of the oscillation signal. 17. A display data processing apparatus according to claim 1, wherein a display panel is arranged in a matrix and a plurality of signal electrodes and scanning electrodes are arranged to intersect, and the signal electrodes of the matrix panel are arranged. Including a signal drive circuit for applying a drive voltage to the, and a scan drive circuit for applying a drive voltage to the scan electrodes of the matrix panel,
A matrix type display device, wherein at least a drive voltage of the signal drive circuit is generated based on data stored in the storage unit of the display data processing device. An oscillation signal generated by an oscillation signal generation method using a buffer means, a feedback means for feeding an output of the buffer means to an input, and a charging means and a discharging means connected to the input of the buffer means ; A display data processing method performed by using N (N is an integer) memories for processing data,
The method for generating an oscillation signal turns on / off a first switching means included in the charging means based on an output of the buffer means, and connects the input to the buffer means via the first switching means. Controlling the flowing current;
Turning on and off the second switching means included in the discharging means based on the output of the buffer means, and controlling the current flowing from the input of the buffer means via the second switching means ,
The display data processing method,
Reading data from the first memory when the first signal generated by the oscillation signal becomes a valid level;
Outputting a second signal based on the first signal, and setting the second signal to an effective level at least at or after a time when data read from the first memory is determined;
Reading the data from the K-th memory based on the output result of the (K-1) -th memory when the K-th signal (1 <K ≦ N, K is an integer) becomes a valid level; Outputting a (K + 1) th signal based on the signal, and setting the (K + 1) th signal to an effective level at least at or after the time when data read from the Kth memory is determined;
Writing the data read from the N-th memory to the storage means when the (N + 1) -th signal becomes a valid level. In claim 18,
A display data processing method, comprising: causing at least one of the first to N-th memories and storage means to perform a precharge operation when the first to (N + 1) -th signals have become ineffective levels. In claim 19,
Outputting the (N + 2) -th signal based on the (N + 1) -th signal, and setting the (N + 2) -th signal to a valid level at least at or after the time when the read data is written to the storage means. When,
When the (N + 2) th signal becomes a valid level, at least one of the first to (N + 1) th signals is set to a non-valid level, and at least one of the first to Nth memories and storage means is precharged. Selecting an operation. In any one of claims 18 to 20,
The storage means comprises first to L-th storage means for capturing first to L-th (L is an integer) types of read data;
A capture signal for storing the read data from the N-th memory in the storage means in a time-divisional manner every horizontal period is generated, and the first to L-th types of read data are stored in the first to L-th memories. Controlling a generation timing of the capture signal so as to be captured by a storage means.

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