JP3588143B2 - Charge coupled device and method of manufacturing the same - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a charge-coupled device and a method for manufacturing the same.
[0002]
[Prior art]
FIG. 6 is a schematic diagram of a conventional frame transfer type CCD solid-state imaging device. The CCD solid-state imaging device 50 is a charge-coupled device, and includes an imaging unit 51, a storage unit 52, a horizontal transfer unit 53, and an output unit 54. In the imaging unit 51, light receiving pixels formed of light receiving elements arranged two-dimensionally are formed, and generate information charges according to the illuminated subject image. This information charge is transferred from the imaging unit 51 to the storage unit 52 in units of one screen, and is temporarily stored by the storage unit 52.
[0003]
Further, the information charges are output from the storage unit 52 to the output unit 54 via the horizontal transfer unit 53 in units of one row. The output unit 54 converts the amount of information charges into a voltage value, and outputs the converted voltage value as an image signal Yt.
[0004]
In the CCD solid-state imaging device 50 as described above, in order to suppress so-called blooming in which information charges overflowing from each light-receiving element of the imaging unit 51 are mixed into adjacent light-receiving pixels, an overflow drain that absorbs excessive charges is provided. Can be As the overflow drain, there are a horizontal type in which a drain is provided in a separation region for separating light-receiving pixels to absorb excess charge, and a vertical type in which the substrate itself acts as a drain to sink excess charge deep into the substrate. In recent years, there has been a tendency to adopt a vertical method that is advantageous for increasing the density of light receiving pixels.
[0005]
FIG. 7 is a cross-sectional view of the imaging unit 51. A P-type well 62 is provided on the surface side of an N-type silicon substrate 61, and an N-type buried region 63 is provided on the surface of the well 62 to form a buried channel structure. A plurality of transfer electrodes 65 and 66 having a two-layer structure are arranged on the buried region 63 via an oxide film 64 in parallel with each other. The transfer electrodes 65 and 66 have a partially overlapped two-layer structure, and are applied with two-phase transfer clocks φ1 and φ2, respectively. On the other hand, a substrate bias voltage VN is applied to the silicon substrate 61. The P-type well 62 is at the ground potential (0 V).
[0006]
FIG. 8 is a diagram illustrating a potential state of the imaging unit 51. The potential of the imaging unit 51 is formed to be minimum in the buried region 63 and maximum in the well 62 as shown by the solid line in FIG. 8 based on the transfer clocks φ1 and φ2 applied and the substrate bias voltage VN. You. The potential in the buried region 63 is controlled by the voltage applied to the transfer electrodes 65 and 66, that is, the voltages of the transfer clocks φ1 and φ2. Then, information charges are stored and transferred in response to transfer clocks φ1 and φ2 applied to the transfer electrodes 65 and 66, respectively.
[0007]
On the other hand, the potential in the well 62 is controlled by the substrate bias voltage VN, and forms a barrier through which information charges in the buried region 63 flow to the silicon substrate 61 side. That is, when the voltage of the substrate bias voltage VN is reduced, the potential changes as shown by the dashed line in FIG. 8, and the barrier is reduced. Then, the information charges easily cross the barrier, and the stored information charges decrease. Therefore, the difference between the height of the barrier and the depth of the potential of the buried region 63 indicates the information charge storage capacity.
[0008]
That is, if the height of the potential barrier is too low, the amount of transferred charges is reduced, and it becomes impossible to obtain a sufficient image signal Yt. On the other hand, if the barrier is high, the amount of transferred charges becomes too large, and the image signal Yt may be saturated. Therefore, it is necessary to adjust the substrate bias voltage VN and appropriately set the height of the barrier.
[0009]
[Problems to be solved by the invention]
However, since the elements have variations, even if the same substrate bias voltage VN is applied, the heights of the barriers are different. Therefore, the substrate bias voltage VN is adjusted for each element and the height of the barrier is set. There is a need. Therefore, when the CCD solid-state imaging device 50 is used, the substrate bias voltage VN is input to the CCD solid-state imaging device 50 via a potentiometer (not shown). Then, it is necessary to adjust the substrate bias voltage VN so as to obtain an appropriate image signal Yt by operating the potentiometer while viewing the image captured by the CCD solid-state imaging device 50. Therefore, there is a problem that adjustment of the substrate bias voltage VN is troublesome.
[0010]
On the other hand, a CCD solid-state imaging device having an adjustment circuit for internally adjusting the substrate bias voltage VN has also been proposed. The adjusting circuit is provided with a voltage dividing resistor composed of a plurality of resistors and a plurality of fuses. By appropriately cutting the plurality of fuses, the voltage dividing ratio of the voltage dividing resistor is changed to adjust the substrate bias voltage VN. It is supposed to. However, there is a problem that a process for forming the adjustment circuit needs to be added, and the manufacturing is troublesome.
[0011]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a charge-coupled device that can save the trouble of adjustment by a user without adding a manufacturing process. It is another object of the present invention to provide a manufacturing method capable of easily manufacturing such a charge-coupled device.
[0012]
[Means for Solving the Problems]
According to a first aspect of the present invention, in a charge-coupled device in which a plurality of transfer electrodes are arranged on a semiconductor substrate, an external voltage of a predetermined voltage is applied.Is enteredAn external input terminal and a non-volatile memory element having a floating gate formed on the same layer as the transfer electrode and arranged on the semiconductor substrate along with the transfer electrode, and stored in the floating gate of the memory element The external input terminal according to the charge amountEntered inExternal voltageIs less than the external voltage value.VoltageToA voltage adjusting unit for adjusting the voltage and outputting the adjusted voltage.
[0013]
According to a second aspect of the present invention, in the charge-coupled device according to the first aspect, the memory element has the same structure as a floating gate and an upper layer formed on the same layer as a lower layer of the transfer electrode having a two-layer structure. And a control gate formed in the layer.
[0014]
According to a third aspect of the present invention, in the charge-coupled device according to the first aspect, the memory element is the same as a floating gate formed on the same layer as the transfer electrode and a wiring for supplying power to the transfer electrode. And a control gate formed in the layer.
[0015]
According to a fourth aspect of the present invention, in the charge-coupled device according to the first aspect, the voltage adjustment unit is configured to include the external input terminal.Entered inExternal voltage is appliedSeries connectionMultiple resistors and each resistorConnection pointAnd the on / off control is performed by the electric charge stored in the floating gate toConnection pointAnd a memory element that is selectively grounded.
[0016]
According to a fifth aspect of the present invention, the charge transfer unit having the first and second transfer electrodes having the two-layer structure is the same as the memory element having the floating gate and the control gate at least partially overlapping each other. A method of manufacturing a charge-coupled device disposed on a semiconductor substrate, comprising: a first step of forming a floating gate of the memory element simultaneously with a first transfer electrode of the charge transfer unit; And forming a control gate of the memory element at the same time as the transfer electrode.
[0017]
According to a sixth aspect of the present invention, there is provided a charge transfer section having a transfer electrode and a power supply wiring disposed on the transfer electrode, and a memory element having a floating gate and a control gate at least partially overlapping each other. Is a method for manufacturing a charge-coupled device disposed on the same semiconductor substrate, wherein the charge transfer unitTurnA first step of forming a floating gate of the memory element simultaneously with the transmission electrode;Wiring for power supplyAnd a second step of forming a control gate of the memory element.
[0018]
[Action]
Therefore, according to the first aspect of the present invention, the external input terminalToExternal voltage of predetermined voltageIs entered. The voltage adjustment unit is arranged on the semiconductor substrate along with the transfer electrode, and has a memory element. A memory element including a nonvolatile memory element has a floating gate and a control gate formed in the same layer as a transfer electrode. The voltage adjustment unit is connected to an external input terminal according to the amount of charge stored in the floating gate of the memory element.Entered inThe voltage of the external voltage is adjusted, and the adjusted voltage is output.
[0019]
According to the invention described in claim 2, the memory element has the floating gate and the control gate. The floating gate is formed in the same layer as the lower layer of the two-layered transfer electrode, and the control gate is formed in the same layer as the upper layer.
[0020]
According to the invention described in claim 3, the memory element has the floating gate and the control gate. The floating gate is formed in the same layer as the transfer electrode, and the control gate is formed in the same layer as a wiring for supplying power to the transfer electrode.
[0021]
According to the fourth aspect of the present invention, the voltage adjustment unit is configured to include an external input terminal.ToInput external voltage is appliedSeries connectionMultiple resistors and each resistorConnection pointAnd is turned on / off by the electric charge stored in the floating gate.Connection point of each resistorAnd a memory element that is selectively grounded.
[0022]
According to the invention described in claim 5, the charge transfer section and the memory element are arranged on the semiconductor substrate. The charge transfer section has first and second transfer electrodes having a two-layer structure. The memory element has a floating gate and a control gate at least partially overlapping each other. Then, a floating gate of the memory element is formed simultaneously with the first transfer electrode of the charge transfer section, and a control gate of the memory element is formed simultaneously with the second transfer electrode of the charge transfer section.
[0023]
According to the invention described in claim 6, the charge transfer section and the memory element are arranged on the semiconductor substrate. The charge transfer section has a transfer electrode and a power supply wiring disposed on the transfer electrode. The memory element has a floating gate and a control gate at least partially overlapping each other. And a first transfer electrode of the charge transfer section.Or the second transfer electrodeAt the same time, the floating gate of the memory element is formed,Wiring for power supply andAt the same time, the control gate of the memory element is formed.
[0024]
【Example】
Hereinafter, an embodiment in which the present invention is embodied in a CCD solid-state imaging device will be described with reference to the drawings.
[0025]
In the present embodiment, the same components as those of the conventional example shown in the drawings are denoted by the same reference numerals, and detailed description thereof will be omitted.
FIG. 1 is a plan view showing a chip of a CCD solid-state imaging device. On the chip 1, an imaging unit 51, a storage unit 52, a horizontal transfer unit 53, an output unit 54, and a voltage adjustment unit 2 are formed. The voltage adjusting unit 2 is a voltage dividing circuit, and receives an external input voltage according to a preset voltage dividing ratio.Was doneA predetermined external voltage VG is divided, and a voltage obtained by the division is applied to the silicon substrate 61 as a substrate bias voltage VN.
[0026]
FIG. 2 is a circuit diagram of the voltage adjustment unit 2. The voltage adjustment unit 2 is provided with an external input terminal 10. A predetermined voltage (40 V in this embodiment) is applied to the external terminal 10 from outside the chip 1.
[0027]
A plurality of resistors (four in this embodiment) 11 to 14 are connected to the external input terminal 10 in series. A silicon substrate 61 is connected between the resistors 11 and 12. The drains of the memory elements 15 to 17 are connected to the resistors 12 to 14, respectively. That is, the drain of the memory element 15 is connected between the resistors 12 and 13, the drain of the memory element 16 is connected between the resistors 13 and 14, and the drain of the memory element 17 is connected to the resistor 14.
[0028]
Each of the memory elements 15 to 17 is a non-volatile memory element including an N-channel MOS transistor having a floating gate, and can be turned on / off in accordance with electric charge stored in the floating gate. Normally, each of the memory elements 15 to 17 is turned on without accumulating electric charge in its floating gate, and can be controlled to be off by accumulating electric charge in each floating gate. ing.
[0029]
The sources of the memory elements 15 to 17 are grounded, and the control gate is applied with a read voltage VR. Then, the resistances 12 to 14 connected to the memory elements 15 to 17 are grounded depending on the on / off state of the memory elements 15 to 17.
[0030]
When all of the memory elements 15 to 17 are off, the external voltage VG is applied to the silicon substrate 61 via the resistor 11 as it is. When the memory element 15 is on, the resistance 12 and 13 are grounded. Then, the external voltage VG input from the external input terminal 10 is divided by the resistors 11 and 12, and the divided voltage is output to the silicon substrate 61. Similarly, when the memory element 15 is off and the memory element 16 is on, the resistance 13 and 14 are grounded. Then, the external voltage VG input from the external input terminal 10 is divided by the resistors 11 to 13, and the divided voltage is output to the silicon substrate 61. When the memory elements 15 and 16 are off and the memory element 17 is on, the resistor 14 is grounded. Then, the external voltage VG input from the external input terminal 10 is divided by the resistors 11 to 14, and the divided voltage is output to the silicon substrate 61.
[0031]
That is, by appropriately selecting the on / off state of the memory elements 15 to 17, the voltage division ratio by the resistors 11 to 14 is selected. The external voltage VG can be divided by the selected voltage division ratio and applied to the silicon substrate 61. Therefore, the voltage of the external voltage VG can be controlled by the on / off states of the memory elements 15 to 17.
[0032]
3A and 3B are cross-sectional views of a CCD solid-state imaging device. FIG. 3A is an imaging unit 51, FIG. 3B is an N-channel MOS transistor (hereinafter referred to as NMOS) 20 formed in an output unit 54, and FIG. FIG. 4 is a cross-sectional view of a memory element 15 of the voltage adjustment unit 2.
[0033]
The NMOS 20 has a P-type well 21 formed on a silicon substrate 61, similarly to the imaging unit 51. On the well 21, an N-type drain region 22 and a source region 23 are formed. The impurity concentration of the drain region 22 and the source region 23 is higher than the concentration of the N-type buried region 63 formed in the imaging unit 51. On a channel between the drain region 22 and the source region 23, a gate layer 24 is formed via an oxide film 64. Further, contacts 25 are formed in the drain region 22 and the source region 23.
[0034]
In the memory element 15, a P-type well 31 is formed on a silicon substrate 61 similarly to the NMOS 20 of the imaging unit 51 and the output unit 54. An N-type drain region 32 and a source region 33 are formed on the well 31 similarly to the NMOS 20, and the impurity concentration of the drain region 32 and the source region 33 is the same as the impurity concentration of the drain region 22 and the source region 23 of the NMOS 20. It has become.
[0035]
A channel is formed between the drain region 32 and the source region 33, and a floating gate 34 is formed above the channel and the source region 33 via an oxide film 64. The floating gate 34 has one end disposed on the source region 33 and the other end disposed so as to cover substantially half of the channel. A control gate 35 is formed above the drain region 32 and the channel via an oxide film 64. The control gate 35 has one end disposed on the drain and the other end formed so as to cover substantially half of the floating gate. The memory element has a floating gate 34 and a control gate 35, and has a two-layer gate structure, like the transfer electrodes 65 and 66 of the imaging unit 51.
[0036]
Similarly to the NMOS 20, contacts 25 are formed in the drain region 32 and the source region 33, respectively.
Since the structures of the memory elements 16 and 17 are formed in the same manner as the memory element 15, the description of the memory elements 16 and 17 will be omitted.
[0037]
FIG. 4 is a schematic circuit diagram when the memory element 15 is controlled to be turned off.
The first write voltage VW1 (12 V in this embodiment) is applied to the source of the memory element 15 and the drain is grounded. Then, a second write voltage VW2 (2 V in this embodiment) is applied to the gate of the memory element 15. Then, the potential of the floating gate rises to a potential corresponding to the first write voltage VW1 applied to the source (it is estimated to be about 10 V in this embodiment). At this time, the channel immediately below the floating gate is turned on, and the channel immediately below the control gate is slightly turned on. As a result, a high electric field is applied only to the central portion of the channel immediately below the two gates, and charges (hot electrons) are injected and stored in the floating gate. As a result, the memory element 15 is turned off. Since the floating gate is insulated by the oxide film 64, the charge stored in the floating gate is held as it is.
[0038]
The description of the case where the memory elements 16 and 17 are controlled to be turned off is the same as the case where the memory element 15 is controlled to be turned off, and thus the description thereof is omitted.
Next, the operation of the CCD solid-state imaging device configured as described above will be described.
[0039]
First, each of the memory elements 15 to 17 is separated from the resistors 12 to 14, and a potentiometer (not shown) is connected to the external input terminal 10 of the CCD solid-state imaging device as in the related art. Then, the potentiometer is adjusted so that the image signal Yt has an appropriate value, and the voltage applied to the external input terminal 10 at that time is measured.
[0040]
Next, a predetermined external voltage V is applied to the external input terminal 10.G Was appliedIn this case, the memory elements 15 to 17 are appropriately turned off so that the voltage divided by the resistors 11 to 14 becomes equal to the previously measured voltage. For example, assuming that the voltage divided by the resistors 11 to 13 is equal to the previously measured voltage, the resistor 13 and the resistor 14 need only be grounded. That is, if the memory element 15 is kept off and the memory element 16 is kept on, the external voltage VG can be divided by the resistors 11 to 13 and the divided voltage can be output to the silicon substrate 61. Therefore, the charge is stored in the floating gate of the memory element 15 to control the memory element 15 to be in the off state, and the other memory elements 16 and 17 are kept in the on state.
[0041]
Then, since the memory element 16 is in the ON state, the space between the resistors 13 and 14 is grounded. As a result, the external voltage VG applied to the external input terminal 10 is divided by the resistors 11 to 13, and the divided voltage is applied to the silicon substrate 61 from between the resistors 11 and 12. Since the off state of the memory element 15 is maintained, the external voltage VG of a predetermined voltage is maintained.ButApply to external input terminal 10If doneThus, an appropriate substrate bias voltage VN is applied to the silicon substrate 61. Therefore, when attempting to use the CCD solid-state imaging device, the user must input a predetermined external voltage VG to the external input terminal 10.Is applied, It is not necessary to perform complicated adjustments as in the related art.
[0042]
Next, a method for manufacturing the CCD solid-state imaging device configured as described above will be described.
A P-type impurity such as boron ions is implanted into an N-type silicon substrate 61 to simultaneously form a P-type well 62 of the imaging unit 51, a P-type well 21 of the NMOS 20, and a P-type well 31 of the memory element 15. Next, a resist film (not shown) having a desired shape is formed, an N-type impurity such as phosphorus is implanted, and a low-concentration n-type semiconductor buried region 63 is formed in the P-type well 62 of the imaging unit 51. I do.
[0043]
Next, an oxide film 64 is formed on the imaging unit 51, the NMOS 20, and the memory element 15. A polycrystalline silicon film is formed on oxide film 64. The polycrystalline silicon film is etched to simultaneously form the first-layer transfer electrode 65 of the imaging section 51, the gate layer 24 of the NMOS 20, and the floating gate 34 of the memory element 15.
[0044]
Further, an oxide film 64 is formed on the imaging unit 51, the NMOS 20, and the memory element 15. A polycrystalline silicon film is formed on the oxide film 64, and the polycrystalline silicon film is etched to simultaneously form the second-layer transfer electrode 66 of the imaging unit 51 and the control gate 35 of the memory element 15.
[0045]
Next, N-type impurities are implanted using the gate layer 24 of the NMOS 20 and the floating gate 34 and the control gate 35 of the memory element 15 as masks, and the NMOS 20 and the P-type wells 21 and 31 of the memory element 15 have high concentration by thermal diffusion. N-type semiconductor drain regions 22 and 32 and source regions 23 and 33 are formed.
[0046]
Therefore, since the memory element 15 is formed by the same process as the NMOS 20 of the imaging unit 51 or the output unit 54, the number of steps for manufacturing the CCD solid-state imaging device does not increase. Further, since the memory element 15 can be formed simultaneously with the NMOS 20 of the imaging unit 51 or the output unit 54, the time required to manufacture the CCD solid-state imaging device does not increase as compared with the related art.
[0047]
As described above, in the present embodiment, the voltage adjusting unit 2 including the resistors 11 to 14 and the memory elements 15 to 17 is provided, and an appropriate substrate bias voltage VN is measured in advance, and the memory is set so that the measured voltage becomes the measured voltage. On / off control of the elements 15 to 17 is performed. Then, the voltage dividing ratio of the resistors 11 to 14 is adjusted based on the on / off of the memory elements 15 to 17, and the external voltage VG of a predetermined voltage applied from the outside is divided by the adjusted voltage dividing ratio to obtain a substrate bias voltage. VN was applied to the silicon substrate 61.
[0048]
As a result, the user can use the CCD solid-state imaging device only by applying the predetermined external voltage VG, so that troublesome adjustment is not required and the CCD solid-state imaging device can be used easily.
[0049]
Further, since the memory elements 15 to 17 can be formed by the same process as the imaging unit 51 or the output unit 54, it is possible to suppress an increase in the number of manufacturing steps of the CCD solid-state imaging device.
[0050]
Note that the present invention is not limited to the above-described embodiment, and may be implemented as follows.
1) The voltage adjusting unit 2 of the above embodiment may be any unit that generates a desired substrate bias voltage VN from an external voltage VG from a predetermined voltage. For example, as shown in FIG. 5, a resistor 40 and a memory element 15 are connected in series to the external input terminal 10, and a silicon substrate 61 is connected between the resistor 40 and the memory element 15. The resistance value between the source and the drain of the memory element 15 changes according to the amount of electric charge stored in the floating gate 34. Therefore, the external input terminal 10Entered inThe external voltage VG is divided by the resistor 41 and the memory element 15, and the divided voltage is applied to the silicon substrate 61 as the substrate bias voltage VN.
[0051]
The memory element 15 injects charges into the floating gate 34 while checking the resistance value between the source and the drain. The charge injection may be stopped when the resistance value between the source and the drain of the memory element 15 becomes a resistance value that becomes a voltage division ratio that can generate the optimum substrate bias voltage VN. . With this configuration, the structure of the voltage adjustment unit 2 is simplified.
[0052]
2) The present invention is embodied in an interline transfer CCD solid-state imaging device.
3) The number of resistors 11 to 14 in the above embodiment is appropriately changed. At this time, it goes without saying that the number of memory elements is changed according to the number of changed resistors.
[0053]
4) In the above embodiment, the voltage adjuster 2 adjusts the substrate bias voltage VN applied to the silicon substrate 61. However, the voltage adjuster 2 adjusts another voltage that needs to be adjusted.
[0054]
For example, the voltage of an output control gate for controlling the transfer of electric charges from the horizontal transfer unit 53 to the output unit 54, the gain control voltage of a source follower circuit provided in the output unit 54, and the like can be increased.
[0055]
5) In addition to the CCD solid-state imaging device, the present invention is embodied as a CCD-based device such as a CCD delay device. For example, a CCD delay element can be used as control means for adjusting the operating point, adjusting the output gain, and changing the setting of the delay amount. In an autofocus sensor in which a plurality of independent line sensors are provided on one substrate, it can be employed as a means for correcting variations in characteristics among the line sensors.
[0056]
6) The floating gate 34 may be formed in the same layer as the transfer electrode 65, and the control gate 35 may be formed in the same layer as the power supply wiring arranged on the transfer electrode 65. In this case, when the power supply wiring is formed of a metal such as aluminum, the control gate 35 is also formed of the same metal, but there is no problem in the operation of the memory element 15. If the control gate 35 is formed in the same layer as the wiring on the transfer electrode 65 in this manner, the memory element 15 can be formed even when the transfer electrodes 65 and 66 have a single-layer structure.
[0057]
While the embodiments of the present invention have been described above, technical ideas other than the claims that can be grasped from the above embodiments will be described below together with their effects.
3. The charge-coupled device according to claim 1, wherein the voltage adjuster has a floating gate and has a resistance value according to an amount of charge stored in the floating gate. 4. It comprises an element 15 and a resistor 40 connected in series to the memory element 15 and dividing the external voltage VG input from the external input terminal 10. With this configuration, the configuration of the voltage adjustment unit can be simplified.
[0058]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide an electric coupling element which can be easily manufactured and can save the trouble of adjustment by a user. Further, a manufacturing method capable of easily manufacturing such a charge-coupled device can be provided.
[Brief description of the drawings]
FIG. 1 is a plan view of a CCD solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a voltage adjusting unit according to one embodiment.
3A is a partial cross-sectional view of an imaging unit, FIG. 3B is a cross-sectional view of an N-channel MOS transistor of an output unit, and FIG. 3C is a cross-sectional view of a memory element.
FIG. 4 is a conceptual diagram in a case where a memory element is controlled to be turned off.
FIG. 5 is a circuit diagram of another voltage adjusting unit.
FIG. 6 is a schematic plan view of a conventional frame transfer type CCD solid-state imaging device.
FIG. 7 is a partial cross-sectional view of the imaging unit.
FIG. 8 is a diagram illustrating a potential state of an imaging unit.
[Explanation of symbols]
2 Voltage regulator
10 External input terminal
12-14,40 resistance
15 Non-volatile memory device
34 Floating gate
35 Control gate
61 Semiconductor substrate
65,66 transfer electrode
VG external voltage

Claims (6)

In a charge-coupled device in which a plurality of transfer electrodes (65) are arranged on a semiconductor substrate (61),
An external input terminal (10) to which an external voltage (VG) of a predetermined voltage is input ;
A nonvolatile memory element (15) disposed on the semiconductor substrate (61) alongside the transfer electrode (65) and having a floating gate (34) formed in the same layer as the transfer electrode (65); ,
The external voltage input to the external input terminal (10) in accordance with the amount of charge accumulated in the floating gate (34) of memory elements (15) (VG), adjusted to a voltage less than the external voltage value was adjusted A charge coupled device comprising: a voltage adjusting unit (2) for outputting a voltage. The memory element (15) includes a floating gate (34) formed on the same layer as a lower layer of the transfer electrode (65, 66) having a two-layer structure and a control gate (34) formed on the same layer as an upper layer. 35. The charge-coupled device according to claim 1, comprising: The memory element (15) includes a floating gate (34) formed on the same layer as the transfer electrode (65) and a control gate formed on the same layer as a wiring for supplying power to the transfer electrode (65). The charge-coupled device according to claim 1, comprising (35). The voltage adjuster (2) includes a plurality of serially connected resistors (12 to 14) to which an external voltage (VG) input to the external input terminal (10) is applied, and a resistor (12 to 14) . is connected to the connection point, configuration out with the memory device (15-17) for selectively grounding a connection point of the resistor its floating gate (34) by the charges accumulated are on / off control (12 to 14) The charge-coupled device according to claim 1, wherein: A memory element (15) having a charge transfer portion having first and second transfer electrodes (65, 66) having a two-layer structure, and a floating gate (34) and a control gate (35) at least partially overlapping each other. ) Is a method for manufacturing a charge-coupled device disposed on the same semiconductor substrate (61),
A first step of forming a floating gate (34) of the memory element (15) simultaneously with a first transfer electrode (65) of the charge transfer section;
Forming a control gate (35) of the memory element (15) simultaneously with the second transfer electrode (66) of the charge transfer section. A charge transfer unit having a transfer electrode (65 , 66 ) and a power supply wiring disposed on the transfer electrode (65 , 66 ); a floating gate (34) and a control gate ( 35. A method of manufacturing a charge-coupled device, wherein the memory device (15) having the component (35) is disposed on the same semiconductor substrate (61).
A first step of forming a floating gate (34) of the transfer electrodes of the charge transfer section (65, 66) simultaneously with said memory device (15),
Forming a control gate (35) of the memory element (15) simultaneously with the power supply wiring .

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