JP3581217B2 - Register circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a master-slave type register circuit. In particular, the present invention relates to clock signal stop control for saving power by stopping a slave clock signal when there is no clock input such as a master clock signal.
[0002]
[Prior art]
2. Description of the Related Art In recent years, the development of portable electronic devices driven by batteries, such as cellular phones, has been active.
Many of these portable electronic devices are equipped with a DSP (Digital Signal Processor), a semiconductor memory, and the like. The DSP has a large number of registers for temporarily holding data because of the pipeline processing, and also has a large number of registers for each multiplier and adder as an accumulator. In a semiconductor memory, many registers are used to temporarily hold data in a data input / output unit.
[0003]
In many cases, the configuration of this register is controlled by a plurality of clock signals to take in and transfer data, as represented by a so-called master-slave shift register.
For example, in a master / slave type shift register built in a DSP that performs voice signal compression or the like of a cellular telephone, the register circuit includes a plurality of master clock signals for taking in data and a master unit in the shift register. It is controlled by a slave clock signal or a test clock signal for data transfer between the slave and the slave unit and data transfer between the registers.
[0004]
In view of the fact that many such register circuits are incorporated in a portable electronic device driven by a battery, how to reduce power consumption is an important issue to be addressed.
[0005]
[Problems to be solved by the invention]
In this conventional register circuit, the master clock signal is controlled by a control circuit so as to generate a clock pulse only when data is taken in. Similarly, the test clock signal is output only when performing an internal test, emulation, or the like.
[0006]
On the other hand, the slave clock signal is often not controlled to stop, and the register circuit in this case always receives clock pulses even when it is not necessary. Had.
Conventionally, a clock enable signal has been generated, and the stop control of the slave clock signal has been possible by using the clock enable signal. For example, in a case where registers of the same kind are arranged in a large scale and are controlled by the same clock signal, a control is also performed in which a slave clock signal is gated by a clock enable signal and stopped when not necessary. Was.
[0007]
Except for the special case where the effect of reducing the power consumption is large, generating the clock enable signal only for the control of stopping the clock imposes too much a circuit burden. There has been a strong demand for a clock stop control circuit having a simple configuration used.
[0008]
The present invention has been made in view of such circumstances, and does not need to generate a clock enable signal or the like, and can be easily implemented by incorporating a simple circuit that operates using an existing signal input to a register unit. It is an object of the present invention to provide a register circuit capable of controlling clock stop.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problems of the related art and achieve the above object, the register circuit of the present invention uses only a clock signal used for a master-slave type register including the first and second register units. Stop control of the slave clock signal (second clock signal) is performed.
[0010]
A register circuit according to the present invention includes a clock input detection unit that inputs a first clock signal and outputs a detection signal, a second clock signal and the detection signal, and based on a logical value of the detection signal. The second clock signal is output when the first clock signal is supplied to the clock input detection unit, and the second clock signal is output when the first clock signal is not supplied to the clock input detection unit. A clock output control unit for stopping the output of the first clock signal, a first register unit for receiving and holding data from outside in response to the first clock signal, and a second clock signal output from the clock output control unit And a second register unit for receiving and holding the output of the first register unit in response to the
[0011]
Further, the clock input detecting section includes first and second inverters connected in opposite directions between a first node and a second node, a first power supply potential and the first node, And a second transistor and a third transistor connected in series between a second power supply potential and the first node. The clock output control unit includes: , A logic circuit for receiving a detection signal and a second clock signal, and outputting a second clock signal in accordance with a logic value of the detection signal, wherein the first clock signal is output in response to the first clock signal. When the transistor is turned on, a detection signal is generated at the second node, and in response to a second clock signal output from the logic circuit, the second transistor is turned on and the second signal input to the logic circuit is input. Responds to 2 clock signals The second node is reset by the third transistor conducts Te.
[0012]
Further, the clock input detection unit includes first and second inverters connected in opposite directions between a first node and a second node, a first power supply potential and the first node. And a second transistor and a third transistor connected in series between the first power supply potential and the second node. The unit has a logic circuit that receives a detection signal and a second clock signal and outputs a second clock signal in accordance with a logic value of the detection signal, and the logic circuit responds to the first clock signal. The detection signal is generated at the second node when the one transistor is turned on, and the second transistor is turned on and input to the logic circuit in response to the second clock signal output from the logic circuit. Second clock signal In response the third transistor is the second node is reset by conduction.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a register circuit according to the present invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram of a register circuit according to the present invention.
The register circuit 2 has a master-slave type register unit 4. A first clock signal for instructing the register unit 4 to take in data is provided to a clock input side of the register unit 4, When the unit 4 is a shift register, a clock control circuit 6 that controls whether or not to output a second clock signal to the register side by using a third clock signal that instructs a shift operation is provided.
[0014]
The clock control circuit 6 includes a clock input detection unit 8 that outputs a detection signal S1 in response to input of a first clock signal (or a third clock signal), and a clock input detection unit 8 based on the input detection signal S1. A clock output control unit for outputting the second clock signal to the register unit only when the first clock signal (or the third clock signal) is being input;
[0015]
【Example】
Hereinafter, a more specific embodiment of the present invention will be described, taking as an example a case where a master-slave type shift register having a two-input configuration is used as the register unit 4.
First Embodiment FIG. 2 shows a schematic configuration diagram of a two-input master-slave type shift register that can be used as the register section 4 of the present invention.
[0016]
In this shift register 4, as shown in FIG. 2, flip-flop circuits FF (1), FF (2),..., FF (i) having a 2-input / 1-output configuration so as to be used as a normal parallel register. ,..., FF (n) are arranged in parallel in a number corresponding to the number n of data bits.
[0017]
Each flip-flop circuit FF (i) is composed of an input-side master unit M that holds data and a slave unit S on the output side. Each flip-flop circuit FF (i) has input terminals D1 and D2 to which first data d1 (i) and second data d2 (i) can be inputted, respectively, and data d1 (i) and d2. An output terminal Q for outputting any one of (i), a scan input terminal SCin and a scan output terminal SCout for connecting each flip-flop circuit FF (i) in series are provided.
[0018]
Input connection MOS transistors TRin are connected to connection paths between the input terminals D1 and D2 and the master unit M, respectively. The first master clock signal mCLK1 and the second master clock signal mCLK2 are input to the gates of the input selection MOS transistors TRin, respectively, and the MOS transistors TRin are turned on or off by these master clock signals. , And the data fetch control is performed.
[0019]
The scan input terminal SCin is connected to the master unit M, and a MOS transistor TRout is connected to the connection path. The test clock signal tCLK is input to the gate of the MOS transistor TRout, and the MOS transistor TRout is switched between a conductive state and a non-conductive state by the test clock signal tCLK.
[0020]
A MOS transistor TRtrn for data transfer is connected to a connection path between the master unit M and the slave unit S. Slave clock signal sCLK is input to the gate of data transfer MOS transistor TRtrn, and MOS transistor TRtrn is switched between a conductive state and a non-conductive state by this slave clock signal sCLK. Data transfer is controlled.
[0021]
On the other hand, in each flip-flop circuit FF (i), its scan output terminal SCout is connected to the scan input terminal SCin on the bit side of the next stage, thereby enabling a shift operation of data as a purpose of the shift register. ing. This data shift operation can be performed by a combination of the test clock signal tCLK and the slave clock signal sCLK. This makes it possible to convert parallel data into serial data, or scan data between states inside the device when performing an internal inspection or emulation.
[0022]
FIG. 3 is a circuit diagram of a slave control circuit that performs stop control of the slave clock signal sCLK as the clock control circuit according to the first embodiment. FIG. 4 is a timing chart for explaining the operation of the slave control circuit of FIG.
The slave control circuit 6 has a latch circuit composed of a first inverter INV1 and a second inverter INV2. Three nMOS transistors TR1, TR2, TR3 are connected in parallel between nodes ND1 and GND on the input side of this latch circuit, and their gates have a clock signal common to the shift register 4, that is, The first master clock signal mCLK1, the second master clock signal mCLK2, and the test clock signal tCLK are input.
[0023]
The output node ND2 of the latch circuit is connected to one input of an AND circuit 12, and the other input of the AND circuit 12 is supplied with a slave clock signal sCLK. Therefore, the slave clock signal sCLK is output to the output of the AND circuit 12 only when the output of the latch circuit is at a high level.
[0024]
Further, between the input node ND1 of the latch circuit and the power supply voltage supply line VDD, two pMOS transistors TR4 and TR5 are connected in series as a reset unit. The gate of the pMOS transistor TR4 receives the slave clock signal sCLK, and the gate of the pMOS transistor TR5 receives a signal obtained by inverting the output of the AND circuit 12 by the inverter INV3.
[0025]
Next, the operation of the thus-configured slave control circuit 6 will be described with reference to the timing chart of FIG.
Here, a case where the first master clock signal mCLK1 is input as the first clock signal to the slave control circuit 6 of the illustrated example will be described. At the rise of the first master clock signal mCLK1, the slave control circuit 6 in the illustrated example shifts the output of the latch circuit to a high level, outputs the slave clock signal sCLK to the shift register 4, and outputs the slave clock signal sCLK. At the falling edge, the latch circuit is reset (the output of the latch circuit is set to low level), and the supply of the slave clock signal sCLK to the shift register 4 is stopped.
[0026]
Hereinafter, the operation of the slave control circuit 6 will be described in detail.
As shown in FIG. 4, the slave clock signal sCLK is input to the slave control circuit 6 as a pulse train having a constant period. Further, the first master clock signal mCLK1 is input to the slave control circuit 6 with a slight delay in phase from the slave clock signal sCLK. The master clock signal mCLK1 is a clock signal having a pulse train only while the data d1 (i) is taken into the shift register 4 in FIG. 2 under the control of, for example, a CPU or the like. The reason why the phase of the first master clock signal mCLK1 is slightly delayed from that of the slave clock signal sCLK is that a delay margin dm for reliably performing the reset operation of the latch circuit is provided in consideration of the delay of the logic circuit. .
[0027]
First, at the first rise of the first master clock signal mCLK1, the input gate nMOS transistor TR1 transitions to the conductive state, and the input node ND1 of the latch circuit is dropped to the GND level. Further, the node ND2 on the output side of the latch circuit shifts to the high level by the first inverter INV1. The state of the node ND2 is maintained by the second inverter INV2 even after the first pulse of the first master clock signal mCLK1 falls. The high level of the output node ND2 corresponds to the output state of the detection signal s1 in FIG.
[0028]
With the transition of the node ND2 to the high level, the slave clock signal sCLK appears at the node ND3 on the output side of the AND circuit 12, and is output to the shift register 4 described above.
When the slave clock signal sCLK attains a high level at the node ND3 on the output side of the AND circuit 12, this is inverted by the inverter INV3 and the transistor TR5 transitions to the conductive state.
[0029]
Next, when the slave clock signal sCLK shifts to the low level, one of the pMOS transistors TR4 of the reset unit shifts to the conductive state. Further, since the output node ND3 of the AND circuit 12 shifts to the low level, the other pMOS transistor TR5 of the reset unit shifts to the non-conductive state with a delay of the delay time of the AND circuit 12 and the inverter INV3.
[0030]
After the pMOS transistor TR4 changes to the conductive state, the latch circuit is reset within a short time when the pMOS transistor TR5 changes to the non-conductive state. That is, within this short time, the node ND1 is connected to the power supply voltage supply line VDD via the pMOS transistors TR4 and TR5, and the node ND1 shifts from the GND level to the high level. Then, the nodes ND2 shift from the high level to the GND level and are held by the inverters INV1 and INV2.
[0031]
In the case of FIG. 4, the second pulse of the first master clock signal mCLK1 is input immediately after the node ND2 is dropped to the GND level, so that the node ND1 is again brought to the GND level as described above. , And the node ND2 shifts to a high level, so that the second pulse of the slave clock signal sCLK is output from the AND circuit 12 without any trouble.
[0032]
Then, as described above, the latch circuit is reset at the falling edge of the second pulse of the slave clock signal sCLK. Thereafter, as shown in the figure, if the first master clock signal mCLK1 is not continuously input, the node ND2 remains at the GND level and even if the third pulse of the slave clock signal sCLK is input, the AND pulse is output to the AND circuit. 12 is not output. That is, the output of the slave clock signal sCLK is stopped in synchronization with the first master clock signal mCLK1.
[0033]
When the pulse of the first master clock signal mCLK1 is input again, the slave clock signal sCLK is output from the AND circuit 12 to the shift register 4 side.
Second embodiment This embodiment is a case where a transistor for performing a reset operation quickly is added to the second inverter INV2 of the first embodiment.
[0034]
FIG. 5 is a circuit diagram of the slave control circuit according to the second embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and the description of the operation will be omitted.
Although not shown in the first embodiment, the second inverter INV2 has a pMOS transistor TR6 and an nMOS transistor TR7 having a common input shown in FIG. Are connected in series, and the output of the inverter INV2 is obtained from the connection path between the two.
[0035]
On the other hand, as shown in FIG. 5, in the second inverter INV2 of the present embodiment, the slave clock signal sCLK is input to the gate between the nMOS transistor TR7 and GND in order to quickly perform a reset operation. NMOS transistor TR8 is connected.
[0036]
In the latch circuit holding the node ND1 at the GND level and the node ND2 at the high level, the nMOS transistor TR7 constituting the second inverter is in a conductive state. Then, the reset of the latch circuit causes the nMOS transistor TR7 to transition from the conductive state to the non-conductive state. Further, as described above, when resetting is performed, within a short time when one of the resetting pMOS transistors TR4 transitions to the conducting state and then the other pMOS transistor TR5 transitions to the non-conducting state, Node ND1 is connected to power supply voltage supply line VDD via pMOS transistors TR4 and TR5.
[0037]
In order to perform the reset operation promptly, it is necessary to quickly transition the node ND1 to the high level. However, because of the signal delay due to the first inverter INV1 and the wiring, there is a time difference from the transition of the pMOS transistors TR4 and TR5 to the conducting state to the inversion of the inverter INV1 and the transition of the nMOS transistor TR7 to the non-conducting state. During a period from the transition of the pMOS transistors TR4 and TR5 to the conducting state until the transition of the nMOS transistor TR7 to the non-conducting state, the power supply voltage supply line VDD is connected to GND via the pMOS transistors TR4 and TR5 and the nMOS transistor TR7. Through current flows. Therefore, the reset operation is delayed by that much. In addition, it is necessary to prevent such a through current from the viewpoint of reducing power consumption.
[0038]
In the present embodiment, the nMOS transistor TR8 transitions from the conductive state to the non-conductive state at substantially the same time as the falling of the pulse of the slave clock signal, that is, the start of resetting. Is done. Thus, the reset operation can be performed quickly, and the power consumption can be reduced.
[0039]
In the second inverter INV2 in FIG. 5, a pMOS transistor TR9 having a gate to which a test clock signal tCLK is input is connected between the pMOS transistor TR6 and the power supply voltage supply line VDD. When INV2 outputs a high level, it conducts and is used as a resistor, and may be replaced with a normal resistor or omitted.
[0040]
Third Embodiment While the resetting of the latch circuit is performed on the node ND1 side in the above-described first embodiment, this resetting is performed on the node ND2 side.
FIG. 6 is a circuit diagram of a slave control circuit according to the third embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and the description of the operation will be omitted.
[0041]
In the slave control circuit 6, the reset MOS transistors TR4 and TR5 are both n-channel type, and these are connected in series between a node ND2 on the output side of the latch circuit and GND.
Accordingly, a signal obtained by inverting the slave clock signal sCLK by the inverter INV4 is input to the gate of the nMOS transistor TR4, and a signal having the same logic as the output of the AND circuit 12 via the buffer 14 is input to the gate of the nMOS transistor TR5. Is entered.
[0042]
The operation of the slave control circuit 6 having such a configuration is the same as that of the first embodiment on the timing chart of FIG. 4, but the latch circuit is reset on the output side instead of the input side. This is different from the first embodiment described.
That is, in a state where the node ND1 on the input side of the latch circuit is held at the GND level and the node ND2 on the output side is held at the high level, the pulse of the slave clock signal sCLK is output from the AND circuit 12, and the node ND3 goes high. When the transition is made, one of the nMOS transistors TR5 of the reset unit transitions to the conductive state. Next, when the pulse of the slave clock signal sCLK falls, the other nMOS transistor TR4 of the reset unit transitions to the conducting state, and with a slight delay, the one nMOS transistor TR5 transitions to the non-conducting state. During this time, the node ND2 is forcibly lowered to the GND level, whereby the node ND1 shifts from the GND level to the high level, and the reset operation ends.
[0043]
【The invention's effect】
As described above, according to the register circuit of the present invention, in synchronization with the first clock signal (for example, master clock signals mCLK1 and mCLK2) and the third clock signal (for example, test clock signal tCLK). , The output of the second clock signal (for example, a slave clock signal or the like) to the register section can be controlled. Accordingly, when the first clock signal and the third clock signal used for the register portion are not being output, the second clock signal is also stopped to save power.
[0044]
Further, in the stop control of the second clock signal, since only the signal common to the register unit is used, it is not necessary to newly prepare a signal for stop control such as a conventional clock enable signal.
In order to perform the stop control of the second clock signal, a clock input detection unit and a clock output control unit, which are configured by the simple circuits exemplified in the first to third embodiments, are provided on the clock input side of the register unit. You only need to add them.
[0045]
As described above, according to the present invention, there is no need to generate a clock enable signal or the like, and the stop of the clock can be easily controlled by incorporating a simple circuit that operates using an existing signal common to the register section. A register circuit can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a register circuit of the present invention.
FIG. 2 is a schematic configuration diagram of a two-input master / slave type shift register that can be used as a register unit according to the first to third embodiments of the present invention.
FIG. 3 is a circuit diagram of a slave control circuit that performs stop control of a slave clock signal as a clock control circuit according to the first embodiment of the present invention.
FIG. 4 is a timing chart of the slave control circuit according to the first to third embodiments of the present invention.
FIG. 5 is a circuit diagram of a slave control circuit according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram of a slave control circuit according to a third embodiment of the present invention.
[Explanation of symbols]
2. Register circuit,
4: shift register,
6. Clock control circuit,
8. Clock input detection unit
10. Clock output control unit
12 ... AND circuit,
14 ... buffer,
INV1 a first inverter,
INV2: second inverter,
TR4, TR5, INV2 (INV4 and 14) ... reset unit,
TR6 ... pMOS transistor,
TR7: nMOS transistor,
TR8: nMOS transistor for promptly performing a reset operation;
TRin: MOS transistor for input selection,
TRtrn: MOS transistor for data transfer,
TRout: MOS transistor for selecting an output format,
M: Master part,
S: Slave part,
S1 ... detection signal,
mCLK1, mCLK2 ... master clock signal,
sCLK: slave clock signal,
tCLK: Test clock signal.

Claims (3)

A clock input detection unit that inputs a first clock signal and outputs a detection signal;
Receiving a second clock signal and the detection signal, outputting the second clock signal when the first clock signal is supplied to the clock input detection unit based on a logical value of the detection signal; A clock output control unit that stops outputting the second clock signal when the first clock signal is not supplied to the clock input detection unit;
A first register unit that receives and holds data from outside in response to the first clock signal;
A second register unit that receives and holds an output of the first register unit in response to a second clock signal output from the clock output control unit;
A register circuit having: The clock input detector includes a first and a second inverter connected in opposite directions between a first node and a second node; and a first inverter connected between a first power supply potential and the first node. And a second transistor and a third transistor connected in series between a second power supply potential and the first node.
The clock output control unit has a logic circuit that receives the detection signal and the second clock signal, and outputs a second clock signal according to a logic value of the detection signal.
The detection signal is generated at the second node by the conduction of the first transistor in response to the first clock signal, and the second transistor is responsive to the second clock signal output from the logic circuit. The second transistor is turned on, and the second node is reset by turning on the third transistor in response to a second clock signal input to the logic circuit;
The register circuit according to claim 1. The clock input detector includes a first and a second inverter connected in opposite directions between a first node and a second node; and a first inverter connected between a first power supply potential and the first node. And a second transistor and a third transistor connected in series between the first power supply potential and the second node.
The clock output control unit has a logic circuit that receives the detection signal and the second clock signal, and outputs a second clock signal according to a logic value of the detection signal.
The detection signal is generated at the second node by the conduction of the first transistor in response to the first clock signal, and the second transistor is responsive to the second clock signal output from the logic circuit. The second transistor is turned on, and the second node is reset by turning on the third transistor in response to a second clock signal input to the logic circuit;
The register circuit according to claim 1.

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