JP3578497B2 - Zigzag scan circuit - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a zigzag scan circuit for converting a data order, and is particularly suitable for application to an image encoding / decoding device.
[0002]
[Prior art]
If the same amount of transmission is to be transmitted when the image signal is encoded and transmitted, it is better to make the amount of information of the low-frequency component larger than the amount of information of the high-frequency component, so that a reproduced image that matches human visual characteristics better. Is obtained. In other words, if the compression ratio is to be increased, a reproduced image that is more consistent with human visual characteristics can be obtained by compressing the high-frequency component more. An image coding method has been proposed in view of such a viewpoint. In such an image coding method, a zigzag scan for rearranging quantized data of an image in accordance with horizontal and vertical frequency components is proposed. Has been applied.
[0003]
The zigzag scan used in the image compression / decompression algorithm according to such an image coding method has a hardware configuration, as shown in FIG. 2, which includes a quantization / inverse quantization circuit 1 and a Huffman code. This is a process executed by the zigzag scanning circuit 2 existing between the decoding / decoding circuit 3 and, for example, when 64 pieces of data are temporarily arranged in a square shape as shown in FIG. 3B and a zigzag scan data order which reciprocates in an oblique direction as shown in FIG. 3C.
[0004]
At the time of image compression, the DCT (discrete cosine transform) coefficient quantized by the quantization / inverse quantization circuit 1 is input to the zigzag scan circuit 2 via the data line 101, and the data order is determined by the zigzag scan circuit 2. The data is converted into a zigzag scan form shown in FIG. 3C, input to the Huffman encoding / decoding circuit 3 via the data line 102, and is subjected to variable-length encoding.
[0005]
Conversely, at the time of image decompression, data decoded into DCT coefficients by the Huffman encoding / decoding circuit 3 is input to the zigzag scan circuit 2 via the data line 102, and the zigzag scan circuit 2 performs the zigzag order. The original data is inversely transformed as shown in FIG. 3B and input to the quantization / inverse quantization circuit 1 via the data line 101.
[0006]
FIG. 4 shows an example of a configuration that can be considered when the zigzag scan circuit 2 is simply hardware.
[0007]
In FIG. 4, the data order of 64 words (one word is 11 bits) is converted through writing and reading of the RAM 20, and the order of change of the write address and the read address is different due to the conversion.
[0008]
Hereinafter, the operation at the time of image compression of the zigzag scan circuit 2 shown in FIG. 4, that is, the operation of converting the data order shown in FIG. 3B into the data order shown in FIG. The description focuses on the changes.
[0009]
The counter 22 has 6 bits, and sequentially outputs addresses 0 to 63 to the address conversion ROM 21 and the selector 23 in 64 cycles. When writing the input data 201 to the RAM 20, the selector 23 is in a state of selecting the output address 203 of the counter 22, and the selected address 205 is given to the RAM 20. Thus, the RAM 20 is given the write address shown in FIG. 3D, which changes from 0, 1, 2, 3,..., 63, and the input data 201 is stored in each address area. The address conversion ROM 21 converts the address 203, which changes from 0 to 63 from the counter 22 in increments of one, into an address 204 which changes in a zigzag scan form (0, 1, 8, 16,..., 64) shown in FIG. Is converted to When reading the output data 202 from the RAM 20, the selector 23 is in a state of selecting the output address 204 of the ROM 21, and the selected address 205 is given to the RAM 20. Thus, the read address shown in FIG. 3D, which changes to 0, 1, 8, 16,..., 64, is given to the RAM 20, and data 202 is output from each address area.
[0010]
On the other hand, when the input data 201 is sequentially written into the RAM 20 at the time of image expansion, the address 204 from the address conversion ROM 21 is selected as a write address as shown in FIG. When outputting, as shown in FIG. 3E, the address 203 from the counter 22 is selected as the read address, and the zigzag scan data 201 is converted into the original raster scan data 202.
[0011]
[Problems to be solved by the invention]
However, the zigzag scan circuit 2 shown in FIG. 4 has the following problem because one address for data order conversion is generated using the ROM 21.
[0012]
When the clock synchronous type ROM 21 is used, a cycle for inputting an address to the ROM 21 and reading data (conversion address) and a cycle for providing the read conversion address to the RAM 20 are required, and one data is required. Requires two cycles to access the RAM 20 and the processing speed is reduced. To avoid this, it is necessary to operate the ROM 21 in a pipelined manner, but the configuration becomes complicated because a selector register and the like are required. Note that the asynchronous ROM 21 consumes a large amount of power and has a lower processing speed than the clock synchronous type.
[0013]
The ROM 21 occupies a larger area than other integrated circuits, and is not suitable for miniaturizing a zigzag scan circuit. Even if the ROM 21 is formed in the same integrated circuit chip as the RAM 20, the large occupied area limits the area for other components.
[0014]
For this reason, a zigzag scan circuit that can convert the data order at high speed and a zigzag scan circuit that can contribute to miniaturization are desired.
[0015]
[Means for Solving the Problems]
To solve such issues,BookThe invention provides a RAM for temporarily storing input data,When writing the input data to the RAMWrite address to give andProvided when reading stored data from the RAMAn address generation circuit for generating a read address.TajiZag scan circuitWherein the address generation circuit is constituted by the following components.
[0016]
That is,The address generation circuit (1) A state transition register that stores state transition parameters used to generate an address for zigzag scanning; (2) An address register configured by an upper bit indicating a Y address and a lower bit indicating an X address, and temporarily storing an address output to the RAM; (3) An incrementer for increasing the address output from the address register by one, (Four) A zigzag address operation circuit that generates an address for zigzag scanning using the state transition parameter; (Five) The address output from the incrementer is selected when the input data is written to the RAM at the time of image compression or when the storage data is read from the RAM at the time of image expansion, and the storage data is read from the RAM at the time of image compression. And a selection circuit for selecting the address output from the zigzag operation circuit when the input data is written to the RAM when reading out or when decompressing an image.It is characterized by the following.
[0019]
[Action]
TheThe address change in the zigzag scan form is one of several types of states when attention is paid to the change state of two consecutive addresses. Therefore, when the current address and the state transition are determined, the next address and the next state transition can be determined.
[0020]
In the present invention, the transition state of the address isThe specified state transition parameters are held in the state transition register, and the zigzag address arithmetic circuitShapeAn address for zigzag scanning is generated using the state transition parameter. Further, an address for raster scanning is generated by the address register and the incrementer. AndThe selection circuit selects an address output from the incrementer when input data is written to the RAM at the time of image compression or reads out stored data from the RAM at the time of image expansion, and reads out the stored data from the RAM at the time of image compression. Alternatively, the address output from the zigzag operation circuit is selected when the input data is written to the RAM at the time of image expansion.
[0021]
The zigzag address operation circuit processes the current address consisting of bit data and the state transition parameter, so that it can be constituted by logic gates. As a result, high-speed processing can be performed and the zigzag scan circuit can be downsized as a whole.
[0024]
In addition,In the present invention,By providing two (or three or more) RAMs and performing a symmetric operation (or a switching operation), processing can be performed at a higher speed.
[0025]
【Example】
(A) First embodiment
Hereinafter, a first embodiment of a zigzag scan circuit according to the present invention will be described in detail with reference to the drawings. FIG. 1 shows the configuration of the zigzag scan circuit 2-1 of the first embodiment, and the same or corresponding parts as those in FIG. 4 described above are denoted by the same reference numerals.
[0026]
In FIG. 1, the zigzag scan circuit 2-1 of the first embodiment also includes a RAM 20 and an address generation circuit 24, and the input data 201 is stored in the RAM 20 based on the write address 205 generated by the address generation circuit 24. The order of 64-word data (1 word is 11 bits) is converted by reading the stored data 202 from the RAM 20 on the basis of the read address 205 generated by the write and then by the address generation circuit 24.
[0027]
However, the detailed configuration of the address generation circuit 24 is different from that of the zigzag scan circuit 2 shown in FIG. The RAM 20 is the same. The RAM 20 is provided with a write data terminal WD, a read data terminal RD, and an address terminal A shown in FIG. It naturally has input / output terminals.
[0028]
The address generating circuit 24 of the first embodiment, for example, is entirely composed of one chip, and includes an address register 25, a state transition register 26, an incrementer 27, a zigzag address operation circuit 28, and a selector 29. It is composed of
[0029]
The address register 25 temporarily stores an address 205 having a 6-bit configuration to be provided to the RAM 20. The temporarily stored address 205 is provided not only to the RAM 20 but also to the incrementer 27 and the zigzag address operation circuit 28.
[0030]
The state transition register 26 temporarily stores the 4-bit state transition parameters 207 (SYU, SYD, SXU, SXD) output from the zigzag address operation circuit 28, and stores the temporarily stored state transition parameters 207 in the zigzag address. This is output to the arithmetic circuit 28.
[0031]
The incrementer 27 increments the address 205 temporarily stored in the address register 25 by one and supplies it to the selector 29.
[0032]
The zigzag address operation circuit 28 is configured by, for example, a gate array as in an example described later, and based on the address 205 from the address register 25 and the state transition parameter 207 from the state transition register 26, the address 209 and the address 209 at the next timing. The state transition parameters 208 are formed and output to the selector 209 and the state transition register 26, respectively.
[0033]
The operation principle, configuration and operation of the zigzag address operation circuit 28 will be described later in detail.
[0034]
The selector 29 selects one of the address 209 from the zigzag address arithmetic circuit 28 or the address 206 from the incrementer 27 based on an externally applied address type signal (not shown), and assigns the selected address 210 to the address. This is input to the register 25. Here, when writing the input data 201 to the RAM 20 at the time of image compression or reading out the stored data 202 from the RAM 20 at the time of image expansion, the selector 29 sets the address from the incrementer 27 based on the address type signal. When the storage data 202 is read from the RAM 20 during image compression or when the input data 201 is written into the RAM 20 during image expansion, the address 209 from the zigzag address calculation circuit 28 is selected based on the address type signal. To select.
[0035]
The zigzag scan circuit 2-1 having the above configuration operates as follows during image compression.
[0036]
When the input data 201 is written to the RAM 20 at the time of image compression, the selector 29 selects the address 206 from the incrementer 27, and the address register 25 sets the initial value to “000000” (binary notation). ) Is set. Thus, the RAM 20 is provided with the write address 205 (see FIG. 3D) that changes from 0, 1, 2, 3,..., 63 (decimal notation) in which the increment 27 is updated by one increment. Input data 201 is stored in the address area. When the input data 201 of all 64 words is stored in the RAM 20, the operation shifts to a read operation from the RAM 20.
[0037]
At the time of image compression, when reading the stored data 202 from the RAM 20, the selector 29 selects the address 209 from the zigzag address operation circuit 28, and the address register 25 sets the initial value to "000000" ( "Binary notation" is set, and "0110" (binary notation; meaning will be described later) is set in the state transition register 26 as an initial value. The zigzag address arithmetic circuit 28 includes, based on the data stored in the registers 25 and 26, a next address 209 according to a zigzag scan state, and a state transition parameter 208 that defines a state transition when transitioning from the current address to the next address. , And the read address 205 held in the address register 25 and given to the RAM 20 changes in a zigzag scan manner like 0, 1, 8, 16,..., 64 (decimal notation) ( FIG. 3D).
[0038]
Thus, the input data 201 according to the raster scan data order as shown in FIG. 3B is converted into the output data 202 according to the zigzag scan data order as shown in FIG. 3C.
[0039]
On the other hand, when sequentially writing the input data 201 into the RAM 20 at the time of image decompression, the zigzag address operation circuit 28 is formed and given to the address register 25 via the selector 29 to temporarily store 0, 1,. An address 209 that changes in a zigzag scan manner, such as 8, 16,..., 64 (decimal notation), is given to the RAM 20 as a write address 205 (see FIG. 3E). , 64 (decimal notation), which is incremented by the incrementer 27 and incremented by one, and is temporarily supplied to the address register 25 via the selector 29 and temporarily stored. An address 206 that changes in a scan manner is given to the RAM 20 as a read address 205 (see FIG. 3E).
[0040]
Thus, the input data 201 according to the zigzag scan data order as shown in FIG. 3C is converted into the output data 202 according to the raster scan data order as shown in FIG. 3B.
[0041]
Hereinafter, the operation principle, operation and configuration of the zigzag address generation circuit 28 will be described in detail.
[0042]
In the case of this embodiment, the 6-bit address 205 is classified into upper 3 bits and lower 3 bits in relation to the processing in the zigzag address operation circuit 28. At this time, addresses 000000 to 111111 (binary notation; 0 to 63 in decimal notation) are associated with each of 64 words of data input serially at the time of image compression. When the 6-bit address for each word is considered to be arranged in a raster shape, the lower three bits define the position in the horizontal direction (hereinafter referred to as the X direction) as shown in FIG. That is, three bits define the position in the vertical direction (hereinafter, referred to as X direction). Hereinafter, the lower three bits are referred to as an X address in relation to the zigzag address generation circuit 28, and the upper three bits are referred to as a Y address in relation to the zigzag address generation circuit 28.
[0043]
Further, when the address of each data is captured as a set of the X address and the Y address as shown in FIG. 5, the address change state on the zigzag scan includes four states S1 to S4 as shown in FIG. Can be classified. That is, the next address is a state S1 (shown by a solid line in the figure) where only the X address is +1 from the current address, and the next address is a state S2 (only the Y address is +1 from the current address). The next address is a state S3 (shown by a dashed line in the figure) where the X address is -1 and the Y address is +1 from the current address, and the next address is the current address from the current address. The state can be classified into a state S4 in which the X address is +1 and the Y address is -1 (shown by a two-dot chain line in the figure).
[0044]
There are various expressions of state transition parameters for distinguishing these four states S1 to S4.
[0045]
For example, a one-bit parameter indicating whether the Y address has changed (“1”) or not (“0”), and +1 or (“1”) − 1 or (“0”) when the Y address changes. A 1-bit parameter indicating whether the X address has changed (“1”) or not (“0”), and a +1 or (“1”) − 1 or (“ 0 ") and a 4-bit parameter representing a 1-bit parameter. Also, for example, a one-bit parameter SYU indicating whether the Y address has changed by +1 ("1") or not ("0") and whether or not the Y address has changed by -1 ("1") ("0") )), A 1-bit parameter SXU indicating whether the X address has changed by +1 (“1”) or not (“0”), and whether the X address has changed by −1 (“1”). ) Or 1-bit parameter SXD indicating whether or not (“0”).
[0046]
In this embodiment, the latter expression is used. It is to be noted that a circuit to which a zigzag address arithmetic circuit configured using the former expression is applied also constitutes another embodiment of the present invention.
[0047]
Therefore, as shown in FIG. 6, the state S1 is “0010” with 4-bit state transition parameters SYU, SYD, SXU, and SXD, the state S2 is “1000”, the state S3 is “1001”, and the state S4 is “0110”. ".
[0048]
These state transition parameters SYU, SYD, SXU, and SXD are temporarily stored in the state transition register 26 described above.
[0049]
Here, the state transition parameter 207 (SYU, SYD, SXU, SXD) temporarily stored in the state transition register 26 at the same time that the current address 205 is temporarily stored in the address register 25 is Storing the state transition parameters 207 (SYU, SYD, SXU, SXD) and temporarily storing the state transition parameters 207 (SYU, SYD, SXU, SXD) representing the transition from the current address 205 to the next address. However, in this embodiment, the former is adopted. Note that the latter temporary storage method also constitutes another embodiment of the present invention.
[0050]
As is clear from FIG. 6, the transitions among the four states S1 to S4 can be represented by a state transition diagram shown in FIG.
[0051]
First, consider the transition from the state S1. From the state S1, a transition can be made to the states S3 and S4 (A13, A14). The transition to the state S3 or the state S4 can be distinguished by the Y address at that time. That is, as is clear from FIG. 6, the state changes from state S1 when the Y address is "000" to state S3, and from state S1 when the Y address is "111" changes to state S4. Can be distinguished by address.
[0052]
Next, consider a transition from the state S2. A transition from the state S2 to the states S3 and S4 is possible (A23, A24). The transition to the state S3 or the state S4 can be distinguished by the X address at that time. That is, as is apparent from FIG. 6, the state transits from the state S2 when the X address is "000" to the state S4, and from the state S2 when the X address is "111" to the state S3. Can be distinguished by address.
[0053]
Next, consider the transition from the state S3. From the state S3, transition can be made to the states S1, S2 and S3 (A31, A32, A33). Which of the states S1, S2, and S3 transits can be distinguished by the X address or Y address at that time. That is, as is apparent from FIG. 6, the state transits from state S3 when the X address is "000" to state S2, transitions from state S3 when the Y address is "111" to state S1, and otherwise. Since the state S3 changes to the state S3, it can be distinguished by the X address and the Y address.
[0054]
Finally, consider the transition from state S4. A transition from the state S4 to the states S1, S2 and S4 can be made (A41, A42, A44). Which of the states S1, S2, and S4 transits can be distinguished by the X address or Y address at that time. That is, as is apparent from FIG. 6, the state changes from the state S4 when the Y address is "000" to the state S1, the state S4 when the X address is "111" changes to the state S2. Since the state S4 changes to the state S4, it can be distinguished by the X address and the Y address.
[0055]
When the next state is determined from the current address and the current state, the next address can be determined from the current address and the next state.
[0056]
As an initial value when an address is generated, the current address is naturally “000000”, and the state represented by the initial state transition parameter 207 is the state S4 (“0110”) when considered in reverse from the above transition conditions.
[0057]
FIG. 8 shows changes of the Y address, the X address, and the state transition parameters SYU, SYD, SXU, and SXD for each cycle when the above transition rules are applied. Here, since the Y address, the X address, and the state transition parameters SYU, SYD, SXU, and SXD are all bit data, the zigzag address operation circuit 28 that realizes such transition can be realized by a combination of logic gates.
[0058]
9 to 11 show one configuration example of the zigzag address operation circuit 28 realized by a combination of logic gates to which the above transition rules are applied.
[0059]
In this configuration example, a state in which there is a change in the X address appears after a state in which there is no change in the X address (from S2 to S3 or from S2 to S4), and a state in which there is no change in the Y address. Are used to form the next state transition parameters SYU, SYD, SXU, and SXD. Further, the fact that the change of the X address or the Y address is any of +1, 0, and -1 is used for forming the next address.
[0060]
FIG. 9 mainly shows a portion for creating condition values for forming the next state transition parameters SYU, SYD, SXU, SXD and the next address. The part shown in FIG. 9A is a part that takes in the address 205 from the address register 25 separately from the Y address and the X address. The part shown in FIG. 9B is a part for separately taking in the state transition parameter 207 from the state transition register 26 as a parameter in the Y direction and the X direction and forming a negative value thereof. The part shown in FIG. 9C is a part for forming a condition value indicating whether or not the Y address is “000” or “111”. The part shown in FIG. 9D is a part for forming a condition value indicating whether or not the X address is “000” or “111”. The part shown in FIG. 9E is a part for forming a condition value indicating whether or not the current state has changed in the Y direction. The part shown in FIG. 9F is a part for forming a condition value indicating whether or not the current state has changed in the X direction. The part shown in FIG. 9G is a part indicating whether or not the final address (“111111”) has been reached.
[0061]
FIG. 10 shows a portion that forms the next state transition parameter based on various condition values and outputs the same to the state transition register 26. The portions shown in FIGS. 10A, 10B, 10C, and 10D are portions forming state transition parameters SYU, SYD, SXU, and SXD of the next state, respectively.
[0062]
FIG. 11 shows a portion for forming the next address from the next state, the current address, and the like. The portions shown in FIGS. 11A and 11B are portions for forming the next X address and Y address and outputting them to the address register 25, respectively. The next X address and Y address can be formed by performing any one operation of +1, 0, and -1 on the current X address and the current Y address, respectively. 3B shows a detailed configuration example of a portion 28a for performing such an operation in b).
[0063]
As described above, according to the first embodiment, the zigzag scan is regarded as a kind of state transition, and the generation of the zigzag scan address is performed in cooperation with the zigzag address operation circuit including the logic gate, the state transition register, and the address register. Since the operation is performed by the operation, the area occupied by the zigzag scan generation circuit can be reduced, which can contribute to downsizing and can generate addresses at high speed. In the zigzag scan circuit of the first embodiment, the address generation circuit 24 is particularly suitable for a semi-custom gate array.
[0064]
In the above description, some other embodiments obtained by modifying the first embodiment have been described. However, some other embodiments obtained by modifying the first embodiment as described below can be given.
[0065]
The first embodiment is characterized by the configuration of forming a zigzag scan address, and the configuration of forming a raster scan address is not limited to that of the first embodiment. For example, a counter using a counter that increments by one with a clock may be used. It is also possible to provide a selector 29 on the output side of the address register 25 and the incrementer 27 (or counter).
[0066]
In the first embodiment, the next address is formed by separately operating the X address and the Y address. However, the entire address is operated without discriminating the X address and the Y address. Address may be formed. For example, as is apparent from FIG. 5, there are only four types of changes in the total address in each cycle, +1, +7, +8, and -7, and these changes are unique due to state transitions. May be formed.
[0067]
Further, in the first embodiment, the next state transition parameter is formed, and then the next address is formed. However, the next address may be formed in the reverse order. For example, in the case of storing a state transition parameter relating to a change state from the current address to the next address in the state transition register 26 described above as another embodiment, the processing in this order simplifies the configuration.
[0068]
Furthermore, in the first embodiment, the zigzag address operation circuit 28 is configured by dividing the address change state in the zigzag scan into four types. However, the viewpoint of distinguishing the number of states and the states is not limited thereto. Not something. For example, the above-described state S1 is divided into a state where the Y address is “000” and a state where the Y address is “111”. The state may be divided into the state where the address is "111", and a total of six types of states may be formed, and the zigzag address operation circuit 28 may be formed according to these six types of state transition.
[0069]
(B) Second embodiment
Next, a second embodiment of the zigzag scan circuit according to the present invention will be described in detail with reference to the drawings. Here, FIG. 12 shows the configuration of the zigzag scan circuit 2-2 of the second embodiment.
[0070]
In the second embodiment, two RAMs 20a and 20b having the same configuration are provided as RAMs in which data is written to convert the data order and read out thereafter. This is similar to the embodiment. These RAMs 20a and 20b operate complementarily (symmetrically) in response to a write / read control signal (not shown). That is, when the RAM 20a is writing the input data 201, the RAM 20b reads the stored data 202b, and when the RAM 20a is reading the stored data 202a, the RAM 20b writes the input data 201.
[0071]
The address generation configuration for the RAMs 20a and 20b is shared, and the address generation configuration corresponds to the counter 22, the zigzag address generation circuit 24a, and the two selectors 38 and 39.
[0072]
The counter 22 has a 6-bit configuration and generates addresses in a raster scan manner. The generated address 203 is provided to selectors 38 and 39 as a selection input.
[0073]
The zigzag address generation circuit 24a has the same internal configuration as the address generation circuit 24 of the first embodiment except that the incrementer 27 and the selector 29 are removed and the data lines 209 and 210 are directly connected (FIG. 1). reference). Accordingly, the zigzag address generation circuit 24a generates an address 205 according to a zigzag scan pattern, and this address 205 is also supplied to the selectors 38 and 39 as a selection input.
[0074]
The selector 38 selects one of the address 205 from the zigzag address generation circuit 24a and the address 203 from the counter 26 and inputs the selected address to the RAM 20a. On the other hand, the selector 39 selects one of the address 205 from the zigzag address generation circuit 24a and the address 203 from the counter 26 and inputs the selected address to the RAM 20b. Here, when one of the selectors 38 and 39 selects the address 205 from the zigzag address generation circuit 24a in response to a selection control signal (not shown), the other selects the address 203 from the counter 26. Controlled.
[0075]
The data 202a and 202b read from both RAMs 20a and 20b are both supplied to the selector 37, and the selector 37 responds to a selection control signal (not shown) so that the RAM 20a or 20b executing the read operation at that time. And outputs it as output data from the zigzag scan circuit 2-2.
[0076]
As described above, at the time of image compression and at the time of image decompression, the only difference is whether to select a raster scan or zigzag scan address as a write address and a read address, and otherwise the same. In the following, only the operation during image compression will be described with reference to FIG. FIG. 13 shows the relationship between the operation clock (omitted in FIG. 12) applied to the zigzag scan circuit 2-2 and the operation contents of the RAMs 20a and 20b.
[0077]
First, the selector 38 is switched to a state where the address 203 from the counter 22 is selected, and the address 203 that changes in a raster scan manner from the counter 22 is given to the RAM 20a, and the input data 201 of the first 64 cycles T1 is stored in the RAM 20a. Let it.
[0078]
When all writing to the RAM 20a is completed, the selector 38 is switched to a state of selecting the address 205 from the zigzag address generation circuit 24a, while the selector 39 is switched to a state of selecting the address 203 from the counter 22. The selector 37 is switched to a state of selecting the output data 202a from the RAM 22a. As a result, in the new 64 cycle T2, the 64-word data 202a stored in the previous 64 cycle T1 is read from the RAM 20a in a zigzag scan and output to the outside, and in parallel with this, 64 words are stored in the RAM 20b. Is written in a raster scan manner.
[0079]
When the 64 cycle T2 is completed, the selector 38 is switched to a state of selecting the address 203 from the counter 22, while the selector 39 is switched to a state of selecting the address 205 from the zigzag address generation circuit 24a. Switch 37 is switched to a state of selecting the output data 202b from the RAM 22b. As a result, in the new 64 cycle T3, the 64-word data 202b stored in the previous 64 cycle T2 is read out from the RAM 20b in a zigzag scan and output to the outside. In parallel with this, 64 words are stored in the RAM 20a. Is written in a raster scan manner.
[0080]
Thereafter, the above-described complementary operations for the RAMs 22a and 22b are repeated, and the input data 201 can be continuously converted into data in a zigzag scan order without waiting for the input data 201.
[0081]
Therefore, according to the second embodiment, the data order conversion RAM is used to continuously convert the data order by using two sides, and the zigzag address generation circuit is configured to consider the zigzag scan as a kind of state transition. Since this is applied, it is possible to provide a zigzag scan circuit capable of realizing a considerably high speed with a slight increase in hardware. The zigzag scan circuit of the second embodiment is suitable for a high-speed semi-custom, gate array.
[0082]
As a modified example of the second embodiment, a raster scan address is generated by an incrementer instead of the counter 22, or a 2-port RAM having an address of 7 bits or more is used as the RAMs 20a and 20b. And the like. In the latter case, it is necessary to specify the memory area that operates as the RAMs 20a and 20b with the address having the upper 7th bit or more.
[0083]
(C) Third embodiment
Next, a third embodiment of the zigzag scan circuit according to the present invention will be described in detail with reference to the drawings. Here, FIG. 14 shows the configuration of the zigzag scan circuit 2-3 of the third embodiment.
[0084]
The zigzag scan circuit 2-3 of the third embodiment includes a RAM 20-1 for temporarily storing input data 201 for data order conversion, and a counter 22 for generating a raster scan address.
[0085]
The RAM 20-1 of the third embodiment has two types of address input ports AA and BA, to which the address 203 from the counter 22 is input. Is also input.
[0086]
The inside of the RAM 20-1 includes a raster scan address decoder 30, a RAM cell array 31, a zigzag scan address decoder 32, first tristate buffer groups 33a to 33n, second tristate buffer groups 34a to 34n, and an inverter 35. It is configured.
[0087]
The RAM cell array 31 has the same internal configuration (cells, sense amplifiers, etc.) as that of a general RAM. However, the RAM cell array 31 receives a desired signal from the raster scan address decoder 30 via the first tristate buffer groups 33a to 33n. And the driving voltage can be appropriately supplied to the desired word line from the zigzag scanning address decoder 32 via the second tri-state buffer groups 34a to 34n. .
[0088]
The raster scan address decoder 30 performs the same decoding as the RAMs 20, 20a, and 20b of the first and second embodiments, and supplies a drive voltage to the word line of the RAM cell array 31 determined by the input address 203. Things. On the other hand, the zigzag scan address decoder 32 decodes the input address 203 as shown in column C3 in FIG. 15 when the decoded content of the raster scan address decoder 30 is as shown in columns C1 and C2 in FIG. A drive voltage is supplied to a word line determined by decoding the RAM cell array 31.
[0089]
When the address control signal 220 is “1”, the first tristate buffer groups 33 a to 33 n connect the raster scan address decoder 30 to the RAM cell array 31, whereas the address control signal 220 is set to “0”. ", The raster scan address decoder 30 is separated from the RAM cell array 31. The address control signal 220 is inverted and supplied to the second group of tristate buffers 33 a to 33 n via the inverter 35. Therefore, when the address control signal 220 is “0”, the second tristate buffer groups 33 a to 33 n connect the zigzag scan address decoder 32 to the RAM cell array 31, whereas the address control signal 220 When “1”, the zigzag scan address decoder 32 is disconnected from the RAM cell array 31.
[0090]
In FIG. 14, signal lines such as a control signal for instructing writing or reading and a processing configuration thereof are omitted.
[0091]
Next, an operation at the time of image compression will be described. When the input data 201 of 64 words is sequentially written to each word of the RAM 20-1 in the first 64 cycles, the address control signal 220 indicates "1" during that period. The counter 22 sequentially counts up from the initial value 0, and the address 203 sequentially changes from 0 to 63. When the raster scan address decoder 30 decodes the address 203 in a certain cycle, a drive voltage is supplied to a desired word line of the RAM cell array 31 via the first tristate buffer groups 33a to 33n, and the input in that cycle is input. Data 201 is stored. In this way, data is written into the RAM 20-1 in order from the address 0 to the address 63.
[0092]
After the 64-word data 201 is written to the RAM 20-1, the data is read out in 64 cycles. When reading and outputting the stored data 202 from the RAM 20-1, the address control signal 220 indicates "0". During this time, the drive voltage of the word line to the RAM cell array 31 is changed to the second tri-state. The data is supplied from the zigzag scan address decoder 32 via the buffer groups 34a to 34n. The address decoder 32 supplies a desired word line drive voltage in a zigzag scan form to the RAM cell array 31 as the count of the counter 22 is sequentially counted up from 0 to 63, and thereby the zigzag scan of the RAM cell array 31 is performed. The data 202 is read out in order.
[0093]
Therefore, according to the third embodiment, since the decoder for zigzag scanning is provided in the RAM 20-1, the occupied area can be reduced to contribute to downsizing, and the design can be made without the need to separately provide a gate circuit. A zigzag scan circuit capable of easy high-speed operation can be provided. The zigzag scan circuit according to the third embodiment is suitable for custom design and area-oriented design.
[0094]
As a modified example of the third embodiment, the counter 22 may be formed on the same chip as the RAM 22-1, or the counter 22 may be replaced by another address generating configuration.
[0095]
(D) Fourth embodiment
Next, a fourth embodiment of the zigzag scan circuit according to the present invention will be described in detail with reference to the drawings. FIG. 16 shows the configuration of the zigzag scan circuit 2-4 of the fourth embodiment.
[0096]
The zigzag scanning circuit 2-4 of the fourth embodiment has two surfaces of the configuration shown in the third embodiment to perform complementary operation (symmetric operation) and has a selector 37 for selecting the output data 202a and 202b. It is a thing. Therefore, the operation of each surface is the same as that of the third embodiment, and the control of the surface is the same as that of the second embodiment.
[0097]
According to the fourth embodiment, two RAMs for zigzag scanning are provided for complementary operation, so that a zigzag scanning circuit capable of performing data order conversion at a much higher speed than the conventional one is provided. Can be provided. The zigzag scan circuit of the fourth embodiment is suitable for a custom design or a design that emphasizes processing speed.
[0098]
As modified examples of the fourth embodiment, there can be cited one in which the counters 22a and 22b on two sides are shared, and one in which another address generation configuration is applied instead of the counters 22a and 22b.
[0099]
(E) Another embodiment
Although various other embodiments of the present invention have been described above, some other embodiments are as follows.
[0100]
In each of the embodiments described above, the number of words to be used for data order conversion is 64. However, the present invention can be applied to the case where the other square of the integer is the number of words. Further, the number of bits of each word is not limited to 11 bits.
[0101]
In each of the above embodiments, the input data terminal and the output data terminal are separate RAMs, but they may be RAMs having the same terminal.
[0102]
The zigzag scan circuit of the present invention can be applied not only to an image encoding / decoding device but also to an image encoding dedicated device or an image decoding exclusive device. Further, the present invention can be applied to an apparatus that requires data shuffling.
[0103]
In the second and fourth embodiments, two RAMs are provided. However, if complete symmetric operation is difficult due to timing or the like, three or more RAMs may be provided for switching. good.
[0104]
【The invention's effect】
As above,BookAccording to the invention, it is possible to provide a small zigzag scan circuit capable of high-speed processing.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment.
FIG. 2 is a block diagram illustrating a position of a zigzag scan circuit in the image encoding / decoding device.
FIG. 3 is an explanatory diagram showing a state of conversion of a data order by a zigzag scan circuit and the like.
FIG. 4 is a block diagram illustrating a possible conventional zigzag scan circuit.
FIG. 5 is an explanatory diagram of processing in which an address is divided into direction-specific addresses in the first embodiment.
FIG. 6 is an explanatory diagram of state types in the first embodiment.
FIG. 7 is a state transition diagram in the first embodiment.
FIG. 8 is an explanatory diagram showing changes in addresses and state transition parameters during zigzag scanning according to the first embodiment.
FIG. 9 is a detailed configuration diagram (part 1) of a zigzag address operation circuit of the first embodiment.
FIG. 10 is a detailed configuration diagram (part 2) of the zigzag address operation circuit of the first embodiment.
FIG. 11 is a detailed configuration diagram (part 3) of the zigzag address operation circuit of the first embodiment.
FIG. 12 is a block diagram showing a second embodiment.
FIG. 13 is an explanatory diagram of the operation of the second embodiment.
FIG. 14 is a block diagram showing a third embodiment.
FIG. 15 is an explanatory diagram of decoding contents of a decoder in a RAM according to a third embodiment.
FIG. 16 is a block diagram showing a fourth embodiment.
[Explanation of symbols]
2-1, 2-2, 2-3, 2-4... Zigzag scanning circuit, 20, 20a, 20b, 20-1, 20-1a, 20-1b... RAM, 22, 22, 22a, 22b. Address generation circuit, 24a Zigzag address generation circuit, 25 ... Address register, 26 ... State transition register, 27 ... Incrementer, 28 ... Zigzag address operation circuit, 29, 37-39 ... Selector, 30, 32 ... Address decoder, 31 RAM cell array, 33a-33n, 34a-34n Tristate buffer, 35 inverter.

Claims (2)

A RAM for temporarily storing input data, di Guzagusukyan circuit and an address generation circuit for generating a read address to be given to when reading the stored data from the write address and the RAM give when writing input data to the RAM And
The address generation circuit ,
A state transition register that stores state transition parameters used to generate an address for zigzag scanning;
An address register configured by an upper bit indicating a Y address and a lower bit indicating an X address, and temporarily storing an address output to the RAM;
An incrementer for increasing the address output from the address register by one,
A zigzag address operation circuit that generates an address for zigzag scanning and the state transition parameter using the state transition parameter and the output address of the address register;
The address output from the incrementer is selected when the input data is written to the RAM at the time of image compression or when the storage data is read from the RAM at the time of image expansion, and the storage data is read from the RAM at the time of image compression. And a selection circuit for selecting the address output from the zigzag arithmetic circuit when the input data is written to the RAM at the time of reading the image or at the time of image expansion. circuit. Two RAMs are used, two RAMs are provided for each RAM as the selection means, and output data selection means for selecting data read from the two RAMs is provided.
Two of the selection circuit symmetrically operated, when giving a raster scan-like address on one of the RAM, giving di Guzagusukyan like addresses to the other of said RAM, said RAM during a read operation 2. The zigzag scanning circuit according to claim 1, wherein the output data selecting means selects the data from the output data.

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