JP4547503B2 - Arithmetic coding apparatus, arithmetic coding method, arithmetic coding program, and computer-readable recording medium storing the program - Google Patents

Description

  The present invention relates to an arithmetic coding technique used for moving picture coding / decoding, and particularly H.264 which is a moving picture coding standard. H.264 / AVC CABAC (Context-based Adaptive Binary Arithmetic Coding) compliant arithmetic coding device, arithmetic coding method, arithmetic coding program, and computer readable program The present invention relates to a recording medium.

  In recent years, high-definition moving images such as DVD and terrestrial digital high-definition have been rapidly spreading, and the amount of information has increased dramatically due to the high bit rate and high resolution of moving images. It is essential. There are five main configuration techniques for digital moving image compression: predictive coding, motion processing, transform coding, quantization, and code allocation. Among these, code allocation efficiently allocates codes “0” and “1” to quantization levels and the like, and reduces redundant codes. For code allocation, variable length coding, adaptive coding, fixed length coding, and the like are known. Variable length coding (VLC) is divided into Huffman coding, run length coding, arithmetic coding, adaptive bit allocation, and the like. Among these, arithmetic coding is to create a coding table according to the appearance probability of a symbol and perform code allocation.

  Arithmetic coding is capable of optimal code allocation according to the characteristics of image data, and therefore has better coding efficiency than Huffman coding using a fixed coding table. However, arithmetic coding is a dynamic method that creates a coding table and assigns codes while calculating the appearance probability of symbols, so it generally requires a lot of calculation processing compared to Huffman coding. There's a problem.

  On the other hand, in ITU-T (International Telecommunication Union-Telecommunication Standardization Sector), H.264 is used as a moving image encoding / decoding technique. H.264 standards are being developed (see Non-Patent Document 1). Patent Document 1 discloses ITU-T standard H.264. An example of a specific implementation method of an arithmetic encoding / decoding process according to H.264 is disclosed. FIG. 3 is a flowchart of a process for arithmetic coding / decoding according to H.264 / AVC. This figure is shown in FIG. 9-1 is re-edited with a focus on functions. The flow of arithmetic encoding / decoding will be described below with reference to FIG.

  When encoding or decoding of a certain syntax element (SE) is started, context calculation is performed on the syntax element in step 1. In context calculation, a context number corresponding to a context is obtained, and a symbol value and a probability state are obtained from the context number. The symbol value is obtained by referring to the correspondence table with some exceptions. The probability state is obtained by referring to the value stored in step 3 described later. The obtained symbol values and probability states are given to the arithmetic encoding / decoding process, and the process proceeds to Step 2.

  In step 2, the symbol value and probability state received from step 1 are used to perform arithmetic coding or decoding of the syntax, and the result is output as an output signal. At the same time, the encoded or decoded symbol information is output to the symbol appearance probability control process, and the process proceeds to Step 3.

  In step 3, the information of the encoded or decoded symbol is received, the symbol value used in the next processing and the update value of the probability state are obtained and stored as the probability state.

  In Step 4, it is determined whether or not the encoding or decoding of the syntax element is completed. If not, the process returns to Step 1 and the same process is repeated until the encoding or decoding is completed. When the encoding or decoding of the syntax element is completed, the next syntax element is encoded or decoded.

  In FIG. 1 is a block diagram of an arithmetic coding apparatus that embodies a processing process of H.264 / AVC arithmetic coding. The arithmetic coding apparatus 700 includes an adaptive arithmetic coding / decoding unit 710, a context calculation unit 720, and an encoding / decoding control unit 730. The adaptive arithmetic coding / decoding unit 710 includes an arithmetic coding / decoding unit 711. A symbol appearance probability control unit 712 and a probability state storage unit 713. The context calculation unit 720 generates a context number from the type of the syntax element (SE) of the input signal (Sin) S11 and the number of encoded bits or the number of decoded bits (corresponding to the process of step 1 in FIG. 26). .

  In this arithmetic coding apparatus 700, each processing step needs to start the processing at the previous step in response to the processing result at the previous step. The time for which the tax element is processed is the sum of the processing steps. That is, for example, the section S0 necessary for the processing of the syntax element 0 is the sum of the time spent for the processing 51, the processing 52, the processing 53, and the processing 54, respectively.

  When the processing code amount (that is, the number of syntax elements) per coding or decoding time is large, it is an essential requirement to shorten the coding or decoding processing time. In the arithmetic encoding / decoding device 40 of the present study example, each step performs sequential processing. Therefore, in order to reduce the overall processing time, the processing time of each step must be reduced, At the current technology level, there is a limit to speeding up.

  On the other hand, Patent Document 1 discloses an arithmetic encoding device that speeds up arithmetic encoding processing. This arithmetic coding apparatus 800 includes an adaptive arithmetic coding unit 810, a context calculation unit 820, and a coding control unit 830 as shown in the block diagram of FIG. The context calculation unit 820 includes a register 821 and a comparison determination unit 822. The adaptive arithmetic coding unit 810 includes an arithmetic coding unit 811, a symbol appearance probability control unit 814, and a probability state storage unit 815. According to this, while a certain input signal is encoded by the arithmetic encoding unit 811, the context calculation unit 820 can obtain a context for the next input signal, so that the arithmetic encoding unit 811 Immediately after encoding the signal, the next input signal can be encoded. Accordingly, the encoding process can be speeded up.

Furthermore, while a certain signal is encoded by the arithmetic encoding unit 811, the symbol appearance probability control unit 814 determines whether the encoded symbol by the arithmetic encoding unit 811 is a dominant symbol or an inferior symbol. Each symbol value and the update value of the probability state are obtained, and after the encoded symbol is determined, one update value is selected. As a result, the arithmetic encoding unit 811 obtains a necessary symbol value and a probability state in the encoding of the next code, and can immediately perform the encoding process and the writing process to the probability state recording unit 815. The processing can be further speeded up.
Japanese Patent Laid-Open No. 2005-13003 Joint Video Team (JVT) of ISO / IEC MPEG &ITU-TVCEG;"DraftI TU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 | ISO / IEC 14496-10 MPEG-AVC ). " Hassan Shojania and Subramania Sudharsanan, "A VLSI Architecture for High Performance CABAC Encoding." Visual Communications and Image Processing 2005, Proc. Of SPIE Vol. 5960, pp.1444. Satoshi Okubo et al. “Revised H.264 / AVC Textbook” Impress "Patent Map by Technology Field Electricity 14 Digital Video Compression Technology" Japan Patent Office Roberto R. Osorio, Javier D. Bruguera, "High-Throughput Architecture for H.264 / AVC CABAC Compression System" IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 16, NO. 11, NOVEMBER 2006.

  However, even this method does not realize 1-bit encoding in one cycle, and is not sufficient as a measure for speeding up. On the other hand, Non-Patent Document 2 proposes a high-speed method capable of processing one binary symbol in one cycle. However, this method is not sufficient, and multiple processing is not performed in one cycle. It is hard to say that processing can be realized.

  H. In the H.264 / AVC encoding processing, variable length coding (VLC) which is entropy coding is employed. VLC is actually H.264. This is a module that generates a H.264 / AVC bitstream. There are CABAC and CAVLC as encoding methods. CAVLC (Context-Adaptive Variable Length Coding) is used only for encoding quantized DCT coefficient values. On the other hand, CABAC (Context Adaptive Binary Arithmetic Coding) is an entropy coding method using arithmetic coding, and has an advantage of higher coding efficiency than CAVLC.

  However, while CABAC processing can obtain high coding efficiency, there is a problem that processing time is long. In particular, in a high-resolution application, in order to perform encoding in real time, a very high operating frequency is required for processing. The existing MPU and CPU require a calculation frequency of several GHz in calculation, and there is a problem that it cannot cope with media such as high-definition broadcasting. For this reason, although a configuration for performing CABAC processing at high speed is desired, the conventional method is still insufficient as described above.

  The present invention has been made to solve such problems. The main object of the present invention is H.264. The present invention provides an arithmetic coding apparatus, an arithmetic coding method, an arithmetic coding program, and a computer-readable recording medium storing the program, which can reduce the amount of computation of CABAC processing in H.264 / AVC and can be easily implemented. is there.

  In order to achieve the above object, a first arithmetic coding apparatus according to the present invention performs arithmetic on a binarization unit for binarizing a multilevel signal and a binary symbol generated by the binarization unit. An arithmetic encoding unit for encoding, a context calculation unit for generating a context number, and a symbol value and symbol appearance indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarizing unit An arithmetic coding apparatus comprising: an update unit for updating a probability; and a probability state storage unit for storing a symbol value and a symbol appearance probability using the context number calculated by the context calculation unit as an index. The arithmetic coding unit stores the predicted value of the region rLPS obtained by dividing the inferior symbol section based on the occurrence probability, and also stores the predicted value of rLPS. The part includes a second storage unit separate, and a calculation unit for referring to the predicted value of rLPS stored in the first storage unit and the second storing unit performing arithmetic coding. As a result, high-speed arithmetic coding capable of processing 2 bits or more in one cycle can be realized.

  Further, the second arithmetic encoding device includes a binarizing unit for binarizing the multilevel signal, an arithmetic encoding unit for arithmetically encoding the binary symbol generated by the binarizing unit, A context calculation unit for generating a context number, an update unit for updating the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit; An arithmetic encoding device comprising a probability state storage unit for storing a symbol value and a symbol appearance probability using the context number calculated by the context calculation unit as an index, wherein the arithmetic encoding unit is configured to process a dominant symbol. Update section storage unit for storing the predicted value of the update section determined based on the number of consecutive dominant symbol processes, the initial section, and the symbol appearance probability, and the superiority at the time of dominant symbol processing A context update table for storing a prediction value of a symbol appearance probability determined based on the number of consecutive symbol processing and an initial symbol appearance probability, and a low that is a complement of the update interval based on the number of renormalizations And a renormalization unit having a renormalization table for updating. As a result, the arithmetic coding process when the dominant symbol process is continuously performed can be reduced by several cycles, and the process can be reduced and speeded up.

  Furthermore, a third arithmetic encoding device includes: a binarizing unit for binarizing the multilevel signal; an arithmetic encoding unit for arithmetically encoding the binary symbol generated by the binarizing unit; A context calculating unit for generating a context number, and an updating unit for updating the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarizing unit; An arithmetic coding apparatus comprising a probability state storage unit for storing a symbol value and a symbol appearance probability using the context number calculated by the context calculation unit as an index, wherein the arithmetic encoding unit performs dominant symbol processing A first update interval storage unit that stores a predicted value of an update interval determined based on the number of consecutive dominant symbol processes at the time, an initial interval, and a symbol appearance probability; A second update interval storage unit that is separate from the first update interval storage unit for storing the measured value, the number of consecutive dominant symbol processes during the dominant symbol processing, and the symbol appearance probability determined based on the initial symbol appearance probability Prediction value of symbol appearance probability determined based on first context update table for storing prediction value, number of consecutive dominant symbol processes at the time of dominant symbol processing, and symbol appearance probability updated by the first context update table And a second context update table that is separate from the first context update table, and a renormalization table that updates a low that is a complement of the update interval based on the number of renormalizations A part. As a result, the arithmetic coding process when the dominant symbol process is continuously performed can be reduced even when a plurality of different contexts are used.

  Furthermore, a fourth arithmetic encoding device includes: a binarizing unit for binarizing the multilevel signal; an arithmetic encoding unit for arithmetically encoding the binary symbol generated by the binarizing unit; A context calculating unit for generating a context number, and an updating unit for updating the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarizing unit; , An arithmetic coding device comprising a probability state storage unit for storing a symbol value and a symbol appearance probability using the context number calculated by the context calculation unit as an index, wherein the arithmetic encoding unit A first storage unit that stores the predicted value of the region rLPS obtained by dividing the section based on the occurrence probability, and a second storage unit that stores the predicted value of the rLPS and is separate from the first storage unit. A two-cycle prediction unit comprising an arithmetic unit that performs arithmetic coding with reference to the predicted values of rLPS stored in the first storage unit and the second storage unit, and the number of consecutive dominant symbol processes at the time of dominant symbol processing, An update interval storage unit for storing a prediction value of an update interval determined based on the interval and the symbol appearance probability, the number of consecutive dominant symbol processes during the dominant symbol processing, and the symbol appearance determined based on the initial symbol appearance probability A continuous dominant symbol comprising a context update table for storing a predicted value of probability and a renormalization unit having a renormalization table for updating low, which is a complement of the update interval, based on the number of renormalizations A processing prediction unit; and a prediction method switching unit that switches between a 2-cycle prediction unit and a continuous dominant symbol processing prediction unit. Thereby, 2-cycle prediction or continuous dominant symbol processing prediction is switched as appropriate, and the number of cycles can be efficiently reduced to realize faster arithmetic coding.

  On the other hand, in the arithmetic coding of a binary symbol, the arithmetic coding method uses a dominant symbol that is a symbol with a high appearance probability and an inferior symbol that is a symbol with a low appearance probability as a section on the number line up to the previous symbol and the inferior symbol. An arithmetic coding method for outputting a coded signal from a binary symbol inputted as a result of corresponding to a section on the number line based on a coordinate value of a section on the number line Referring to the first rLPS table in which the section coordinate value at the time of dominant symbol processing when the symbol to be encoded is the dominant symbol and the section coordinate value at the time of inferior symbol processing when it is the inferior symbol are recorded in advance. Referring to a step of obtaining a divided region in which a section of one symbol is updated, the obtained divided region, and a second rLPS table separate from the first rLPS table, And a step of determining the divided region updating the section of the second symbols following the symbol, and re-normalization as needed, and outputting an output code, and a step of updating the context number. As a result, high-speed arithmetic coding capable of processing 2 bits or more in one cycle can be realized.

  In addition, in the arithmetic coding of binary symbols, the arithmetic coding method uses a dominant symbol that is a symbol having a high appearance probability and an inferior symbol that is a symbol that has a low appearance probability as a symbol line interval and an inferior symbol. An arithmetic coding method for outputting a coded signal from a binary symbol inputted in accordance with a section correspondence result on a number line based on a coordinate value of a section on the number line, corresponding to a predetermined section on the number line, When the dominant symbols of the binary symbols are consecutive, a step of obtaining a predicted value of the update section with reference to the update section storage unit based on the number of consecutive dominant symbols and the context number, and a context update table for storing the context number And updating using. As a result, the arithmetic coding process when the dominant symbol process is continuously performed can be reduced by several cycles, and the process can be reduced and speeded up.

  Further, in the arithmetic coding of the binary symbol, the arithmetic coding program converts the dominant symbol that is a symbol with a high appearance probability and the inferior symbol that is a symbol with a low appearance probability into a section on the number line to the previous symbol and the inferior symbol. An arithmetic code program that outputs a coded signal from a binary symbol inputted as a result of corresponding to a section on the number line, based on a coordinate value of a section on the number line, and corresponding to a predetermined section on the number line, Referring to the first rLPS table in which the interval coordinate value at the time of dominant symbol processing when the symbol to be encoded is the dominant symbol and the interval coordinate value at the time of inferior symbol processing when it is the inferior symbol are recorded in advance. A function for obtaining a divided area in which a symbol section is updated, an obtained divided area, and a second rLPS table separate from the first rLPS table. In view of this, a function for obtaining a divided region obtained by updating a section of the second symbol following the first symbol, a function for performing renormalization as necessary, and outputting an output code, and a function for updating a context number are provided. Make it a computer. As a result, high-speed arithmetic coding capable of processing 2 bits or more in one cycle can be realized.

  Further, in the arithmetic coding of the binary symbol, the arithmetic coding program converts the dominant symbol that is a symbol having a high appearance probability and the inferior symbol that is a symbol having a low appearance probability into a section on the number line up to the previous symbol and the inferior symbol. An arithmetic coding program that outputs a coded signal from a binary symbol inputted as a result of corresponding to a section on the number line, based on a coordinate value of a section on the number line, and corresponding to a predetermined section on the number line. A function for obtaining a predicted value of an update interval by referring to an update interval storage unit based on the number of consecutive dominant symbols and a context number when a dominant symbol of binary symbols is continuous, and context update for storing a context number A function of updating using a table is realized in a computer. As a result, the arithmetic coding process when the dominant symbol process is continuously performed can be reduced by several cycles, and the process can be reduced and speeded up.

  A computer-readable recording medium stores the above program. CD-ROM, CD-R, CD-RW, flexible disk, magnetic tape, MO, DVD-ROM, DVD-RAM, DVD-R, DVD + R, DVD-RW, DVD + RW, Blue-ray (registered) Trademark), HD DVD (registered trademark) (AOD), and other magnetic disks, optical disks, magneto-optical disks, semiconductor memories, and other media that can store programs. The program includes a program distributed in a download manner through a network line such as the Internet, in addition to a program stored and distributed in the recording medium. Further, the recording medium includes general-purpose or dedicated equipment in which the above-described program is mounted in a state where it can be executed in the form of software, firmware, or the like. Furthermore, each process and function included in the program may be executed by program software that can be executed by a computer, or each part of the process or function may be executed by hardware such as a predetermined gate array (FPGA, ASIC), or program software. It may be realized in the form of a mixture of hardware and partial hardware modules that realize some elements of hardware.

  According to the arithmetic coding apparatus, arithmetic coding method, arithmetic coding program, and computer-readable recording medium storing the program of the present invention, The number of cycles of CABAC processing in H.264 / AVC can be reduced, and the processing load and speed can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below exemplify an arithmetic encoding device, an arithmetic encoding method, an arithmetic encoding program, and a computer-readable recording medium storing the program for embodying the technical idea of the present invention. However, the present invention does not specify an arithmetic encoding device, an arithmetic encoding method, an arithmetic encoding program, and a computer-readable recording medium storing the program as follows. Further, the present specification by no means specifies the members shown in the claims as the members of the embodiment. In particular, the dimensions, materials, shapes, relative arrangements, and the like of the component parts described in the embodiments are not intended to limit the scope of the present invention unless otherwise specified, but are merely described. It's just an example. Note that the size, positional relationship, and the like of the members shown in each drawing may be exaggerated for clarity of explanation. Furthermore, in the following description, the same name and symbol indicate the same or the same members, and detailed description thereof will be omitted as appropriate. Furthermore, each element constituting the present invention may be configured such that a plurality of elements are constituted by the same member and the plurality of elements are shared by one member, and conversely, the function of one member is constituted by a plurality of members. It can also be realized by sharing.

In this specification, connection to computers, printers, external storage devices and other peripheral devices for operations, control, input / output, display, and other processing connected to the arithmetic coding device is, for example, IEEE1394, RS-232x. , RS-422, RS-423, RS-485, serial connection such as USB, parallel connection, or electrical connection via a network such as 10BASE-T, 100BASE-TX, 1000BASE-T, and the like. The connection is not limited to a physical connection using a wire, but may be a wireless connection using a wireless LAN such as IEEE 802.1x or OFDM, radio waves such as Bluetooth, infrared rays, optical communication, or the like. Further, a memory card, a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like can be used as a recording medium for storing text and image data to be searched, database construction, setting for searching, and the like.
(Moving image encoding / decoding device)

  In FIG. FIG. 1 shows an example of a block diagram of a moving image encoding / decoding device that obtains a bit stream from image data by H.264 / AVC encoding processing. The moving image encoding / decoding device 100 shown in this figure includes a DMA 1 (Direct Memory Access) that performs memory management, a motion search unit 2 (ME), a deblocking filter 3 (DF: Deblocking Filter), and a motion compensation unit. 4 (MC), a conversion unit 5, a quantization unit 6, an inverse quantization unit 7, an inverse conversion unit 8, an overall control unit 9, and a variable length coding unit (VLC). An arithmetic encoding / decoding device 10 and a variable length decoding unit 11 (VLD: Variable Length Decoder) are provided. The arithmetic encoding / decoding device 10 performs CABAC and CAVLC as arithmetic encoding techniques. The moving image encoding / decoding device 100 is configured by hardware, and can also be processed by software by a processor. In this case, arithmetic encoding is performed by an arithmetic encoding program installed in the computer. In addition to general-purpose personal computers and workstations, devices that can display moving images, such as mobile phones, smartphones, PDAs, car navigation systems with communication functions, and fixed telephones capable of data communication, can be used as computers.

  In the moving image encoding / decoding device 100, first, a moving image to be encoded is input, and the motion search unit 2 performs a motion detection process. The motion compensation unit 4, the conversion unit 5, and the quantization unit 6 perform motion compensation processing, conversion processing, and quantization processing using the motion vector obtained by this processing. The block coefficients subjected to the quantization process and all information used for encoding are collected in the arithmetic encoding / decoding device 10 to create a bit stream. In order to create a reference frame to be used for the code of the next frame, the inverse encoding unit 7, the inverse transform unit 8, and the motion compensation unit 4 are used to perform reverse processing to create a reference frame and store it in the frame memory FM. To do. If the deblocking filter 3 is used before storing it in the frame memory FM, an effect of reducing block noise can be obtained.

The moving image encoding / decoding device 100 can perform decoding processing in addition to encoding. The processing procedure is as follows. First, the input bit stream is analyzed by the variable length decoding unit 11 that performs decoding processing, the image information in the bit stream is decoded, and the inverse quantization unit 7 and inverse transformation are performed as in the reference frame generation procedure. The image frame is restored using the unit 8 and the motion compensation unit 4 and stored in the frame memory FM. Thus, the arithmetic encoding technique includes decoding of encoded data. In the present specification, an arithmetic coding apparatus, method, program, and the like are described as including not only arithmetic coding but also a decoding apparatus, method, and program.
(Arithmetic coding method)

  In the present embodiment, H.264. Accelerate CABAC processing in H.264 / AVC. CABAC is an arithmetic coding method. The concept of alias coding / decoding, which is basic arithmetic coding, is shown in FIG. In arithmetic coding, a real straight line having a lower limit value of 0 or more and an upper limit value of 1 or less is generally considered. This section is set as the initial range. In arithmetic coding, a real line is divided based on the occurrence probability of a dominant symbol (MPS) and an inferior symbol (Least Possible Symbol: LPS). Let the divided areas be rMPS and rLPS, respectively. Thereafter, a region to which a symbol to be encoded output belongs is selected. Here, it is assumed that rMPS is selected. Thereafter, the selected rMPS is set as the next range, and this range is similarly divided into rMPS and rLPS, and an area to be encoded is selected. This operation is repeated until there is no encoding output target, and the value that falls within the range of the range that is finally specified is output as the output value value, thereby completing the encoding. Normally, the lower limit value of the range is output as the output value value. In such basic arithmetic coding, the range of the section and the value that is the input value are real values, which is not practical due to the problem of calculation accuracy. Therefore, the real number line is set to an integer interval having a finite bit width, and the problem is solved by introducing a normalization process to the range that is the width of the specified interval and the value that is the lower limit value of the specified interval. The normalization process is performed by a left shift calculation, and the normalization process ensures the calculation accuracy of range and value. In CABAC, a plurality of context variable information is used to improve encoding efficiency.

  Next, a procedure for performing arithmetic coding (AC) will be described with reference to FIG. In the case of binary arithmetic coding used in CABAC, a section is sequentially divided between real numbers 0.0 to 1.0 according to an input signal based on a given binary symbol occurrence probability. Here, when the input signal is 00001, the occurrence probability of “0” is 0.8, and the occurrence probability of “1” is 0.2. For this reason, when “0” of the input signal is encoded, the lower 0.8 part of the previous section is updated as a new section. On the other hand, when “1” is encoded, the upper 0.2 of the previous section is updated as a new section.

  In the first step 1 of FIG. 3, “0” is encoded. As a result, the lower 0.8 part (0.0 to 0.8) of 0.0-1.0 in the initial section is updated as a new section.

  Next, in step 2, “0” is encoded. As a result, the section (0.0 to 0.64) of 0.8 × 0.8 = 0.64 is updated below the current section (0.0 to 0.8).

  Similarly, in step 3, “0” is encoded. As a result, the portion of 0.64 × 0.8 = 0.512 (0.0 to 0.512) becomes the update interval further below the current interval (0.0 to 0.64).

  Next, in step 4, "1" is encoded. As a result, above the current section (0.0 to 0.512), a portion of 0.512 × 0.2 = 0.1024, that is, ((0.512−0.1024 = 0.4096) to 0 .512) = (0.4096 to 0.512) is the update interval.

  In step 5, “0” is encoded again. As a result, a portion of 0.1024 × 0.8 = 0.08192 (0.4096 to (0.4096 + 0.08192)) = (0.4096) below the current section (0.4096 to 0.512). ˜0.49152) is the update interval.

Finally, the code is determined in step 6. The code word of the arithmetic code is a binary representation of a real value that specifies the last interval. In this example, since the last update interval is (0.4096 to 0.49152), 0.4375 in which the binary representation is the shortest among the real numbers included in the interval can be taken. Since the binary representation of 0.4375 is 0.0111, “0111” below the decimal point, excluding the first digit that is always 0, is output as the code word.
(Block diagram of arithmetic coding device)

  Next, FIG. 4 shows an example of an arithmetic coding apparatus that performs CABAC processing. As shown in this figure, the arithmetic encoding device 10A includes a binarizing unit 12 that converts a multilevel signal into a binary symbol, and calculates the occurrence probability of the binary symbol to be encoded according to the surrounding situation, that is, the context. A context calculation unit 14 for updating and a binary arithmetic encoding unit 16 that performs arithmetic encoding based on these binary symbols and binary symbol occurrence probabilities are configured.

Details of the binary arithmetic encoding unit 16 are shown in FIG. As shown in this figure, the binary arithmetic encoding unit 16 includes an rLPS table 20, a context change table 30, a calculation unit 40, and a renormalization unit 50.
(Renormalization)

  The binary arithmetic encoding unit in CABAC also performs the same operation as described above for arithmetic encoding. However, since the number of digits in the register, which is the storage element that actually holds the interval section, is finite, the regular bit is output in a timely manner when the upper bits of the section to be output are finalized, and the width of the update section is expanded. Renormalization processing is added.

  The renormalization procedure will be described with reference to FIG. As a result of encoding 0 in step 1, the update interval becomes (0 to 0.8). Next, as a result of encoding 1 in step 2, the upper 0.2 part (0.64 to 0.8) of the section (0.0 to 0.8) becomes the update section. At this stage, it is determined that the representative value of the section to be output is 0.5 or more. That is, since it is determined that the first bit is “1”, “1” is output as Step 3 at this time, and the section of (0.5 to 1.0) is (0.0 to 1). .0) is mapped (associated). Here, the section of (0.64 to 0.8) is defined as (((0.64-0.5) × 2 = 0.28) to ((0.8−0.5) × 2 = 0.6). )) = Enlarge to (0.28 to 0.6). In this way, it is found that the coordinate value of the section becomes 0.5 (0.1 in binary expression) or more during the processing (in this example, when 1 is encoded in step 2). At the time, “1” with the first decimal point is output. At the same time, by subtracting 0.5 from the interval and doubling the interval, the interval can be substantially expanded and the number of usable digits can be increased. On the other hand, when the coordinate value of the section becomes smaller than 0.25, it is found that the first bit is “0”. By this processing, it is possible to prevent the real number of digits representing the width of the section from being continuously increased, and it is possible to perform encoding by calculation with a finite number of digits.

In the above example, the occurrence probability of the binary symbol is fixed for the sake of explanation, but actually, it can be changed adaptively for each operation. The context calculation unit 14 plays a role of giving a binary symbol occurrence probability to the binary arithmetic coding unit.
(CABAC operation)

  There are two types of CABAC operations: updating the update interval, that is, dividing the range into update (range) and low (other than update interval), MPS (Most Possible Symbol) processing and LPS (Least Possible Symbol) processing. is there. In the example of FIG. 3, the process for encoding 0 corresponds to MPS, and the process for encoding 1 corresponds to LPS.

During MPS processing, range and low are determined by the following equations.
range = range-rLPS
low = low

On the other hand, at the time of LPS processing, range and low are determined by the following equations.
range = rLPS
low = low + range-rLPS
Which of these processes is performed is determined by the context and the range. The context indicates the occurrence probability of the binary symbol and is updated when the symbol is processed.

The context is held and updated by the context calculation unit 14 shown in FIG. The context calculation unit 14 holds a plurality of occurrence probabilities of binary symbols, switches the occurrence probabilities according to the current encoding target and the surrounding situation, that is, the context, and gives it to the binary arithmetic encoding unit 16. The occurrence probability of the binary symbol is held in the occurrence probability table, and either 0 or 1 symbol (MPS: Most Probable Symbol) having the highest occurrence probability and its occurrence probability table number (pStateIdx) Are held in association with each other. When the occurrence probability table number is designated, the corresponding occurrence probability is obtained.
(Conventional CABAC processing)

  Next, in the conventional arithmetic coding apparatus that performs CABAC processing, the binary arithmetic coding unit 16 gives a binary symbol given from the binarizing unit 12 according to the occurrence probability (context) given from the context calculation unit 14 The procedure for performing the coding of and updating the section will be described with reference to the block diagram of FIG. 7 and the operation diagram of FIG.

  The arithmetic coding apparatus 200 illustrated in FIG. 7 includes a calculation unit 40, an rLPS table 20, and a context update unit 70. The arithmetic coding apparatus 200 includes a range input and / or a low input, a binary string input, and a context input for inputting a section as input terminals. The range input and the low input are connected to the arithmetic unit 40 and the rLPS table 20, respectively. The binary string input is connected to the calculation unit 40, the rLPS table 20, and the context update unit 70. Further, the context input is connected to the rLPS table 20 and the context update unit 70. Here, the rLPS table 20 is a table for selecting an rLPS according to a specified range and context. The calculation unit 40 includes a renormalization unit, generates a sign bit at the time of renormalization, and outputs an output code from the calculation unit 40. The context is updated after the range and low are updated. The context update unit 70 updates and outputs the context based on the previous processing result.

  The calculation unit 40 performs arithmetic coding calculation. Here, the input section range and / or low and the corresponding rLPS are determined with reference to the rLPS table 20, the section is updated based on these, and range 'and low' are output.

This process will be described based on the operation diagram of FIG. Here, (cycle 1) MPS processing, (cycle 2) LPS processing and renormalization processing are described for a predetermined section. That is, first, in cycle 1, for the interval in which range and low are determined, the arithmetic unit 40 performs MPS processing and encoding for the binary symbol A and the corresponding context X, and the interval is defined as range ′. Update to low '. here,
range ′ = range-rLPS,
low '= low
It becomes. On the other hand, the context update unit 70 updates the context X. Then, in cycle 2, when the range ′ and low ′ are the binary symbol B and the corresponding context Y, the arithmetic unit 40 performs encoding by LSP processing, and updates the interval to range ″ and low ″. Here, “range” = rLPS ′,
low "= low '+ range'-rLPS'
It becomes. On the other hand, the context update unit 70 updates the context Y.

Further, renormalization is performed to expand the section to range “′” and low “′. As a result,
range "'= (range" -0.5) * 2
low "'= (low" -0.5) * 2
It becomes. Further, the calculation unit 40 outputs the output code “1”. Thus, in the conventional CABAC process, two cycles were required to complete the above process.

  On the other hand, H.P. There is a high demand for high speed such as H.264 / AVC encoding processing in real time, and there is a demand for reducing the amount of CABAC processing. However, in the above configuration, there is a problem that operations cannot be pipelined because the values of range and low depend on the previous processing. That is, in arithmetic coding of adjacent symbols, the processing of the second symbol depends on the previous processing (processing of the first symbol) not only for range and low but also for the value of rLPS. For this reason, it has been difficult to process two symbols or more in one cycle.

  In other words, conventionally, as a method for increasing the execution speed of CABAC, focusing on the processing of each processing unit of the CABAC device, memory access, parallel operation of the encoder portion, etc., how efficiently data processing is performed The realization of processing of one symbol / one cycle has been studied with a focus on the above technique. However, the CABAC symbol processing always has a feature that depends on the appearance probability of a past symbol, and the context that needs to be updated when processing each symbol, rLPS, must obtain the processing result of the immediately preceding symbol. For this reason, in the past, due to the nature of dependence on the processing in the previous stage, it has been considered that increasing the processing hardware will not be able to increase the processing efficiency, and even though sufficiently high speed is not realized. First, it was understood that the processing speed of one symbol / one cycle is the limit of speeding up.

On the other hand, in the present invention, the calculation procedure of the appearance probability of the symbol is analyzed, and the detailed relationship of the dependency between symbols is clarified. As a result, the inter-symbol dependency is lost depending on the situation, and the process of the next cycle is executed in advance, and a method capable of simultaneously updating the table has been developed.
(2 cycle prediction)

  In the present embodiment, two context update tables, two rLPS tables, and two arithmetic units are provided in order to collectively input information necessary for processing two symbols and perform two symbols in one cycle. Here, an rLPS table for determining a context to be used for a generated binary string based on a context necessary for calculating range and low, that is, a binary string, a syntax element, and a surrounding situation (context). Is created in advance, and it is possible to predict the previous calculation by referring to this during processing. Furthermore, by preparing two rLPS tables, different rLPS for performing processing for two cycles can be referred simultaneously. For example, one table is a first rLPS table that records LPS for MPS processing, and the other is a table that holds a second rLPS that records LPS for LPS processing, and supports both MPS processing and LPS processing in one cycle. it can. Each rLPS table uses a multi-port (dual port) memory, and enables simultaneous writing and reading from two access ports. As a result, when data is read from or written to one access port, data can be read using the other access port. As a result, two processors can access the same memory at the same time, and two cycles of processing can be completed within one cycle, and the number of processing cycles is reduced to increase the speed of CABAC processing.

In order to read and write two contexts from the memory at the same time, it is expected that a memory amount that is about four times as large as the conventional one will be required depending on the contents of the update context. In addition, when the memory amount is used only twice that of the conventional case, two cycles of processing are required when the same context needs to be updated, and the processing speed is reduced. Similarly, processing of three symbols is possible, but the amount of context memory is about six times that of the conventional one. Thus, it is necessary to design an appropriate configuration according to the balance between performance and hardware specifications, and required processing capacity and speed. Preferably, the information to be input at a time is for two symbols, and the two-cycle prediction and the continuous MPS processing prediction described later are used in combination, and switching between them can maintain a high processing speed without depending much on the image. it can. Hereinafter, description will be made sequentially.
(Embodiment 1)

FIG. 9 shows the arithmetic coding apparatus according to the first embodiment. The arithmetic coding apparatus shown in this figure calculates / updates a binarization unit 112 that converts a multilevel signal into a binary symbol, and a probability of occurrence of the binary symbol to be encoded according to the surrounding situation (context). Context calculation unit 114, arithmetic coding unit 116 that performs arithmetic coding based on these binary symbols and binary symbol occurrence probability, first memory unit 117 that holds context, and range and low A second memory unit 118, a prediction unit 119 that performs two-cycle prediction, and an output buffer 121 are provided. In this arithmetic encoding apparatus, when a multilevel signal and / or a syntax element to be encoded is input by the binarization unit 112, it is converted into a binary sequence and sent to the arithmetic encoding unit 116 and the prediction unit 119. In addition, the surrounding situation (context) is also input to the context calculation unit 114 as necessary. Then, while the prediction unit 119 performs the range prediction, the arithmetic encoding unit 116 performs arithmetic encoding, and outputs the obtained result to the output buffer 121 as a code bit. Needless to say, a buffer can be provided on the input side as required.
(First memory unit 117)

  The first memory unit 117 functions as a context table that holds contexts. The context table is updated as needed. For this reason, an updatable memory, such as a RAM, is used for the first memory unit 117. An example of the first memory unit 117 is shown in FIG. As shown in this figure, contexts # 1, # 2, # 3,... Are held in the first memory unit 117, and each context is associated with a binary string (0, 1). At this time, it is also possible to assign a plurality of binary strings to one context.

  The second memory unit 118 functions as a second context update table that holds contexts. A register or the like can be used to hold the range and low values.

  Further, as shown in the modification of FIG. 11, the first memory unit and the second memory unit can be configured as a common memory unit 117A, and the context, range, and low can be held in one memory. .

The first memory unit 117 uses a dual port memory. As a result, it is possible to simultaneously read / write to the context table.
(Arithmetic coding unit 116)

  Details of the arithmetic encoding unit 116 in FIG. 9 will be described based on the block diagram in FIG. 12 and the operation diagram in FIG. 13. The arithmetic encoding unit 116 illustrated in FIG. 12 includes a calculation unit 140, a first rLPS table 120, a second rLPS table 122, a code bit generation unit 160, and a context update unit 170. The arithmetic coding unit 116 includes a range input and / or a low input for inputting a section as an input terminal, a binary string input, and a context X input and a context Y input as context inputs. The range input is connected to the calculation unit 140, the first rLPS table 120, the second rLPS table 122, and the code bit generation unit 160. On the other hand, the low input is connected to the calculation unit 140, the second rLPS table 122, and the sign bit generation unit 160. The binary string input is connected to the arithmetic unit 140, the second rLPS table 122, the sign bit generation unit 160, and the context update unit 170. Further, the context X input is connected to the first rLPS table 120, the second rLPS table 122, the code bit generation unit 160, and the context update unit 170. On the other hand, the context Y input is connected to the second rLPS table 122, the sign bit generation unit 160, and the context update unit 170.

  The first rLPS table 120 and the second rLPS table 122 are tables that determine the rLPS according to the input range and context. By providing two tables, it is possible to read and write 2 bits in one cycle, and high-speed processing is expected. On the other hand, it is necessary to control which table holds the latest data and switch the table as necessary. Therefore, the arithmetic encoding unit 116 in FIG. 9 includes a table management unit.

  The sign bit generation unit 160 outputs an output code at the time of renormalization. Furthermore, the context update unit 170 updates and outputs the context based on the previous processing result. The calculation unit 140 determines the input section range and / or low and the corresponding rLPS with reference to the rLPS table 20, updates the section based on these, and outputs range ′ and low ′.

This process will be described based on the operation diagram of FIG. FIG. 13 illustrates processing for performing MPS processing, LPS processing, and renormalization on a predetermined section, as in FIG. Here, in the case where the range where the range and low are determined, in the case of the binary symbol A and the corresponding context X, the calculation unit 140 performs MPS processing and performs encoding, and updates the range to range ′ and low ′. In the case of the binary symbol B and the corresponding context Y, the processing unit 140 encodes the range ′ and low ′ by the LSP processing to update the interval to “range” and “low”, and renormalization. The process of expanding the section to range “′” and “low” ′ and the process of updating the context X and the context Y by the context update unit 170 are performed in one cycle. That is, the calculation unit 140 refers to the first rLPS table 120 to obtain the rLPS at the time of MPS, and refers to the second rLPS table 122 to obtain the rLPS ′ at the time of LPS, and performs the following calculation.
range "'= (rLPS'-0.5) * 2
low "'= (low + range-rLPS-rLPS'-0.5) * 2

  In the same cycle, the sign bit generation unit 160 outputs the output code “1”, and the context update unit 170 updates the context X and the context Y, respectively. Thereby, MPS processing, LPS processing, and renormalization can be completed in one cycle.

  Next, FIG. 14 illustrates an example of an arithmetic encoding unit 300 according to another configuration. In order to process two symbols in one cycle, the arithmetic encoding unit 300 shown in this figure has a first arithmetic encoding unit 301 for processing the first symbol and a second arithmetic encoding unit for processing the second symbol. 302 and a sign bit generation unit 360. The first arithmetic encoding unit 301 includes a first rLPS table 320, a first context update table 330, a first calculation unit 340, and a first renormalization unit 350. Similarly, the second arithmetic encoding unit 302 includes a second rLPS table 322, a second context update table 332, a second calculation unit 342, and a second renormalization unit 352. When the symbol A and the context X are input as a binary string, the arithmetic encoding unit 300 obtains an rLPS corresponding to the context X and the range with reference to the first rLPS table 320, and performs the first operation with this value and the symbol A. The unit 340 performs arithmetic coding and updates range and low. Further, if necessary, the first renormalization unit 350 performs renormalization, and ranges ′ and low ′ are sent to the second arithmetic coding unit 302 and the code bits are output to the code bit generation unit 360. Further, the first context update table 330 is updated, and the context X ′ is output.

  On the other hand, the second arithmetic coding unit 302 obtains rLPS corresponding to the context Y and range ′ with reference to the second rLPS table 322, and the second arithmetic unit 342 performs arithmetic coding based on this value, range ′, and low ′. And update range ′ and low ′. Further, the second renormalization unit 352 performs renormalization as necessary, and outputs “range” and “low” and also outputs a code bit to the code bit generation unit 360. The sign bit generation unit 360 outputs an output sign bit. Further, the second context update table 332 is updated based on the symbol B and the context Y, and the context Y ′ is output.

The above processing can be completed in one cycle. That is, the first arithmetic coding unit 301 performs arithmetic coding on the first symbol A based on the range and low and the context X, and the second arithmetic based on the obtained range ′ and low ′ and the context Y. The encoding means 302 arithmetically encodes the second symbol B. As described above, in the present embodiment, an rLPS table for determining a context to be used for a generated binary string based on a binary string, a syntax element, and a surrounding situation (context) is created in advance. By preparing two rLPS tables, the calculation unit can read and update necessary data from each table during one cycle, and two cycles of calculations can be completed in one cycle. As a result, it is possible to reduce the number of processing cycles of CABAC, which has been a problem with the length of processing time while achieving high coding efficiency, thereby speeding up the processing and realizing real-time coding for high-resolution applications. It is possible to construct a system that can be implemented in a system. This method can be implemented by software using a general-purpose CPU or MPU, but more efficient processing is preferably possible by constructing and executing dedicated hardware.
(Modification example of arithmetic coding unit performing 2-cycle prediction)

  In the configuration of the arithmetic encoding device shown in the block diagram of FIG. 9, the arithmetic encoding unit 116 performs arithmetic encoding operations. As a specific configuration of the arithmetic encoding unit 116, for example, the configuration shown in the block diagram of FIG. 5 can be used. Here, if each context update table is composed of ROMs, each determines a context according to a symbol, so the ROM size needs to be increased. In addition, since a ROM requires one cycle to access data, a delay occurs. Therefore, by configuring one context update table with a combinational circuit, the size of the ROM can be reduced and the configuration can be made inexpensively. Furthermore, in the combinational circuit, the result of the arithmetic logic is generated during the cycle, so that an extra cycle is not required and the advantage of speeding up the processing can be obtained. An example of the arithmetic encoding unit 216 using a combinational circuit is shown in FIG.

  The arithmetic encoding unit 216 shown in this figure is connected to the context memory unit 217, the first context update table 230 connected to the first output side of the context memory unit 217 in FIG. 29, and the second output side. The second context update table 232, the first rLPS table 220 connected to the first output side of the context memory unit 217, and the second rLPS connected to the adder outputs of the first context update table 230 and the context memory unit 217. A table 222; a range memory unit 218 for holding a range value; a first selector 224 connected to the output side of the range memory unit 218 and the first rLPS table 220; a first selector 224 and a range memory unit; A first range updating unit 240 connected to H.218, The second selector 226 connected to the output side of the 2rLPS table 222 and the first range update unit 240, and connected to the output side of the second selector 226 and the first range update unit 240, and the output side to the range memory unit 218 A connected second range update unit 242; a low memory unit 219 that holds a low value; a low memory unit 219, a first range update unit 240, and a first low update unit 250 connected to the output side of the first selector 224; , A first low update unit 250, a second range update unit 242, and a second low update unit 252 connected to the output side of the second selector 226 and having the output side connected to the low memory unit 219.

  Note that FIG. 29 is a block diagram representing the processing steps and the data flow, and therefore does not necessarily match the actual hardware connection. For example, with respect to the range value, the range is sequentially updated in the range of the range memory unit 218 → the first range table → the second range table → the range memory unit 218. In practice, the range is updated, but the first range table and the second range are actually shown. Each table is connected to the range memory unit 218, and the range value updated in each range table can be written to the range memory unit 218. Although the context memory unit 217 is displayed in duplicate, both are the same. In FIG. 29, the left side context memory unit 217 shows the operation at the time of reading, and the middle context memory unit 217 shows the operation at the time of writing. Yes.

  The context memory unit 217 corresponds to the first memory unit 117 that holds a context in FIG. Here, it is composed of a dual port RAM or the like having four inputs of a symbol A and a context X corresponding thereto, a symbol B and a context Y corresponding thereto, and two outputs of updated contexts X ′ and Y ′. The context memory unit 217 holds the updated context, reads the corresponding context in accordance with the specified address, and further updates the two contexts X ′ and Y updated by the first and second context update tables 232. Each 'is written. Here, the second context update table 232 is configured by a ROM, while the first context update table 230 is configured by a combinational circuit. By configuring one context update table with a combinational circuit, the contexts X and Y can be updated simultaneously in the second stage, which greatly contributes to speeding up processing of two symbols in one cycle.

  Note that in the example of the arithmetic encoding unit 216 shown in FIG. 29, both the first context update table 230 and the second context update table 232 can be configured by a combinational circuit. In this case, it is possible to further increase the speed. Note that when storing a large amount of data in the context update table, it is not suitable because the area is increased and the cost is increased if implemented by a combinational circuit. However, when the amount of data to be stored is small, the area is not so large even if it is implemented by a combinational circuit as compared with the case of a ROM.

  The first and second rLPS tables 222 are each composed of a ROM, and output rLPS according to the input context. Since the rLPS table data held in the ROM is divided into four according to the context, each rLPS table has four outputs. The rLPS output from each rLPS table is input to the first and second selectors 226, respectively. The first and second selectors 226 select the corresponding rLPS according to each input range, and output the selected rLPS to the first and second range update unit 242. The first and second range update unit 242 updates the range value and rewrites the range value of the range memory unit 218. Similarly, the low memory unit 219 holds a low value. The range memory unit 218 and the low memory unit 219 can be configured by registers. The first and second low update units 252 implement the function of a renormalization unit, and renormalize and update low according to the number of ranges and renormalization. In this way, the first low update unit 250 outputs the code bit 1 that is arithmetically encoded for the symbol A, and the second low update unit 252 outputs the code bit 2 that is arithmetically encoded for the symbol B.

In the example of FIG. 29, members that perform each process are functionally expressed, and in an actual hardware configuration, a plurality of functions can be realized by one member. For example, the context memory unit 217 corresponds to the first memory unit 117 in FIG. 9, and the range memory unit 218 and the low memory unit 219 correspond to the second memory unit 118. Further, the first range update unit 240 and the first low update unit 250 correspond to the first calculation unit shown in FIG. 14, the second range update unit 242 and the second low update unit 252 correspond to the second calculation unit, respectively. Can be summarized as appropriate.
(DSE arithmetic coding process)

  The above-described processing of performing arithmetic encoding operation of two symbols in one cycle by the arithmetic encoding unit 216 can be divided into four stages as shown in the flowcharts of FIGS. That is, in the first stage shown in step S1, each context is read. Specifically, the context memory unit 217 reads the contexts X and Y corresponding to the symbols A and B according to the address. In FIG. 29, the context memory unit 217 on the left side shows a read state.

  Next, in the second stage shown in step S2, each context is updated and each rLPS is read. Specifically, the first context update table 230 reads the context X from the first output of the context memory unit 217 and updates it to the context X ′. Further, the updated context X ′ is referred to by the second context update table 232, and on the other hand, the context Y obtained from the second output of the context memory unit 217 is updated to the context Y ′. Here, the context update table is not two ROMs, one is the first context update table 230 configured with a combinational circuit, and the other is the second context update table 232 configured with a ROM, thereby speeding up the processing. It is possible to simultaneously update the contexts X and Y of the two symbols A and B. Further, as described above, it is possible to further increase the speed by configuring all context update tables with combinational circuits.

  On the other hand, in the second stage, based on the context X before update, the rLPS of the symbol A is obtained by referring to the rLPS table. That is, the first rLPS table 220 outputs rLPS to the first selector 224 based on the context X obtained from the first output of the context memory unit 217. On the other hand, the AND output of the context Y obtained from the context X ′ obtained from the first context update table 230 and the second output of the context memory unit 217 is sent to the second rLPS table 222, and similarly the rLPS of the context Y before the update. Is obtained and output to the second selector 226.

  Further, in the third stage shown in step S3, the updated context is written and the range is updated. First, the contexts X ′ and Y ′ output from the first context update table 230 and the second context update table 232 are written in the context memory unit 217. In FIG. 29, the context memory unit 217 in the lower center part shows a write state.

  On the other hand, the first selector 224 selects an rLPS corresponding to the symbol A according to the range obtained by referring to the range memory unit 218 and outputs the selected rLPS to the first range update unit 240. The first range update unit 240 updates the current range held in the range memory unit 218 to range ′ according to the selected rLPS, and determines the range corresponding to the next stage symbol B in order to determine the second range. The data is output to the update unit 242. On the other hand, the number of renormalizations is determined according to the updated range ′, and is output to the first low update unit 250.

  The second range updating unit 242 updates the range ′ updated by the first range updating unit 240 to “range” according to the rLPS selected by the second selector 226, and updates the range value of the range memory unit 218 to “range”. To do. On the other hand, the number of renormalizations is determined according to the updated range ”, and is output to the second low update unit 252.

  Finally, low is updated in the fourth stage shown in step S4. The first low update unit 250 updates the low value held in the low memory unit 219 to low ′ in accordance with the range ′ and the number of renormalizations, and outputs the sign bit 1 of the symbol A. On the other hand, the second low update unit 252 updates low 'to low "according to the range" and the number of renormalizations, and updates the low value of the low memory unit 219 to low ". Also, the sign bit 2 of the symbol B Is output.

As described above, one of the two context update tables is composed of ROM and the other is composed of a combinational circuit, so that arithmetic encoding of two symbols in one cycle can be realized at low cost.
(Continuous MPS process prediction)

  On the other hand, as a characteristic of binarization by CABAC processing, it is easy to generate the same symbol continuously. Further, among the MPS processing and LPS processing included in the CABAC processing, as a feature of the MPS processing, low does not change and only the range value tends to decrease gradually. Therefore, when the binary sequence is a sequence of MPSs, it is possible to predict the result up to several cycles ahead from the number of sequences, range, and context.

The procedure of this process will be described based on the operation diagram of FIG. Here, it is assumed that the context X is a constant value and the MPS process continues four times. First, if range 0 is updated to range 1 in the first cycle, if rLPS used in the MPS process at this time is rLPS1,
range1 = range0-rLPS1
low0 = low1
It becomes. If range1 is updated to range2 in the next second cycle, if rLPS used in the MPS process at this time is rLPS2,
range2 = range1-rLPS2
= Range0-rLPS1-rLPS2
low2 = low1 = low0
It becomes. Furthermore, in the third cycle, range2 is updated to range3. At this time, if rLPS3,
range3 = range2-rLPS3
= Range0-rLPS1-rLPS2-rLPS3
low3 = low2 = low1 = low0
Finally, in the fourth cycle, range 3 is updated to range 4, and at this time, if rLPS4,
range4 = range3-rLPS4
= Range0-rLPS1-rLPS2-rLPS3-rLPS4
low4 = low3 = low2 = low1 = low0
It becomes. In this way, continuous processing of MPS using the same context can be calculated from range, context X, and continuous number, so by recording the result calculated in advance in a table, several cycles from the above parameters It becomes predictable to the future. In order to realize this, an MPS continuous number table is prepared.
(MPS continuous number table)

FIG. 16 shows an example of the MPS continuous number table when the context is constant. As shown in this figure, the MPS continuous number table holds a range corresponding to the range, context, and MPS continuous number as a table. Therefore, by referring to the table with these parameters, the range value after the continuous MPS process can be extracted. In the example of FIG. 15, the initial value “range” is the rangeAm context X (constant) and the MPS continuity number 4, so the range prediction value is the value stored at the position E in the MPS continuity number table of FIG. 16. . In this way, an update interval several cycles ahead can be obtained only by referring to the table, and therefore, especially when MPS processing is continued, an extremely large amount of computation is expected to be reduced. It is done.
(Change due to renormalization)

  In the above MPS process, low is constant while the LPS process does not occur, that is, while the MPS process continues. However, when renormalization is performed as shown in FIG. 17A, the value of low changes. However, the renormalization value is determined by the range. Therefore, if the range value and the number of times of renormalization are known, the low value can be obtained. In this way, it is possible to table the low that changes due to renormalization.

  FIG. 18 shows a block diagram of the continuous MPS process prediction unit 400 considering renormalization. The continuous MPS process prediction unit 400 shown in this figure includes a range table 420, a context update table 430, and a renormalization unit 450. The continuous MPS process prediction unit 400 refers to the range table 420 according to the range, the number of MPS continuations, and the context, and updates the range to range ′. On the other hand, based on the renormalization count and low, the renormalization unit 450 outputs low ′ and a sign bit. Further, based on the number of consecutive MPSs and the context, the context update table 430 is referred to update the context (context → context ′).

An example of range prediction considering renormalization is shown in FIG. As shown in this figure, the range value can be predicted and the context can be updated according to the number of consecutive MPSs and the number of renormalizations.
(Change in context)

  In the above example, the context is constant, but the context may be switched in the middle. Since the above method is based on the premise that the same context is used for the same symbol, if the context is changed, subsequent changes cannot be predicted. Therefore, by preparing two range tables and two context update tables, continuous MPS process prediction that can cope with such a change in context is realized.

  FIG. 19 shows an example in which the context is switched to the context X until the fourth cycle and the subsequent two cycles are switched to the context Y in the continuous MPS processing. Also in this case, it is possible to create a table for each context. FIG. 20 shows an example of the MPS continuous number table in which the range predicted value corresponding to the range, the context (variable), and the MPS continuous number is recorded. In the example of FIG. 19, the range of the initial value is rangeA, the number of consecutive MPSs in the context X is 4, the range at that time is rangeE, and the number of consecutive MPSs in the subsequent context Y is 2, so the range prediction The value is the sum E + I of the value stored at the position E and the value stored at the position I in the MPS continuous number table of FIG. Thus, even when the context changes, the update interval can be easily obtained by referring to the table in the same manner, so that the processing can be greatly reduced and the processing speed can be increased.

  FIG. 21 shows an example of a block diagram constituting the continuous MPS process prediction unit 400B that realizes continuous MPS process prediction when the context changes. The continuous MPS process predicting unit 400B shown in this figure provides two prediction tables 420A and 420B (MPS continuous number table), and when a range, a context, and an MPS continuous number are input, a range corresponding to these parameters is input. The prediction value is referred to, and “range” is output as the corresponding value. The contexts in the prediction tables 420A and 420B are updated as appropriate. In this example, the context is described as having two types of X and Y. Needless to say, it is possible to prepare a plurality of tables corresponding to more contexts.

FIG. 22 shows a more detailed block diagram of the continuous MPS process prediction unit 500. As shown in this figure, the continuous MPS process prediction unit 500 includes a first context update table 530, a second context update table 532, a first range table 520, a second range table 522, and a renormalization table. A renormalization unit 550 is provided. The continuous MPS process predicting unit 500 refers to the second range table 522 based on the range, the MPS continuous number X (4 in the example of FIG. 19), and the context A (context X in FIG. 19), and ranges ′ (range E). Ask for. On the other hand, based on the context B (context Y in FIG. 19), the MPS continuation number Y (2 in FIG. 19), and the range ′ obtained in the second range table 522, the first range table 520 is referred to and range ″ is obtained. On the other hand, based on the number of renormalizations in the first range table 520 and the second range table 522 and the value of low, the renormalization unit 550 refers to the renormalization table to low ′ and the sign bit by renormalization. Thus, the renormalization with different contexts can be added by one renormalization unit 550 to output appropriate code bits, which contributes to simplification of the circuit. A is updated to context A ′ by referring to the second context update table 532 based on the number of consecutive MPSs, and the context is updated. Refers to the first context update table 530 based on the B on MPS number of consecutive updates the context B '. Further, as described above, it is possible to increase the number of context change.
(Modification of arithmetic coding unit for performing continuous MPS process prediction)

  Similarly to FIG. 29 described above, in the continuous MPS process prediction, the context update table is composed of each ROM, and one of them is composed of a combinational circuit in order to obtain a cheaper and more stable speed. Both can be configured by a combinational circuit. An example of such an arithmetic encoding unit 316 is shown in FIG. FIG. 31 is also a block representation of processing steps, so the context memory unit 217B is displayed in duplicate, but both are the same.

  The arithmetic encoding unit 316 shown in this figure also includes a context memory unit 217B connected to the output side of the first and second context update tables 230B and 232B, and a first output side connected to the first output side of the context memory unit 217B. 1 context update table 230B, and 2nd context update table 232B connected to the 2nd output side, These structures are as substantially the same as FIG. That is, the first context update table 230B is configured by a combinational circuit, and the second context update table 232B is configured by a ROM. Alternatively, both the first context update table 230B and the second context update table 232B may be configured by combinational circuits. In particular, when the amount of data to be stored is small, the mounting area does not increase, and therefore a configuration with only a combinational circuit that can achieve higher speed is preferable.

  The arithmetic encoding unit 316 also includes a range memory unit 218B that holds a value of “range” and a low memory unit 219B that holds a value of “low”, which can also be configured by a register or the like. Since these members can be configured in substantially the same manner as in FIG. 29, detailed description will be omitted.

  On the other hand, the arithmetic coding unit 316 receives the number m of consecutive symbols A (MPS) and the corresponding context X, receives the first range table 520B for updating the range read from the range memory unit 218B to range ′, and the symbol B ( MPS) is provided with a second range table 522B that inputs the number of consecutive n and the corresponding context Y, updates range ′ of the first range table 520B, and outputs “range”. These range tables are based on the number of MPS sequences. Further, the arithmetic encoding unit 316 performs renormalization based on the range ′ updated in the first range table 520B and the number of renormalizations, and updates low in the low memory unit 219B, as in FIG. And low 'and the sign bit 1 are output. 1 low update unit 250B, and the second range table 522B is re-normalized based on “range” and the number of re-normalization, and low ”obtained by the first low update unit 250B is updated to low” and the sign bit 2 is output. A second low update unit 252B.

FIG. 31 is also a block diagram representing the processing steps and the data flow in the same manner as FIG. 29, and therefore does not necessarily match the actual hardware connection. For example, the context memory unit 217B is displayed in an overlapping manner, but both are the same. In FIG. 31, the left context memory unit 217B shows an operation at the time of reading, and the central context memory unit 217B shows an operation at the time of writing. Yes.
(MPSE arithmetic coding process)

  This arithmetic encoding unit 316 can also perform arithmetic encoding processing of symbols A and B in four stages of steps S′1 to S′4 as shown in the flowcharts of FIGS. 31 and 32. That is, in the first stage shown in step S′1, each context is read. Specifically, the context memory unit 217B reads (reads) the contexts X and Y corresponding to the symbols A and B.

  Next, in the second stage indicated by step S'2, each context is updated. Specifically, the first context update table 230B reads the context X from the first output of the context memory unit 217B, and further updates it to the context X ′ based on the MPS consecutive number m of the symbol A. Also, the updated context X ′ is referred to by the second context update table 232B, and on the other hand, the context Y ′ is determined based on the context Y obtained from the second output of the context memory unit 217B and the MPS continuous number n. Update.

  Further, in the third stage indicated by step S'3, the updated context is written and the range is updated. That is, the contexts X ′ and Y ′ output from the first context update table 230B and the second context update table 232B are written in the context memory unit 217B. In this way, in the first and second context update tables 232B, the contexts (occurrence probabilities) corresponding to the MPS processed are updated in step S'2, and written in the context memory unit 217B in step S'3.

  On the other hand, for the symbol A, the first range table 520B updates the range value to range ′ based on the MPS continuation number m and its context X. The range value is read from the range memory unit 218B. Further, for the symbol B, the second range table 522B updates the value of range ′ to “range” based on the MPS consecutive number n and its context Y. The updated value of “range” is written to the range memory unit 218B.

  Finally, low is updated in the fourth stage indicated by step S'4. The first low update unit 250B updates the low value held in the low memory unit 219B to low ′ according to the range ′ and the number of renormalizations, and outputs the sign bit 1 of the symbol A. On the other hand, the second low update unit 252B updates low 'to low "according to the range" and the number of renormalizations, and updates the low value of the low memory unit 219B to low ". Also, the sign bit 2 of the symbol B This method is effective only when the symbol is MPS, but an arithmetic coding unit 316 capable of processing two symbols in one cycle can be realized with a simple arithmetic circuit as in FIG.

In this way, it is possible to perform arithmetic coding of the next symbol without waiting for the calculation of the previous symbol, so that pipeline processing is possible, and high-speed processing that was previously considered impossible is possible. Figured. FIG. 33 shows an example of such pipeline processing. As shown in FIG. 33, arithmetic coding processing can be performed in parallel for three symbols, so processing of two symbols or more can be performed in one cycle.
(Switching between the two methods)

  As described above, the 2-cycle prediction has an advantage that processing for one cycle is reduced and prediction is possible in many scenes. On the other hand, the continuous MPS process prediction can reduce the processing for several cycles and has a large reduction amount, but has a restriction that it can be predicted only when the MPS continues.

  Therefore, it is possible to further increase the speed by combining these two-cycle prediction and continuous MPS process prediction, selecting a more effective method according to the situation, and switching and using these methods. As Embodiment 3 of the present invention, an example of an arithmetic coding apparatus including such a prediction technique switching unit is shown in FIGS. The arithmetic coding apparatus 600 shown in these figures also includes a context calculation unit 614, a first memory unit 617, a second memory unit 618, and an arithmetic coding unit 610, as in FIG. These members are basically the same as those shown in FIG. The arithmetic coding unit 610 includes an input buffer 621 for buffering two input signals, a 2-cycle prediction unit 622, a continuous MPS process prediction unit 623, and a prediction method switching unit 624 for switching these. The prediction method switching unit 624 selects and switches an appropriate prediction method at that time according to the input context, range, or the like. In the example of FIG. 23, the state where the 2-cycle prediction unit 622 is selected is shown, and in the example of FIG. 24, the state where the continuous MPS process prediction unit 623 is selected is shown. Thereby, the number of cycles can be reduced by appropriately combining the 2-cycle prediction and the continuous MPS process prediction.

FIG. 25 shows how the prediction method switching unit 624 switches between 2-cycle prediction and continuous MPS process prediction. As shown in this figure, based on the state of the binarized bit string, the prediction method switching unit 624 performs these switching. Here, as a switching condition, continuous MPS process prediction is used only when the input bits are continuous “0”, and in other cases, 2-cycle prediction is used. The prediction method switching unit 624 selects one of the methods according to this condition, and performs processing according to the selected method.
(Example)

  Next, as an example of the present invention, arithmetic coding was performed for each of two-cycle prediction, continuous MPS process prediction, and switching between them, and the ratio of the number of cycles to be reduced was obtained by simulation. Here, the number of contexts input in a batch is set to 2, and arithmetic coding is performed on various image sequences for simulation (akiyo, bridge-close, bridge-far, carphone, clair), and the simulation results are respectively displayed. 1 to Table 5. In the table, DSE indicates 2-cycle prediction, MPSE indicates continuous MPS process prediction, and DSE + MPSE indicates an example in which these are switched. As shown in this table, the calculation amount can be reduced by 2-cycle prediction and continuous MPS process prediction for any sequence, and the 2-cycle prediction shows particularly good results. Moreover, in the method of switching between them, the calculation amount can be further reduced, and the usefulness of the present embodiment has been confirmed. According to the simulation results, the reduction rate improved as the number of context change permission increases. However, increasing the number of context changes allowed increases the number of cycles that can be reduced, but it also has the demerit that the circuit configuration becomes complex and the circuit area increases, so the cycle number reduction effect and the cost required for the circuit configuration are required. It is determined as appropriate according to the specifications.

  Note that an arithmetic coding apparatus according to another embodiment includes a binarization unit for binarizing a multilevel signal and an arithmetic code for arithmetic coding of a binary symbol generated by the binarization unit. An update unit, a context calculation unit for generating a context number, and a symbol value and a symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit An arithmetic coding device comprising: an update unit; and a probability state storage unit for storing a symbol value and a symbol appearance probability, with the context number calculated by the context calculation unit as an index. A first storage unit that stores the predicted value of the region rLPS obtained by dividing the inferior symbol section based on the occurrence probability, and a second storage unit that is also separate from the first storage unit that stores the predicted value of rLPS. A storage unit, a first arithmetic unit that performs arithmetic coding with reference to the predicted value of rLPS stored in the first storage unit and an initial section, and updates the section, and an rLPS stored in the second storage unit. A second arithmetic unit that performs arithmetic coding with reference to the predicted value and the update interval updated by the first arithmetic unit, and updates the symbol appearance probability and the symbol value indicated by the dominant symbol. And a second context update table separate from the first context update table for updating the symbol appearance probability and the symbol value indicated by the dominant symbol, and the first context update table is input The combinational circuit can input the output to the second context table during the same cycle. As a result, high-speed arithmetic coding capable of processing 2 bits or more in one cycle can be realized.

  In the arithmetic coding apparatus, the first context update table and the second context update table can be configured by a combinational circuit. This speeds up the processing. Note that the first context update table may be composed of a ROM and the second context update table may be composed of a combinational circuit, whereby arithmetic coding can be realized at low cost.

  The arithmetic coding apparatus, the arithmetic coding method, the arithmetic coding program, and the computer-readable recording medium storing the program of the present invention are useful for applications in which a moving image signal is compressed and recorded or transmitted. The present invention can be suitably used in devices that process high-quality moving images, such as portable terminal devices, moving image capturing devices, and moving image recording / reproducing devices, and their application fields.

H. 1 is a block diagram illustrating a moving image encoding / decoding device that obtains a bitstream from image data by H.264 / AVC encoding processing. It is a conceptual diagram for demonstrating the concept of arithmetic encoding / decoding. It is a conceptual diagram which shows the procedure which performs binary arithmetic coding. It is a block diagram which shows the arithmetic coding apparatus which performs a CABAC process. It is a block diagram which shows the detail of the binary arithmetic coding part of FIG. It is a conceptual diagram which shows the procedure of renormalization. It is a block diagram which shows an arithmetic coding apparatus. It is a conceptual diagram which shows operation | movement of the arithmetic coding apparatus of FIG. It is a block diagram which shows the arithmetic coding apparatus which concerns on this Embodiment 1. FIG. 10 is a conceptual diagram illustrating a first memory unit in FIG. 9. It is a block diagram which shows the modification of the arithmetic coding apparatus which concerns on this Embodiment 1. FIG. It is a block diagram of the arithmetic coding part of the arithmetic coding apparatus shown in FIG. It is a conceptual diagram which shows the operation | movement of the arithmetic coding part of FIG. It is a block diagram which shows the arithmetic coding part which concerns on another structure. It is a conceptual diagram which shows the procedure of continuous MPS process prediction. It is a conceptual diagram which shows the MPS continuous number table in case a context is constant. FIG. 17A is a conceptual diagram showing how renormalization is performed, and FIG. 17B is a conceptual diagram showing range prediction taking renormalization into consideration. It is a block diagram of the continuous MPS process prediction part in consideration of renormalization. It is a conceptual diagram which shows a mode that a context changes in a continuous MPS process. It is a conceptual diagram which shows the example of a MPS continuous number table. It is a block diagram which comprises the continuous MPS process prediction part which implement | achieves continuous MPS process prediction when a context changes. The block diagram of a detailed continuous MPS process prediction part is shown. It is a block diagram which shows the arithmetic coding apparatus which concerns on Embodiment 3 of this invention. It is a block diagram which shows the arithmetic coding apparatus which concerns on Embodiment 3 of this invention. It is a block diagram which shows a mode that 2-cycle prediction and continuous MPS process prediction are switched by the prediction method switch part. H. 3 is a flowchart of a process for arithmetic coding / decoding according to H.264 / AVC. H. 1 is a block diagram illustrating an arithmetic coding apparatus that embodies a processing process of H.264 / AVC arithmetic coding. It is a block diagram which shows the conventional arithmetic coding apparatus. It is a block diagram which shows the modification of the arithmetic coding part which performs 2 cycle prediction. It is a flowchart which shows the procedure of the arithmetic encoding by the arithmetic encoding part of FIG. It is a block diagram which shows the modification of the arithmetic coding part which performs continuous MPS process prediction. It is a flowchart which shows the procedure of the arithmetic encoding by the arithmetic encoding part of FIG. FIG. 32 is a timing chart showing how the arithmetic codes in FIGS. 29 and 31 are performed by pipeline processing. FIG.

Explanation of symbols

1 ... DMA
2 ... motion search unit 3 ... deblocking filter 4 ... motion compensation unit 5 ... transform unit 6 ... quantization unit 7 ... inverse quantization unit 8 ... inverse transform unit 9 ... overall control unit 10 ... arithmetic coding / decoding device 10A ... Arithmetic coding device 11 ... variable length decoding unit 12, 112 ... binarization unit 14, 114, 614 ... context calculation unit 16, 116 ... binary arithmetic coding unit 20 ... rLPS table 30 ... context change tables 40, 140 ... Calculation unit 50 ... Renormalization unit 70, 170 ... Context update unit 100 ... Moving image encoding / decoding device 117 ... First memory unit 117A ... Memory unit 118 ... Second memory unit 119 ... Prediction unit 120 ... First rLPS table 121... Output buffer 122... Second rLPS table 160, 360... Code bit generation unit 200, 300. 7, 217B ... context memory unit 218, 218B ... range memory unit 219, 219B ... low memory unit 220 ... first rLPS table 222 ... second rLPS table 224 ... first selector 226 ... second selector 230, 230B ... first context Update table 232, 232B ... second context update table 240 ... first range update unit 242 ... second range update unit 250, 250B ... first low update unit 252, 252B ... second low update unit 301 ... first arithmetic encoding means 302 ... first 2 arithmetic encoding means 320 ... 1st rLPS table 322 ... 2nd rLPS table 330 ... 1st context update table 332 ... 2nd context update table 340 ... 1st calculating part 342 ... 2nd calculating part 350 ... 1st renormalization part 352 ... second re-correction Normalization unit 400, 400B, 500 ... Continuous MPS process prediction unit 420 ... Range table 420A, 420B ... Prediction table 430 ... Context update table 450 ... Renormalization unit 520, 520B ... First range table 522, 522B ... Second range table 530 ... 1st context update table 532 ... 2nd context update table 550 ... Re-normalization unit 600 ... Arithmetic coding device 610 ... Arithmetic coding unit 617 ... 1st memory unit 618 ... 2nd memory unit 621 ... Input buffer 622 ... 2 cycles Prediction unit 623 ... Continuous MPS process prediction unit 624 ... Prediction method switching unit 700 ... Arithmetic coding device 710 ... Adaptive arithmetic coding / decoding unit 711 ... Arithmetic coding / decoding unit 712 ... Symbol appearance probability control unit 713 ... Probability state storage Unit 720 ... Context calculation unit 730 ... encoding / decoding control unit 800 ... arithmetic coding device 810 ... adaptive arithmetic coding unit 811 ... arithmetic coding unit 814 ... symbol appearance probability control unit 815 ... probability state storage unit 820 ... context calculation unit 821 ... register 822 ... comparison Determination unit 830 ... Coding control unit FM ... Frame memory

Claims (9)

A binarization unit for binarizing the multilevel signal;
An arithmetic encoding unit for arithmetically encoding the binary symbol generated by the binarization unit;
A context calculator for generating a context number;
An update unit for updating the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit;
Using the context number calculated by the context calculation unit as an index, a probability state storage unit for storing the symbol value and the symbol appearance probability;
An arithmetic encoding device comprising:
The arithmetic encoding unit is
A first storage unit that stores a predicted value of a region rLPS obtained by dividing an inferior symbol section based on the occurrence probability;
A second storage unit separate from the first storage unit, which also stores a predicted value of rLPS;
An arithmetic unit that performs arithmetic coding with reference to predicted values of rLPS stored in the first storage unit and the second storage unit;
An arithmetic coding apparatus comprising: A binarization unit for binarizing the multilevel signal;
An arithmetic encoding unit for arithmetically encoding the binary symbol generated by the binarization unit;
A context calculator for generating a context number;
An update unit for updating the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit;
Using the context number calculated by the context calculation unit as an index, a probability state storage unit for storing the symbol value and the symbol appearance probability;
An arithmetic encoding device comprising:
The arithmetic encoding unit is
An update interval storage unit for storing a predicted value of an update interval determined based on the number of consecutive dominant symbol processing at the time of dominant symbol processing, an initial interval, and a symbol appearance probability;
A context update table for storing a predicted value of the symbol appearance probability determined based on the number of consecutive dominant symbol processing during the dominant symbol processing and the initial symbol appearance probability;
A renormalization unit having a renormalization table for updating low, which is a complement of the update interval, based on the number of renormalizations;
An arithmetic coding apparatus comprising: A binarization unit for binarizing the multilevel signal;
An arithmetic encoding unit for arithmetically encoding the binary symbol generated by the binarization unit;
A context calculator for generating a context number;
An update unit for updating the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit;
Using the context number calculated by the context calculation unit as an index, a probability state storage unit for storing the symbol value and the symbol appearance probability;
An arithmetic encoding device comprising:
The arithmetic encoding unit is
A first update section storage unit that stores a predicted value of an update section determined based on the number of consecutive dominant symbol processes at the time of dominant symbol processing, an initial section, and a symbol appearance probability;
A second update interval storage unit separately from the first update interval storage unit, which also stores a predicted value of the update interval;
A first context update table for storing a predicted value of a symbol appearance probability determined based on the number of consecutive dominant symbol processing during the dominant symbol processing and an initial symbol appearance probability;
The first context update table for storing a predicted value of a symbol appearance probability determined based on the number of consecutive dominant symbol processes at the time of dominant symbol processing and the symbol appearance probability updated in the first context update table; A separate second context update table;
A renormalization unit having a renormalization table for updating low, which is a complement of the update interval, based on the number of renormalizations;
An arithmetic coding apparatus comprising: A binarization unit for binarizing the multilevel signal;
An arithmetic encoding unit for arithmetically encoding the binary symbol generated by the binarization unit;
A context calculator for generating a context number;
An update unit for updating the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit;
Using the context number calculated by the context calculation unit as an index, a probability state storage unit for storing the symbol value and the symbol appearance probability;
An arithmetic encoding device comprising:
The arithmetic encoding unit is
A first storage unit that stores a predicted value of a region rLPS obtained by dividing an inferior symbol section based on the occurrence probability;
A second storage unit separate from the first storage unit, which also stores a predicted value of rLPS;
An arithmetic unit that performs arithmetic coding with reference to predicted values of rLPS stored in the first storage unit and the second storage unit;
A two-cycle prediction unit comprising:
An update interval storage unit for storing a predicted value of an update interval determined based on the number of consecutive dominant symbol processing at the time of dominant symbol processing, an initial interval, and a symbol appearance probability;
A context update table for storing a predicted value of the symbol appearance probability determined based on the number of consecutive dominant symbol processing during the dominant symbol processing and the initial symbol appearance probability;
A renormalization unit having a renormalization table for updating low, which is a complement of the update interval, based on the number of renormalizations;
A continuous dominant symbol processing prediction unit comprising: a prediction method switching unit that switches between the two-cycle prediction unit and the continuous dominant symbol processing prediction unit;
An arithmetic coding apparatus comprising: In the arithmetic coding of binary symbols, the dominant symbol that is a symbol with a high appearance probability and the inferior symbol that is a symbol with a low appearance probability are coordinate values of a section on the number line to the previous symbol and a section on the number line of the inferior symbol. To correspond to a predetermined section on the number line,
An arithmetic encoding method for outputting an encoded signal from an interval correspondence result on the number line and an input binary symbol,
Referring to the first rLPS table in which the interval coordinate value at the time of dominant symbol processing when the symbol to be encoded is the dominant symbol and the interval coordinate value at the time of inferior symbol processing when it is the inferior symbol are recorded in advance. Obtaining a segmented area in which the symbol interval is updated;
A step of obtaining a divided region in which a section of a second symbol following the first symbol is updated with reference to the obtained divided region and a second rLPS table separate from the first rLPS table;
Performing renormalization as necessary and outputting an output code;
Updating the context number;
An arithmetic coding method comprising: In the arithmetic coding of binary symbols, the dominant symbol that is a symbol with a high appearance probability and the inferior symbol that is a symbol with a low appearance probability are coordinate values of a section on the number line to the previous symbol and a section on the number line of the inferior symbol. To correspond to a predetermined section on the number line,
An arithmetic encoding method for outputting an encoded signal from an interval correspondence result on the number line and an input binary symbol,
A step of obtaining a predicted value of an update section with reference to the update section storage unit based on the number of consecutive dominant symbols and the context number when the dominant symbols of the binary symbols are continuous;
Updating using a context update table that stores context numbers;
An arithmetic coding method comprising: In the arithmetic coding of binary symbols, the dominant symbol that is a symbol with a high appearance probability and the inferior symbol that is a symbol with a low appearance probability are coordinate values of a section on the number line to the previous symbol and a section on the number line of the inferior symbol. To correspond to a predetermined section on the number line,
An arithmetic code program for outputting an encoded signal from an interval corresponding result on the number line and an input binary symbol,
Referring to the first rLPS table in which the interval coordinate value at the time of dominant symbol processing when the symbol to be encoded is the dominant symbol and the interval coordinate value at the time of inferior symbol processing when it is the inferior symbol are recorded in advance. A function for obtaining a divided region in which a symbol section is updated;
A function for obtaining a divided region obtained by updating a section of a second symbol following the first symbol with reference to the obtained divided region and a second rLPS table separate from the first rLPS table;
A function that performs renormalization as necessary and outputs an output code;
The ability to update the context number,
An arithmetic coding program characterized by causing a computer to realize the above. In the arithmetic coding of binary symbols, the dominant symbol that is a symbol with a high appearance probability and the inferior symbol that is a symbol with a low appearance probability are coordinate values of a section on the number line to the previous symbol and a section on the number line of the inferior symbol. To correspond to a predetermined section on the number line,
An arithmetic encoding program for outputting an encoded signal from a section correspondence result on the number line and an input binary symbol,
A function for obtaining a predicted value of an update interval by referring to an update interval storage unit based on the number of consecutive dominant symbols and a context number when the dominant symbol of the binary symbol is continuous;
A function for updating using a context update table for storing context numbers;
An arithmetic coding program characterized by causing a computer to realize the above.   A computer-readable recording medium storing the program according to claim 7 or 8.

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