WO2007102518A1 - Arithmetic encoding device, arithmetic encoding method, arithmetic encoding program, and computer-readable recording medium containing the program - Google Patents

Abstract

[PROBLEMS] To reduce a calculation amount of the process of CABAC in H.264/AVC. [MEANS FOR SOLVING PROBLEMS] An arithmetic encoding device includes: an arithmetic encoding unit for arithmetically encoding a digital symbol generated by a digitization unit; a context calculation unit for generating a context number; an update unit for updating a symbol value indicated by a superior symbol or an inferior symbol and symbol appearance possibility according to the digitized symbol generated by the digitization unit; and a possibility state storage unit for storing the symbol value and the symbol appearance possibility by using the context number calculated by the context calculation unit as an index. The arithmetic encoding unit includes: a first storage unit for storing a prediction value of a region rLPS obtained by dividing an inferior symbol section according to the generation possibility; a second storage unit different from the first storage unit, also for storing a prediction value of the rLPS; and a calculation unit for performing arithmetic encoding by referencing a prediction value of the rLPS stored in the first storage unit and the second storage unit.

Description

 Specification

 Arithmetic encoding device, arithmetic encoding method, arithmetic encoding program, and computer-readable recording medium storing program

 Technical field

 [0001] The present invention relates to an arithmetic coding technique used for video coding 'decoding, and in particular, CABAC (Context-based Adaptive Binary Arithmetic Coding) in H.264ZAVC, which is a video coding standard. The present invention relates to an arithmetic encoding device, an arithmetic encoding method, an arithmetic encoding program, and a computer-readable recording medium storing the program.

 Background art

 [0002] In recent years, high-definition moving images such as DVDs and terrestrial digital high-definition have been rapidly spreading, and the amount of information has increased dramatically due to the high bit rate and high resolution of moving images. Image data must be compressed. There are five main technologies for digital video compression: predictive coding, motion processing, transform coding, quantization, and code allocation. Among these, code allocation efficiently assigns codes “0” and “1” to the quantization level and the like to reduce redundant codes. For code allocation, variable-length coding, adaptive coding, fixed-length coding, and the like are known. Variable length coding (VLC) is divided into Huffman coding, run length coding, arithmetic coding, and adaptive bit allocation. Among these, arithmetic coding is to create a code table according to the appearance probability of a symbol and perform code allocation.

 Arithmetic coding is capable of optimal code allocation according to the characteristics of image data, and therefore has better coding efficiency than Huffman coding using a fixed coding table. However, since arithmetic coding is a dynamic method that creates a coding table and assigns codes while calculating the appearance probability of symbols, it generally requires more computational processing than Huffman coding. There is a problem of need.

[0004] On the other hand, the ITU-T (International Telecommunication Union-Telecommunication Standardization Sector) has developed the H.264 standard as a video coding * decoding technology. (See Non-Patent Document 1). Patent Document 1 discloses an example of a specific method for realizing an arithmetic code decoding process according to ITU-T standard H.264. FIG. 26 is a flowchart of the process of arithmetic coding / decoding according to H.264 / AVC. This figure is a re-edited version of Fig. 9-1 of Non-Patent Document 1 with a focus on functions. The flow of arithmetic coding and decoding will be described below with reference to FIG.

 [0005] When encoding or decoding of a syntax element (SE) is started, context calculation is performed on the syntax element in step 1. In context calculation, the context number corresponding to the context is obtained, and the symbol value and the probability state are obtained from the context number. Symbol values are often obtained by referring to the correspondence table, with some exceptions. The probability state is obtained by referring to the value stored in Step 3 described later. The determined symbol values and probability states are given to the arithmetic coding 'decoding process and go to step 2.

 [0006] In step 2, the symbol value and probability state received in step 1 are used to perform arithmetic coding or decoding of the syntax, and the result is output as an output signal. At the same time, the code information or the decoded symbol information is output to the symbol appearance probability control process, and the process proceeds to Step 3.

 [0007] In step 3, the information of the encoded or decoded symbol is received, the symbol value and the update value of the probability state used in the next processing are obtained and stored as the probability state.

 [0008] In step 4, it is determined whether or not the encoding or decoding of the syntax element has been completed. If not, the process returns to step 1 and the same process is performed until encoding or decoding is completed. repeat. When the encoding or decoding of the syntax element is completed, the next syntax element is encoded or decoded.

FIG. 27 shows a block diagram of an arithmetic coding apparatus that embodies the H.264 / AVC arithmetic coding process. The arithmetic coding apparatus 700 includes an adaptive arithmetic coding / decoding unit 710, a context calculation unit 720, and an encoding / decoding control unit 730. The adaptive arithmetic coding / decoding unit 710 includes an arithmetic coding / decoding unit. 711, a symbol appearance probability control unit 712, and a probability state storage unit 713. The context calculation unit 720 obtains a context number from the type of the syntax element (SE) of the input signal (Sin) S11 and the number of already-signed bits or the number of decoded bits. Generate (corresponds to step 1 in Fig. 26).

 [0010] In this arithmetic coding apparatus 700, each processing step needs to start processing in that step in response to the processing result in the previous step, so the operation is sequential processing. The time for which one syntax element is processed is the sum of each processing step. That is, for example, the section SO required for the processing of the syntax element 0 is the sum of the time spent for the processing 51, the processing 52, the processing 53, and the processing 54, respectively.

 [0011] When the processing code amount (that is, the number of syntax elements) per coding or decoding time is large, it is an essential requirement to shorten the coding or decoding processing time. In the arithmetic coding / decoding device 40 of the present study example, each step performs sequential processing. Therefore, in order to reduce the overall processing time, the processing time of each step must be reduced. However, at the current technology level, there is a limit to speeding up.

 On the other hand, Patent Document 1 discloses an arithmetic encoding device that speeds up arithmetic encoding processing. This arithmetic coding apparatus 800 includes an adaptive arithmetic coding unit 810, a context calculation unit 820, and a coding control unit 830 as shown in the block diagram of FIG. The context calculation unit 820 includes a register 821 and a comparison determination unit 822. The adaptive arithmetic coding unit 810 includes an arithmetic code key unit 811, a symbol appearance probability control unit 814, and a probability state storage unit 815. According to this, since a context calculation unit 820 can obtain a context for the next input signal while a certain input signal is encoded by the arithmetic code input unit 811, the arithmetic encoding unit 811 Immediately after encoding an input signal, the next input signal can be encoded. Accordingly, the encoding process can be speeded up.

 [0013] Further, while a certain signal is encoded by the arithmetic encoding unit 811, the symbol appearance probability control unit 814 performs coding symbol power dominant symbols by the arithmetic code unit 811 and inferior symbols. In some cases, an update value of each symbol value and probability state is obtained, and after the encoded symbol is determined, one update value is selected. As a result, the arithmetic encoding unit 811 obtains a necessary symbol value and a probability state in the sign of the next code, and can immediately perform the encoding process and the writing process to the probability state recording unit 815. The arithmetic encoding process can be further speeded up.

Patent Document 1: Japanese Patent Laid-Open No. 2005-130099 Non-Patent Document 1: Joint Video Team (JVT) of ISO / IEC MPEG &ITU-TVCEG;"Draftl T U_T Recommendation and Final Draft International Standard of Joint Video Specific ation (ITU-T Rec. H.264 | lSO / IEC 14496 —10 MPEG— AVC). "

 Non-Patent Document 2: Hassan Shojania and Subramania Sudharsanan, "A VLSI Architecture for High Performance CABAC Encoding. Visual Communications and Image Proces sing 2005, Pro of SPIE Vol. 5960, pp.1444.

 Non-Patent Document 3: Rei Okubo et al. “Revised H.264ZAVC Textbook” Impress

 Non-Patent Document 4: "Patent Map by Technology Field: Electricity 14 Digital Video Compression Technology" Patent Office ^^ Patent Contribution 5: Roberto R. Osorio, Javier D. Bruguera, riigh-Throughput Architecture for H.264 / AVC CABAC Compression System "IEEE TRANSACTIONS ON CIRC UITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 16, NO. 11, NOVEMBE R 2006.

 Disclosure of the invention

 Problems to be solved by the invention

[0014] However, even this method is not sufficient as a measure for increasing the speed, which cannot realize 1-bit encoding in one cycle. On the other hand, Non-Patent Document 2 proposes a high-speed method that can process one binary symbol in one cycle. However, this method is not sufficient, and multiple processing is not performed in one cycle. It is difficult to say that high-speed processing can be realized.

 In the H.264 / AVC encoding processing, variable length encoding (VLC) that is entropy encoding is employed. VLC is a module that actually generates and streams H.264 / AVC bitstreams. There are CABAC and CAVLC as encoding methods. CAVLC (Context-Adaptive Variable Length Coding) is used only for the sign of quantized DCT coefficient values. CABAC (Context Adaptive Binary Arithmetic Coding), on the other hand, is an entropy coding method that uses arithmetic codes and has the advantage of higher coding efficiency than CAVLC. Have.

[0016] However, CABAC processing can achieve high coding efficiency, but processing time. There is a problem that is long. In particular, in high-resolution applications, encoding in real time requires a very high operating frequency. With existing MPUs and CPUs, operating frequencies of several GHz are required for calculations, and there is a problem that media such as media and IB broadcasts cannot be handled. For this reason, although a configuration for performing CABAC processing at high speed is desired, the conventional method is still insufficient as described above.

[0017] The present invention has been made to solve such problems. The main object of the present invention is to store an arithmetic coding device, an arithmetic coding method, an arithmetic coding program, and a program that reduce the amount of computation of CABAC processing in H.264 / AVC and facilitate implementation. To provide a computer-readable recording medium.

 Means for solving the problem

 [0018] In order to achieve the above object, a first arithmetic coding apparatus of the present invention includes a binarization unit for binarizing a multilevel signal, and a binary generated by the binarization unit The dominant symbol or the inferior symbol is indicated based on the arithmetic encoding unit for arithmetically encoding the symbol, the context calculating unit for generating the context number, and the binary symbol generated by the binarizing unit. An arithmetic code comprising: an update unit for updating the symbol value and the symbol appearance probability; and a probability state storage unit for storing the symbol value and the symbol appearance probability using the context number calculated by the context calculation unit as an index The arithmetic coding unit is a first storage unit that stores a prediction value of a region rLPS divided by dividing an inferior symbol section based on an occurrence probability, and similarly stores a prediction value of rLPS. First storage A second storage unit separate from the first storage unit, and an arithmetic unit that performs arithmetic coding with reference to the predicted values of rLPS stored in the first storage unit and the second storage unit. This makes it possible to realize high-speed arithmetic coding that can process more than 2 bits in one cycle.

[0019] Further, the second arithmetic encoding device includes a binarizing unit for binarizing the multilevel signal, and an arithmetic encoding for arithmetically encoding the binary symbol generated by the binarizing unit. The symbol value and the symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the component, the context calculation unit for generating the context number, and the binary symbol generated by the binarization unit. And the context number calculated by the context calculator An arithmetic coding apparatus comprising a probability state storage unit for storing symbol values and symbol appearance probabilities as an indeterminate, wherein the arithmetic encoding unit includes a number of consecutive dominant symbol processes during the dominant symbol processing, An update interval storage unit that stores a predicted value of an update interval determined based on a symbol appearance probability, a symbol appearance probability, and a symbol determined based on an initial symbol appearance probability A context update table for storing the predicted value of the probability of occurrence and a renormalization unit having a renormalization table for updating low, which is a complement of the update interval, based on the number of renormalizations . As a result, arithmetic code processing when dominant symbol processing is continuously performed can be reduced by several cycles, and processing can be reduced and speeded up.

Furthermore, the third arithmetic coding unit includes a binarizing unit for binarizing the multilevel signal and an arithmetic encoding unit for arithmetically encoding the binary symbol generated by the binarizing unit. And the symbol calculation and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit and the context calculation unit for generating the context number. An arithmetic coding apparatus comprising: an updating unit for storing a probability state storage unit for storing symbol values and symbol appearance probabilities using the context number calculated by the context calculating unit as an index The update unit is the same as the first update interval storage unit that stores the predicted value of the update interval that is determined based on the number of dominant symbol processes, the initial interval, and the symbol appearance probability during dominant symbol processing. A second update interval storage unit that is separate from the first update interval storage unit, the number of consecutive dominant symbol processes during the dominant symbol processing, and the initial symbol appearance probability. Based on the first context update table for storing the predicted value of the symbol appearance probability to be determined, the number of consecutive dominant symbol processing during the dominant symbol processing, and the symbol appearance probability updated by the first context update table Based on the number of renormalizations and the second context update table separate from the first context update table to store the predicted value of the symbol appearance probability to be determined, low is updated as the complement of the update interval A renormalization unit having a renormalization table. As a result, the arithmetic coding process when the dominant symbol process is continuously performed can be reduced even when a plurality of different contexts are used. [0021] Further, the fourth arithmetic coding apparatus includes a binarizing unit for binarizing the multilevel signal and an arithmetic coding for binarizing the binary symbol generated by the binarizing unit. Based on the binary symbol generated by the encoding unit, context number generation unit, and binarization unit, the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol An arithmetic code input device comprising: an update unit for updating a symbol; and a probability state storage unit for storing a symbol value and a symbol appearance probability using the context number calculated by the context calculation unit as an indent What is the first storage unit that stores the predicted value of rLPS and the first storage unit that stores the predicted value of rLP S, where the arithmetic coding unit divides the inferior symbol section based on the occurrence probability? With a separate second storage A two-site prediction unit comprising an arithmetic unit that performs arithmetic coding with reference to the rLPS prediction values stored in the first storage unit and the second storage unit, and the number of consecutive dominant symbol processes during the dominant symbol processing An update interval storage unit that stores the predicted value of the update interval determined based on the initial interval and symbol appearance probability, the number of consecutive dominant symbol processing during the dominant symbol processing, and the initial symbol appearance probability A context update table for storing the predicted value of the symbol appearance probability determined, and a renormalization unit having a renormalization table for updating low, which is a complement of the update interval, based on the number of renormalizations A continuous dominant symbol processing prediction unit, and a prediction method switching unit that switches between the two-cycle prediction unit and the continuous dominant symbol processing prediction unit. As a result, the 2-cycle prediction or the continuous dominant symbol processing prediction is appropriately switched to efficiently reduce the number of cycles and realize a faster arithmetic code.

On the other hand, in the arithmetic coding method of binary symbols, a dominant symbol that is a symbol with high appearance probability and an inferior symbol that is a symbol with low appearance probability are represented on the number line up to the previous symbol. Based on the coordinate value of the section and the section on the number line of the inferior symbol, the encoded signal is output from the binary symbol input corresponding to the section correspondence result on the number line, corresponding to the predetermined section on the number line. An arithmetic coding method in which section coordinate values at the time of dominant symbol processing when the symbol to be encoded is a dominant symbol and section coordinate values at the time of inferior symbol processing when the symbol to be encoded is an inferior symbol are recorded in advance. Referring to the lrLPS table, a step of obtaining a segmented area in which the first symbol section is updated and obtained Referring to the divided region and the second rLPS table that is separate from the first rrLPS table, a step of obtaining a divided region obtained by updating the section of the second symbol following the first symbol, and performing renormalization as necessary. Outputting an output code and updating a context number. This makes it possible to realize high-speed arithmetic coding that can process more than 2 bits in one cycle.

 [0023] In addition, the arithmetic coding method uses a dominant symbol that is a symbol having a high appearance probability and a low symbol that has a high probability of appearance and an inferior symbol that is a symbol having a high appearance probability up to the previous symbol. Based on the coordinate values of the section on the number line and the section on the number line of the inferior symbol, it is made to correspond to a predetermined section on the number line, and the sign signal is derived from the section corresponding result on the number line and the input binary symbol. This is an arithmetic coding method to be output. When the dominant symbols of binary symbols are consecutive, the predicted value of the update interval is calculated by referring to the update interval storage unit based on the number of consecutive dominant symbols and the context number. And a step of updating using a context update table storing a context number. As a result, the arithmetic coding process when the dominant symbol processing is continuously performed can be reduced by several cycles, and the processing can be reduced and speeded up.

[0024] Further, in the arithmetic coding of the binary symbol, the arithmetic code 匕 program converts the symbol with a high appearance probability, a dominant symbol as a symbol, a symbol with a low appearance probability, and a symbol as an inferior symbol to the previous symbol. Based on the coordinate values of the section on the number line and the section on the number line of the inferior symbol, it is made to correspond to a predetermined section on the number line, and the sign signal from the binary symbol inputted as a result of the section correspondence on the number line An arithmetic code program to be output, which records in advance the coordinate values for the dominant symbol processing when the symbol to be encoded is the dominant symbol, and the coordinate values for the inferior symbol processing when the symbol is an inferior symbol. The first rLPS table is referred to, and a function for obtaining a divided region in which the first symbol section is updated, and the obtained divided region and a second rLPS table separate from the lrLPS table are referred to. Then, a function for obtaining a segmented area obtained by updating the second symbol section following the first symbol, a function for performing renormalization as necessary, outputting an output code, and a function for updating a context number are provided. Make it a computer. This makes it possible to realize high-speed arithmetic coding that can process more than 2 bits in one cycle. [0025] Furthermore, the arithmetic coding program uses a symbol having a high probability of occurrence, a symbol having a high probability of appearance and a symbol having a low probability of appearance, and a symbol having a low probability of occurrence as a symbol. Based on the coordinate values of the section on the number line up to the symbol and the section on the number line of the inferior symbol, it is made to correspond to a predetermined section on the number line and encoded from the section corresponding result on the number line and the input binary symbol An arithmetic coding program that outputs a signal, and when the dominant symbols of the binary symbol are consecutive, the predicted value of the update interval is referred to the update interval storage unit based on the number of consecutive dominant symbols and the context number. And a function to update using a context update table that stores context numbers. As a result, the arithmetic coding process when the dominant symbol process is continuously performed can be reduced by several cycles, and the process can be reduced and speeded up.

 [0026] A computer-readable recording medium stores the above-described program. Recording media include CD_ROM, CD-R, CD_RW, flexible disk, magnetic tape, M〇, DVD-ROM, DVD-RAM, DVD-R, DVD + R, DVD-RW, DVD + RW, Blue— This includes media that can store magnetic disks such as ray (registered trademark) and HD DVD (registered trademark) (AOD), optical disks, magneto-optical disks, semiconductor memories, and other programs. The program includes a program distributed in a download form through a network line such as the Internet, in addition to a program stored and distributed in the recording medium. Furthermore, the recording medium includes general-purpose or dedicated equipment in which the program is implemented in a state where it can be executed in the form of software, firmware, or the like. Furthermore, each process and function included in the program may be executed by program software that can be executed by a computer, or each part of the process or function may be performed by hardware such as a predetermined gate array (FPGA, ASIC), or It may be realized in the form of a mixture of partial hardware modules that realize some elements of software and hardware. The invention's effect

[0027] According to the computer-readable recording medium storing the arithmetic encoding device, arithmetic encoding method, arithmetic encoding program, and program of the present invention, the number of CABAC processing cycles in H.264 / AVC Can be reduced, and the processing load can be reduced and the processing speed can be increased. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiment described below exemplifies an arithmetic encoding device, an arithmetic encoding method, an arithmetic encoding program, and a computer-readable recording medium storing the program for embodying the technical idea of the present invention. Therefore, the present invention specifies an arithmetic encoding device, an arithmetic encoding method, an arithmetic encoding program, and a computer-readable recording medium storing the program as follows. Further, the present specification by no means specifies the member shown in the claims as the member of the embodiment. In particular, the dimensions, materials, shapes, relative arrangements, and the like of the components described in the embodiments are merely illustrative examples that are not intended to limit the scope of the present invention unless otherwise specified. Only. Note that the size and positional relationship of the members shown in each drawing may be exaggerated for clarity of explanation. Further, in the following description, the same name and reference sign indicate the same or the same members, and detailed description will be omitted as appropriate. Furthermore, each element constituting the present invention may be configured such that a plurality of elements are constituted by the same member and the plurality of elements are shared by one member, and conversely, the function of one member is plural members. It can also be realized by sharing.

 [0029] In this specification, connection to computers, printers, external storage devices and other peripheral devices for operation, control, input / output, display, other processing, etc. connected to the arithmetic coding device is, for example, IEEE1394, RS-232x, RS-422, RS-423, RS-485, USB, etc., serial connection, parallel connection, or 10BASE-T, 100BASE-TX, 1000B ASE—electrically connected via a network such as Τ And communicate. The connection is not limited to a physical connection using a wired connection, but may be a wireless connection using wireless LAN such as 802.lx or OFDM, radio waves such as Bluetooth, infrared, or optical communication. In addition, memory cards, magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc. can be used as storage media for storing text and image data to be searched, database construction, storage of search settings, etc.

 (Video encoding / decoding device)

[0030] FIG. 1 shows that the image data power is also converted into a bitstream by the H.264 / AVC encoding processing. FIG. 1 shows an example of a block diagram of a moving image encoding / decoding device that obtains the above. The moving image encoding / decoding device 100 shown in this figure includes a DMA1 (Direct Memory Access), a motion search unit 2 (ME), a deblocking filter 3 (DF: Deblocking Filter), and a motion compensation unit that perform memory management. 4 (MC), conversion unit 5, quantization unit 6, inverse quantization unit 7, inverse conversion unit 8, overall control unit 9, and variable length coder (VLC) A certain arithmetic encoding / decoding device 10 and a variable length decoding unit 11 (VLD: Variable Length Decoder) are provided. The arithmetic encoding / decoding device 10 performs CABAC and CAVLC as arithmetic encoding techniques. The moving image encoding / decoding device 100 is configured by hardware, and can also be processed in software by a processor. In this case, arithmetic coding is performed by an arithmetic coding program installed in the computer. In addition to general-purpose personal computers and workstations, devices that can display moving images, such as mobile phones, smartphones, PDAs, car navigation systems with communication functions, and landlines that can perform data communication, can be used as computers. .

[0031] In the moving image encoding / decoding device 100, first, a moving image to be encoded is input, and the motion search unit 2 performs a motion detection process. The motion compensation unit 4, the conversion unit 5, and the quantization unit 6 perform motion compensation processing, conversion processing, and quantization processing using the motion vector obtained by this processing. The block coefficients subjected to the quantization process and all information used for encoding are collected in the arithmetic code decoder / decoder 10 to create a bitstream. In order to create a reference frame to be used for the code of the next frame, the inverse encoding unit 7, the inverse transform unit 8, and the motion compensation unit 4 are used to perform reverse processing to create a reference frame, and the frame memory FM Keep in. If deblocking filter 3 is used before storing in frame memory FM, the effect of reducing block noise can be obtained.

[0032] The moving image encoding / decoding device 100 can perform decoding processing in addition to encoding. The processing procedure is as follows. First, the input bit stream is analyzed by the variable length decoding unit 11 that performs decoding processing, the image information in the bit stream is decoded, and the inverse quantization unit 7, The image frame is restored using the inverse transform unit 8 and the motion compensation unit 4 and stored in the frame memory FM. Thus, arithmetic coding techniques include decoding of encoded data. In this specification, arithmetic coding devices, methods, programs, etc. A description will be given on the assumption that not only encoding but also an apparatus, method, and program for performing decoding. (Arithmetic coding method)

 [0033] In the present embodiment, the CABAC processing in H.264 / AVC is accelerated. CAB AC is an arithmetic sign method. Figure 2 shows the concept of alias coding and decoding, which is basic arithmetic coding. In arithmetic coding, a real line with a lower limit of 0 or more and an upper limit of 1 is generally considered. This section is the initial range. In arithmetic sign 匕, the real line is divided based on the probability of occurrence of the dominant symbol (MPS) and the inferior symbol (Least Possible Symbol: LPS). Let the divided areas be rMPS and rLPS, respectively. After that, the area to which the symbol that is the target of code output belongs is selected. Here, it is assumed that rMPS is selected. After that, the selected rMPS is set as the next range, and this range is divided into rMPS and rLPS in the same manner, and the region to be encoded output is selected. This operation is repeated until there are no more encoding output targets, and the value that falls within the range of the range that is finally specified is output as the output value value, thereby completing the encoding. Normally, the lower limit value of the range is output as the output value value. Such a basic arithmetic sign 匕 is not realistic because the range of the interval and the value that is the input value are real values, and it is not a matter of accuracy. Therefore, the real line is made an integer interval with a finite bit width, and the problem is solved by introducing normalization to the range that is the width of the specified interval and the value that is the lower limit value of the specified interval. Normalization processing is performed by left shift operation, and the accuracy of range and value is ensured by this normalization processing. CABAC uses multiple context variable information to improve encoding efficiency.

 Next, a procedure for performing arithmetic coding (AC Arithmetic Coding) will be described with reference to FIG. In the case of binary arithmetic coding used in CABAC, based on the occurrence probability of a given binary symbol, the interval is sequentially divided between real numbers 0.0 and 1.0 according to the input signal. Here, when the input signal is 00010, the occurrence probability of “0” is 0.8, and the occurrence probability of “1” is 0.2. Therefore, when “0” in the input signal is encoded, the lower 0.8 part of the previous interval is updated as a new interval. On the other hand, if "1" is encoded, the upper 0.2 of the previous interval is updated as a new interval.

[0035] The first step 1 in Fig. 3 encodes '0', which results in an initial interval of 0.0-1.0. The lower 0.8 part (0.0 to 0.8) is updated as a new section.

[0036] Next, in step 2, "0" is encoded. As a result, on the lower side of the current section (0 · 0 to 0 · 8)

0. 8 X 0. 8 = 0.6. Apportioning (0.0 to 0.64) force S This is an updated section.

Similarly, in step 3, “0” is signed. As a result, in addition to the current interval (0.0 to 0.64), the lower limit J is 0.664 X 0.8 = 0.512 (S0.0 to 0.512) force S update interval. Become.

Next, in step 4, “1” is encoded. As a result, in the upper part of the current interval (0.0 to 0.512), the portion of 0.512 x 0.2 = 0.1024, ie ((0.512—0.1024 = 0. 4096

) ~ 0.512) = (0.4096 ~ 0.512) update interval.

[0039] In step 5, "0" is encoded again. As a result, the current interval (0. 4096-0. 5

12) The lower part of 0.1024 x 0. 8 = 0.0.08192 (0.4096 to (0.4096 + 0.0.0819

2)) = (0.4096 to 0.449152) is the update interval.

[0040] Finally, the code is determined in Step 6. The code word of arithmetic code is a binary representation of a real value that specifies the last interval. In this example, since the last update interval is (0.4096-0.49152), it is possible to take 0 · 4375, which is the shortest binary representation among the real numbers included in the interval. 0. The binary representation of 4375 is 0 · 0111, so “0111” below the decimal point is always output as a code word, excluding the first digit that is 0.

 (Block diagram of arithmetic coding device)

Next, FIG. 4 shows an example of an arithmetic coding device that performs CABAC processing. As shown in this figure, the arithmetic coding apparatus 10A includes a binarization unit 12 that converts a multilevel signal into a binary symbol, and calculates the occurrence probability of the binary symbol to be encoded according to the surrounding situation, that is, the context. It consists of a context calculation unit 14 for updating, and a binary arithmetic code unit 16 for performing arithmetic coding based on these binary symbols and binary symbol occurrence probabilities.

FIG. 5 shows details of the binary arithmetic encoding unit 16. As shown in this figure, binary arithmetic coding unit

16 includes an rLPS tape knob 20, a context change tape knob 30, an arithmetic unit, and a renormalization unit 50.

 (Renormalization)

[0043] The binary arithmetic encoding unit in CABAC also performs the same operation as described above for arithmetic encoding. However, the number of digits in the register, which is the storage element that actually holds the section, is finite. For this reason, when the upper bits of the section to be output are determined, a fixed bit is output in a timely manner, and renormalization processing is added to widen the update section.

 [0044] The renormalization procedure will be described with reference to FIG. As a result of signing 0 in step 1, the update interval is (0 to 0.8). Next, as a result of encoding 1 in step 2, the upper 0.2 part (0.64 to 0.8) of the interval (0.0 to 0.8) becomes the update interval. At this stage, it is determined that the representative value of the section to be output is 0.5 or more. In other words, since it is determined that the first bit is “1”, “1” is output as step 3 at this time, and the interval from (0.5 to 1.0) is set to (0. : Map (map) to enlarge to 1.0). Here, the interval from (0. 64 to 0.8) is defined as (((0. 64-0.5) X 2 = 0.28) to ((0. 8-0.5) X 2 = 0.6. )) = (0. 28-0. 6). In this way, it becomes clear that the coordinate value of the section becomes 0.5 (0.1 in binary expression) or more during the processing (in this example, when 1 is encoded in step 2). At that time, the first decimal place "1" is output. At the same time, by subtracting 0.5 from the interval and doubling it, the interval can be substantially expanded and the number of usable digits can be increased. On the other hand, when the coordinate value of the section is smaller than 0.25, it is found that the first bit is “0”. This process prevents the number of real digits representing the width of the interval from increasing, and makes it possible to perform sign-up by calculating a limited number of digits.

 [0045] In the above example, for the sake of explanation, the force with a fixed occurrence probability of binary symbols can be changed adaptively for each operation in practice. The context calculator 14 plays the role of giving the occurrence probability of the binary symbol to the binary arithmetic code part.

 (CABAC operation)

 [0046] The CABAC operation is to update the update interval, that is, range (update interval) and low

 There are two types of operations (MPS (Most Possible Symbol) processing) and LPS (Least Possible Symbol) processing, which are classified into (except for the update interval). In the example of FIG. 3, this corresponds to the processing power SMPS for encoding 0, and the process for encoding 1 corresponds to LPS.

 [0047] During MPS processing, range and low are determined by the following equations.

 range = range— rLP¾

 low = low

On the other hand, during LPS processing, range and low are determined by the following equations. range = rLPS

 low = low + range— rLPS

 Which of these processes is performed is determined by the context and range. The context indicates the probability of occurrence of the binary symbol and is updated when the symbol is processed

[0049] The context is held and updated by the context calculator 14 shown in FIG. The context calculation unit 14 holds a plurality of binary symbol occurrence probabilities, and switches the occurrence probabilities according to the current encoding target and the surrounding situation, that is, the context, and supplies it to the binary arithmetic encoding unit 16. The occurrence probability of a binary symbol is stored in the occurrence probability table, and the occurrence probability is high. Either 0 or 1 (MPS: Most Probable Symbol: the symbol with the highest occurrence probability) and its occurrence probability table number (pStateldx) is stored in association with each other. When the occurrence probability table number is specified, the corresponding occurrence probability is obtained.

 (Conventional CABAC processing)

 [0050] Next, in the conventional arithmetic coding apparatus that performs CABAC processing, the binary arithmetic code input section 16 is given from the binarization section 12 according to the occurrence probability (context) given from the context calculation section 14 The procedure for encoding binary symbols and updating intervals will be described with reference to the block diagram in FIG. 7 and the operation diagram in FIG.

7 includes an arithmetic unit 40, an rLPS tape knob 20, and a context update unit 70. The arithmetic coding apparatus 200 includes, as input terminals, a range input and / or low input for inputting a section, a binary string input, and a context input. The range input and low input are connected to the arithmetic unit 40 and the rLPS table 20, respectively. The binary string input is connected to the arithmetic unit 40, the rLPS tape knob 20, and the context update unit 70. Further, the context input is connected to the rLPS tape glue 20 and the context update unit 70. Here, r LPS tape 20 is a table for selecting rLPS according to the specified range and context. The arithmetic unit 40 includes a renormalization unit, generates a sign bit at the time of renormalization, and outputs an output code from the arithmetic unit 40. The context is updated after updating range, low. The context update unit 70 updates and outputs the context based on the previous processing result. [0052] The calculation unit 40 performs arithmetic coding calculation. Here, the input range “range” and / or “low” and the corresponding rLPS are determined by referring to the rLPS table 20, the range is updated based on these, and range “low” is output.

 This processing will be described based on the operation diagram of FIG. Here, (cycle 1) MPS processing, (cycle 2) LPS processing and renormalization processing are described for a predetermined section. That is, first, in cycle 1, for the interval for which range and low are determined, in the case of binary symbol A and the corresponding context X, the arithmetic unit 40 performs MPS processing and performs sign sign 、, Update to range 'and low'. here,

range = range— ^ Ρ¾ _Λ

 low = low

 It becomes. On the other hand, the context update unit 70 updates the context X. Then, in cycle 2, in the case of binary symbol B and corresponding context Y, the range and low 'are encoded by the arithmetic unit 40-power SLSP process, and the interval is updated to range "and low". Here range = rLPS,

 iow = iow + range — rLP ^

 It becomes. On the other hand, the context update unit 70 updates the context Y.

[0054] Further, renormalization is performed to expand the interval to range "'and low"'. As a result,

 range = grange —0. 5) X 2

 low "'= (low, 1 0 · 5) Χ 2

 It becomes. Further, the calculation unit 40 outputs the output code “1”. Thus, the conventional CABAC process required two cycles to complete the above process.

[0055] On the other hand, with the recent high definition of images, H.264ZAVC code processing is performed in real time. It is. However, in the above configuration, the range and low values depend on the previous processing, so there is a problem that the operation cannot be pipelined. In other words, in the arithmetic coding of P-connected symbols, the processing of the second symbol depends on the previous processing (the processing of the first symbol) not only for range and low but also for the value of rLPS. For this reason, it was considered difficult to process more than 2 symbols in one cycle. In other words, conventionally, as a method for increasing the execution speed of CABAC, focusing on processing of each processing unit of the CABAC device, memory access, parallel operation of the encoder portion, etc., how efficiently data processing is performed. Realization of processing of 1 symbol / cycle is being researched, focusing on the method of whether or not to perform. However, CABAC symbol processing always has a feature that depends on the appearance probability of past symbols. The context that needs to be updated when processing each symbol, rLPS, must obtain the processing result of the immediately preceding symbol. Les. For this reason, in the past, due to the nature of dependence on the processing in the previous stage, it is thought that increasing the processing hardware will not improve the efficiency of the processing, and sufficient speedup is not realized. Regardless, it was understood that the processing speed of one symbol / cycle was the limit of speedup.

 On the other hand, in the present invention, the calculation procedure of the appearance probability of the symbol is analyzed, and the detailed relationship of the dependency between the symbols is clarified. As a result, depending on the situation, the dependency between symbols was lost, and the process of the next cycle was executed in advance, and a method that could simultaneously update the table was developed.

 (2 cycle prediction)

[0058] In the present embodiment, two pieces of context update table, rLPS table, and operation unit are provided in order to input information necessary for 2-symbol processing at once and perform 2-symbol processing in one cycle. ing. Here, the context required to calculate range and low, ie, the binary string, syntax elements, and surrounding context (context) is used to determine the context to use for the generated binary string. The rLPS table is created in advance, and it is possible to predict the previous calculation by referring to it during processing. Furthermore, by preparing two rLPS tables, different rLPS for processing for two cycles can be referred to at the same time. For example, one table is the first rLPS tape record that records LPS for MPS processing, and the other is a table that stores the second rLPS that records LPS for LPS processing. Both MPS processing and LPS processing are performed in one cycle. It can correspond to. Each rLP S table uses multi-port (dual port) memory, and can be written and read simultaneously from two access ports. As a result, when data is being read from or written to one access port, data can be read using the other access port. Etc. can be done. As a result, two processors can access the same memory at the same time, and two cycles of processing can be completed within one cycle, reducing the number of processing cycles and increasing the speed of CABA C processing.

[0059] Note that to read and write two contexts from memory at the same time, it is expected that a maximum amount of memory four times that of the conventional one will be required depending on the contents of the update context. Also, if only twice the amount of memory is used, two cycles of processing are required when the same context needs to be updated, reducing the processing speed. Similarly, 3 symbols can be processed. The memory capacity of the power context is about six times that of the conventional one. In this way, it is necessary to design an appropriate configuration according to the balance between performance and hardware specifications, and required processing capacity and speed. Preferably, the information to be input at a time is for two symbols, and switching between two-cycle prediction and continuous MPS processing prediction described later can maintain high processing speed without depending much on the image. it can. Hereinafter, the description will be made sequentially.

 (Embodiment 1)

 FIG. 9 shows the arithmetic coding apparatus according to the first embodiment. The arithmetic coding apparatus shown in this figure calculates a binarization unit 112 that converts a multilevel signal into a binary symbol, and calculates the occurrence probability of a binary symbol to be encoded according to the surrounding situation (context). The context calculation unit 114 for updating, the arithmetic coding unit 116 that performs arithmetic coding based on these binary symbols and the binary symbol occurrence probability, the first memory unit 117 that holds the context, and range and low Are provided, a second memory unit 118 that holds the data, a prediction unit 119 that performs two-cycle prediction, and an output buffer 121. In this arithmetic encoding apparatus, when a multilevel signal and / or a syntax element to be encoded is input to the binarizing unit 112, the arithmetic unit converts it into a binary string and sends it to the arithmetic encoding unit 116 and the prediction unit 119. In addition, the surrounding situation (context) is also input to the context calculation unit 114 as necessary. The prediction unit 119 performs range prediction, while the arithmetic encoding unit 116 performs arithmetic encoding, and outputs the obtained result to the output buffer 121 as a code bit. It goes without saying that a buffer can be provided on the input side as required.

(First memory part 117) [0061] The first memory unit 117 functions as a context table that holds contexts. The context table is updated as needed. Therefore, the first memory unit 117 uses an updatable memory such as a RAM. An example of the first memory unit 117 is shown in FIG. As shown in this figure, contexts # 1, # 2, # 3,... Are held in the first memory unit 117, and each context is associated with a binary string (0, 1). At this time, it is possible to assign multiple binary sequences to one context.

 [0062] The second memory unit 118 functions as a second context update table that holds contexts. Registers can be used to hold range and low values.

 [0063] Also, as shown in the modification of FIG. 11, the first memory unit and the second memory unit are configured as a common memory unit 117A, and the context, range, and low are each held in one memory. Is also possible.

 The first memory unit 117 uses a dual port memory. This makes it possible to read / write to the context table at the same time.

 (Arithmetic coding part 116)

 Details of arithmetic coding section 116 in FIG. 9 will be described based on the block diagram in FIG. 12 and the operation diagram in FIG. The arithmetic coding unit 116 shown in FIG. 12 includes a computing unit 140, an lrLPS tape node 120, a second rLPS table 122, a code bit generation unit 160, and a context update unit 170. The arithmetic coding unit 116 includes a range input and / or a low input for inputting a section as an input terminal, a binary string input, and a context X input and a context Y input as context inputs. The range input is connected to the arithmetic unit 140, the first lrLPS table 120, the second rLPS table 122, and the code bit generation unit 160. On the other hand, the low input is connected to the operation unit 140, the second rLPS tape NOR 122, and the code bit generation unit 160. The binary string input is connected to the calculation unit 140, the second rLPS table 122, the sign bit generation unit 160, and the context update unit 170. Further, the context X input is connected to the lrLPS table 120, the second rLP S table 122, the code bit generation unit 160, and the context update unit 170. On the other hand, the context Y input is connected to the second rLPS tape relay 122, the sign bit generation unit 160, and the context update unit 170.

[0066] The first lrLPS tape glue 120 and the second rLPS table 122 are respectively input to the input range and This table determines rLPS according to the context. By providing two tables, two bits can be read and written in one cycle, and high-speed processing is expected. On the other hand, it is necessary to control which table holds the latest data and switch the table as needed. For this reason, the arithmetic coding unit 116 of FIG. 9 includes table management means.

[0067] The sign bit generation unit 160 outputs an output code at the time of renormalization. Further, the context update unit 170 updates and outputs the context based on the previous processing result. The calculation unit 140 determines the input range range and Z or low, and the corresponding rLPS with reference to the rLPS table 20, updates the interval based on these, and outputs range 'and low'. .

 This process will be described based on the operation diagram of FIG. FIG. 13 illustrates the processing for performing MPS processing, LPS processing, and renormalization for a predetermined section, as in FIG. In this case, for the interval for which range and low are determined, in the case of binary symbol A and the corresponding context X, arithmetic unit 140 performs MPS processing and performs encoding, and the interval is set to range 'and low'. In the case of the update process and the range 'and low' for the binary symbol B and the corresponding context Y, the calculation unit 140 performs encoding by LSP processing and updates the interval to range "and low". In addition, the process that expands the interval to range "'and low"' by performing renormalization and the process in which the context update unit 170 updates context X and context Y are performed in one cycle. That is, the arithmetic unit 140 obtains rLPS at the time of MPS by referring to the lrLPS table 120 and rLPS ′ at the time of LPS by referring to the second rLPS table 122 and performs the following calculation. range '"= (rLPS, —0 · 5) X 2

 low "'= Qow + range-rLPS-rLPS' —0. 5) X 2

 In addition, in the same cycle, the sign bit generation unit 160 outputs the output code “Τ”, and the context update unit 170 updates the context X and the context Υ, respectively. As a result, MPS processing, LPS processing, and renormalization can be completed in one cycle.

Next, FIG. 14 shows an example of an arithmetic encoding unit 300 according to another configuration. Arithmetic coding section 300 shown in this figure, in order to process two symbols in one cycle, first arithmetic coding means 301 for the first symbol processing and second arithmetic coding means for the second symbol processing 302 and the mark No. bit generation unit 360 is provided. The first arithmetic encoding means 301 includes an lrLPS table 320, a first context update table 330, a first calculation unit 340, and a first renormalization unit 350. Similarly, the second arithmetic encoding means 302 includes a second rLPS table 322, a second context update table 332, a second calculation unit 342, and a second renormalization unit 352. When the symbol A and the context X are input as a binary string, the arithmetic sign part 300 obtains an rLPS corresponding to the context X and the range by referring to the lrLPS table 320, and this value and the symbol A Then, the first operation unit 340 updates the arithmetic sign y and updates range and low. Further, if necessary, the first renormalization unit 350 performs renormalization, sends range 'and low' to the second arithmetic coding means 302, and outputs the sign bit to the sign bit generation unit 360. The Also, the first context update table 330 is updated, and the context X ′ is output.

 On the other hand, the second arithmetic encoding unit 302 obtains rLPS corresponding to the context Y and range ′ with reference to the second rLPS table 322, and based on this value and range ′ and low ′, the second arithmetic unit 342 Perform arithmetic encoding with and update range 'and low'. Further, the second renormalization unit 352 performs renormalization as necessary, and outputs range “and low” and also outputs the sign bit to the sign bit generation unit 360. The sign bit generation unit 360 outputs an output sign bit. Also, the second context update table 332 is updated based on the symbol B and the context Y, and the context Y ′ is output.

[0072] The above processing can be completed in one cycle. That is, first symbol A is arithmetically encoded by the first arithmetic coding means 301 based on range and low and context X, and the first symbol A based on the obtained range ′ and low ′ and context Y. Two arithmetic coding means 302 arithmetically codes the second symbol B. As described above, in this embodiment, an rLPS table for determining a context to be used for a generated binary string based on a binary string, a syntax element, and a surrounding situation (context) is created in advance. By preparing two rLPS tables, the calculation unit can read and update necessary data from each table during one cycle, and can complete the calculation for two cycles in one cycle. As a result, it is possible to reduce the number of CABAC processing cycles, which has been a problem with the length of processing time, while achieving high coding efficiency, thereby speeding up processing and enabling real-time coding for high-resolution applications. That can be mounted on You can build a stem. This method can be implemented as a software with a general-purpose CPU or MPU. Preferably, it is possible to perform more efficient processing by constructing and executing dedicated hardware.

 (Modification of arithmetic code part that performs 2-cycle prediction)

In the configuration of the arithmetic code unit shown in the block diagram of FIG. 9, the arithmetic code unit 116 performs arithmetic encoding operations. As a specific configuration of the arithmetic code key unit 116, for example, the configuration shown in the block diagram of FIG. 5 can be used. Here, if each context update table is composed of ROM, each determines the context according to the symbol, so the ROM size must be increased. In addition, ROM requires a cycle because data access requires one cycle. Therefore, by configuring one context update table with a combinational circuit, the ROM size can be reduced and the configuration can be made inexpensively. Furthermore, in the combinational circuit, the result of the arithmetic logic is generated during that cycle, so that an extra cycle is not required and the processing speed can be increased. An example of the arithmetic coding unit 216 using a combinational circuit is shown in FIG.

[0074] The arithmetic coding unit 216 shown in this figure includes a context memory unit 217, a first context update table 230 connected to the first output side of the context memory unit 217 in Fig. 29, and a second output. The second context update table 232 connected to the first side, the lrLPS table 220 connected to the first output side of the context memory unit 217, the adder output of the first context update table 230 and the context memory unit 217 2nd rLPS table No. 222 connected to, 1st selector 224 connected to the output side of the range memory 218 218 and the range memory 及 び and 1st rrLPS table 220 to hold the range value, and 1st selection Device 2 24 and range memory unit 218 connected to first range update unit 240, second rLPS tape nozzle 222 and second selector 226 connected to the output side of first range update unit 240, and second selector 226 And the second lmnge update unit 24 The second range update unit 242 connected to the output side of 0 and the output side connected to the range memory unit 218, the low memory unit 219 holding the low value, the low memory unit 219, the lrange update unit 240 and The first low update unit 250 connected to the output side of the first selector 224, the first low update unit 250, the second range update unit 242 and the second selector 2 26 are connected to the output side and the output side is a low memory. Part 21ow update part 2 connected to part 219 52.

 Note that FIG. 29 is a block diagram representing the processing steps and the data flow, and therefore does not necessarily match the actual hardware connection. For example, for the range value, the range memory section 218 → the lrange table → the second range table → the range memory section 218 is shown as a force indicating that the range is sequentially updated. Each of the two range tables is connected to the range memory unit 218, and the range value updated in each range table can be written to the range memory unit 218. In addition, in FIG. 29, the context memory unit 217 is displayed in duplicate, and the context memory unit 217 on the left side in FIG. Show each one.

 [0076] The context memory unit 217 corresponds to the first memory unit 117 that holds a context in FIG. Here, it consists of a dual-port RAM with four inputs, symbol A and corresponding context X, symbol B and corresponding context Y, and two updated context X 'and Y' outputs. The context memory unit 217 holds the updated context, reads the corresponding context according to the specified address, and further, the two contexts X,... Updated by the first and second context update tables 232. Write Y, respectively. Here, the second context update table 232 is composed of a ROM, while the first context update table 230 is composed of a combinational circuit. By constructing one context update table with a combinational circuit, contexts X and Y can be updated simultaneously in the second stage, which greatly contributes to speeding up the processing of two symbols in one cycle.

Note that, in the example of the arithmetic encoding unit 216 shown in FIG. 29, both the first context update tape node 230 and the second context update table 232 can be configured by combinational circuits. In this case, it is possible to further increase the speed. When storing a large amount of data in the context update table, it is not appropriate to use a combinational circuit because of the large area and cost. However, when the amount of data to be stored is small, even if it is implemented with a combinational circuit, it is not so large as compared with the case of the area power SROM. [0078] The first and second rLPS tables 222 are each composed of a ROM, and output rLPS according to the input context. Since the rLPS table data held in ROM is divided into four according to the context, each rLPS table has four outputs. The rLPS output from each rLPS tape recorder is input to the first and second selectors 226, respectively. The first and second selectors 226 select the corresponding rLPS according to each input range, and output the selected rLPS to the first and second mnge update unit 242. First, second 2Mng _e update unit 242 rewrites the range value of the range memory portion 218 updates the value of the range. Similarly, the low memory unit 219 holds a low value. These range memory unit 218 and low memory unit 219 can be configured by registers. The first and 21st update units 252 realize the function of the renormalization unit, and renormalize and update low according to the range and the number of renormalizations. In this way, the llow update unit 250 outputs the sign bit 1 that is arithmetically encoded for the symbol A, and the 21st w update unit 252 outputs the sign bit 2 that is arithmetically encoded for the symbol Β.

 In the example of FIG. 29, members that perform each process are functionally expressed, and in an actual hardware configuration, a plurality of functions can be realized with one member. For example, the context memory unit 217 corresponds to the first memory unit 117 in FIG. 9, and the range memory unit 218 and the low memory unit 219 correspond to the second memory unit 118 in FIG. Further, the lrange update unit 240 and the llow update unit 250 correspond to the first calculation unit shown in FIG. 14, the second range update unit 242 and the 21ow update unit 252 correspond to the second calculation unit, respectively. Can be summarized as appropriate.

 (DSE arithmetic coding process)

The processing of performing arithmetic coding operation of two symbols in one cycle in the arithmetic code key unit 216 described above can be divided into four stages as shown in the flowcharts of FIGS. In other words, in the first stage shown in step S1, each context is read. Specifically, the context memory unit 217 reads the contexts X and Y corresponding to the symbols A and B according to the address. In FIG. 29, the context memory unit 217 on the left indicates a read state.

[0081] Next, in the second stage shown in step S2, each context is updated and each rLPS is read. Specifically, the first context update from the first output of the context memory unit 217. New table 230 reads context X and updates to context X '. Also, the updated context X ′ is referred to by the second context update table 232, and on the other hand, the context Y obtained from the second output of the context memory unit 217 is updated to the context Y ′. Here, the context update table is not two ROMs, one is the first context update table 230 configured with a combinational circuit, and the other is the second context update table 232 configured with ROM, thereby enabling high-speed processing. It is possible to update the contexts X and Y of two symbols A and B at the same time. In addition, as described above, all the context update tables are composed of combinational circuits, which can further increase the speed.

 On the other hand, in the second stage, based on the context X before update, the rLP S of the symbol A is obtained by referring to the rLPS table. That is, based on the context X obtained from the first output of the context memory unit 217, the lrLPS table 220 outputs rLPS to the first selector 224. On the other hand, the AND output of the context Y obtained from the context X ′ obtained from the first context update table 230 and the second output of the context memory unit 217 is sent to the second rLPS table 222, and similarly the rLPS of the context Y before the update. Is output to the second selector 226.

 [0083] Further, in the third stage shown in step S3, the updated context is written and the range is updated. First, the contexts X ′ and Y ′ output from the first context update table 230 and the second context update table 232 are written in the context memory unit 217. In FIG. 29, the context memory unit 217 in the lower center part shows a write state.

 On the other hand, the first selector 224 selects the corresponding rLPS of the symbol A according to the range obtained by referring to the range memory unit 218, and outputs the selected rLPS to the lrange update unit 240. The first range update unit 240 updates the current range held in the range memory unit 218 to range ′ according to the selected rLP S and determines the range corresponding to the symbol B in the next stage. Output to second range updater 242. On the other hand, the number of re-normalizations is determined according to the updated range 'and output to the llow update unit 250.

[0085] The second range updating unit 242 selects the range 'updated by the lrange updating unit 240, as the second selection. In accordance with the rLPS selected by the device 226, the range is updated to “range”, and the range value in the range memory unit 218 is updated to “range”. On the other hand, the number of re-normalizations is determined according to the updated “range”, and is output to the 21st update unit 252.

 [0086] Finally, low is updated in the fourth stage shown in step S4. The llow update unit 250 updates the low value held in the low memory unit 219 to low w ′ according to range ′ and the number of renormalizations, and outputs the sign bit 1 of the symbol A. On the other hand, the 21 ow update unit 252 updates low 'to low "according to the range" and the number of renormalizations, and updates the low value of the low memory unit 219 to low ". Also, the sign bit of symbol B 2 is output.

 [0087] As described above, one of the two context update tables is composed of a ROM and the other is composed of a combination circuit, so that two symbols of arithmetic codes can be realized at low cost in one cycle. (Continuous MPS processing prediction)

 [0088] On the other hand, as a characteristic of binarization by CABAC processing, it is easy to generate the same symbol continuously. Among the MPS processing and LPS processing included in CABAC processing, the characteristic of MPS processing is that low does not change and only the range value tends to decrease gradually. Therefore, when the binary sequence is a sequence of MPSs, it is possible to predict the results up to several cycles ahead from the number of sequences, range, and context.

 The procedure of this process will be described based on the operation diagram of FIG. Here, it is assumed that context X is a constant value and MPS processing continues four times. First, if rangeO is updated to random in the first cycle, if rLPS used in MPS processing at this time is rLPS l,

 range 1 = rangeO— rLPS 丄

 iowO = lowl

 It becomes. If rangel is updated to range2 in the next second cycle, if rLPS used in the MPS process at this time is rLPS2,

 range 2 = rangel— rLPS 2

 = rangeO -rLPS l -rLPS2

 iow2 = low 1 = lowO

It becomes. In the third cycle, range2 is updated to range3. range3 = range2— rLPS3

 = rangeO -rLPS l -rLPS2 -rLPS3

 low3 = low2 = lowl = lowO

 Finally, range3 is updated to range4 in the fourth cycle. At this time, if rLPS4, range4 = range3—rLPS4

 = rangeO -rLPS l -rLPS2 -rLPS3 -rLPS4

 iow4 = low3 = low2 = low 1 = lowO

 It becomes. In this way, MPS continuous processing using the same context can be calculated from range, context X, and the number of consecutive numbers. It becomes possible to predict even the cycle ahead. To achieve this, an MPS continuous number table is prepared.

 (MPS continuous number table)

FIG. 16 shows an example of the MPS continuous number table when the context is constant. As shown in this figure, the MPS sequence number table holds a range according to the range, context, and MPS sequence number. Therefore, by referring to the table with these parameters, the range value after the continuous MPS processing can be extracted. In the example of Fig. 15, the initial range is the rangeAm context X (—constant) and the MPS continuous number is 4. Therefore, the range predicted value is the value stored at the position E in the MPS continuous number table of Fig. 16. Become. In this way, an update interval several cycles ahead can be obtained only by referring to the table. Therefore, especially when MPS processing continues, the amount of computation can be significantly reduced, and the speed can be increased by reducing the number of processing. Is planned.

 (Change due to renormalization)

In the above MPS processing, low is constant while LPS processing does not occur, that is, while MPS processing continues. However, when renormalization is performed as shown in Fig. 17 (a), the low value changes. However, the renormalization value is determined by range. For this reason, if the value of range and the number of renormalizations are known, the value of low can be obtained. In this way, renormalization Therefore, it is possible to table the changing low.

FIG. 18 shows a block diagram of the continuous MPS process prediction unit 400 in consideration of renormalization. The continuous MPS process prediction unit 400 shown in this figure includes a range table 420, a context update table 430, and a renormalization unit 450. The continuous MPS processing prediction unit 400 refers to the range table 420 according to the range, the number of MPS consecutive numbers, and the context, and updates renge to range '. On the other hand, based on the number of times of renormalization and low, the renormalization unit 450 outputs low 'and a sign bit. Further, the context is updated by referring to the context update table 430 based on the number of consecutive MPSs and the context (context → context ′).

[0093] An example of range prediction considering renormalization is shown in Fig. 17 (b). As shown in this figure, the range value can be predicted and the context can be updated according to the number of consecutive MPSs and the number of renormalizations.

 (Change in context)

 [0094] In addition, in the above example, the force S with a constant context may occur, and the context may change in the middle. In the above method, it is assumed that the same context is used for the same symbol, so if the context is changed, subsequent changes cannot be predicted. Therefore, by preparing two range tables and two context update tables, continuous MPS process prediction that can cope with such context changes is realized.

 FIG. 19 shows an example in which the context is switched to the context X until the fourth cycle and the subsequent two cycles are switched to the context Y in the continuous MPS processing. In this case as well, it is possible to create a table for each context. Fig. 20 shows an example of the MPS continuous number table that records the range prediction value according to the range, context (variable), and MPS continuous number. In the example of Figure 19, the initial range is rangeA, the number of consecutive MPSs in context X is 4, the range at that point is rangeE, and the subsequent number of MPSs in context Y is 2. The predicted range value is the sum E + I of the value stored at position E and the value stored at position I in the MPS continuous number table in Fig. 20. In this way, even when the context changes, the update interval can be easily obtained by referring to the table in the same manner, so that the processing can be greatly reduced and the processing speed can be increased.

[0096] Continuous MPS processing prediction that realizes continuous MPS processing prediction when context changes FIG. 21 shows an example of a block diagram constituting the part 400B. The continuous MPS processing prediction unit 400B shown in this figure provides two prediction tables 420A and 420B (MPS continuous number table), so that when a range, context, and MPS continuous number are input, these parameters correspond to these parameters. The range prediction value is referred to, and range "is output as the corresponding value. The contexts in the prediction table nozzles 420A and 420B are updated appropriately. In this example, two types of contexts, X and Y, are described. It goes without saying that it is possible to prepare multiple tables corresponding to more contexts.

 FIG. 22 shows a more detailed block diagram of continuous MPS process prediction section 500. As shown in this figure, the continuous MPS process prediction unit 500 includes a first context update table 530, a second context update table 532, a first lrange table 520, a second range table 522, and a renormalization table. The re-normalization unit 550 is provided. This continuous MPS processing prediction unit 500 refers to the second range table 522 based on range and the number of MPS consecutive X (4 in the example of FIG. 19) and context A (context X in FIG. 19), and range '(rangeE ). On the other hand, based on the context B (context Y in FIG. 19), the MPS continuous number Y (2 in FIG. 19), and the range 'obtained in the second range table 522, the range l is obtained by referring to the lrange table 520. On the other hand, based on the number of renormalizations in the lrange table 520 and the second range table 52 2 and the value of low, the renormalization unit 550 refers to the renormalization table and sets low ' In this way, one renormalization unit 550 can add renormalizations with different contexts and output appropriate sign bits, contributing to simplification of the circuit. , Context A is updated to context A 'by referring to the second context update table 532 based on the MPS continuous number, and context B is referred to the first context update table 530 based on the MPS continuous number and to context B'. Update Also as described above, it is possible to increase the number of context change. (Modification of arithmetic coding unit that performs continuous MPS processing prediction)

[0098] Similarly to the description in Fig. 29 above, in the continuous MPS process prediction, the context update table is composed of each ROM, and one of them is a combinational circuit in order to obtain a cheaper and more stable speedup. It is also possible to configure both with a combinational circuit. An example of such an arithmetic encoding unit 316 is shown in FIG. Figure 31 is also a block of processing. Since the context memory unit 217B is displayed in duplicate, the two are the same.

 [0099] The arithmetic sign key section 316 shown in this figure also includes the first and second context update tables 230B,

 The context memory unit 217B connected to the output side of 232B, the first context update table 230B connected to the first output side of the context memory unit 217B, and the second context update table connected to the second output side These configurations are almost the same as those in FIG. That is, the first context update table 230B is composed of combinational circuits, and the second context update table 232B is composed of ROM. Alternatively, both the first context update table 230B and the second context update table 232B may be configured by combinational circuits. In particular, when the amount of data to be stored is small, the mounting area does not increase, so a configuration with only combinational circuits that can achieve higher speed is preferable.

 [0100] The arithmetic encoding unit 316 also includes a range memory unit 218B that holds a range value and a low memory unit 219B that holds a low value, and these can also be configured by a register or the like. Since these members can be configured in substantially the same manner as in FIG. 29, detailed description thereof will be omitted.

 On the other hand, the arithmetic coding unit 316 receives the number m of consecutive symbols A (MPS) and the corresponding context X, and the first lrange tape master 520B that updates the range read from the range memory unit 218B to range '. The second range tape No. 522B that inputs the number of consecutive symbols B (MPS) n and the corresponding context Y, updates the range 'of the lrange table 520B and outputs the range "is provided. The arithmetic encoding unit 316 performs renormalization based on the range 'updated in the lrange table 520B and the number of renormalization, as in FIG. The first low update unit 250B that updates low of the memory unit 219B and outputs low 'and the sign bit 1, re-normalization based on the range "of the second range table 522B and the number of re-normalization, Llow w update unit lowB obtained by 250B Comprising a first 21ow update unit 252B for outputting a No. bit 2.

[0102] Since FIG. 31 is also a block diagram representing the processing steps and the data flow in the same manner as FIG. 29, the actual hardware connection does not necessarily match. For example, context memo The power displayed in the overlapping area 217B is the same. In FIG. 31, the left context memory section 217B shows the operation during reading, and the central context memory section 217B shows the operation during writing. .

 (MPSE arithmetic process)

This arithmetic encoding unit 316 can also perform arithmetic encoding processing of symbols A and B in four stages of steps S ′ 1 to S ′ 4 as shown in the flowcharts of FIGS. That is, in the first stage indicated by step S′1, each context is read. Specifically, the context memory unit 217B reads (reads) the contexts X and Y corresponding to the symbols A and B.

 Next, in the second stage indicated by step S′2, each context is updated. Specifically, the first context update table 230B output S context X is read from the first output of the context memory unit 217B, and further updated to the context X ′ based on the number of consecutive MPSs of the symbol A. In addition, the second context update table 2 32B refers to the updated context X ′, and on the other hand, based on the context Y obtained from the second output of the context memory unit 217B and its MPS continuity η, the context Y Update to '.

 [0105] Further, in the third stage shown in step S'3, the updated context is written and the range is updated. That is, the contexts X ′ and Y ′ output from the first context update table 230B and the second context update table 232B are written in the context memory unit 217B. In this way, in the first and second context update tables 232B, the context (occurrence probability) for the amount of MPS processed is updated in step S′2, and written in the context memory unit 217B in step S′3.

 On the other hand, for symbol A, based on the number of consecutive MPS m and its context X, the first lrange table 520B updates the value of range to range ′. The range value is read from the range memory section 218B. Further, for the symbol B, based on the MPS consecutive number n and its context Y, the second range table 522B updates the value of range 'to range ". The updated value of range" is written to the range memory unit 218B.

[0107] Finally, in the fourth stage indicated by step S'4, a low update is performed. The llow update unit 25 OB is low stored in the low memory unit 219B according to the range 'and the number of renormalization. The value is updated to low 'and the sign bit 1 of symbol A is output. On the other hand, the 21ow update unit 252B updates low 'to low "according to the range" and the number of renormalizations, and updates the low value of the low memory unit 219B to low ". Also, the sign bit 2 of symbol B This method is effective only when the symbol is MPS. Similarly to Fig. 29, the arithmetic coding unit 316 capable of processing two symbols in one cycle can be realized with a simple arithmetic circuit.

 [0108] In this way, since it is possible to perform arithmetic coding of the next stage symbol without waiting for the computation of the previous stage symbol, pipeline processing becomes possible, and processing that was previously considered impossible is possible. High speed is achieved. Figure 33 shows an example of such pipeline processing. As shown in Fig. 33, arithmetic coding can be performed in parallel for three symbols, so processing of two or more symbols is possible in one cycle.

 (Switching between the two methods)

 [0109] As described above, the 2-cycle prediction has an advantage that the processing for one cycle is reduced and prediction is possible in many scenes. On the other hand, continuous MPS processing prediction can reduce processing for several cycles and the amount of reduction is large, but there is a restriction that prediction is possible only when MPS continues.

 [0110] Therefore, by combining these two-cycle prediction and continuous MPS process prediction, selecting a more effective method according to the situation, and switching these to use, it is possible to further increase the speed. As an embodiment 3 of the present invention, an example of an arithmetic coding apparatus including such a prediction technique switching unit is shown in FIG. 23 and FIG. The arithmetic coding apparatus 600 shown in these figures also includes a context calculation unit 614, a first memory unit 617, a second memory unit 618, and an arithmetic coding unit 610 as in FIG. These members are basically the same as those shown in FIG. 9 and the like and will not be described in detail. The arithmetic code input unit 610 includes an input buffer 622 for buffering two input signals, a 2-cycle prediction unit 622, a continuous MPS processing prediction unit 623, and a prediction method switching unit 624 for switching between them. . The prediction method switching unit 624 selects and switches an appropriate prediction method at that time according to the input context, range, and the like. In the example of FIG. 23, the state where the 2-cycle prediction unit 622 is selected is shown, and in the example of FIG. 24, the state where the continuous MPS process prediction unit 623 is selected is shown. As a result, the number of cycles can be reduced by appropriately combining two-cycle prediction and continuous MPS processing prediction.

[0111] In Fig. 25, the two-cycle prediction and the continuous MPS processing prediction are switched by the prediction method switching unit 624. Show the state. As shown in this figure, the prediction method switching unit 624 performs switching based on the state of the binarized bit string. Here, as a condition for switching, continuous MPS processing prediction is used only when the input bit force S is “0”, and in other cases, 2-cycle prediction is used. The prediction method switching unit 624 follows this condition, selects one of the methods, and performs processing according to the selected method.

 (Example)

[0112] Next, as an embodiment of the present invention, two-cycle prediction, continuous MPS process prediction, and switching between these are performed with an arithmetic sign 符号, and the ratio of the number of cycles to be reduced is simulated. Asked. Here, the number of contexts input in a batch is set to 2, and arithmetic coding is performed on various simulation ghost image sequences (akiyo, bridge-close ^ b ridge-far _Λ earphone ^ c lair), and the simulation results Are shown in Table 1 to Table 5, respectively. In the table, DSE is 2-cycle prediction, MPSE is continuous MPS processing prediction, and DSE + MPSE is an example of switching between these. As shown in this table, the computational complexity can be reduced by 2-cycle prediction and continuous MPS process prediction for any sequence, and the 2-cycle prediction shows particularly good results. Further, in the method of switching between them, the calculation amount can be further reduced, and the usefulness of the present embodiment has been confirmed. Also, according to the simulation results, the reduction rate improved as the number of context changes allowed increased. However, increasing the number of context changes allowed increases the number of cycles that can be reduced, but it also has the demerit of increasing the circuit area by complicating the circuit configuration. It is determined as appropriate according to the specifications.

 [0113] [Table 1]

[0114] [Table 2] bridge—close

 Number of input contexts MPSE (%) DSE (%) MPSE + DSE (%)

 1 3.18

 2 19.00 36.68 40.78

3 26.08 47.72 68. BO

4 29.66 63.24 66. BO

B 31.85 56.52 69.66

[0115] [Table 3]

[0116]

 [0117] [Table 5]

[0118] An arithmetic coding apparatus according to another embodiment performs arithmetic coding on a binarization unit for binarizing a multilevel signal and a binary symbol generated by the binarization unit. The symbol value and symbol indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binary code generated by the binarization unit, the context calculation unit for generating the context number An arithmetic coding apparatus comprising: an update unit for updating an appearance probability; and a probability state storage unit for storing a symbol value and a symbol appearance probability using the context number calculated by the context calculation unit as an index And the arithmetic coding unit The first storage unit that stores the predicted value of rLPS, the second storage unit that stores the predicted value of rLPS separately from the first storage unit, and the first storage unit that stores the predicted value of rLPS The first calculation unit that performs arithmetic coding with reference to the rLPS prediction value and the initial interval stored in the storage unit and updates the interval, and the rLPS prediction value stored in the second storage unit and the first interval. A second arithmetic unit that performs arithmetic encoding with reference to the update section updated by the arithmetic unit, and that updates the symbol appearance probability and the symbol value indicated by the dominant symbol, separately from the first arithmetic unit. And a second context update table separate from the first context update table, which also updates the symbol appearance probability and the symbol value indicated by the dominant symbol, and the first context update table corresponds to the input context. That the output and an input possible combinations circuit to the second context table during the same cycle. This makes it possible to realize high-speed arithmetic coding that can process more than 2 bits in one cycle.

In the arithmetic coding apparatus, the first context update table and the second context update table can be configured by a combinational circuit. This speeds up the processing. Note that the first context update table may be composed of ROM and the second context update table may be composed of a combinational circuit, which makes it possible to realize arithmetic coding at low cost. Industrial applicability

[0120] The computer-readable recording medium storing the arithmetic coding apparatus, arithmetic coding method, arithmetic coding program, and program of the present invention is suitable for use in recording and transmitting moving image signals after compression. It is useful and can be suitably used in devices that process high-quality moving images, such as portable terminal devices, moving image capturing devices, and moving image recording / reproducing devices, and their application fields.

 Brief Description of Drawings

 FIG. 1 is a block diagram showing a moving image encoding / decoding device that obtains a bit stream from image data by H.264 / AVC encoding processing.

 FIG. 2 is a conceptual diagram for explaining the concept of arithmetic coding / decoding.

 FIG. 3 is a conceptual diagram showing a procedure for performing binary arithmetic coding.

FIG. 4 is a block diagram showing an arithmetic coding apparatus that performs CABAC processing. 5] FIG. 5 is a block diagram showing details of the binary arithmetic code portion of FIG.

 FIG. 6 is a conceptual diagram showing a renormalization procedure.

FIG. 7 is a block diagram showing an arithmetic encoding device.

8] FIG. 8 is a conceptual diagram showing the operation of the arithmetic coding apparatus shown in FIG.

FIG. 9] is a block diagram showing an arithmetic coding apparatus according to the first embodiment.

10] FIG. 10 is a conceptual diagram showing the first memory unit of FIG.

11] A block diagram showing a modification of the arithmetic coding apparatus according to the first embodiment. 12] FIG. 10 is a block diagram of the arithmetic coding unit of the arithmetic coding apparatus shown in FIG.

13] FIG. 13 is a conceptual diagram showing the operation of the arithmetic sign key portion of FIG.

FIG. 14] is a block diagram showing an arithmetic sign key section according to another configuration.

FIG. 15 is a conceptual diagram showing a procedure for predicting continuous MPS processing.

 FIG. 16 is a conceptual diagram showing an MPS continuous number table when the context is constant.

 FIG. 17 (a) is a conceptual diagram showing how renormalization is performed, and FIG. 17 (b) is a conceptual diagram showing range prediction considering renormalization.

 FIG. 18 is a block diagram of a continuous MPS process prediction unit considering renormalization.

 FIG. 19 is a conceptual diagram showing how context changes in continuous MPS processing.

20] It is a conceptual diagram showing an example of the MPS continuous number table.

 FIG. 21 is a block diagram of a continuous MPS process prediction unit that realizes continuous MPS process prediction when the context changes.

22) A detailed block diagram of the continuous MPS process prediction unit is shown.

FIG. 23] is a block diagram showing an arithmetic coding apparatus according to Embodiment 3 of the present invention. Sono]] is a block diagram showing an arithmetic coding apparatus according to Embodiment 3 of the present invention.

 FIG. 25 is a block diagram showing a state in which 2-cycle prediction and continuous MPS process prediction are switched by a prediction method switching unit.

 FIG. 26 is a flowchart of the process of arithmetic coding / decoding by H.264ZAVC.

27] H. 264ZAVC's arithmetic code system that embodies the processing process of arithmetic code FIG.

 FIG. 28 is a block diagram showing a conventional arithmetic coding device.

FIG. 29] is a block diagram showing a modified example of the arithmetic code key part that performs 2-cycle prediction.

[30] FIG. 30 is a flowchart showing a procedure of arithmetic coding by the arithmetic sign key part of FIG.

 FIG. 31 is a block diagram showing a modification of the arithmetic encoding unit that performs continuous MPS process prediction. [32] FIG. 32 is a flowchart showing a procedure of arithmetic coding by the arithmetic sign key part of FIG. 33] This is a timing chart showing how the arithmetic codes in Figs. 29 and 31 are performed by pipeline processing.

Explanation of symbols

 1---DMA

 2… Motion search unit

 3… Deblocking filter

 4… Motion compensation unit

 5… Conversion unit

 6 ... Quantization part

 7 · · · Inverse quantization section

 8 ... Inverse conversion part

 9 ... Overall control unit

 10: Arithmetic encoding / decoding device

 10A: Arithmetic coding device

 11… Variable length decoding part

 12, 112

 14, 114, 614 ... Context calculator

 16, 116— Binary arithmetic sign

 20 "'rLPS tape'

 30 ... Context change table

 40, 140 ... Calculation unit

50 ... Renormalization part , 170… Context 卜 Update Department

0 .. Video encoding / decoding device

7 ··· First memory section

7A… Memo 卿

8- · Second memory section

9- --Predictor

0- ·-lrLPS table

1 ... Output buffer

2- --2nd rLPS table

 , 360 ... sign bit generator

 300 ... Arithmetic encoder

 316 ... Arithmetic sign

7, 217B ... Context memory section, 218B "range memory"

 , 219B --- low ^ y¾

 · '' · LrLPS table

 ····· 2nd rLPS table

 ··· First selector

 ··· Second selector

 , 230B ... first context update table, 232B ... second context update table-brother-lrange update unit

 ··· 2nd range update section

 , 250B ... llow update section

 , 252B ... 21ow update section

 --First arithmetic encoding means

 -·-Second arithmetic coding means

...-lrLPS table 322… 2nd rLPS tape nore

 330 ... First context update table

332 ... Second context update table

340 ... 1st operation part

 342… Second calculation unit

 350 ... 1st renormalization part

 352 ... Second renormalization unit

 400, 400B, 500 ... Continuous MPS processing prediction unit

420- · -range tape

 420A, 420B ... predicted tape

 430 ... Context update table

 450 ... Renormalization part

 520, 520B ... lrange table

 522, 522B ... 2nd range table

 530 ... First context update table

532 ... Second context update table

550 ... Renormalization unit

600 ... Arithmetic encoder

610: Arithmetic coding part

617 ... 1st memory section

618 ... Second memory section

621 ... Input buffer

 622 ... 2-cycle prediction unit

 623… Continuous MPS processing prediction unit

624 ... Prediction method switching part

700 ... Arithmetic encoder

710 ... Adaptive arithmetic coding / decoding part

711 · · · Arithmetic coding * Decoding part 712 ··· Symbol appearance probability control unit

713 ··· Probability state storage

 720 ... Context calculator

730- Encoding * Decoding control unit

800- Arithmetic encoder

 810- --Adaptive arithmetic coding part

811- --arithmetic encoding part

 814- --Symbol appearance probability controller

815- --Probability state storage

 820- --Context calculator

821 --- Register

 822- --Comparison judgment part

 830 ... Encoding control unit

 FM-- 'frame memory

Claims

The scope of the claims

[1] A binarization unit for binarizing a multilevel signal,

 An arithmetic code unit for arithmetically encoding the binary symbol generated by the binarization unit, and a context calculation unit for generating a context number;

 An update unit for updating the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit, and the context number calculated by the context calculation unit And a probability state storage unit for storing the symbol value and the symbol appearance probability using as an index,

 The arithmetic encoding unit is

 A first storage unit for storing a prediction value of a region rLPS obtained by dividing an inferior symbol section based on an occurrence probability;

 Similarly, the second storage unit that stores the rLPS prediction value is separate from the first storage unit, and is arithmetically encoded with reference to the rLPS prediction values stored in the first storage unit and the second storage unit. An arithmetic unit for performing

 An arithmetic coding apparatus comprising:

[2] A binarization unit for binarizing a multilevel signal,

 An arithmetic code unit for arithmetically encoding the binary symbol generated by the binarization unit, and a context calculation unit for generating a context number;

 An update unit for updating the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit, and the context number calculated by the context calculation unit And a probability state storage unit for storing the symbol value and the symbol appearance probability using as an index,

 The arithmetic encoding unit is

Number of consecutive dominant symbol processing during dominant symbol processing, initial interval, symbol appearance probability An update interval storage unit that stores a predicted value of an update interval determined based on a rate, a number of consecutive dominant symbol processings during dominant symbol processing, and a predicted value of a symbol appearance probability determined based on an initial symbol appearance probability A context update table to store

 A renormalization unit having a renormalization table for updating low, which is a complement of the update interval, based on the number of renormalizations;

An arithmetic coding apparatus comprising:

 A binarization unit for binarizing a multilevel signal;

 An arithmetic code unit for arithmetically encoding the binary symbol generated by the binarization unit, and a context calculation unit for generating a context number;

 An updating unit for updating a symbol value and a symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit;

 An arithmetic coding apparatus comprising: a probability state storage unit for storing the symbol value and the symbol appearance probability using the context number calculated by the context calculation unit as an index;

 The arithmetic encoding unit is

 The first update interval storage unit that stores the predicted value of the update interval determined based on the number of dominant symbol processes at the time of dominant symbol processing, the initial interval, and the symbol appearance probability, and similarly stores the predicted value of the update interval A second update interval storage unit separate from the first update interval storage unit,

 A first context update table for storing a predicted number of symbol appearance probabilities determined based on the number of consecutive dominant symbol processing during dominant symbol processing and an initial symbol appearance probability;

The first context update table for storing a predicted value of the symbol appearance probability determined based on the number of consecutive dominant symbol processing during the dominant symbol processing and the symbol appearance probability updated in the first context update table; A separate second context update table, A renormalization unit having a renormalization table for updating low, which is a complement of the update interval, based on the number of renormalizations;

An arithmetic coding apparatus comprising:

 A binarization unit for binarizing a multilevel signal;

 An arithmetic code unit for arithmetically encoding the binary symbol generated by the binarization unit, and a context calculation unit for generating a context number;

 An update unit for updating the symbol value and symbol appearance probability indicated by the dominant symbol or the inferior symbol based on the binary symbol generated by the binarization unit, and the context number calculated by the context calculation unit And a probability state storage unit for storing the symbol value and the symbol appearance probability using as an index,

 The arithmetic encoding unit is

 A first storage unit for storing a prediction value of a region rLPS obtained by dividing an inferior symbol section based on an occurrence probability;

 Similarly, the second storage unit that stores the rLPS prediction value is separate from the first storage unit, and is arithmetically encoded with reference to the rLPS prediction values stored in the first storage unit and the second storage unit. An arithmetic unit for performing

A 2-cycle prediction unit comprising:

 An update interval storage unit for storing a predicted value of an update interval determined based on the number of consecutive dominant symbol processing at the time of dominant symbol processing, an initial interval, and a symbol appearance probability;

 A context update table for storing predicted number of symbol appearance probabilities determined based on the number of consecutive dominant symbol processing at the time of dominant symbol processing and initial symbol appearance probability;

 A renormalization unit having a renormalization table for updating low, which is a complement of the update interval, based on the number of renormalizations;

A continuous dominant symbol processing prediction unit comprising:

It is planned to switch between the 2-cycle prediction unit and the continuous dominant symbol processing prediction unit. A measurement method switching unit;

 An arithmetic coding apparatus comprising:

[5] In arithmetic coding of binary symbols, the dominant symbol, which is a symbol with a high appearance probability, and the inferior symbol, which is a symbol with a low appearance probability, is divided into a number line and the number of inferior symbols. Based on the coordinate value of the section on the line, it corresponds to the predetermined section on the number line,

 An arithmetic coding method for outputting a sign signal from an interval correspondence result on the number line and an input binary symbol,

 Referring to the first lrLPS table in which the coordinates of the interval at the time of dominant symbol processing when the symbol to be encoded is the dominant symbol and the interval coordinate values at the time of processing of the inferior symbol when the symbol to be encoded are recorded in advance are referred to A step of obtaining a divided region in which the symbol section is updated;

 Referring to the obtained divided region and the second rLPS table separate from the lrLPS table, a step of obtaining a divided region obtained by updating the second symbol section following the first symbol, and performing renormalization as necessary Outputting an output code;

 Updating the context number;

 An arithmetic coding method comprising:

[6] In arithmetic coding of binary symbols, a dominant symbol that is a symbol with a high appearance probability and a low symbol with a low probability of appearance, an inferior symbol that is a symbol, and the number of inferior symbols and the number of inferior symbols Based on the coordinate value of the section on the line, it corresponds to the predetermined section on the number line,

 An arithmetic coding method for outputting a sign signal from an interval correspondence result on the number line and an input binary symbol,

Context update table that stores the process of obtaining the predicted value of the update section by referring to the update section storage unit based on the number of consecutive dominant symbols and the context number when the dominant symbol of the binary symbol is continuous and the context number And a step of updating using the arithmetic coding method. [7] In arithmetic coding of binary symbols, a dominant symbol that is a symbol with a high appearance probability and a low symbol with a low probability of appearance, an inferior symbol that is a symbol, the number of inferior symbols and the number of inferior symbols Based on the coordinate value of the section on the line, it corresponds to the predetermined section on the number line,

 An arithmetic code program for outputting a sign key signal from the interval correspondence result on the number line and the input binary symbol,

 Referring to the first lrLPS table in which the coordinates of the interval at the time of dominant symbol processing when the symbol to be encoded is the dominant symbol and the interval coordinate values at the time of processing of the inferior symbol when the symbol to be encoded are recorded in advance are referred to A function for obtaining a segmented area in which a symbol section is updated;

 Refers to the obtained divided region and the second rLPS table separate from the lrLPS table, obtains a divided region by updating the second symbol section following the first symbol, and performs renormalization as necessary. A function of outputting an output code;

 The ability to update the context number,

 An arithmetic code program that causes a computer to realize the above.

[8] In arithmetic coding of binary symbols, a dominant symbol that has a high probability of appearance and a low symbol that has a low probability of appearance, an inferior symbol that has a low probability of occurrence, and the number of inferior symbols and the number of inferior symbols. Based on the coordinate value of the section on the line, it corresponds to the predetermined section on the number line,

 An arithmetic coding program that outputs a sign signal from the result of interval correspondence on the number line and an input binary symbol,

 Context update table that stores a context number and a function for obtaining a predicted value of an update section by referring to the update section storage section based on the number of consecutive dominant symbols and the context number when the dominant symbol of the binary symbol is continuous An arithmetic code program characterized by having a computer implement a function to update using

[9] A computer-readable recording medium storing the program according to claim 7 or 8.