JP3576980B2

JP3576980B2 - Operation system switching method by hardware control

Info

Publication number: JP3576980B2
Application number: JP2001016311A
Authority: JP
Inventors: 清彦千葉
Original assignee: NEC Communication Systems Ltd
Current assignee: NEC Communication Systems Ltd
Priority date: 2001-01-24
Filing date: 2001-01-24
Publication date: 2004-10-13
Anticipated expiration: 2021-01-24
Also published as: JP2002223181A

Description

【０００１】
【発明の属する技術分野】
本発明はハードウエア制御による運用系切り替え方式に関し、特に２重化された装置の運用系／待機系の切り替え制御を、ハードウエア回路により行うことを可能とする、ハードウエア制御による運用系切り替え方式に関する。
【０００２】
【従来の技術】
伝送装置や交換装置など、高信頼性を要求されている装置においては、装置を２重化して一方を運用系とし、他方を待機系として運用することが一般的に行われており、運用系に故障などのトラブルが発生した場合には、それまで待機していた待機系を運用系に切り替えて、装置の運用を継続できる様になっている。
【０００３】
そして、装置間の主信号データによって運用系と待機系を切り替える機能を有する２重化装置においては、装置間の主信号データから切り替え指示信号を終端して取り出し、取り出した切り替え指示信号をファームウエアに通知し、ファームウエアにおいて２重化装置の有する各種パッケージの状態を判別して、運用系を切り替える方式が一般的にとられている。
【０００４】
【発明が解決しようとする課題】
上述した従来のファームウエア制御による運用系／待機系の切り替え方式は、ファームウエアによるアクセス時間と処理時間の分、切り替えの発生が遅くなり、また、２重化装置の有するパッケージ数が多くなるほど、ファームウエアを動作させるＣＰＵの負荷が増し、ファームウエア処理が更に遅くなるという欠点を有している。
【０００５】
本発明の目的は、装置間の主信号データによって運用系と待機系を切り替える機能を有する２重化装置において、２重化された装置の運用系／待機系の切り替え制御をハードウエア回路だけで行い、切り替え時間の短縮を図ることを可能とする、ハードウエア制御による運用系切り替え方式を提供することにある。
【０００６】
【課題を解決するための手段】
本発明のハードウエア制御による運用系切り替え方式は、系切り替え許可信号を送信する主装置と、０系装置と１系装置とを備えて前記主装置から送信される前記系切り替え許可信号を受信し、前記系切り替え許可信号に応じて前記０系装置と前記１系装置の何れか一方を運用系とし他方を待機系として稼動させうる２重化構成の従装置とから構成されるシステムであって、前記従装置は、前記主装置と前記０系装置との通信を第１の通信回線を介してインタフェースする０系パッケージと、前記主装置と前記１系装置との通信を第２の通信回線を介してインタフェースする１系パッケージとを備え、前記従装置の前記０系パッケージと前記１系パッケージの各々が同時に前記主装置から前記系切り替え許可信号を受信した場合に、前記０系パッケージと前記１系パッケージの各々が自パッケージで終端した前記系切り替え許可信号を相互に送受することにより、自パッケージが運用系となるか待機系となるかを判定し、判定した結果をそれぞれ前記０系装置と前記１系装置に伝達することにより、前記０系装置と前記１系装置の何れか一方を運用系とし他方を待機系として稼動させることを特徴とする。
【０００７】
また、前記０系パッケージと前記１系パッケージとはそれぞれ相互に同一の構成及び機能を備え、前記０系パッケージと前記１系パッケージは、それぞれ、フォーマット変換部と運用系判定回路を備え、前記フォーマット変換部は、前記主装置から前記従装置へ送信される第１の主信号のフォーマット変換を行って自系装置（前記０系装置或いは前記１系装置）へ第２の主信号として送信すると共に、前記第１の主信号から前記系切り替え許可信号を終端して第１のＳＷビット信号として前記運用系判定回路に送出し、かつ、前記第１の主信号のデータフレームに異常を検出したか否かを示す入力異常信号を前記運用系判定回路に送出し、前記自系装置（前記０系装置或いは前記１系装置）からの第３の主信号のフォーマット変換を行うと共に、現在前記０系装置と前記１系装置の何れの系が運用系となっているかを示す第２のＳＷビット信号と、系切り替え要求信号としてのＦＬビット信号を挿入して第４の主信号を生成し、前記第４の主信号を前記主装置に対して送信することを特徴とする。
【０００８】
さらに、前記フォーマット変換部には、さらに、前記第１の主信号内の前記系切り替え許可信号の位置を指示するＳＷビット終端位置指示信号を出力すると共に、前記第４の主信号内の第２のＳＷビット信号の位置を指示するＳＷビット挿入位置指示信号と、ＦＬビット信号の位置を指示するＦＬビット挿入位置指示信号を出力するパターンジェネレータが接続されることを特徴とする。
【０００９】
また、前記運用系判定回路には、自系パッケージ（前記０系パッケージ或いは前記１系パッケージの何れか）が前記従装置に実装されたときのパッケージ挿入位置を示すスロットＩＤ信号が更に入力されていることを特徴とする。
【００１０】
さらに、前記運用系判定回路には、他系の運用系判定回路から他系の前記第１のＳＷビット信号と、他系の前記入力異常信号と、他系パッケージ（前記１系パッケージ或いは前記０系パッケージ）が実装されていることを示す他系の実装信号とが更に入力されていることを特徴とする。
【００１１】
また、前記運用系判定回路は、自系パッケージ（前記０系パッケージ或いは前記１系パッケージ）が運用系となるか待機系となるかを判定するために、前記運用系判定回路に入力される自系の前記第１のＳＷビット信号と他系の前記第１のＳＷビット信号の比較、前記運用系判定回路に入力される自系の前記入力異常信号と他系の前記入力異常信号の判定、及び、何らかの要因で自系の前記第１のＳＷビット信号と他系の前記第１のＳＷビット信号とが一致しない場合に他系の前記実装信号なども含めての判断を行う論理回路から構成され、自系パッケージが運用系になると判定した場合には、前記自系装置（前記０系装置或いは前記１系装置）に対して運用系指示信号を出力して、前記自系装置が運用系となったことを伝達し、自系パッケージが待機系になると判定した場合には、前記自系装置（前記０系装置或いは前記１系装置）に対して前記運用系指示信号の出力を停止して、前記自系装置が待機系となったことを伝達する、ことを特徴とする。
【００１２】
さらに、前記運用系判定回路の運用系切り替え制御動作は、前記フォーマット変換部が前記第１の主信号から前記系切り替え許可信号を終端して前記第１のＳＷビット信号として前記運用系判定回路に送出したときに開始される、ことを特徴とする。
【００１３】
また、前記運用系判定回路の運用系切り替え制御動作が開始されると（Ｓ１）、先ず、他系の前記第１のＳＷビット信号と自系の前記第１のＳＷビット信号とを比較し（Ｓ２）、他系の前記第１のＳＷビット信号と自系の前記第１のＳＷビット信号とが一致した場合は（ステップＳ２で一致）、自系の前記第１のＳＷビット信号で示された系が運用系となるよう指示されたものとＳＷビットを確定して、ステップＳ９に進み、ステップＳ９では、確定した前記ＳＷビットと自系の前記スロットＩＤ信号とを比較し、両者が一致していた場合は（ステップＳ９で一致）、自系が運用系となり（Ｓ１０）、前記自系装置（前記０系装置或いは前記１系装置）に対して前記運用系指示信号を出力して（Ｓ１１）、前記自系パッケージと前記自系装置が運用系となった事を伝達し、ステップＳ９で両者が一致しない場合は（ステップＳ９で不一致）、自系は待機系となり（Ｓ１２）、前記自系装置（前記０系装置或いは前記１系装置）に対する前記運用系指示信号の出力を停止して（Ｓ１３）、自系パッケージと前記自系装置が待機系となった事を伝達する、ことを特徴とする。
【００１４】
さらに、前記ステップＳ２で、他系の前記第１のＳＷビット信号と自系の前記第１のＳＷビット信号とが不一致の場合は（ステップＳ２で不一致）、まず、自系パッケージの前記入力異常信号を参照して自系パッケージの入力異常が無いか判定し（Ｓ３）、自系パッケージの前記入力異常信号が入力異常無しであれば（ステップＳ３でＯＫ）、次に、他系の前記入力異常信号と他系の前記実装信号とを参照して、他系パッケージの入力異常が無いか及び他系パッケージの実装状態について判定し（Ｓ４）、ステップＳ４の判定の結果、他系パッケージの前記入力異常信号が入力異常有りを示しているか、或いは、他系パッケージの前記実装信号が他系パッケージの実装無しを示している場合には（ステップＳ４で未実装）、ステップＳ６に進み、ステップＳ６では自系の前記第１のＳＷビット信号で示される系が運用系となるよう指示されたものとみなしてＳＷビットを確定し、ステップＳ９に進む、ことを特徴とする。
【００１５】
また、前記ステップＳ４の判定の結果、他系パッケージの前記実装信号が他系パッケージの実装有りを示しており、かつ、他系パッケージの前記入力異常信号が入力異常無しを示している場合には（ステップＳ４で実装）、ステップＳ７に進み、ステップＳ７では、直前の状態が、０系が運用系（１系が待機系）であれば「０系が運用系」となるようＳＷビットを確定し、１系が運用系（０系が待機系）であれば「１系が運用系」となるようＳＷビットを確定して、ステップＳ９に進む、ことを特徴とする。
【００１６】
さらに、前記ステップＳ３の判定の結果、自系パッケージの前記入力異常信号が入力異常有りであれば（ステップＳ３で異常）、次に、他系の前記入力異常信号と他系の前記実装信号とを参照して、他系パッケージの入力異常が無いか及び他系パッケージの実装状態について判定し（Ｓ５）、ステップＳ５の判定の結果、他系パッケージの前記入力異常信号が入力異常有りを示しているか、或いは、他系パッケージの前記実装信号が他系パッケージの実装無しを示している場合には（ステップＳ５で未実装）、ステップＳ７に進み、ステップＳ７の後はステップＳ９に進む、ことを特徴とする。
【００１７】
また、前記ステップＳ５の判定の結果、他系パッケージの前記実装信号が他系パッケージの実装有りを示しており、かつ、他系パッケージの前記入力異常信号が入力異常無しを示している場合には（ステップＳ５で実装）、ステップＳ８に進み、ステップＳ８では、他系の前記第１のＳＷビット信号で示される系が運用系となるよう指示されたものとみなしてＳＷビットを確定し、ステップＳ９に進む、ことを特徴とする。
【００１８】
【発明の実施の形態】
次に、本発明の実施の形態について図面を参照して説明する。
【００１９】
図１は、本発明のハードウエア制御による運用系切り替え方式の一実施形態を示すブロック図である。
【００２０】
図１に示す本実施の形態は、主従関係にあり主側となる伝送装置などの装置２と、従側になる伝送装置などの装置１とから構成されており、装置２と装置１間は通信回線４０−１、通信回線４０−２を介して通信を行う構成となっている。装置１は２重化構成となっており、０系装置２０−１と１系装置２０−２を備えており、０系装置２０−１と１系装置２０−２の何れか一方が運用系となり、他方が待機系となる構成を有している。主側の装置２は、従側の装置１からの要求に応じて、装置１内の０系装置２０−１と１系装置２０−２との何れが運用系となるかを許可する系切り替え許可信号を送出する機能を有している。
【００２１】
装置１は、２重化構成となっており、装置２と０系装置２０−１との通信をインタフェースするＰＫＧ（パッケージ）３−１と、装置２と１系装置２０−２との通信をインタフェースするＰＫＧ３−２とを備えている。装置２から装置１のＰＫＧ３−１へは主信号１０１−１が送信され、逆にＰＫＧ３−１から装置２へは主信号１０２−１が送信される。装置２から装置１のＰＫＧ３−２へは主信号１０１−２が送信され、逆にＰＫＧ３−２から装置２へは主信号１０２−２が送信される。主信号１０１−１と主信号１０１−２とは同一の信号である。
【００２２】
装置１のＰＫＧ３（ＰＫＧ３−１とＰＫＧ３−２）は、フォーマット変換部４（フォーマット変換部４−１とフォーマット変換部４−２）を備えており、フォーマット変換部４は、装置２から装置１へ送信される主信号１０１（主信号１０１−１と主信号１０１−２）を、装置１内のデータフォーマットへ変換して０系装置２０−１、１系装置２０−２へ、主信号１１１（主信号１１１−１と主信号１１１−２）として送出すると共に、０系装置２０−１、１系装置２０−２から送出される主信号１１２（主信号１１２−１と主信号１１２−２）のフォーマット変換を行って、主信号１０２（主信号１０２−１と主信号１０２−２）として装置２へ送信する。また、フォーマット変換部４は、後述するＳＷビットとＦＬビットを主信号１０２に挿入する機能と、主信号１０１のＳＷビットを終端する機能を備えている。
【００２３】
ここで、図２を参照して、装置２と装置１間で送受信される主信号１０１（主信号１０１−１と主信号１０１−２）と主信号１０２（主信号１０２−１と主信号１０２−２）のデータフォーマットについて説明する。
【００２４】
図２は、装置間主信号のデータフォーマットを示す図である。
【００２５】
図２（ａ）は、装置１から装置２へ送信される主信号１０２である。主信号１０２は、装置間の運用・保守情報などを格納するオーバーヘッド（ＯｖｅｒＨｅａｄ）としてのＯＨ１０２１と、ＳＷと名づけた１ビットのＳＷ１０２２と、ＦＬと名づけた１ビットのＦＬ１０２３と、装置１から装置２へ送信するデータを格納するデータ領域１０２４とを備えている。
【００２６】
ＳＷ１０２２は、装置１の何れの系が運用系となっているかについて装置２に伝達するためのモニタ用のＳＷビットとして使用され、ＳＷ＝０であれば、現在、０系装置２０−１が運用系となっていることを示し、ＳＷ＝１であれば、現在、１系装置２０−２が運用系となっていることを示すものである。
【００２７】
ＦＬ１０２３は、装置１の系切り替え要求信号としてのＦＬビットとして使用され、ＦＬ＝０であれば、０系装置２０−１を運用系としたいということを示し、ＦＬ＝１であれば、１系装置２０−２を運用系としたいということを示すものである。
【００２８】
図２（ｂ）は、装置２から装置１へ送信される主信号１０１である。主信号１０１は、装置間の運用・保守情報などを格納するオーバーヘッド（ＯｖｅｒＨｅａｄ）としてのＯＨ１０１１と、ＳＷと名づけた１ビットのＳＷ１０１２と、ＦＬと名づけた１ビットのＦＬ１０１３と、装置２から装置１へ送信するデータを格納するデータ領域１０１４とを備えている。
【００２９】
ＳＷ１０１２は、装置１の系切り替え許可信号としてのＳＷビットとして使用され、ＳＷ＝０であれば、０系装置２０−１を運用系とせよということを示し、ＳＷ＝１であれば、１系装置２０−２を運用系とせよということを示すものである。ＦＬ１０１３のＦＬビットは、使用しないものとする。
【００３０】
図１に戻り、本実施形態についての説明を継続する。
【００３１】
装置１のＰＫＧ３（ＰＫＧ３−１とＰＫＧ３−２）は、フォーマット変換部４（フォーマット変換部４−１とフォーマット変換部４−２）に接続された運用系判定部５（運用系判定部５−１と運用系判定部５−２）とパターンジェネレータとしてのＰＧ６（ＰＧ６−１とＰＧ６−２）を備えている。
【００３２】
ＰＧ６は、フォーマット変換部４に対してＳＷビットとＦＬビットの位置指示信号を出力する機能を備えている。すなわち、ＰＧ６（ＰＧ６−１とＰＧ６−２）は、ＳＷビット終端位置指示信号１６（ＳＷ１０１２（図２（ｂ））の主信号１０１内における位置を指示する信号）と、ＳＷビット挿入位置指示信号１７（ＳＷ１０２２（図２（ａ））の主信号１０２内における位置を指示する信号）と、ＦＬビット挿入位置指示信号１８（ＦＬ１０２３（図２（ａ））の主信号１０２内における位置を指示する信号）とを、フォーマット変換部４（フォーマット変換部４−１とフォーマット変換部４−２）に対して送出する。
【００３３】
運用系判定部５は、自パッケージ（ＰＫＧ３−１またはＰＫＧ３−２）が運用系となるか否かを判定する機能を有しており、フォーマット変換部４が主信号１０１から終端したＳＷビット信号７と、フォーマット変換部４が検出した入力異常信号９を受信すると共に、フォーマット変換部４に対して、主信号１０２に挿入するＳＷビット信号８（ＳＷビット信号８−１、ＳＷビット信号８−２）を送信する。なお、入力異常信号９は、フォーマット変換部４が主信号１０１のデータフレームに異常を検出した場合に入力異常有りとされ、主信号１０１のデータフレームを異常無く受信できれば入力異常無しとされる。
【００３４】
また、運用系判定部５には、自パッケージ（ＰＫＧ３−１またはＰＫＧ３−２）が装置１に実装された時のパッケージ挿入位置を示すスロットＩＤ３０（スロットＩＤ３０−１とスロットＩＤ３０−２）が入力されている。ここで、スロットＩＤ３０の値は、以下の説明の容易化のため、スロットＩＤ３０−１＝０（すなわち、ＰＫＧ３−１は０系装置２０−１のインタフェースパッケージとして使用され、その挿入位置のスロット番号が０であることを示す）とし、スロットＩＤ３０−２＝１（すなわち、ＰＫＧ３−２は１系装置２０−２のインタフェースパッケージとして使用され、その挿入位置のスロット番号が１であることを示す）とする。
【００３５】
運用系判定部５−１と運用系判定部５−２とは相互に、以下に示す信号を送受する。すなわち、運用系判定部５−１から運用系判定部５−２に対しては、ＰＫＧ３−１のフォーマット変換部４−１で終端したＳＷビット信号１０−１（ＳＷビット信号７−１と同一）と、ＰＫＧ３−１のフォーマット変換部４−１で検出した入力異常信号１２−１（入力異常信号９−１と同一）と、ＰＫＧ３−１が実装されていることを示す実装信号１４−１とを送出し、運用系判定部５−２から運用系判定部５−１に対しては、ＰＫＧ３−２のフォーマット変換部４−２で終端したＳＷビット信号１０−２（ＳＷビット信号７−２と同一）と、ＰＫＧ３−２のフォーマット変換部４−２で検出した入力異常信号１２−２（入力異常信号９−２と同一）と、ＰＫＧ３−２が実装されていることを示す実装信号１４−２とを送出する。
【００３６】
運用系判定部５は、自パッケージ（ＰＫＧ３−１またはＰＫＧ３−２）が運用系となるか待機系となるかを判定するために、運用系判定部５に入力される自系のＳＷビット信号７と他系のＳＷビット信号１０の比較、運用系判定部５に入力される自系の入力異常信号９と他系の入力異常信号１２の判定、及び、何らかの要因で自系のＳＷビット信号７と他系のＳＷビット信号１０とが一致しない場合に他系の実装信号１４なども含めての判断を行う論理回路から構成され、自パッケージが運用系になると判定した場合には、自系の装置（０系装置２０−１或いは１系装置２０−２）に対して運用系指示信号１２１（運用系指示信号１２１−１或いは運用系指示信号１２１−２）を出力して、自系が運用系となったことを伝達し、自パッケージが待機系になると判定した場合には、自系の装置（０系装置２０−１或いは１系装置２０−２）に対して運用系指示信号１２１の出力を停止して、自系が待機系となったことを伝達する。
【００３７】
上述した運用系判定部５の運用系／待機系判定論理について、図３を参照して説明する。図３においても、以下の説明の容易化のため、ＰＫＧ３−１が０系のインタフェースパッケージであり、ＰＫＧ３−２が１系のインタフェースパッケージであるものとする。
【００３８】
図３は、運用系判定部の運用系／待機系判定論理を示す図である。
【００３９】
図３において、横方向（イ１とイ２の行）は０系の状態を示し、縦方向（ロ１とロ２の列）は１系の状態を示している。イ１の行の「０系正常」とは、０系のＰＫＧ３−１の運用系判定部５−１が受信した入力異常信号９−１は、入力異常無しであった場合を示しており、イ１の行の「０系異常」とは、０系のＰＫＧ３−１の運用系判定部５−１が受信した入力異常信号９−１は、入力異常有りであった場合を示している。また、イ２の行の「０系指定」とは、０系のＰＫＧ３−１のフォーマット変換部４−１が主信号１０１−１から終端したＳＷビットは、０系を運用系に指定する「０」であった場合（すなわちＳＷビット信号７−１＝０であった場合）を示しており、イ２の行の「１系指定」とは、０系のＰＫＧ３−１のフォーマット変換部４−１が主信号１０１−１から終端したＳＷビットは、１系を運用系に指定する「１」であった場合（すなわちＳＷビット信号７−１＝１であった場合）を示している。
【００４０】
同様に、ロ１の列の「１系正常」とは、１系のＰＫＧ３−２の運用系判定部５−２が受信した入力異常信号９−２は、入力異常無しであった場合を示しており、ロ１の列の「１系異常」とは、１系のＰＫＧ３−２の運用系判定部５−２が受信した入力異常信号９−２は、入力異常有りであった場合を示している。また、ロ２の列の「０系指定」とは、１系のＰＫＧ３−２のフォーマット変換部４−２が主信号１０１−２から終端したＳＷビットは、０系を運用系に指定する「０」であった場合（すなわちＳＷビット信号７−２＝０であった場合）を示しており、ロ２の列の「１系指定」とは、１系のＰＫＧ３−２のフォーマット変換部４−２が主信号１０１−２から終端したＳＷビットは、１系を運用系に指定する「１」であった場合（すなわちＳＷビット信号７−２＝１であった場合）を示している。
【００４１】
運用系判定部５−１は、前述したように、実装信号１４−１と共に、ＳＷビット信号７−１をＳＷビット信号１０−１として、また、入力異常信号９−１を入力異常信号１２−１として運用系判定部５−２に対して送出し、逆に、運用系判定部５−２は、実装信号１４−２と共に、ＳＷビット信号７−２をＳＷビット信号１０−２として、また、入力異常信号９−２を入力異常信号１２−２として運用系判定部５−１に対して送出しているため、互いに他系の状態を認識することが可能となっている。
【００４２】
そして、運用系判定部５において、自系が運用系となるか待機系となるかについて判定する運用系／待機系判定論理は以下のようになる。
【００４３】
イ３行とロ３列の交点では、０系正常で０系指定、かつ、１系正常で０系指定であるため、「０系が運用系」となると判定され、１系は待機系となると判定される。同様に、イ４行とロ４列の交点では、０系正常で１系指定、かつ、１系正常で１系指定であるため、「１系が運用系」となると判定され、０系は待機系となると判定される。
【００４４】
イ３行とロ４列の交点では、０系正常で１系指定、かつ、１系正常で０系指定であり、０系と１系の双方が正常であるにもかかわらず、双方で運用系に指定する系が異なっているため、正しい判定は不可能であり、この時は「前状態保持」と判定する。「前状態保持」とは、この判定を行う直前の状態を保持する、ということであり、直前の状態が、０系が運用系で（１系が待機系で）あれば「０系が運用系」と判定し、１系が運用系で（０系が待機系で）あれば「１系が運用系」と判定するものとする。同様に、イ４行とロ３列の交点では、０系正常で０系指定、かつ、１系正常で１系指定であり、０系と１系の双方が正常であるにもかかわらず、双方で運用系に指定する系が異なっているため、正しい判定は不可能であり、この時は「前状態保持」と判定する。「前状態保持」は前述の通りであり、直前の状態が、０系が運用系で（１系が待機系で）あれば「０系が運用系」と判定し、１系が運用系で（０系が待機系で）あれば「１系が運用系」と判定するものとする。
【００４５】
イ５の行は、１系異常の状態を示しているため、１系は判定に使用しないものとする。すなわち、０系正常であれば０系だけを判定に使用し、０系正常で０系指定であれば「０系が運用系」となると判定し（イ５行とロ３列の交点）、０系正常で１系指定であれば「１系が運用系」となると判定する（イ５行とロ４列の交点）ものとする。また、０系異常であれば０系も判定に使用せず、この時は「前状態保持」と判定する（イ５行とロ５列の交点）。
【００４６】
ロ５の列は、０系異常の状態を示しているため、０系は判定に使用しないものとし、１系正常で０系指定であれば「０系が運用系」となると判定し（イ３行とロ５列の交点）、１系正常で１系指定であれば「１系が運用系」となると判定する（イ４行とロ５列の交点）ものとする。
【００４７】
次に、図４を参照して、運用系判定部５が行う運用系切り替え制御動作について説明する。図４においても、以下の説明の容易化のため、ＰＫＧ３−１が０系のインタフェースパッケージであり、ＰＫＧ３−２が１系のインタフェースパッケージであるものとし、ＰＫＧ３−１を自系（或いは自系ＰＫＧ）と称し、ＰＫＧ３−２を他系（或いは他系ＰＫＧ）と称することとする。
【００４８】
図４は、運用系判定部が行う運用系切り替え制御動作を説明する図である。
【００４９】
運用系判定部５の運用系切り替え制御動作は、フォーマット変換部４が主信号１０１からＳＷビット（系切り替え許可信号）を終端し、これをＳＷビット信号７として運用系判定部５に送出したときに開始される。運用系判定部５−１は、自系のＳＷビット信号７−１と、他系のＳＷビット信号１０−２（ＳＷビット信号７−２と同一）と、自系の入力異常信号９−１と、他系の入力異常信号１２−２（入力異常信号９−２と同一）と、他系の実装信号１４−２とを用いて運用系切り替え制御動作を行う。
【００５０】
運用系判定部５−１の運用系切り替え制御動作が開始されると（Ｓ１）、先ず、他系のＳＷビット信号１０−２と自系のＳＷビット信号７−１とを比較する（Ｓ２）。他系のＳＷビット信号１０−２と自系のＳＷビット信号７−１とが一致した場合は（ステップＳ２で一致）、装置１が受信したＳＷビットは正常であったと判定できるため、自系ＰＫＧが受信したＳＷビットを正当なものとして確定する。すなわち自系のＳＷビット信号７−１で示された系が運用系となるよう指示されたものとＳＷビットを確定して、ステップＳ９に進む。ステップＳ９では、確定したＳＷビットと自系のスロットＩＤ３０−１とを比較し、両者が一致していた場合は（ステップＳ９で一致）、自系が運用系となり（Ｓ１０）、自系の０系装置２０−１に対して運用系指示信号１２１−１を出力して（Ｓ１１）、自系ＰＫＧと０系装置２０−１が運用系となった事を伝達する。ステップＳ９で両者が一致しない場合は（ステップＳ９で不一致）、自系は待機系となり（Ｓ１２）、自系の０系装置２０−１に対する運用系指示信号１２１−１の出力を停止して（Ｓ１３）、自系ＰＫＧと０系装置２０−１が待機系となった事を伝達する。
【００５１】
ステップＳ２で、他系のＳＷビット信号１０−２と自系のＳＷビット信号７−１とが不一致の場合は（ステップＳ２で不一致）、まず、自系ＰＫＧの入力異常信号９−１を参照して自系ＰＫＧの入力異常が無いか判定する（Ｓ３）。自系ＰＫＧの入力異常信号９−１が入力異常無しであれば（ステップＳ３でＯＫ）、次に、他系の入力異常信号１２−２と他系の実装信号１４−２とを参照して、他系ＰＫＧの入力異常が無いか及び他系ＰＫＧの実装状態について判定する（Ｓ４）。ステップＳ４の判定の結果、他系ＰＫＧの入力異常信号１２−２が入力異常有りを示しているか、或いは、他系ＰＫＧの実装信号１４−２が他系ＰＫＧの実装無しを示している場合には（ステップＳ４で未実装）、ステップＳ６に進み、自系ＰＫＧが受信したＳＷビットを正当な物として確定する（Ｓ６）。すなわち、ステップＳ６では、自系のＳＷビット信号７−１で示される系が運用系となるよう指示されたものとみなしてＳＷビットを確定する。ＳＷビットを確定した後、ステップＳ９に進む。
【００５２】
ステップＳ４の判定の結果、他系ＰＫＧの実装信号１４−２が他系ＰＫＧの実装有りを示しており、かつ、他系ＰＫＧの入力異常信号１２−２が入力異常無しを示している場合には（ステップＳ４で実装）、ステップＳ７に進み、図３で示したと同様の「前状態保持」となる（Ｓ７）。すなわち、ステップＳ７では、直前の状態が、０系が運用系（１系が待機系）であれば「０系が運用系」となるようＳＷビットを確定し、１系が運用系（０系が待機系）であれば「１系が運用系」となるようＳＷビットを確定して、ステップＳ９に進む。
【００５３】
ステップＳ３の判定の結果、自系ＰＫＧの入力異常信号９−１が入力異常有りであれば（ステップＳ３で異常）、次に、他系の入力異常信号１２−２と他系の実装信号１４−２とを参照して、他系ＰＫＧの入力異常が無いか及び他系ＰＫＧの実装状態について判定する（Ｓ５）。ステップＳ５の判定の結果、他系ＰＫＧの入力異常信号１２−２が入力異常有りを示しているか、或いは、他系ＰＫＧの実装信号１４−２が他系ＰＫＧの実装無しを示している場合には（ステップＳ５で未実装）、ステップＳ７に進み、「前状態保持」となる。ステップＳ７の後はステップＳ９に進む。
【００５４】
ステップＳ５の判定の結果、他系ＰＫＧの実装信号１４−２が他系ＰＫＧの実装有りを示しており、かつ、他系ＰＫＧの入力異常信号１２−２が入力異常無しを示している場合には（ステップＳ５で実装）、ステップＳ８に進み、他系ＰＫＧが受信したＳＷビットを正当な物として確定する（Ｓ８）。すなわち、ステップＳ８では、他系のＳＷビット信号１０−２で示される系が運用系となるよう指示されたものとみなしてＳＷビットを確定する。ＳＷビットを確定した後、ステップＳ９に進む。
【００５５】
以上、図４を参照して、運用系判定部５−１が行う運用系切り替え制御動作について説明した。運用系判定部５−２は運用系判定部５−１と対照的な構成となっているため、運用系判定部５−２が行う運用系切り替え制御動作も、図４に示した動作と同一である。従って、運用系判定部５−２の運用系切り替え制御動作については、これ以上の説明を省略する。
【００５６】
次に、図１、図２を再度参照して、本実施形態における運用系切り替えの総合動作の一例について説明する。
【００５７】
２重化構成の装置１内で、０系装置２０−１とＰＫＧ３−１が０系であり、１系装置２０−２とＰＫＧ３−２が１系であり、ＰＫＧ３−１は通信回線４０−１を介して装置２と通信を行っており、ＰＫＧ３−２は通信回線４０−２を介して装置２と通信を行っている。今、０系が運用系で、１系が待機系の状態にあるものとする。
【００５８】
ここで、運用系を、０系のＰＫＧ３−１から１系のＰＫＧ３−２へ切り替える要求が生じると、ＰＫＧ３−１は装置２に対して系切り替え要求信号を送出する。すなわち、ＰＫＧ３−１は、図２（ａ）に示した主信号１０２でＦＬ＝１を設定し、１系を運用系としたい旨を送出する。この時、図２（ａ）の主信号１０２のＳＷビットはＳＷ＝０で、現在０系が運用系である旨を示している。
【００５９】
装置２は、系切り替え要求信号を受信すると、装置１のＰＫＧ３−１とＰＫＧ３−２の双方に対し、系切り替え許可信号を送出する。すなわち、装置２は、図２（ｂ）に示した主信号１０１でＳＷ＝１を設定し、１系を運用系とせよとする旨を、ＰＫＧ３−１とＰＫＧ３−２に対して送出する。
【００６０】
装置１のＰＫＧ３−１とＰＫＧ３−２が主信号１０１を受信すると、各々のフォーマット変換部４は、主信号１０１からＳＷビット（系切り替え許可信号）を終端し、これをＳＷビット信号７として、各々の運用系判定部５に送出する。この時、ＳＷビット信号７は「１」（１系を運用系とせよ）となっている。
【００６１】
ＰＫＧ３−１とＰＫＧ３−２の運用系判定部５では、自系のＳＷビット信号７と他系のＳＷビット信号７とを、図４に示した運用系切り替え制御動作に従って比較判定を行い、運用系であったＰＫＧ３−１が待機系となり、待機系であったＰＫＧ３−２が運用系に切り替えられる。ＰＫＧ３−１が待機系となると、ＰＫＧ３−１は０系装置２０−１に対して運用系指示信号１２１−１の出力を停止するため、０系装置２０−１も同時に待機系となる。ＰＫＧ３−２が運用系となると、ＰＫＧ３−２は１系装置２０−２に対して運用系指示信号１２１−２を出力するため、１系装置２０−２も同時に運用系となる。このようにして、運用系であった０系が待機系となり、待機系であった１系が運用系となる。
【００６２】
【発明の効果】
以上説明したように、本発明のハードウエア制御による運用系切り替え方式は、２重化された装置の運用系／待機系の切り替え制御をハードウエア回路だけで行うことができるので、切り替え時間の短縮を図ることが可能となるという効果を有している。
【図面の簡単な説明】
【図１】本発明のハードウエア制御による運用系切り替え方式の一実施形態を示すブロック図である。
【図２】装置間主信号のデータフォーマットを示す図である。
【図３】運用系判定部の運用系／待機系判定論理を示す図である。
【図４】運用系判定部が行う運用系切り替え制御動作を説明する図である。
【符号の説明】
１装置
２装置
３−１、３−２ＰＫＧ
４−１、４−２フォーマット変換部
５−１、５−２運用系判定部
６−１、６−２ＰＧ
７−１、７−２ＳＷビット信号
８−１、８−２ＳＷビット信号
９−１、９−２入力異常信号
１０−１、１０−２ＳＷビット信号
１２−１、１２−２入力異常信号
１４−１、１４−２実装信号
１６ＳＷビット終端位置指示信号
１７ＳＷビット挿入位置指示信号
１８ＦＬビット挿入位置指示信号
２０−１０系装置
２０−２１系装置
３０−１、３０−２スロットＩＤ
４０−１、４０−２通信回線
１０１−１、１０１−２主信号
１０２−１、１０２−２主信号
１１１−１、１１１−２主信号
１１２−１、１１２−２主信号
１２１−１、１２１−２運用系指示信号[0001]
TECHNICAL FIELD OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active system switching method by hardware control, and more particularly, to an active system switching method by hardware control that enables a hardware circuit to perform switching control between an active system and a standby system of a duplexed device. About.
[0002]
[Prior art]
In devices requiring high reliability, such as transmission devices and switching devices, it is common practice to duplicate devices so that one is used as an active system and the other is used as a standby system. When a trouble such as a failure occurs, the standby system that has been waiting until then is switched to the active system so that the operation of the device can be continued.
[0003]
In a duplex device having a function of switching between an active system and a standby system according to main signal data between devices, a switching instruction signal is terminated and extracted from the main signal data between devices, and the extracted switching instruction signal is firmware In general, a method of switching the operation system by determining the state of various packages included in the duplex device in firmware is adopted.
[0004]
[Problems to be solved by the invention]
In the conventional switching method between the active system and the standby system based on the firmware control, the occurrence of the switching is delayed by the access time and the processing time by the firmware, and as the number of packages of the duplexer increases, There is a disadvantage that the load on the CPU for operating the firmware increases, and the firmware processing is further slowed down.
[0005]
An object of the present invention is to provide a duplexer having a function of switching between an active system and a standby system according to main signal data between the devices, in which only the hardware circuit controls switching between the active system and the standby system of the duplexed device. It is an object of the present invention to provide an operation system switching method based on hardware control, which makes it possible to shorten the switching time.
[0006]
[Means for Solving the Problems]
The active system switching method by hardware control according to the present invention includes a main device that transmits a system switching permission signal, a system 0 device and a system 1 device, and receives the system switching permission signal transmitted from the main device. A system comprising: a secondary device having a dual configuration capable of operating one of the system 0 device and the system 1 device as an operation system and the other as a standby system in response to the system switching permission signal. The slave device, a 0-system package for interfacing communication between the main device and the 0-system device via a first communication line, and a second communication line for communicating between the main device and the 1-system device. And a first system package interfacing with the first system package. When each of the zero system package and the first system package of the slave device simultaneously receives the system switching permission signal from the main device, the zero system system Package and the first system package mutually transmit and receive the system switching permission signal terminated in the own package, thereby determining whether the own package is to be the active system or the standby system, and determining the determined results by By transmitting the signals to the 0-system apparatus and the 1-system apparatus, one of the 0-system apparatus and the 1-system apparatus is operated and the other is operated as a standby system.
[0007]
The 0-system package and the 1-system package each have the same configuration and function as each other, and the 0-system package and the 1-system package each include a format conversion unit and an operating system determination circuit, The conversion unit converts the format of a first main signal transmitted from the main device to the slave device, and transmits the first main signal to the self-system device (the zero-system device or the first-system device) as a second main signal. Whether the system switching permission signal is terminated from the first main signal and sent to the operation system determination circuit as a first SW bit signal, and whether an abnormality is detected in the data frame of the first main signal. An input abnormal signal indicating whether or not the third main signal is transmitted from the self-system device (the zero-system device or the one-system device) to the active system determination circuit. A second SW bit signal indicating which of the 0-system device and the 1-system device is currently the active system, and an FL bit signal as a system switching request signal, and a fourth main signal And transmitting the fourth main signal to the main device.
[0008]
Further, the format conversion unit further outputs a SW bit end position indicating signal indicating the position of the system switching permission signal in the first main signal, and outputs the second bit in the fourth main signal. And a pattern generator that outputs a SW bit insertion position indicating signal indicating the position of the SW bit signal and an FL bit insertion position indicating signal indicating the position of the FL bit signal.
[0009]
Further, a slot ID signal indicating a package insertion position when a self-system package (either the zero-system package or the first-system package) is mounted on the slave device is further input to the active system determination circuit. It is characterized by having.
[0010]
Further, the operating system determination circuit includes, from the operating system determining circuit of the other system, the first SW bit signal of the other system, the input abnormal signal of the other system, and the other system package (the first system package or the 0th package). And a mounting signal of another system indicating that the system package is mounted.
[0011]
Further, the active system determination circuit is configured to determine whether the own system package (the zero system package or the first system package) is to be the active system or the standby system, and input to the active system determination circuit. Comparing the first SW bit signal of the system with the first SW bit signal of the other system, determining the input abnormal signal of the own system and the input abnormal signal of the other system input to the active system determination circuit, And a logic circuit for making a determination including the mounting signal of another system when the first SW bit signal of the own system does not match the first SW bit signal of the other system for some reason. If it is determined that the own system package becomes the active system, an active system instruction signal is output to the own system device (the zero system device or the first system device), and the own system device becomes the active system. That the If it is determined that the standby system becomes the standby system, the output of the operation system instruction signal to the own system device (the 0 system device or the 1 system device) is stopped, and the own system device becomes the standby system. It is characterized by the fact that it has become.
[0012]
Further, in the operation switching control operation of the operation determination circuit, the format conversion unit terminates the system switching permission signal from the first main signal and outputs the signal as the first SW bit signal to the operation system determination circuit. It is started when it is sent.
[0013]
When the active system switching control operation of the active system determination circuit is started (S1), first, the first SW bit signal of the other system is compared with the first SW bit signal of the own system ( S2) If the first SW bit signal of the other system matches the first SW bit signal of the own system (matched in step S2), it is indicated by the first SW bit signal of the own system. The SW bit that has been instructed to become the active system and the SW bit are determined, and the process proceeds to step S9. In step S9, the determined SW bit is compared with the slot ID signal of the own system, and both are determined. If they have been matched (coincident in step S9), the own system becomes the active system (S10), and the active system instruction signal is output to the own system device (the zero system device or the first system device) ( S11), the self-system package and the self-system device The fact that the system has become the active system is communicated, and if the two do not match in step S9 (mismatch in step S9), the own system becomes the standby system (S12), and the own system device (the 0 system device or the 1 system device) ), The output of the operation system instruction signal is stopped (S13), and the fact that the self system package and the self system device have become the standby system is transmitted.
[0014]
Further, when the first SW bit signal of the other system and the first SW bit signal of the own system do not match in the step S2 (mismatch in step S2), first, the input abnormality of the own system package is performed. With reference to the signal, it is determined whether there is an input abnormality in the own system package (S3). If the input abnormality signal of the own system package does not have an input abnormality (OK in step S3), then, the input of another system is performed. With reference to the abnormal signal and the mounting signal of the other system, it is determined whether there is an input abnormality of the other system package and the mounting state of the other system package (S4). If the input abnormality signal indicates that there is an input abnormality, or if the mounting signal of the other system package indicates that no other system package is mounted (not mounted in step S4), the process proceeds to step S6. , To confirm the SW bit assumes that system represented by the first SW bit-signal of the system at the step S6 is instructed to the operation system, the process proceeds to step S9, wherein the.
[0015]
Also, as a result of the determination in step S4, when the mounting signal of the other system package indicates that the other system package is mounted and the input abnormal signal of the other system package indicates that there is no input abnormality, (Implemented in step S4), the process proceeds to step S7, and in step S7, the SW bit is determined so that if the immediately preceding system is the active system (system 1 is the standby system), "0 system is the active system" If the 1st system is the active system (0 system is the standby system), the SW bit is determined so that "1 system is the active system", and the process proceeds to step S9.
[0016]
Further, as a result of the determination in step S3, if the input abnormal signal of the own system package has an input abnormality (abnormal in step S3), then the input abnormal signal of another system and the mounting signal of another system are compared. With reference to, it is determined whether there is an input abnormality of the other system package and the mounting state of the other system package (S5). As a result of the determination in step S5, the input abnormality signal of the other system package indicates that there is an input abnormality. Or if the mounting signal of the other system package indicates that no other system package is mounted (not mounted in step S5), the process proceeds to step S7, and after step S7, the process proceeds to step S9. Features.
[0017]
Also, as a result of the determination in step S5, when the mounting signal of the other system package indicates that the other system package is mounted, and the input abnormal signal of the other system package indicates that there is no input abnormality, (Implemented in step S5), the process proceeds to step S8, and in step S8, the SW bit is determined by assuming that the system indicated by the first SW bit signal of the other system has been instructed to be the active system. Go to S9.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0019]
FIG. 1 is a block diagram showing an embodiment of an active system switching method by hardware control according to the present invention.
[0020]
The present embodiment shown in FIG. 1 includes a device 2 such as a transmission device that is in a master-slave relationship and is a master side, and a device 1 such as a transmission device that is a slave side. Communication is performed via a communication line 40-1 and a communication line 40-2. The device 1 has a duplex configuration and includes a 0-system device 20-1 and a 1-system device 20-2, and one of the 0-system device 20-1 and the 1-system device 20-2 is used as an active system. And the other is a standby system. In response to a request from the slave device 1, the main device 2 performs system switching that permits which of the 0-system device 20-1 and the 1-system device 20-2 in the device 1 becomes the active system. It has a function of sending a permission signal.
[0021]
The device 1 has a duplex configuration, and communicates with the PKG (package) 3-1 that interfaces the communication between the device 2 and the 0-system device 20-1, and the communication between the device 2 and the 1-system device 20-2. PKG3-2 for interfacing. The main signal 101-1 is transmitted from the device 2 to the PKG 3-1 of the device 1, and the main signal 102-1 is transmitted from the PKG 3-1 to the device 2. The main signal 101-2 is transmitted from the device 2 to the PKG 3-2 of the device 1, and the main signal 102-2 is transmitted from the PKG 3-2 to the device 2. The main signal 101-1 and the main signal 101-2 are the same signal.
[0022]
The PKG 3 (PKG 3-1 and PKG 3-2) of the device 1 includes a format conversion unit 4 (a format conversion unit 4-1 and a format conversion unit 4-2). The main signal 101 (main signal 101-1 and main signal 101-2) transmitted to the device 1 is converted into the data format in the device 1, and the main signal 111 is transmitted to the 0-system device 20-1 and the 1-system device 20-2. (Main signal 111-1 and main signal 111-2) and main signal 112 (main signal 112-1 and main signal 112-2) transmitted from system 0 device 20-1 and system 1 device 20-2. ), And transmits the result to the device 2 as the main signal 102 (main signal 102-1 and main signal 102-2). The format conversion unit 4 has a function of inserting a SW bit and an FL bit, which will be described later, into the main signal 102 and a function of terminating the SW bit of the main signal 101.
[0023]
Here, referring to FIG. 2, main signal 101 (main signal 101-1 and main signal 101-2) and main signal 102 (main signal 102-1 and main signal 102) transmitted and received between apparatus 2 and apparatus 1 The data format of -2) will be described.
[0024]
FIG. 2 is a diagram illustrating the data format of the inter-device main signal.
[0025]
FIG. 2A shows a main signal 102 transmitted from the device 1 to the device 2. The main signal 102 includes an OH 1021 as an overhead (Over Head) for storing operation / maintenance information between apparatuses, a 1-bit SW 1022 named SW, a 1-bit FL 1023 named FL, and And a data area 1024 for storing data to be transmitted to the second area.
[0026]
The SW 1022 is used as a monitor SW bit for transmitting to the device 2 which system of the device 1 is the active system. If SW = 0, the 0-system device 20-1 is currently operated. If SW = 1, it indicates that the first system device 20-2 is currently operating.
[0027]
The FL 1023 is used as an FL bit as a system switching request signal of the device 1. If FL = 0, it indicates that the system 0 device 20-1 is to be used as an active system. This indicates that the device 20-2 is to be used as an active system.
[0028]
FIG. 2B shows a main signal 101 transmitted from the device 2 to the device 1. The main signal 101 includes an OH 1011 as an overhead (Over Head) for storing operation / maintenance information between devices, a 1-bit SW 1012 named SW, a 1-bit FL 1013 named FL, and And a data area 1014 for storing data to be transmitted to the data area 1.
[0029]
The SW 1012 is used as a SW bit as a system switching permission signal of the device 1. If SW = 0, it indicates that the 0-system device 20-1 is to be used as the active system. This indicates that the device 20-2 is to be used as the active system. The FL bit of FL1013 is not used.
[0030]
Returning to FIG. 1, the description of the present embodiment will be continued.
[0031]
The PKG 3 (PKG 3-1 and PKG 3-2) of the device 1 is an operation determination unit 5 (operation determination unit 5-) connected to the format conversion unit 4 (the format conversion unit 4-1 and the format conversion unit 4-2). 1 and an operation system determination unit 5-2) and PG6 (PG6-1 and PG6-2) as a pattern generator.
[0032]
The PG 6 has a function of outputting a position indication signal of the SW bit and the FL bit to the format conversion unit 4. That is, PG6 (PG6-1 and PG6-2) is composed of the SW bit end position indicating signal 16 (signal indicating the position of the SW 1012 (FIG. 2B) in the main signal 101) and the SW bit insertion position indicating signal. 17 (the signal indicating the position of the SW 1022 (FIG. 2A) in the main signal 102) and the FL bit insertion position indicating signal 18 (the position of the FL 1023 (FIG. 2A)) in the main signal 102. ) To the format conversion unit 4 (the format conversion units 4-1 and 4-2).
[0033]
The active system determination unit 5 has a function of determining whether or not its own package (PKG3-1 or PKG3-2) becomes the active system. The format conversion unit 4 terminates the SW bit signal from the main signal 101. 7 and the input abnormal signal 9 detected by the format conversion unit 4, and at the same time, sends to the format conversion unit 4 a SW bit signal 8 (SW bit signal 8-1, SW bit signal 8- Send 2). The input abnormal signal 9 is determined to have an input abnormality when the format conversion unit 4 detects an abnormality in the data frame of the main signal 101, and is determined to have no input abnormality if the data frame of the main signal 101 can be received without abnormality.
[0034]
Further, the slot ID 30 (slot ID 30-1 and slot ID 30-2) indicating the package insertion position when the own package (PKG 3-1 or PKG 3-2) is mounted on the device 1 is input to the active system determination unit 5. Have been. Here, the value of the slot ID 30 is set to the slot ID 30-1 = 0 (that is, the PKG 3-1 is used as an interface package of the 0-system apparatus 20-1 and the slot number of the insertion position is set, Is 0), and the slot ID 30-2 = 1 (that is, the PKG3-2 is used as an interface package of the first system device 20-2, and the slot number at the insertion position is 1). And
[0035]
The active system determining unit 5-1 and the active system determining unit 5-2 transmit and receive the following signals to and from each other. That is, from the active system determination unit 5-1 to the active system determination unit 5-2, the SW bit signal 10-1 terminated by the format converter 4-1 of the PKG 3-1 (the same as the SW bit signal 7-1). ), The input abnormal signal 12-1 detected by the format converter 4-1 of the PKG 3-1 (same as the input abnormal signal 9-1), and the mounting signal 14-1 indicating that the PKG 3-1 is mounted. Is transmitted from the active system determination unit 5-2 to the active system determination unit 5-1. The SW bit signal 10-2 (SW bit signal 7-terminal) terminated by the format conversion unit 4-2 of the PKG 3-2. 2), an input abnormal signal 12-2 detected by the format converter 4-2 of the PKG 3-2 (same as the input abnormal signal 9-2), and a mounting signal indicating that the PKG 3-2 is mounted. 14-2.
[0036]
The active system determination unit 5 inputs the SW bit signal of the own system input to the active system determination unit 5 to determine whether the own package (PKG3-1 or PKG3-2) becomes the active system or the standby system. 7 and the SW bit signal 10 of the other system, the judgment of the input abnormal signal 9 of the own system and the input abnormal signal 12 of the other system inputted to the active system judging unit 5, and the SW bit signal of the own system due to some factor. 7 and a logic circuit for making a determination including the mounting signal 14 of the other system when the SW bit signal 10 of the other system does not match. The active system instruction signal 121 (the active system instruction signal 121-1 or the active system instruction signal 121-2) is output to the device (0 system device 20-1 or 1 system device 20-2). Communicate that it has become an operation system, and own package If the standby system is determined, the output of the operation system instruction signal 121 to the device of the own system (0 system device 20-1 or 1 system device 20-2) is stopped, and the own system becomes the standby system. Communicate what has become.
[0037]
The active / standby determination logic of the active determination unit 5 described above will be described with reference to FIG. 3, it is assumed that PKG3-1 is a 0-system interface package and PKG3-2 is a 1-system interface package for ease of description below.
[0038]
FIG. 3 is a diagram illustrating the active / standby determination logic of the active determination unit.
[0039]
In FIG. 3, the horizontal direction (rows A1 and A2) indicates the state of system 0, and the vertical direction (columns B1 and B2) indicates the state of system 1. The “0 system normal” in the row of 1 indicates that the input abnormality signal 9-1 received by the active system determination unit 5-1 of the 0 system PKG 3-1 has no input abnormality, The “0-system abnormality” in the row of b1 indicates that the input abnormality signal 9-1 received by the active-system determination unit 5-1 of the 0-system PKG 3-1 has an input abnormality. The “0 system designation” in the row of a 2 means that the SW bit terminated by the format converter 4-1 of the 0 system PKG 3-1 from the main signal 101-1 designates the 0 system as the active system. "0" (that is, the case where the SW bit signal 7-1 = 0) is shown, and "1 system designation" in the row of (b) is the format conversion unit 4 of the 0 system PKG3-1. The SW bit terminating from the main signal 101-1 with “−1” indicates a case where “1” is designated to designate the system 1 as the active system (that is, a case where the SW bit signal 7-1 = 1).
[0040]
Similarly, "1 system normal" in the row of b1 indicates that the input abnormality signal 9-2 received by the active system determination unit 5-2 of the 1 system PKG 3-2 has no input abnormality. The "1 system abnormality" in the row of b1 indicates that the input abnormality signal 9-2 received by the active system determination unit 5-2 of the 1 system PKG 3-2 has an input abnormality. ing. The “0-system designation” in the row of B2 refers to the SW bit terminated by the format converter 4-2 of the 1-system PKG 3-2 from the main signal 101-2 to designate the 0-system as the active system. "0" (that is, the case where the SW bit signal 7-2 = 0) is shown, and the "1 system designation" in the row of b2 is the format conversion unit 4 of the 1 system PKG3-2. -2 indicates that the SW bit terminated from the main signal 101-2 is "1" which designates the system 1 as the active system (that is, the case where the SW bit signal 7-2 = 1).
[0041]
As described above, the active system determination unit 5-1 sets the SW bit signal 7-1 as the SW bit signal 10-1 together with the mounting signal 14-1, and converts the input abnormal signal 9-1 into the input abnormal signal 12-. 1 is sent to the active system determination unit 5-2, and conversely, the active system determination unit 5-2 converts the SW bit signal 7-2 into the SW bit signal 10-2 together with the mounting signal 14-2. Since the input abnormal signal 9-2 is transmitted as the input abnormal signal 12-2 to the active system determination unit 5-1, it is possible to recognize the state of the other system.
[0042]
The active / standby system determination logic for determining whether the own system becomes the active system or the standby system in the active system determination unit 5 is as follows.
[0043]
(A) At the intersection of the third row and the third column, the system 0 is designated as normal for system 0 and the system 0 is designated as normal for system 1, so it is determined that "system 0 is active" and system 1 is designated as the standby system. Is determined. Similarly, at the intersection of the 4th row and the 4th column, the system 1 is designated as normal for system 0, and the system 1 is designated as normal for system 1, so it is determined that "system 1 is active" and system 0 is designated as active. It is determined to be a standby system.
[0044]
(A) At the intersection of the third row and the fourth column, system 1 is specified when system 0 is normal, and system 0 is specified when system 1 is normal. Even though both system 0 and system 1 are normal, both systems operate. Since the system specified as the system is different, it is impossible to make a correct determination, and in this case, it is determined that "previous state holding". “Preservation of previous state” means that the state immediately before making this determination is retained. If the immediately preceding state is that system 0 is the active system (system 1 is the standby system), “system 0 is operating If the first system is the active system (the zero system is the standby system), it is determined that the first system is the active system. Similarly, at the intersection of row 4 and row 3 column, system 0 is designated as normal for system 0, and system 1 is designated as normal for system 1, and although both system 0 and system 1 are normal, Since the system designated as the active system differs between the two, it is impossible to make a correct determination, and in this case, it is determined that "previous state holding". The “previous state holding” is as described above. If the immediately preceding state is that the system 0 is the active system (the system 1 is the standby system), it is determined that the system 0 is the active system and the system 1 is the active system. If (system 0 is the standby system), it is determined that “system 1 is the active system”.
[0045]
The row 5a shows the status of the system 1 abnormality, so the system 1 is not used for the determination. That is, if the 0 system is normal, only the 0 system is used for the determination, and if the 0 system is normal and the 0 system is specified, it is determined that “0 system is the active system” (the intersection of row a and row b and column b). If system 0 is normal and system 1 is designated, it is determined that "system 1 is active" (the intersection of row 5 and row 4). Further, if the system 0 is abnormal, the system 0 is not used for the determination, and at this time, it is determined that "previous state is held" (the intersection of row a and row b).
[0046]
Column B5 indicates the status of the system 0 abnormality. Therefore, the system 0 is not used for the determination, and if the system 1 is normal and the system 0 is designated, it is determined that the system 0 is the active system (a). If the first system is normal and the first system is specified, it is determined that "the first system is the active system" (the intersection of the fourth row and the fifth column).
[0047]
Next, an active system switching control operation performed by the active system determination unit 5 will be described with reference to FIG. In FIG. 4 as well, for simplicity of the following description, it is assumed that PKG3-1 is a 0-system interface package, PKG3-2 is a 1-system interface package, and PKG3-1 is a local system (or a local system). PKG), and PKG3-2 is referred to as another system (or another system PKG).
[0048]
FIG. 4 is a diagram illustrating an active system switching control operation performed by the active system determination unit.
[0049]
The active system switching control operation of the active system determination unit 5 is performed when the format conversion unit 4 terminates the SW bit (system switching permission signal) from the main signal 101 and sends it to the active system determination unit 5 as the SW bit signal 7. Is started. The active system determination unit 5-1 includes a self system SW bit signal 7-1, another system SW bit signal 10-2 (same as the SW bit signal 7-2), and a self system input abnormal signal 9-1. Then, the active system switching control operation is performed using the other system input abnormal signal 12-2 (same as the input abnormal signal 9-2) and the other system mounted signal 14-2.
[0050]
When the active system switching control operation of the active system determination unit 5-1 is started (S1), first, the SW bit signal 10-2 of the other system is compared with the SW bit signal 7-1 of the own system (S2). . If the SW bit signal 10-2 of the other system matches the SW bit signal 7-1 of the own system (match at step S2), it can be determined that the SW bit received by the device 1 is normal. The SW bit received by the PKG is determined as valid. That is, the system instructed to make the system indicated by the SW bit signal 7-1 of the own system the active system and the SW bit are determined, and the process proceeds to step S9. In step S9, the determined SW bit is compared with the slot ID 30-1 of the own system, and if they match (match in step S9), the own system becomes the active system (S10), and the 0 of the own system is set. The active system instruction signal 121-1 is output to the system device 20-1 (S11), and the fact that the own system PKG and the zero system device 20-1 have become active systems is transmitted. If the two do not match in step S9 (they do not match in step S9), the own system becomes the standby system (S12), and the output of the active system instruction signal 121-1 to the own system 0 device 20-1 is stopped ( S13), the self-system PKG and the 0-system apparatus 20-1 are notified that they have become standby systems.
[0051]
In step S2, when the other system SW bit signal 10-2 and the own system SW bit signal 7-1 do not match (mismatch in step S2), first, refer to the input abnormal signal 9-1 of the own system PKG. Then, it is determined whether there is an input abnormality of the own system PKG (S3). If the input abnormal signal 9-1 of the own system PKG has no input abnormality (OK in step S3), then, referring to the other system input abnormal signal 12-2 and the other system mounted signal 14-2. Then, it is determined whether there is an input abnormality of the other system PKG and the mounting state of the other system PKG (S4). As a result of the determination in step S4, when the input abnormal signal 12-2 of the other system PKG indicates that there is an input abnormality, or when the mounting signal 14-2 of the other system PKG indicates that the other system PKG is not mounted. (Not implemented in step S4), the process proceeds to step S6, and the SW bit received by the own system PKG is determined as a valid one (S6). That is, in step S6, the SW bit is determined assuming that the system indicated by the SW bit signal 7-1 of the own system has been instructed to be the active system. After determining the SW bit, the process proceeds to step S9.
[0052]
As a result of the determination in step S4, when the mounting signal 14-2 of the other system PKG indicates that the other system PKG is mounted and the input abnormal signal 12-2 of the other system PKG indicates that there is no input abnormality. (Implemented in step S4), the process proceeds to step S7, and "previous state holding" similar to that shown in FIG. 3 is performed (S7). That is, in step S7, if the immediately preceding state is that the 0 system is the active system (1 system is the standby system), the SW bit is determined so that “0 system is the active system”, and the 1 system is the active system (0 system). Is the standby system), the SW bit is determined so that "1 is the active system", and the process proceeds to step S9.
[0053]
As a result of the determination in step S3, if the input abnormal signal 9-1 of the own system PKG has an input abnormality (abnormal in step S3), then the other system input abnormal signal 12-2 and the other system mounted signal 14 With reference to -2, it is determined whether there is an input abnormality of the other system PKG and the mounting state of the other system PKG (S5). As a result of the determination in step S5, when the input abnormality signal 12-2 of the other system PKG indicates that there is an input abnormality, or the mounting signal 14-2 of the other system PKG indicates that the other system PKG is not mounted. (Not implemented in step S5), the process proceeds to step S7, and the state is maintained. After step S7, the process proceeds to step S9.
[0054]
As a result of the determination in step S5, when the mounting signal 14-2 of the other system PKG indicates that the other system PKG is mounted and the input abnormal signal 12-2 of the other system PKG indicates that there is no input abnormality. (Implemented in step S5), the process proceeds to step S8, and the SW bit received by the other system PKG is determined as a valid one (S8). That is, in step S8, the SW bit is determined assuming that the system indicated by the SW bit signal 10-2 of the other system has been instructed to be the active system. After determining the SW bit, the process proceeds to step S9.
[0055]
The active system switching control operation performed by the active system determination unit 5-1 has been described above with reference to FIG. The active system determination unit 5-2 has a configuration in contrast to the active system determination unit 5-1. Therefore, the operation system switching control operation performed by the active system determination unit 5-2 is the same as the operation illustrated in FIG. It is. Therefore, further description of the operation system switching control operation of the operation system determination unit 5-2 is omitted.
[0056]
Next, with reference to FIGS. 1 and 2 again, an example of the overall operation of the active system switching in the present embodiment will be described.
[0057]
In the device 1 of the duplex configuration, the 0-system device 20-1 and the PKG3-1 are the 0-system, the 1-system device 20-2 and the PKG3-2 are the 1-system, and the PKG3-1 is a communication line 40-. 1, and the PKG 3-2 communicates with the device 2 via the communication line 40-2. Now, it is assumed that the system 0 is in the active system and the system 1 is in the standby system.
[0058]
Here, when a request for switching the active system from the PKG 3-1 of the system 0 to the PKG 3-2 of the system 1 occurs, the PKG 3-1 sends a system switching request signal to the device 2. That is, the PKG 3-1 sets FL = 1 in the main signal 102 shown in FIG. 2A and sends a message indicating that the system 1 is to be used as the active system. At this time, the SW bit of the main signal 102 in FIG. 2A is SW = 0, indicating that the 0 system is currently the active system.
[0059]
Upon receiving the system switching request signal, the device 2 sends a system switching permission signal to both the PKG 3-1 and the PKG 3-2 of the device 1. That is, the device 2 sets SW = 1 with the main signal 101 shown in FIG. 2B and sends a message to the PKG3-1 and PKG3-2 that the first system is to be the active system.
[0060]
When the PKG 3-1 and the PKG 3-2 of the device 1 receive the main signal 101, each format converter 4 terminates the SW bit (system switching permission signal) from the main signal 101, and uses this as a SW bit signal 7, It is sent to each active system determination unit 5. At this time, the SW bit signal 7 is "1" (let 1 be the active system).
[0061]
The active system determination unit 5 of the PKG 3-1 and the PKG 3-2 performs a comparison determination between the SW bit signal 7 of the own system and the SW bit signal 7 of the other system according to the active system switching control operation shown in FIG. The PKG 3-1 which was the system becomes the standby system, and the PKG 3-2 which was the standby system is switched to the active system. When the PKG 3-1 becomes the standby system, the PKG 3-1 stops outputting the operation system instruction signal 121-1 to the 0 system device 20-1, so that the 0 system device 20-1 also becomes the standby system at the same time. When the PKG 3-2 becomes the active system, the PKG 3-2 outputs the active system instruction signal 121-2 to the first system device 20-2, so that the first system device 20-2 simultaneously becomes the active system. In this way, the system 0 that was the active system becomes the standby system, and the system 1 that was the standby system becomes the active system.
[0062]
【The invention's effect】
As described above, in the active system switching method by hardware control of the present invention, the switching between the active system and the standby system of the duplexed device can be controlled only by the hardware circuit, so that the switching time can be reduced. It is possible to achieve the effect.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an active system switching method by hardware control according to the present invention.
FIG. 2 is a diagram showing a data format of an inter-device main signal.
FIG. 3 is a diagram illustrating an active / standby determination logic of an active determination unit;
FIG. 4 is a diagram illustrating an active system switching control operation performed by an active system determination unit.
[Explanation of symbols]
1 device
2 Equipment
3-1、3-2 PKG
4-1 and 4-2 format conversion unit
5-1 and 5-2 active system determination unit
6-1 and 6-2 PG
7-1, 7-2 SW bit signal
8-1, 8-2 SW bit signal
9-1, 9-2 Input abnormal signal
10-1, 10-2 SW bit signal
12-1, 12-2 Input abnormal signal
14-1, 14-2 Mounting signals
16 SW bit end position indication signal
17 SW bit insertion position indication signal
18 FL bit insertion position indication signal
20-10 system equipment
20-2 System 1 device
30-1, 30-2 Slot ID
40-1, 40-2 communication line
101-1, 101-2 Main signal
102-1, 102-2 Main signal
111-1, 111-2 main signal
112-1, 112-2 main signal
121-1, 121-2 Operation system instruction signal

Claims

A main device for transmitting a system switching permission signal; a system 0 device and a system 1 device; receiving the system switching permission signal transmitted from the main device; And a slave device having a duplex configuration capable of operating one of the first system devices as an active system and the other as a standby system, wherein the slave device includes the main device and the zero system. A 0-system package for interfacing communication with the device via a first communication line, and a 1-system package for interfacing communication between the main device and the first system device via a second communication line, When each of the 0-system package and the 1-system package of the slave device receives the system switching permission signal from the main device at the same time, each of the 0-system package and the 1-system package becomes its own package. By mutually transmitting and receiving the terminated system switching permission signal, it is determined whether the own package becomes the active system or the standby system, and the determined result is transmitted to the 0-system apparatus and the 1-system apparatus, respectively. A system switching method by hardware control, wherein one of the system 0 and the system 1 is operated as an active system and the other is operated as a standby system.

The 0-system package and the 1-system package have the same configuration and function as each other, and the 0-system package and the 1-system package each include a format conversion unit and an operation system determination circuit, and the format conversion unit Performs a format conversion of a first main signal transmitted from the master device to the slave device, transmits the format signal to a self-system device (the zero-system device or the first-system device) as a second main signal, and Whether the system switching permission signal is terminated from the first main signal and sent to the operation system determination circuit as a first SW bit signal, and whether an abnormality is detected in the data frame of the first main signal; Is transmitted to the operation system determination circuit, and the format conversion of the third main signal from the own system device (the 0 system device or the 1 system device) is performed. A fourth main signal is generated by inserting a second SW bit signal indicating which of the system 0 and the system 1 is the active system and an FL bit signal as a system switching request signal. 2. The operating system switching method according to claim 1, wherein the fourth main signal is transmitted to the main device.

The format converter further outputs a SW bit end position indicating signal indicating the position of the system switching permission signal in the first main signal, and outputs a second SW in the fourth main signal. 3. The hardware according to claim 2, wherein a pattern generator that outputs a SW bit insertion position indication signal indicating a bit signal position and an FL bit insertion position indication signal indicating a FL bit signal position is connected. Operation system switching method by wear control.

A slot ID signal indicating a package insertion position when a self-system package (either the zero-system package or the one-system package) is mounted on the slave device is further input to the active system determination circuit. The operating system switching method by hardware control according to any one of claims 2 and 3, characterized in that:

The active-system determination circuit includes a first SW bit signal of another system, an input abnormal signal of another system, and another-system package (the first-system package or the zero-system package). 5. The active system switching method according to claim 4, further comprising an input signal of another system indicating that said system is implemented.

The operating system determination circuit is configured to determine whether the own system package (the 0 system package or the 1 system package) is to be the active system or the standby system, and input to the active system determining circuit. Comparing the first SW bit signal with the first SW bit signal of another system, determining the input abnormal signal of the own system and the input abnormal signal of the other system input to the active system determination circuit, and When the first SW bit signal of the own system does not match the first SW bit signal of the other system for some reason, the logic circuit is configured to make a determination including the mounting signal of the other system. When it is determined that the own system package becomes the active system, an active system instruction signal is output to the own system device (the zero system device or the first system device), and the own system device becomes the active system. That your own package If it is determined that the system is to be the system, the output of the operation system instruction signal to the system (the system 0 or the system 1) is stopped, and the system becomes the standby system. The operating system switching method by hardware control according to claim 5, wherein the communication is transmitted.

In the active system switching control operation of the active system determination circuit, the format conversion unit terminates the system switching permission signal from the first main signal and sends it to the active system determination circuit as the first SW bit signal. 7. The active system switching method by hardware control according to claim 6, wherein the active system switching method is started at any time.

When the active system switching control operation of the active system determination circuit is started (S1), first, the first SW bit signal of the other system is compared with the first SW bit signal of the own system (S2). When the first SW bit signal of the other system and the first SW bit signal of the own system match (match at step S2), the system indicated by the first SW bit signal of the own system. Are determined to be the active system and the SW bit are determined, and the process proceeds to step S9. In step S9, the determined SW bit is compared with the slot ID signal of the own system, and the two match. In this case (coincidence in step S9), the own system becomes the active system (S10), and the active system instruction signal is output to the own system device (the 0 system device or the 1 system device) (S11). , The own package and the own device are operated If the two do not match at step S9 (they do not match at step S9), the own system becomes a standby system (S12), and the own system (the 0-system device or the 1-system device) 8. The operation by hardware control according to claim 7, wherein the output of the operation system instruction signal is stopped (S13), and the fact that the self system package and the self system device have become the standby system is transmitted. System switching method.

If the first SW bit signal of the other system does not match the first SW bit signal of the own system in step S2 (mismatch in step S2), first, the input abnormal signal of the own system package is transmitted. It is determined whether or not there is an input abnormality of the own system package by referring to (S3). If the input abnormality signal of the own system package does not have an input abnormality (OK in step S3), then the input abnormality signal of another system is next. It is determined whether or not there is an input abnormality of the other system package and the mounting state of the other system package with reference to the above and the mounting signal of the other system (S4). If the signal indicates that there is an input abnormality, or if the mounting signal of the other system package indicates that no other system package is mounted (not mounted in step S4), the process proceeds to step S6. 9. The system according to claim 8, wherein in step S6, the SW bit is determined assuming that the system indicated by the first SW bit signal of the own system has been instructed to be the active system, and the process proceeds to step S9. The operating system switching method by the hardware control described.

As a result of the determination in step S4, if the mounting signal of the other system package indicates that the other system package is mounted and the input abnormal signal of the other system package indicates that there is no input abnormality (step S4). In step S7, the SW bit is determined so that the immediately preceding state becomes "0 is the active system" if the 0 system is the active system (1 system is the standby system). 10. The hardware according to claim 9, wherein if the system 1 is the active system (the system 0 is the standby system), the SW bit is determined so that the system 1 becomes the active system, and the process proceeds to step S9. Operation system switching method by control.

If the result of determination in step S3 is that the input abnormality signal of the own package has an input abnormality (abnormal in step S3), then reference is made to the input abnormality signal of another system and the mounting signal of another system. Then, it is determined whether there is an input abnormality of the other system package and the mounting state of the other system package (S5). As a result of the determination in step S5, whether the input abnormality signal of the other system package indicates that there is an input abnormality, Alternatively, if the mounting signal of the other system package indicates that no other system package is mounted (not mounted in step S5), the process proceeds to step S7, and after step S7, the process proceeds to step S9. An operating system switching method by hardware control according to claim 10.

As a result of the determination in the step S5, when the mounting signal of the other system package indicates that the other system package is mounted and the input abnormal signal of the other system package indicates that there is no input abnormality (step S5). In step S8, the SW bit is determined assuming that the system indicated by the first SW bit signal of the other system has been instructed to be the active system, and the process proceeds to step S9. The system switching method based on hardware control according to claim 11, further comprising: