JP3572788B2 - Semiconductor device for detecting alignment accuracy, method for manufacturing the same, and method for detecting alignment accuracy - Google Patents

Description

と表される。ここで、
α＝Ｔ×ε_０ ×（ε−１）／ｄ
β＝Ｔ×Ｌ０ ×ε_０ ／ｄ
とする。また、
Ｃｎ：挿入量Ｌｎの場合の電気容量
Ｃｎ（ＳｉＯ_２ ）：挿入量Ｌｎの場合の層間絶縁膜と電極との重なる部位の電気容量
Ｃｎ（ｎｏｎＳｉＯ_２ ）：挿入量Ｌｎの場合の層間絶縁膜と電極との重ならない部位の電気容量
Ｌｎ：層間絶縁膜の電極間への挿入量
Ｌ０ ：電極の向き合う幅
Ｔ：電極の向き合う高さ（配線の膜厚）
ｄ：電極間の距離
ε：電極間に挿入する層間絶縁膜の比誘電率
ε_０ ：真空の誘電率
である。
【００２５】
従って、（１）式のＬ０ 、Ｔ、ｄ、ε、ε_０ は合わせずれとは関係のない定数であるから、（２）式のように置き換えられ、電気容量Ｃｎは挿入量Ｌｎの一次式となって、電気容量Ｃｎと挿入量Ｌｎは比例関係にあることが分かる。例えば層間絶縁膜８を二酸化シリケイト（ＳｉＯ_２ ）とすると、その比誘電率ε＝３．９であるからε−１＞０となり、（２）式の傾きは正であるから挿入量Ｌｎが増えるにしたがって電気容量Ｃｎも増大するという相関関係が得られる。
【００２６】
以上説明したことは図５に示すように、横方向の合わせずれ検出〔同図（ａ）〕と縦方向の合わせずれ検出〔同図（ｂ）〕の何れに用いても良いことは勿論であり、層間絶縁膜８の電極間への挿入方向を合わせずれの検出方向と一致して設けることで、それぞれの方向の合わせずれ量を検出する評価パターンを形成することができる。
【００２７】
図６は上述した縦方向および横方向の合わせずれ検出部を一体として形成した評価パターン５の一例であって、電極７ａ１ 、電極７ｂ、層間絶縁膜８で構成される縦方向の検出パターンと、電極７ａ２ 、電極７ｃ、層間絶縁膜８で構成される横方向の検出パターンとがあり、電極７ａ１ 、７ａ２ は共通で下層メタル配線１０ａにより出力端子１１ａに接続され、また、電極７ｂは下層メタル配線１０ｂで出力端子１１ｂに、電極７ｃは下層メタル配線１０ｃで出力端子１１ｃにそれぞれ接続され、これらの出力端子からテスターにより、合わせずれによる電気容量の変動を測定する。
【００２８】
つぎに、評価パターン５の製造方法について図７を参照して説明する。図７は図２のＡ_１ −Ａ_１ ′線上における断面図である。
【００２９】
まず、第一の工程では図７（ａ）に示すように基盤となる下層の絶縁膜６を、例えばＳｉＯ_２ を気相成長（ＣＶＤ）により成膜する。この部分についてはエッチングを行わない。第二の工程では図７（ｂ）に示すように下層メタル配線層１０となる金属を例えばスパッタリング法により蒸着し、形成する。第三の工程では図７（ｃ）に示すように下層メタル配線層１０をフォトリソグラフィー工程によりパターンニングし、エッチング工程においてエッチングして、所望の配線形状に加工し、電極７ａおよび電極７ｂを形成する。第四の工程では図７（ｄ）に示すように層間絶縁膜８を、例えばＳｉＯ_２ を気相成長（ＣＶＤ）により成膜し、最後に図７（ｅ）に示すように層間絶縁膜８をフォトリソグラフィー工程によりパターンニングし、エッチング工程においてエッチングして、所望の形状に形成する。
【００３０】
上述した評価パターン５の製造は実回路を作成する過程で同時に行われるものであって、別途、そのための工程を必要とするものではない。
【００３１】
つぎに、合わせずれ検出精度を向上させる方法について説明する。その第一は評価パターンを複数段設ける方法であり、その第二は校正用回路を設ける方法である。
【００３２】
まず、第一の方法について図８を参照して説明する。
従来、半導体素子の測定には極めて微弱な電気量を取り扱うために、外部からの電気的ノイズの影響を受け、誤差が生じることが多かった。この電気容量の微小な変化まで精度よく検出するために、複数段の評価パターン５を設けて電気容量の変化を増幅させて検出するものである。
【００３３】
図８（ａ）は８段の構成例を示し、電極７１ａ〜７８ａはそれぞれ下層メタル配線１０ａに接続し、更に、出力端子１１ａに導かれ、また、電極７１ｂ〜７８ｂもそれぞれ下層メタル配線１０ｂに接続し、更に、出力端子１１ｂに導かれている。また、層間絶縁膜８１〜８８が電極７１ａ〜７８ａと電極７１ｂ〜７８ｂに渡って設けられていて、それぞれが容量形成部を構成する。図８（ｂ）は上述した評価パターンの等価回路であって、それぞれの容量形成部はコンデンサＣ_１ 〜Ｃ_８ で示されている。
【００３４】
リソグラフィ工程においてパターンニングに合わせずれが生じると、電極と層間絶縁膜の重なりが一斉に同じ方向に同じ量だけ理想状態からずれるために、電気容量の変化量は、単体の場合に比べて複数倍（図８では８倍）大きくなる。図８では８段の構成であるが、これに限ることなく任意の段数を設けてよいことは当然である。
【００３５】
この段数をｗとし、出力端子１１ａおよび１１ｂより測定される電気容量Ｃｎは
Ｃｎ＝Ｃ_０ ×ｗ＋ΔＣｎ×ｗ （３）
で表される。ここでＣ_０ は合わせずれが無い場合の個々のコンデンサの電気容量であり、ΔＣｎは合わせずれにより発生した個々のコンデンサの電気容量の変化量である。従って、（３）式より変化量はΔＣｎの段数（ｗ）倍に増幅されていることが分かる。これは測定時の外部ノイズの影響を軽減する効果がある。また、複数のコンデンサを同時に測定することにより平均化する効果があり、評価パターンの製造ばらつきの影響を低減することになる。
【００３６】
合わせずれ検出精度を向上させる第二の方法は校正用回路を用いるものであり、これを図９を参照して説明する。従来の問題として、測定精度の低下をおよぼす原因に、半導体装置の種々の製造ばらつきがある。例えば、図３（ａ）の電極７ａ、７ｂの幅Ｌ０ 、膜厚Ｔ、電極間距離ｄ、相関絶縁膜８の挿入量Ｌｎ、相関絶縁膜８の膜質変化（特に比誘電率εの変化）等があり、これらの変化は（１）式または（２）式で表させる電気容量Ｃｎに変化を与えるものであり、電気容量と合わせずれの相関関係を崩すことになり、測定精度を低下させる。この問題を解決するために評価パターン５に校正用回路を付加し、製造誤差の影響を排除しようとするものである。
【００３７】
図９は図６に示す評価パターン５に校正回路を付加したものである。図中校正回路は電極７ａ３ および電極７ｄ、これら電極間に挿入される相関絶縁膜８、出力端子１１ｄおよび電極７ｄと出力端子１１ｄを接続する下層メタル配線１０ｄから構成されている。また、電極７ａ３ は下層メタル配線１０ａで出力端子１１ａに接続されている。
【００３８】
電極７ａ３ および電極７ｄの横幅は他の評価パターンの電極の２倍の大きさに設定され、一方、電極７ａ３ および電極７ｄの電極間ｄ、電極厚みＴは他の電極間と同一である。また、相関絶縁膜８の横方向の幅は電極幅Ｌ０ で作成され、電極７ａ３ 、７ｄの中央に配設する。従って、校正用回路は合わせずれが零の場合の電気容量の２倍の容量をもつコンデンサを構成する。このコンデンサの容量は出力端子１１ａおよび１１ｄからテスターで測定する。
【００３９】
上述した第二の方法によると、校正回路の相関絶縁膜８は実際的な横方向の合わせずれが生じても電極７ａ３ 、７ｄからはみ出すことはなく電極７ａ３ 、７ｄ上に形成され、校正用回路の電気容量は常に一定である。即ち、校正用回路で得られる電気容量Ｃｎ（Ｑ＋〜Ｑ３ −）は、合わせずれに応じた電気容量の変化ΔＣｎ（合わせずれ）とは無関係である。これを合わせずれ量零のときの電気容量の指標とする。
【００４０】
この校正回路で得られる電気容量は

で表される。
【００４１】
また、電極７ａ１ 、電極７ｂおよび層間絶縁膜８で構成される横合わせずれ検出回路で得られる電気容量は、

で表され、更に、電極７ａ２ 、電極７ｃおよび層間絶縁膜８で構成される縦合わせずれ検出回路で得られる電気容量は

で表される。
【００４２】
ここで、Ｃｎは層間絶縁膜８の挿入量をＬｎとしたときの電気容量であり、Ｃ_０ は合わせずれ量零のときの電気容量であり、Ｃ_０ （ＳｉＯ_２ ）は層間絶縁膜（ＳｉＯ_２ ）が電極間に挿入されていない部位の電気容量であり、Ｃ_０ （ｎｏｎＳｉＯ_２ ）は層間絶縁膜（ＳｉＯ_２ ）が電極間に挿入されている部位の電気容量である。また、Ｃ（ＳｉＯ_２ 誤差）およびＣ（配線誤差）は層間絶縁膜８と下層メタル配線の製造誤差による電気容量の変化をそれぞれ示している。更に、ΔＣｎ（横合わせずれ）およびΔＣｎ（縦合わせずれ）はそれぞれ横、縦方向の合わせずれが発生した場合の電気容量の変化量を示している。ここで変化量とは理想状態（合わせずれが零の状態）で得られる電気容量との差分である。
【００４３】
本発明が目的とする合わせずれに対する電気容量の変化を把握するには、（５）式および（６）式から分かるように、製造誤差による電気容量の変化分Ｃ（ＳｉＯ_２ 誤差）とＣ（配線誤差）を取り除き、且つ、合わせずれが発生した場合の電気容量の変化分ΔＣｎ（横合わせずれ）およびΔＣｎ（縦合わせずれ）の情報が検知できればよい。
【００４４】
そこで、（３）式に示すように校正用回路で得られる電気容量Ｃｎ（Ｑ＋〜Ｑ３ −）は合わせずれが発生した場合の電気容量の変化分ΔＣｎ（横合わせずれ）およびΔＣｎ（縦合わせずれ）の情報を含まず、且つ、製造誤差による電気容量の変化分Ｃ（ＳｉＯ_２ 誤差）とＣ（配線誤差）の情報を含んでいることから、（５）式および（６）式を（３）式と比較することにより、測定誤差要因となる製造誤差による電気容量変化を取り除き、合わせずれによる電気容量の変化分ΔＣｎ（横合わせずれ）およびΔＣｎ（縦合わせずれ）のみを検出することが可能である。
【００４５】
この校正用回路を利用して製造誤差を取り除き、合わせずれを算出する式をつぎに示す。
ΔＣｎ（横合わせずれ）
＝Ｃｎ（Ｑ＋〜Ｑ１ −）−Ｃｎ（Ｑ＋〜Ｑ３ −）／２ （７）
ΔＣｎ（縦合わせずれ）
＝Ｃｎ（Ｑ＋〜Ｑ２ −）−Ｃｎ（Ｑ＋〜Ｑ３ −）／２ （８）
【００４６】
これらは校正回路で得られる電気容量の１／２を単純に測定結果から引き算したものであり、この計算結果には製造誤差を含まず、合わせずれがおよぼす電気容量の変化のみを表していることが分かる。即ち、前述した容量に変化を与えるいかなる部位に製造のバラツキが発生しても、校正用回路も同様に電気容量の変化を発生するため（但し、変化量は２倍）、電気容量の差を求めることによりこの電気容量の変化は相殺され、最終的な合わせずれの計算結果には製造のバラツキによる影響は排除される。従って、求められた電気容量に対応して正確な合わせずれ量を求めることができる。
【００４７】
つぎに、本発明の第二の実施形態例について説明する。上述した第一の実施形態例はメタル配線上に形成した、層間絶縁膜の加工時の重ね合わせずれを測定する方法であった。逆に第一の実施形態例では層間絶縁膜上に形成したメタル配線の加工に関しては合わせずれを測定することはできない。従って、第二の本実施形態例はこの制約を除去した方法に関するものである。
【００４８】
図１０は第二の実施形態例の正面図であって、層間絶縁膜８と、電極７ａおよび７ｂとは全く重なりを持たない構成になっている。即ち、電極７ａおよび７ｂは一方向が開いて対向しており、この開いた部位に層間絶縁膜８が合わせずれ量に対応した距離Ｘｎ、Ｙｎ、Ｚｎをもって入り込んでいる。電極７ａおよび７ｂはそれぞれ下層メタル配線１０ａおよび１０ｂにより出力端子１１ａおよび１１ｂに接続されている。図１０からも分かるように、層間絶縁膜８と電極７ａおよび７ｂは上層レイヤーと下層レイヤーの区別はなく、層間絶縁膜上にメタル配線を形成する場合においても合わせずれに応じた所定の電気容量を得ることができる。
【００４９】
つぎに、この評価パターンの作成方法について、メタル配線形成後に絶縁膜を作成する場合と、絶縁膜形成後にメタル配線を作成する場合とに分けて説明する。
【００５０】
メタル配線形成後に絶縁膜を作成する場合は図１１に示すように、まず、第一の工程で基盤となる下層の絶縁膜６上に電極、メタル配線等となる金属１３を、例えばスパッタリング法により蒸着する〔図１１（ａ）〕。つぎに、金属１３をフォトリソグラフィー工程によりパターンニングし、エッチング工程においてエッチングし、所望の形状に加工する〔図１１（ｂ）〕。つぎに、層間絶縁膜８となる、例えばＳｉＯ_２ を気相成長（ＣＶＤ）により成膜する〔図１１（ｃ）〕。最後に層間絶縁膜８をフォトリソグラフィー工程によりパターンニングし、エッチング工程においてエッチングし、所望の形状に加工して〔図１１（ｄ）〕、評価パターンを形成する。
【００５１】
絶縁膜形成後にメタル配線を作成する場合は図１２に示すように、まず、第一の工程で基盤となる下層の絶縁膜６上に層間絶縁膜８となる、例えばＳｉＯ_２ を気相成長（ＣＶＤ）により成膜する〔図１２（ａ）〕。つぎに、層間絶縁膜８をフォトリソグラフィー工程によりパターンニングし、エッチング工程においてエッチングし、所望の形状に加工する〔図１２（ｂ）〕。つぎに、下層の絶縁膜６上に電極、メタル配線等となる金属１３を、例えばスパッタリング法により蒸着する〔図１２（ｃ）〕。最後に、金属１３をフォトリソグラフィー工程によりパターンニングし、エッチング工程においてエッチングし、所望の形状に加工して〔図１２（ｄ）〕、評価パターンを形成する。
【００５２】
これら２つの場合の一連の加工は実回路を作成する過程と同時に行われ、合わせずれ評価パターンを作成するために新たな製造過程を追加する必要はない。
また、この合わせずれ検出方法を用いると、層間膜加工工程においても、その位置合わせを行うことができることになる。
【００５３】
【発明の効果】
以上説明したように本発明の評価パターンを用いた合わせずれ測定法によれば、電極間の電気容量の変化でその合わせ精度を検出するので、従来の画像処理による測定法でのメタル配線の表面状態の影響を排除し、これによる測定精度の低下を防止することができる。
【００５４】
また、校正用回路を利用した補正により、線幅および膜厚のばらつき、膜質変化等の製造における影響を全く受けること無く、安定した合わせずれ量の測定精度が得られ、測定の信頼性が飛躍的に向上する。
【００５５】
また、本発明の回路を複数段の並列回路で構成することにより、合わせずれによる電気容量の変化量を増幅して検出できるため、測定誤差要因のテスターの測定精度や外部からの電気的ノイズに対して効果的にその影響を軽減することができ、測定の信頼性が飛躍的に向上する。
【００５６】
測定の際に必要とされる主要な機器は電気容量測定用のテスターのみであるため、従来の測定方法で用いた大がかりな測定システムは必要とせず、簡単なシステム構成で測定が可能である。また、電気容量の測定に要する時間は従来の方法と比較して短時間で行うことができ、従って、測定器コストおよびランニングコストが大幅に削減できる。
【００５７】
合わせずれ量の測定回路の加工形状を最適化することにより、配線、層間膜のいずれの製造過程においても合わせずれ量の検出可能なパターンを形成することが可能であり、合わせずれ量の測定における自由度が増大する。
【００５８】
電気容量測定感度（精度）を電気的に自由に調整できるので、合わせずれ量の測定精度を容易に向上でき、今後の半導体製造における一層の微細化技術の合わせずれ評価方法に用いて効果が大きい。
【図面の簡単な説明】
【図１】ウェハー上の評価パターンの部位を示す図であって、（ａ）は半導体回路を形成するウェハーの正面図であり、（ｂ）は半導体回路の１ショット分の拡大図である。
【図２】第一の実施形態例である評価パターンの容量形成部を含む形状を示す図であって、（ａ）はその正面図であり、（ｂ）は（ａ）におけるＡ１ −Ａ１ ′線上の断面側面図である。
【図３】評価パターンを示し、（ａ）は図２に示す評価パターンの容量形成部の斜視図であり、（ｂ）は容量成分毎にコンデンサを対応させた等価回路であり、（ｃ）はこの容量を一つのコンデンサで表した等価回路である。
【図４】下層メタル配線と、層間絶縁膜の配置と、これによる電気容量を示す図であって、（ａ）は層間絶縁膜が右方向にずれた場合であり、（ｂ）は層間絶縁膜が左方向にずれた場合であり、（ｃ）は層間絶縁膜のずれと電気容量との関係を示す。
【図５】位置合わせを検出する評価パターンを示し、（ａ）は横方向のずれを検出するパターン図であり、（ｂ）は縦方向のずれを検出するパターン図である。
【図６】図５に示すパターンで構成した縦、横の両方向の評価パターンを一体化したの実施形態例である。
【図７】本発明による評価パターンの製造方法に関し、図３（ａ）に示すＡ２ −Ａ２ ′線上の断面側面に着目して説明するための図である。
【図８】本発明による評価パターンの複数段構成を示す図であって、（ａ）はその模式図であり、（ｂ）はその等価回路である。
【図９】図６に示した評価パターンに校正回路を付加した評価パターンを示す図である。
【図１０】第二の実施形態例を示す図である。
【図１１】図１０に示した評価パターンの製造方法に関し、図１０に示すＡ３ −Ａ３ ′線上の断面側面に着目して説明するための図である。
【図１２】図１０に示した評価パターンの他の製造方法に関し、図１０に示すＡ３ −Ａ３ ′線上の断面側面に着目して説明するための図である。
【図１３】従来のレジストパターンニングの際の位置合わせ精度の測定手段を示す図であって、（ａ）はその正面図であり、（ｂ）は（ａ）におけるＡ４ −Ａ４ ′の断面側面図である。
【図１４】図１３の測定手段による測定法方を説明するための図である。
【符号の説明】
１…ウェハー、２…半導体回路、３…実回路パターン部、４…スクライブライン５…評価パターン、６…絶縁膜
７ａ，７ａ１ ，７ａ２ ，７ａ３ ，７ｂ，７ｃ，７ｄ，７１ａ，７１ｂ，７２ａ，７２ｂ，７３ａ，７３ｂ，７４ａ，７４ｂ，７５ａ，７５ｂ，７６ａ，７６ｂ，７７ａ，７７ｂ，７８ａ，７８ｂ…電極
８、８１、８２、８３、８４、８５、８６、８７、８８…層間絶縁膜
９…容量形成部、１０…下層メタル配線層
１０ａ，１０ｂ，１０ｃ，１０ｄ…下層メタル配線
１１ａ，１１ｂ，１１ｃ，１１ｄ…出力端子、１２…層間絶縁膜の挿入部
１３…金属、１００…評価回路部、１０１…絶縁膜
１０２…下層メタル配線、１０３…層間絶縁膜、１０４…開口部[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device for detecting alignment accuracy for detecting an amount of misalignment at the time of resist patterning in a manufacturing process of a semiconductor device, a method for manufacturing the same, and a method for detecting alignment accuracy.
[0002]
[Prior art]
Conventionally, in the process of manufacturing semiconductor devices, detection of alignment accuracy at the time of resist patterning has been an important technology that has been indispensable for improving product yield. It is even more important.
[0003]
A conventional method of detecting alignment accuracy will be described with reference to FIGS. FIGS. 13A and 13B are views showing a conventional means for measuring the positioning accuracy at the time of resist patterning. FIG. 13A is a front view thereof, and FIG. 13B is a view showing A4- in FIG. It is sectional side view of A4 '. FIG. 14 is a view for explaining a measuring method by the measuring means shown in FIG.
[0004]
Conventionally, as shown in FIG. 13, an evaluation circuit unit 100, which is a means for measuring the alignment accuracy at the time of resist patterning, forms a lower metal wiring 102 and an SiO 2 on an insulating film 101 of a wafer.₂Is formed through a resist patterning and an etching process. These are provided with a rectangular interlayer insulating film 103 to be located at the center, and a lower metal wiring 102 surrounding the interlayer insulating film 103 through a uniform opening 104.
[0005]
The relative positional relationship between the lower metal wiring 102 and the interlayer insulating film 103 of the evaluation circuit unit 100 is checked to detect misalignment. For example, a photograph is taken from the upper surface by a CCD (Charge Coupled Device) image sensor or the like. The amount of misalignment was calculated by processing the image data obtained by the above. As can be seen from the shapes of the lower metal wiring 102 and the interlayer insulating film 103, the amount of misalignment of the center position can be measured separately for horizontal and vertical components.
[0006]
However, in the above-described measurement method, the measurement accuracy is significantly reduced when the components of the evaluation circuit unit 100 are rough. For example, in the case where the lower metal wiring 102 is formed by Al deposition by a sputtering method, fine irregularities are generated on the surface due to Al grains, and the edge of the lower metal wiring 102 becomes rough as shown in FIG. Was significantly reduced. In addition, since the limit of the measurement accuracy is determined by the optical resolution performance of the optical microscope, it is assumed that it is difficult to accurately cope with further miniaturization technology of semiconductor manufacturing in the future.
[0007]
[Problems to be solved by the invention]
Accordingly, an object of the present invention is to provide a semiconductor device for detecting alignment accuracy used for the purpose of improving the detection accuracy of an alignment shift at the time of resist patterning accompanying miniaturization of a semiconductor device, a method of manufacturing the semiconductor device, and the semiconductor device. It is an object of the present invention to provide a method of detecting alignment accuracy using an apparatus.
[0008]
[Means for Solving the Problems]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is directed to detection of alignment accuracy of resist patterning in manufacturing a semiconductor device.A semiconductor device to be used, comprising: two electrodes arranged side by side on a first insulating film so as to face each other; and formed on the first insulating film in a state inserted between the two electrodes. The second insulating film constitutes a capacitor for detecting an amount of misalignment.
[0009]
In addition, a plurality of capacitors are provided, and the capacitors of the plurality of stages are connected in parallel.
[0010]
In addition, a calibration circuit for calibrating a measurement error when measuring the capacitance of the capacitor is added.
[0011]
Further, two electrodes and the second insulating film are arranged so as not to overlap on the first insulating film.
[0014]
According to the configuration of the present invention, a small misalignment in resist patterning can be detected with high accuracy, and therefore, it becomes possible to manufacture a semiconductor device having a further fine structure with a high yield.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to FIGS.
[0016]
The evaluation pattern according to the present invention is provided on the wafer shown in FIG. FIG. 1A shows a semiconductor circuit 2 formed on a wafer 1, and FIG. 2B is an enlarged view of one shot of the semiconductor circuit 2. Here, one shot refers to a region that is patterned by one exposure by the exposure device. One shot includes an actual circuit pattern portion 3, a scribe line 4 separating the actual circuit pattern portion 3, and an evaluation pattern 5 for evaluating the amount of misalignment according to the present invention. In order to measure the amount of misalignment between the center and the periphery of the shot, the evaluation pattern 5 is arranged at the center and four corners of the shot as shown in FIG.
[0017]
Next, the configuration and operation of the first embodiment of the present invention will be described.
As shown in FIG. 2, the misalignment evaluation pattern 5 is composed of electrodes 7a and 7b opposed to each other on the insulating film 6 and an interlayer insulating film 8 provided to cover these electrodes 7a and 7b. The capacitance forming section 9 is constituted, and the electrode 7a is connected to the output terminal 11a by the lower metal wiring 10a, and the electrode 7b is connected to the output terminal 11b by the lower metal wiring 10b. The output terminal 11a and the output terminal 11b are parts to which a tester is applied when measuring the amount of misalignment.
[0018]
The electric capacitance of the capacitance forming section 9 will be described with reference to FIG.
The electric capacitance between the parallel plate electrodes is proportional to the area of the opposing electrodes and inversely proportional to the distance between the electrodes, and the dielectric constant of a substance existing between the electrodes is determined as a proportional coefficient. As shown in the capacitance forming section 9 of the present invention in FIG. 5A, the opposing surfaces of the electrodes 7a and 7b are rectangles of length T and width L, the area is S = L0 × T, and the distance between the electrodes is Is d. The interlayer insulating film 8 having a relative permittivity ε is inserted between the electrodes over a length Ln, and the remaining length (L0−Ln) is set to the permittivity ε.₀Vacuum (actually this dielectric constant ε₀Close to the air).
[0019]
Therefore, the capacitance forming section 9 has a configuration in which two capacitors are connected in parallel. FIG. 3B is an equivalent circuit showing this state, and the electric capacitance Cn (SiO 2) of the portion including the interlayer insulating film 8 is shown.₂) And the capacitance Cn (nonSiO 2) at a portion not including the interlayer insulating film 8.₂) Indicates that they are connected in parallel, and FIG. 3C shows Cn = Cn (SiO₂) + Cn (nonSiO₂) Is represented by one electric capacity Cn.
[0020]
Here, based on a predetermined insertion amount Ln = L0 / 2 of the interlayer insulating film 8, this position is a position where there is no misalignment with the resist pattern. When a misalignment occurs from this position, the insertion amount Ln of the interlayer insulating film 8 changes, and thus the capacitance Cn changes. By measuring the change, the misalignment amount at the time of patterning can be detected. become.
[0021]
Next, a change in the amount of misalignment and a change in the capacitance will be described in detail with reference to FIGS.
[0022]
FIG. 4A is a plan view of the capacitance forming section 9 when the insertion amount Ln = L1, and FIG. 4B is a plan view of the capacitance forming section 9 when the insertion amount Ln = L2. When the electrodes 7a and 7b and the interlayer insulating film 8 overlap with each other by the length Ln as described above, and the electrodes 7a and 7b and the interlayer insulating film 8 are misaligned in the horizontal direction in FIG. The length Ln of the interlayer insulating film 8 inserted between the electrodes is increased or decreased as compared with Ln = L0 / 2 in an ideal state (zero misalignment). Note that reference numeral 12 in the figure denotes an insertion portion of the interlayer insulating film 8.
[0023]
The case of Ln = L1 in FIG. 4A is a case where the interlayer insulating film 8 is shifted to the right with respect to the ideal state, and the insertion amount is larger than that in the ideal state, while Ln = L1 in FIG. 4B. In the case of L2, the interlayer insulating film 8 is shifted to the left, and the insertion amount is smaller than the ideal state, and a correlation is generated between the misalignment amount and the insertion amount of the interlayer insulating film 8 between the electrodes. .
[0024]
Next, the relationship between the insertion amount Ln and the capacitance Cn will be described. The above-mentioned Cn is described in detail.

It is expressed as here,
α = T × ε₀× (ε-1) / d
β = T × L0 × ε₀/ D
And Also,
Cn: electric capacity when the insertion amount is Ln
Cn (SiO₂): Electric capacity at the portion where the interlayer insulating film and the electrode overlap when the insertion amount is Ln
Cn (nonSiO₂): Electric capacity of a portion where the interlayer insulating film and the electrode do not overlap when the insertion amount is Ln
Ln: insertion amount of interlayer insulating film between electrodes
L0: width of the electrodes facing each other
T: height at which electrodes face each other (film thickness of wiring)
d: distance between electrodes
ε: dielectric constant of interlayer insulating film inserted between electrodes
ε₀: Dielectric constant of vacuum
It is.
[0025]
Therefore, L0, T, d, ε, ε in equation (1)₀Is a constant not related to misalignment, it is replaced as in equation (2), the electric capacity Cn becomes a linear expression of the insertion amount Ln, and the electric capacity Cn and the insertion amount Ln are in a proportional relationship. I understand. For example, the interlayer insulating film 8 is made of silicate dioxide (SiO 2).₂), The relative dielectric constant ε = 3.9, so that ε−1> 0. Since the slope of the equation (2) is positive, the capacitance Cn increases as the insertion amount Ln increases. Is obtained.
[0026]
What has been described above, as shown in FIG. 5, may of course be used for either the detection of misalignment in the horizontal direction (FIG. 5A) or the detection of misalignment in the vertical direction (FIG. 5B). In addition, by providing the insertion direction of the interlayer insulating film 8 between the electrodes so as to coincide with the detection direction of the misalignment, it is possible to form an evaluation pattern for detecting the misalignment amount in each direction.
[0027]
FIG. 6 shows an example of an evaluation pattern 5 in which the above-described vertical and horizontal misalignment detection sections are integrally formed, and includes a vertical detection pattern formed of electrodes 7a1, 7b, and an interlayer insulating film 8. There is a lateral detection pattern composed of an electrode 7a2, an electrode 7c, and an interlayer insulating film 8. The electrodes 7a1 and 7a2 are commonly connected to an output terminal 11a by a lower metal wiring 10a, and the electrode 7b is a lower metal wiring. The electrode 7c is connected to the output terminal 11b by a lower layer 10b, and the electrode 7c is connected to the output terminal 11c by a lower metal wiring 10c.
[0028]
Next, a method of manufacturing the evaluation pattern 5 will be described with reference to FIG. FIG. 7 shows A in FIG.₁-A₁FIG.
[0029]
First, in the first step, as shown in FIG. 7A, a lower insulating film 6 serving as a₂Is formed by vapor phase growth (CVD). No etching is performed on this portion. In the second step, as shown in FIG. 7B, a metal to be the lower metal wiring layer 10 is formed by evaporating, for example, by a sputtering method. In the third step, as shown in FIG. 7C, the lower metal wiring layer 10 is patterned by a photolithography step, etched in an etching step, processed into a desired wiring shape, and the electrodes 7a and 7b are formed. I do. In the fourth step, as shown in FIG.₂Is formed by vapor phase epitaxy (CVD). Finally, as shown in FIG. 7E, the interlayer insulating film 8 is patterned by a photolithography process, and is etched in an etching process to form a desired shape.
[0030]
The production of the evaluation pattern 5 described above is performed at the same time as the process of creating the actual circuit, and does not require a separate step for it.
[0031]
Next, a method of improving the misalignment detection accuracy will be described. The first is a method of providing a plurality of evaluation patterns, and the second is a method of providing a calibration circuit.
[0032]
First, the first method will be described with reference to FIG.
Conventionally, in measuring a semiconductor element, since an extremely weak amount of electricity is handled, an error is often caused by the influence of external electrical noise. In order to accurately detect even a minute change in the capacitance, a plurality of evaluation patterns 5 are provided to amplify and detect the change in the capacitance.
[0033]
FIG. 8A shows an example of an eight-stage configuration in which the electrodes 71a to 78a are respectively connected to the lower metal wiring 10a, further led to the output terminal 11a, and the electrodes 71b to 78b are also connected to the lower metal wiring 10b. Connected to the output terminal 11b. Further, interlayer insulating films 81 to 88 are provided over the electrodes 71a to 78a and the electrodes 71b to 78b, and each constitutes a capacitance forming portion. FIG. 8B is an equivalent circuit of the above-described evaluation pattern.₁~ C₈Indicated by
[0034]
If misalignment occurs during patterning in the lithography process, the overlap between the electrode and the interlayer insulating film will deviate from the ideal state by the same amount in the same direction at the same time. (8 times in FIG. 8). Although FIG. 8 shows an eight-stage configuration, it is a matter of course that any number of stages may be provided without being limited to this.
[0035]
When the number of stages is w, the capacitance Cn measured from the output terminals 11a and 11b is
Cn = C₀× w + ΔCn × w (3)
Is represented by Where C₀Is the electric capacity of each capacitor when there is no misalignment, and ΔCn is the amount of change in the electric capacity of each capacitor caused by misalignment. Therefore, it can be seen from equation (3) that the amount of change is amplified by the number of stages (w) times ΔCn. This has the effect of reducing the effect of external noise during measurement. In addition, there is an effect of averaging by simultaneously measuring a plurality of capacitors, thereby reducing the influence of manufacturing variations of the evaluation pattern.
[0036]
A second method for improving the misalignment detection accuracy uses a calibration circuit, which will be described with reference to FIG. As a conventional problem, there are various manufacturing variations of a semiconductor device as a cause of a decrease in measurement accuracy. For example, the width L0, the thickness T of the electrodes 7a and 7b in FIG. 3A, the film thickness T, the distance d between the electrodes, the insertion amount Ln of the correlation insulating film 8, the change in the film quality of the correlation insulating film 8 (particularly, the change in the relative dielectric constant ε). These changes change the electric capacity Cn expressed by the equation (1) or (2), which breaks the correlation between the electric capacity and the misalignment, and lowers the measurement accuracy. . To solve this problem, a calibration circuit is added to the evaluation pattern 5 so as to eliminate the influence of manufacturing errors.
[0037]
FIG. 9 is a diagram obtained by adding a calibration circuit to the evaluation pattern 5 shown in FIG. In the figure, the calibration circuit includes an electrode 7a3 and an electrode 7d, a correlation insulating film 8 inserted between these electrodes, an output terminal 11d, and a lower metal wiring 10d connecting the electrode 7d and the output terminal 11d. The electrode 7a3 is connected to the output terminal 11a by a lower metal wiring 10a.
[0038]
The lateral width of the electrode 7a3 and the electrode 7d is set to be twice as large as the electrodes of the other evaluation patterns, while the distance d between the electrodes 7a3 and the electrode 7d and the electrode thickness T are the same as those between the other electrodes. The width of the correlation insulating film 8 in the lateral direction is determined by the electrode width L0, and is disposed at the center of the electrodes 7a3 and 7d. Therefore, the calibration circuit forms a capacitor having a capacitance twice as large as the capacitance when the misalignment is zero. The capacitance of this capacitor is measured by a tester from the output terminals 11a and 11d.
[0039]
According to the second method described above, the correlation insulating film 8 of the calibration circuit is formed on the electrodes 7a3 and 7d without protruding from the electrodes 7a3 and 7d even if a practical misalignment occurs in the lateral direction. Is always constant. That is, the capacitance Cn (Q + to Q3−) obtained by the calibration circuit is irrelevant to the change ΔCn (misalignment) in the electric capacitance according to the misalignment. This is used as an index of the electric capacity when the misalignment amount is zero.
[0040]
The capacitance obtained by this calibration circuit is

Is represented by
[0041]
Further, the electric capacitance obtained by the horizontal misalignment detecting circuit composed of the electrodes 7a1, 7b and the interlayer insulating film 8 is as follows:

Further, the capacitance obtained by the vertical misalignment detecting circuit composed of the electrodes 7a2, 7c and the interlayer insulating film 8 is

Is represented by
[0042]
Here, Cn is the electric capacity when the insertion amount of the interlayer insulating film 8 is Ln.₀Is the electric capacity when the misalignment is zero, and C₀(SiO₂) Is an interlayer insulating film (SiO₂) Is the capacitance of the part not inserted between the electrodes,₀(NonSiO₂) Is an interlayer insulating film (SiO₂) Is the capacitance of the part inserted between the electrodes. In addition, C (SiO₂Error) and C (wiring error) indicate changes in electrical capacitance due to manufacturing errors in the interlayer insulating film 8 and the lower metal wiring, respectively. Further, ΔCn (horizontal misalignment) and ΔCn (longitudinal misalignment) indicate the amount of change in electric capacity when misalignment occurs in the horizontal and vertical directions, respectively. Here, the change amount is a difference from an electric capacity obtained in an ideal state (a state in which misalignment is zero).
[0043]
In order to grasp the change of the electric capacity due to the misalignment intended by the present invention, as can be seen from the equations (5) and (6), the change C (SiO₂Error) and C (wiring error), and the information of the change ΔCn (horizontal alignment deviation) and ΔCn (vertical alignment deviation) of the electric capacitance when the misalignment occurs can be detected.
[0044]
Therefore, as shown in the equation (3), the capacitances Cn (Q + to Q3−) obtained by the calibration circuit are changed ΔCn (horizontal misalignment) and ΔCn (vertical misalignment) when the misalignment occurs. ), And the change in capacitance C (SiO₂Error) and C (wiring error) information, the equations (5) and (6) are compared with the equation (3) to remove the change in capacitance due to a manufacturing error that is a measurement error factor. It is possible to detect only the change amount ΔCn (horizontal alignment deviation) and ΔCn (vertical alignment deviation) of the electric capacitance due to the misalignment.
[0045]
An equation for calculating the misalignment by removing the manufacturing error by using the calibration circuit is shown below.
ΔCn (Horizontal misalignment)
= Cn (Q + ~ Q1-)-Cn (Q + ~ Q3-) / 2 (7)
ΔCn (vertical misalignment)
= Cn (Q + ~ Q2-)-Cn (Q + ~ Q3-) / 2 (8)
[0046]
These are simply the half of the capacitance obtained by the calibration circuit subtracted from the measurement result, and this calculation result does not include manufacturing errors, and indicates only the change in capacitance caused by misalignment. I understand. That is, even if the manufacturing variation occurs in any of the above-mentioned portions that change the capacitance, the calibration circuit also generates a change in the capacitance (however, the amount of change is twice as large). This change cancels out the change in electric capacity, and eliminates the influence of manufacturing variations on the final misalignment calculation result. Therefore, an accurate misalignment amount can be obtained corresponding to the obtained electric capacity.
[0047]
Next, a second embodiment of the present invention will be described. The first embodiment described above is a method of measuring an overlay shift during processing of an interlayer insulating film formed on a metal wiring. Conversely, in the first embodiment, the misalignment cannot be measured for the processing of the metal wiring formed on the interlayer insulating film. Therefore, the second embodiment relates to a method that eliminates this restriction.
[0048]
FIG. 10 is a front view of the second embodiment, in which the interlayer insulating film 8 and the electrodes 7a and 7b do not have any overlap. That is, the electrodes 7a and 7b are opposed to each other in one direction, and the interlayer insulating film 8 enters the opened portion with the distances Xn, Yn, and Zn corresponding to the amount of misalignment. Electrodes 7a and 7b are connected to output terminals 11a and 11b by lower metal wires 10a and 10b, respectively. As can be seen from FIG. 10, the interlayer insulating film 8 and the electrodes 7a and 7b are not distinguished between the upper layer and the lower layer. Even when a metal wiring is formed on the interlayer insulating film, a predetermined capacitance corresponding to the misalignment is obtained. Can be obtained.
[0049]
Next, a method of creating the evaluation pattern will be described separately for a case where an insulating film is formed after forming a metal wiring and a case where a metal wiring is formed after forming an insulating film.
[0050]
When an insulating film is formed after forming a metal wiring, as shown in FIG. 11, first, a metal 13 serving as an electrode, a metal wiring, or the like is formed on a lower insulating film 6 serving as a base in a first step by, for example, a sputtering method. Vapor deposition is performed (FIG. 11A). Next, the metal 13 is patterned by a photolithography process, etched in an etching process, and processed into a desired shape (FIG. 11B). Next, for example, SiO₂Is formed by vapor phase growth (CVD) [FIG. 11 (c)]. Finally, the interlayer insulating film 8 is patterned by a photolithography process, etched in an etching process, processed into a desired shape (FIG. 11D), and an evaluation pattern is formed.
[0051]
In the case of forming a metal wiring after forming an insulating film, as shown in FIG. 12, first, an interlayer insulating film 8 is formed on a lower insulating film 6 serving as a base in a first step, for example, SiO 2.₂Is formed by vapor phase growth (CVD) [FIG. 12 (a)]. Next, the interlayer insulating film 8 is patterned by a photolithography process, etched in an etching process, and processed into a desired shape (FIG. 12B). Next, a metal 13 to be an electrode, a metal wiring, or the like is deposited on the lower insulating film 6 by, for example, a sputtering method (FIG. 12C). Finally, the metal 13 is patterned by a photolithography process, etched in an etching process, processed into a desired shape (FIG. 12D), and an evaluation pattern is formed.
[0052]
A series of processing in these two cases is performed simultaneously with the process of creating the actual circuit, and it is not necessary to add a new manufacturing process to create the misalignment evaluation pattern.
Also, by using this misalignment detection method, the alignment can be performed even in the interlayer film processing step.
[0053]
【The invention's effect】
As described above, according to the misalignment measurement method using the evaluation pattern of the present invention, the accuracy of the alignment is detected by the change in the capacitance between the electrodes, and therefore the surface of the metal wiring is measured by the conventional image processing measurement method. It is possible to eliminate the influence of the state and prevent the measurement accuracy from being lowered.
[0054]
In addition, the correction using the calibration circuit provides stable measurement accuracy of the amount of misalignment without any influence on manufacturing such as variations in line width and film thickness, changes in film quality, etc., and dramatically increases measurement reliability. To improve.
[0055]
In addition, by configuring the circuit of the present invention with a plurality of parallel circuits, the amount of change in capacitance due to misalignment can be amplified and detected. On the other hand, the influence can be effectively reduced, and the reliability of the measurement is dramatically improved.
[0056]
The main equipment required for the measurement is only a tester for measuring electric capacitance, so that a large-scale measurement system used in the conventional measurement method is not required, and the measurement can be performed with a simple system configuration. In addition, the time required for measuring the electric capacity can be shortened in comparison with the conventional method, and therefore, the cost of the measuring instrument and the running cost can be significantly reduced.
[0057]
By optimizing the processing shape of the circuit for measuring the amount of misalignment, it is possible to form a pattern capable of detecting the amount of misalignment in any of the manufacturing processes of the wiring and the interlayer film. The degree of freedom increases.
[0058]
Since the capacitance measurement sensitivity (accuracy) can be electrically adjusted freely, the accuracy of measurement of the amount of misalignment can be easily improved, and the effect is large when used in the misalignment evaluation method of further miniaturization technology in future semiconductor manufacturing. .
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams showing portions of an evaluation pattern on a wafer, wherein FIG. 1A is a front view of a wafer forming a semiconductor circuit, and FIG. 1B is an enlarged view of one shot of the semiconductor circuit.
FIGS. 2A and 2B are views showing a shape including a capacity forming portion of an evaluation pattern according to the first embodiment, wherein FIG. 2A is a front view thereof, and FIG. 2B is A1-A1 ′ in FIG. It is sectional side view on a line.
3A and 3B show evaluation patterns, FIG. 3A is a perspective view of a capacitance forming portion of the evaluation pattern shown in FIG. 2, FIG. 3B is an equivalent circuit in which a capacitor is associated with each capacitance component, and FIG. Is an equivalent circuit in which this capacitance is represented by one capacitor.
4A and 4B are diagrams showing a lower metal wiring, an arrangement of an interlayer insulating film, and an electric capacitance due to the arrangement, wherein FIG. 4A shows a case where the interlayer insulating film is shifted to the right, and FIG. This is the case where the film is shifted leftward, and (c) shows the relationship between the shift of the interlayer insulating film and the electric capacity.
5A and 5B show an evaluation pattern for detecting alignment, FIG. 5A is a pattern diagram for detecting a horizontal shift, and FIG. 5B is a pattern diagram for detecting a vertical shift.
6 is an example of an embodiment in which evaluation patterns in both the vertical and horizontal directions formed by the pattern shown in FIG. 5 are integrated.
FIG. 7 is a view for explaining a method of manufacturing an evaluation pattern according to the present invention, focusing on a cross-sectional side surface taken along line A2-A2 ′ shown in FIG.
8A and 8B are diagrams showing a multi-stage configuration of an evaluation pattern according to the present invention, wherein FIG. 8A is a schematic diagram thereof, and FIG. 8B is an equivalent circuit thereof.
9 is a diagram showing an evaluation pattern obtained by adding a calibration circuit to the evaluation pattern shown in FIG.
FIG. 10 is a diagram showing a second embodiment.
11 is a view for explaining the method of manufacturing the evaluation pattern shown in FIG. 10 by focusing on the cross-sectional side surface taken along the line A3-A3 ′ shown in FIG. 10;
12 is a diagram for describing another method of manufacturing the evaluation pattern shown in FIG. 10 by focusing on a cross-sectional side surface taken along line A3-A3 ′ shown in FIG. 10;
FIGS. 13A and 13B are views showing a conventional means for measuring alignment accuracy in resist patterning, wherein FIG. 13A is a front view thereof, and FIG. 13B is a sectional side view of A4-A4 ′ in FIG. FIG.
FIG. 14 is a view for explaining a measuring method by the measuring means of FIG. 13;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... Semiconductor circuit, 3 ... Actual circuit pattern part, 4 ... Scribe line 5 ... Evaluation pattern, 6 ... Insulating film
7a, 7a1, 7a2, 7a3, 7b, 7c, 7d, 71a, 71b, 72a, 72b, 73a, 73b, 74a, 74b, 75a, 75b, 76a, 76b, 77a, 77b, 78a, 78b ... electrodes
8, 81, 82, 83, 84, 85, 86, 87, 88 ... interlayer insulating film
9 ... Capacitance forming section, 10 ... Lower metal wiring layer
10a, 10b, 10c, 10d: Lower metal wiring
11a, 11b, 11c, 11d: output terminals, 12: insertion portion of interlayer insulating film
13: metal, 100: evaluation circuit section, 101: insulating film
102: lower metal wiring 103: interlayer insulating film 104: opening

Claims (6)

A semiconductor device used for detecting the alignment accuracy of resist patterning in the manufacture of a semiconductor device,
Two electrodes arranged side by side on the first insulating film so as to face each other, and a second insulating film formed on the first insulating film while being inserted between the two electrodes, A semiconductor device for detecting alignment accuracy , comprising a capacitor for detecting an amount of misalignment . Forming a first insulating film;
Forming two electrodes on the first insulating film in a state of facing each other and forming a second insulating film in a state of being inserted between the two electrodes;
A method for manufacturing a semiconductor device for alignment accuracy detection, comprising: The positioning accuracy of resist patterning in the manufacture of a semiconductor device is detected by measuring the capacitance of a capacitor included in the semiconductor device for detecting positioning accuracy according to claim 1.
A positioning accuracy detection method characterized by the following. A plurality of the capacitors are provided, and the capacitors of the plurality of stages are connected in parallel.
2. The semiconductor device for detecting alignment accuracy according to claim 1, wherein: A calibration circuit for calibrating a measurement error when measuring the capacitance of the capacitor is added.
2. The semiconductor device for detecting alignment accuracy according to claim 1, wherein: The two electrodes and the second insulating film are arranged on the first insulating film so as not to overlap with each other.
2. The semiconductor device for detecting alignment accuracy according to claim 1, wherein:

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