JP3362639B2 - Electrical evaluation system for insulating film of semiconductor device - Google Patents
Electrical evaluation system for insulating film of semiconductor deviceInfo
- Publication number
- JP3362639B2 JP3362639B2 JP19981397A JP19981397A JP3362639B2 JP 3362639 B2 JP3362639 B2 JP 3362639B2 JP 19981397 A JP19981397 A JP 19981397A JP 19981397 A JP19981397 A JP 19981397A JP 3362639 B2 JP3362639 B2 JP 3362639B2
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- Prior art keywords
- input voltage
- insulating film
- capacitor
- electrical evaluation
- relative
- Prior art date
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【０００１】[0001]
【発明の技術分野】本発明は、半導体基板上に形成され
た絶縁膜の特性の電気的評価を行うための電気的評価装
置に関する。TECHNICAL FIELD The present invention relates to an electrical evaluation apparatus for electrically evaluating the characteristics of an insulating film formed on a semiconductor substrate.
【０００２】[0002]
【従来の技術】シリコン基板は、近年、大面積化の傾向
があり、例えば、８インチのものから１２インチのもの
に移行されつつある。基板の面積が大きくなればなる
程、基板表面に形成された絶縁膜の均一性が求められる
が、それと同時に、その均一性を高精度で評価するため
の方法の提供が求められている。絶縁膜の均一性は、通
常、相対容量値、相対誘電率、相対膜厚、及び界面準位
の差、等の評価ファクタに基づいて評価される。これら
評価ファクタの内、相対容量値は、基板上の絶縁膜に電
極を形成してＭＯＳキャパシタを形成し、ＣＶ（容量-
電圧）測定器を用いて基板上の複数の測定点の絶縁膜の
容量値Ｃを求め、そして、測定点の１つを基準点とし
て、その基準容量値と他の測定点の容量値との比を演算
することにより、相対容量値を得ている。2. Description of the Related Art In recent years, a silicon substrate tends to have a large area, and for example, it has been shifting from an 8-inch substrate to a 12-inch substrate. As the area of the substrate increases, the uniformity of the insulating film formed on the surface of the substrate is required. At the same time, it is required to provide a method for evaluating the uniformity with high accuracy. The uniformity of the insulating film is usually evaluated based on evaluation factors such as a relative capacitance value, a relative dielectric constant, a relative film thickness, and a difference in interface state. Among these evaluation factors, the relative capacitance value is the CV (capacitance-
The capacitance value C of the insulating film at a plurality of measurement points on the substrate is obtained using a voltage measuring device, and one of the measurement points is used as a reference point, and the reference capacitance value and the capacitance values of other measurement points are The relative capacity value is obtained by calculating the ratio.
【０００３】また、比誘電率ε及び膜厚Ｔは、以下の式
に基づいて計算される。Further, the relative permittivity ε and the film thickness T are calculated based on the following equations.
【数１】Ｃ＝ε0・ε・Ｓ／Ｔ
ただし、ε0は、真空中の誘電率
Ｓは、ＭＯＳキャパシタの電極面積
この場合、比誘電率εを得る場合には、光干渉式膜厚計
やエリプソメータ等の測定手段によって、膜厚を電極形
成前に測定しておく必要がある。[Number 1] C = ε 0 · ε · S / T , however, epsilon 0 is the dielectric constant S in vacuum, electrode area in this case the MOS capacitor, the case of obtaining the dielectric constant epsilon is an optical interference type film It is necessary to measure the film thickness with a measuring means such as a thickness meter or an ellipsometer before forming the electrodes.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来例
においては、上記したように、ウエハ上の複数の測定点
の容量値をＣＶ測定器により測定することにより得られ
た結果を用いて相対容量値を求めているので、その測定
精度は、ＣＶ測定器の精度に依存してしまい、したがっ
て、ウエハ上の微小容量値の測定は困難である。以上の
点に鑑み、本発明の目的は、ウエハ上の相対容量値を測
定して該ウエハ上の容量分布を評価する場合に、容量測
定器の測定精度に制限されずに、高精度の相対容量値を
得ることができるようにすることである。また、本発明
の他の目的は、相対誘電率、相対膜厚、及び界面凖位の
差の少なくとも１つを、簡単な構成により高精度で測定
できるようにすることである。However, in the conventional example, as described above, the relative capacitance value is obtained by using the results obtained by measuring the capacitance values at a plurality of measurement points on the wafer by the CV measuring device. Therefore, the measurement accuracy depends on the accuracy of the CV measuring device, and thus it is difficult to measure the minute capacitance value on the wafer. In view of the above points, it is an object of the present invention to measure a relative capacitance value on a wafer and evaluate the capacitance distribution on the wafer without being limited to the measurement precision of a capacitance measuring instrument, and to obtain a high-precision relative capacitance. It is to be able to obtain the capacitance value. Another object of the present invention is to make it possible to measure at least one of the relative dielectric constant, the relative film thickness, and the difference in interface height with high accuracy by a simple configuration.
【０００５】上記した目的を達成するために、本発明
は、半導体装置の基板上の絶縁膜の特性を電気的に評価
する装置であって、入力電圧供給手段と、入力端子が、
絶縁膜の第１の測定点における第１の部分によって形成
される第１のキャパシタを介して、入力電圧供給手段に
接続され、出力端子が、絶縁膜の第２の測定点における
第２の部分によって形成される第２のキャパシタを介し
て、入力端子と接続される演算増幅器と、入力電圧供給
手段からの入力電圧と演算増幅器の出力電圧とに基づい
て、絶縁膜の第１及び第２の部分における絶縁膜の相対
的特性を演算する演算手段とからなることを特徴とする
電気的評価装置を提供する。In order to achieve the above-mentioned object, the present invention is an apparatus for electrically evaluating the characteristics of an insulating film on a substrate of a semiconductor device, wherein an input voltage supply means and an input terminal are
The second portion of the insulating film at the second measuring point is connected to the input voltage supply means via the first capacitor formed by the first portion of the insulating film at the first measuring point. The operational amplifier connected to the input terminal via the second capacitor formed by the second capacitor, and the first and second insulating films based on the input voltage from the input voltage supply means and the output voltage of the operational amplifier. There is provided an electrical evaluation device comprising a calculation means for calculating relative characteristics of an insulating film in a portion.
【０００６】そして、上記した本発明に係る電気的評価
装置において、演算手段は、第１のキャパシタと第２の
キャパシタとの比である相対容量値を、演算増幅器の出
力手段と入力電圧供給手段からの入力電圧との比として
演算する手段と、絶縁膜の第１の部分と第２の部分との
相対誘電率を、第１の部分の膜厚と第２の部分の膜厚と
の比である相対膜厚が既知である場合に、該相対膜厚
と、演算増幅器の出力電圧と入力電圧供給手段からの入
力電圧との比とを乗算することによって演算する手段
と、絶縁膜の第１の部分の膜厚と第２の部分の膜厚との
比である相対膜厚を、第１の部分と第２の部分との相対
誘電率が既知である場合に、該相対誘電率と、入力電圧
供給手段からの入力電圧と演算増幅器の出力電圧との比
とを乗算することによって演算する手段と、絶縁膜の第
１の部分と第２の部分との界面准位の差を、絶縁膜の第
１の部分の第１のキャパシタが既知である場合に、該第
１のキャパシタと、入力電圧供給手段からの入力電圧と
演算増幅器の出力電圧との比と、該入力電圧と出力電圧
との和と、電気素量の逆数とを乗算することによって演
算する手段と、絶縁膜の第１の部分と第２の部分との界
面准位の差を、絶縁膜の第２の部分の第２のキャパシタ
が既知である場合に、該第２のキャパシタと、入力電圧
供給手段からの入力電圧と演算増幅器の出力電圧との和
と、電気素量の逆数とを乗算することによって演算する
手段とのいずれか又は任意の組合せを備えていることが
好ましい。In the above-described electrical evaluation apparatus according to the present invention, the arithmetic means outputs the relative capacitance value, which is the ratio of the first capacitor and the second capacitor, to the output means of the operational amplifier and the input voltage supply means. Means for calculating the relative dielectric constant between the first portion and the second portion of the insulating film as a ratio between the thickness of the first portion and the thickness of the second portion. When the relative film thickness is known, the relative film thickness is calculated by multiplying the relative film thickness by the ratio of the output voltage of the operational amplifier and the input voltage from the input voltage supply means. The relative film thickness, which is the ratio of the film thickness of the first portion to the film thickness of the second portion, is defined as the relative dielectric constant when the relative permittivity of the first portion and the second portion is known. , By multiplying the ratio of the input voltage from the input voltage supply means to the output voltage of the operational amplifier. And the difference in interface level between the first portion and the second portion of the insulating film is calculated when the first capacitor of the first portion of the insulating film is known. A capacitor, means for calculating by multiplying the ratio of the input voltage from the input voltage supply means to the output voltage of the operational amplifier, the sum of the input voltage and the output voltage, and the reciprocal of the elementary charge; If the difference in interface level between the first portion and the second portion of the film is known for the second capacitor of the second portion of the insulating film, the second capacitor and the input voltage supply means It is preferable to include any or any combination of means for performing calculation by multiplying the sum of the input voltage from the output voltage and the output voltage of the operational amplifier by the reciprocal of the elementary quantity.
【０００７】[0007]
【発明の実施の態様】図１には、本発明の電気的評価装
置に用いられるアナログ反転器の等価回路が示されてお
り、該アナログ反転器は、非反転入力端子（＋）がアー
ス電位に接続された演算増幅器ＯＰと、演算増幅器ＯＰ
の反転入力端子（−）と入力端子ＩＮとの間に接続され
た入力キャパシタＣ1と、演算増幅器ＯＰの出力端子Ｏ
ＵＴと反転入力端子との間に接続された帰還キャパシタ
Ｃ2とから構成されている。入力端子ＩＮに供給される
電圧をＶin、出力端子ＯＵＴにおける電圧をＶout、演
算増幅器ＯＰの反転入力端子の電圧をＶ0とし、入力キ
ャパシタ及び帰還キャパシタの容量値をＣ1、Ｃ2で表す
と、電荷量保存の法則から、以下の式（１）が成立し、
また式（１）から式（２）が得られる。1 shows an equivalent circuit of an analog inverter used in the electrical evaluation apparatus of the present invention, in which the non-inverting input terminal (+) is at ground potential. Operational amplifier OP connected to the operational amplifier OP
Of the operational amplifier OP and the input capacitor C1 connected between the inverting input terminal (-) and the input terminal IN of the operational amplifier OP.
It is composed of a feedback capacitor C2 connected between the UT and the inverting input terminal. When the voltage supplied to the input terminal IN is Vin, the voltage at the output terminal OUT is Vout, the voltage at the inverting input terminal of the operational amplifier OP is V0, and the capacitance values of the input capacitor and the feedback capacitor are C1 and C2, the charge amount is From the law of conservation, the following formula (1) is established,
Further, the formula (2) is obtained from the formula (1).
【数２】
Ｃ1（Ｖ0−Ｖin）＝Ｃ2（Ｖout−Ｖ0） （１）
∴Ｖout−Ｖ0＝−Ｃ1／Ｃ2（Ｖin−Ｖ0）
∴Ｖout／Ｖin＝−Ｃ1／Ｃ2 （２）
（∵ Ｖ0＝０ 演算増幅器ＯＰの反転入力端子が非反
転入力端子とイマジナルショート状態であるため）[Expression 2] C1 (V0-Vin) = C2 (Vout-V0) (1) ∴Vout-V0 = -C1 / C2 (Vin-V0) ∴Vout / Vin = -C1 / C2 (2) (∵V0 = 0 The inverting input terminal of the operational amplifier OP is in an imaginary short state with the non-inverting input terminal)
【０００８】式（２）から明らかなように、入力電圧Ｖ
inと出力電圧Ｖoutとの比Ｖout／Ｖinは、キャパシタの
容量比−Ｃ1／Ｃ2で表され、キャパシタＣ1及びＣ2に差
がある場合は、
Ｖout／Ｖin≠ −１
となり、これにより、キャパシタの差が微小であって
も、Ｖout／Ｖinの値からキャパシタに差があることが
分かる。以上の点から、ウエハ上に演算増幅器ＯＰを多
数形成して、該演算増幅器にウエハ上のキャパシタを図
１に示すような関係で接続し、既知の電圧Ｖinを入力端
子ＩＮに供給して出力端子ＯＵＴの電圧Ｖoutを測定す
れば、キャパシタの相対容量値が入出力電圧の比として
求めることができる。本発明は、このようにしてウエハ
上の測定点Ｐ1及びＰ2における容量値Ｃ1及びＣ2の比、
すなわち相対容量値を求めることをその基本原理として
いる。なお、入力電圧Ｖinは、入力電圧供給手段（不図
示）から供給され、相対容量値を表す−Ｖout／Ｖin
は、コンピュータ等の所望の演算手段（不図示）によっ
て演算される。測定点Ｐ1及びＰ2の何れか一方を基準点
として、他方を基板上で適宜選択できるようにしてもよ
い。As is clear from the equation (2), the input voltage V
The ratio Vout / Vin between in and the output voltage Vout is represented by the capacitance ratio of the capacitors −C1 / C2, and when there is a difference between the capacitors C1 and C2, Vout / Vin ≠ −1, which results in the difference between the capacitors. It can be seen from the value of Vout / Vin that there is a difference in the capacitors even if is small. From the above points, a large number of operational amplifiers OP are formed on the wafer, capacitors on the wafer are connected to the operational amplifiers in a relationship as shown in FIG. 1, and a known voltage Vin is supplied to the input terminal IN and output. By measuring the voltage Vout at the terminal OUT, the relative capacitance value of the capacitor can be obtained as the ratio of the input / output voltage. According to the present invention, the ratio of the capacitance values C1 and C2 at the measurement points P1 and P2 on the wafer is
That is, the basic principle is to obtain the relative capacitance value. The input voltage Vin is supplied from an input voltage supply means (not shown) and represents a relative capacitance value of −Vout / Vin.
Is calculated by a desired calculation means (not shown) such as a computer. One of the measurement points P1 and P2 may be used as a reference point, and the other may be appropriately selected on the substrate.
【０００９】また、式（２）を変形すると、式（３）が
得られる。Further, by modifying the equation (2), the equation (3) is obtained.
【数３】
Ｖout＝−Ｖin・Ｃ1／Ｃ2
＝−Ｖin・（ε1／Ｔ1）／（ε2／Ｔ2） （３）
ただし、ε1は、測定点Ｐ1の誘電率又は比誘電率
Ｔ1は、測定点Ｐ1の膜厚
ε2は、測定点Ｐ2の誘電率又は比誘電率
Ｔ2は、測定点Ｐ2の膜厚
したがって、膜厚Ｔ1、Ｔ2を測定しておけば、式（３）
から相対誘電率ε1／ε2を演算することができ、逆に、
誘電率又は比誘電率ε1、ε2を測定しておけば、式
（３）から相対膜厚Ｔ1／Ｔ2を演算することができる。
いずれにしても、一方のみを測定すれば、他方を演算に
より求めることができる。## EQU3 ## Vout = -Vin.multidot.C1 / C2 = -Vin.multidot. (. Epsilon.1 / T1) / (. Epsilon.2 / T2) (3) where .epsilon.1 is the dielectric constant of the measurement point P1 or the relative dielectric constant T1 is the measurement point. The film thickness ε2 of P1 is the dielectric constant or the relative dielectric constant T2 of the measurement point P2, and the film thickness T1 and T2 of the measurement point P2 are calculated by the equation (3).
The relative permittivity ε1 / ε2 can be calculated from
If the permittivity or the relative permittivity ε1, ε2 is measured, the relative film thickness T1 / T2 can be calculated from the equation (3).
In any case, if only one is measured, the other can be calculated.
【００１０】次に、界面凖位分布を求める場合につい
て、図２を参照して説明する。図２は、図１のキャパシ
タＣ1及びＣ2が異なる特性を有している場合の、それぞ
れのキャパシタ（ＭＯＳキャパシタ）のＣＶ（容量-電
圧）曲線を表している。このようにキャパシタＣ1、Ｃ2
のＣＶ曲線がずれている場合、このずれが界面凖位の差
△Ｄitに相当するものである。ただし、酸化膜中の固定
電荷密度が等しいと仮定する。２つのキャパシタの容量
値Ｃ1及びＣ2の比をβとおくと（Ｃ1／Ｃ2＝β）とおく
と、２つのキャパシタの容量の差△Ｃは式（４）で表さ
れ、そして、該差△Ｃに相当する界面凖位の差△Ｄitは
式（５）で表される。Next, the case of obtaining the interface gradient distribution will be described with reference to FIG. FIG. 2 shows CV (capacitance-voltage) curves of respective capacitors (MOS capacitors) when the capacitors C1 and C2 of FIG. 1 have different characteristics. In this way, capacitors C1 and C2
When the CV curve of No. 1 is deviated, this deviation corresponds to the difference ΔDit in the interface level. However, it is assumed that the fixed charge densities in the oxide film are equal. If the ratio of the capacitance values C1 and C2 of the two capacitors is β (C1 / C2 = β), the difference ΔC of the capacitances of the two capacitors is expressed by equation (4), and the difference ΔC The interface difference ΔDit corresponding to C is expressed by equation (5).
【数４】 △Ｃ＝Ｃ1−Ｃ2＝Ｃ2（β−１） （４） △Ｄit＝△Ｑit／ｑ＝△Ｃ・Ｖin／ｑ ＝Ｃ2（β−１）・Ｖin／ｑ （５） ただし、△Ｑitは、界面準位に捕獲された総電荷量 ｑは、電気素量[Equation 4] ΔC = C1-C2 = C2 (β-1) (4) △ Dit = △ Qit / q = △ C ・ Vin / q = C2 (β-1) · Vin / q (5) However, ΔQit is the total amount of charge trapped in the interface state. q is the elementary charge
【００１１】また、式（２）から、From equation (2),
【数５】Ｖout＝−Ｖin・Ｃ1／Ｃ2＝−βＶin ∴β＝−Ｖout／Ｖin であるから、これを式（５）に代入すると、[Equation 5] Vout = −Vin · C1 / C2 = −βVin ∴β = -Vout / Vin Therefore, when substituting this into equation (5),
【数６】 △Ｄit＝Ｃ2（β−１）・Ｖin／ｑ ＝−Ｃ2（Ｖout＋Ｖin）／ｑ （６） が得られる。[Equation 6] △ Dit = C2 (β-1) ・ Vin / q = -C2 (Vout + Vin) / q (6) Is obtained.
【００１２】したがって、一方のキャパシタＣ2を基準
キャパシタとしてその容量値を求めておけば、２つのキ
ャパシタＣ1、Ｃ2の界面凖位の差△Ｄitを、式（６）か
ら演算することができる。これにより、ウエハ上の絶縁
膜の界面凖位の分布を得ることができる。なお、界面凖
位の絶対値Ｄitを求める場合には、基準キャパシタの界
面凖位の値を何らかの方法で求め、その値と△Ｄitとか
ら絶対値Ｄitを得ることができる。また、キャパシタＣ
1すなわち入力キャパシタを基準キャパシタとすること
ができことは勿論であり、その場合、界面凖位の差△Ｄ
itを求めるための式（６）は、以下のように変形され
る。Therefore, if one of the capacitors C2 is used as a reference capacitor and its capacitance value is obtained, the difference ΔDit in interface between the two capacitors C1 and C2 can be calculated from the equation (6). This makes it possible to obtain a distribution of interface levels of the insulating film on the wafer. When obtaining the absolute value Dit of the interface depression, the value of the interface depression of the reference capacitor is obtained by some method, and the absolute value Dit can be obtained from the value and ΔDit. Also, the capacitor C
Of course, the input capacitor can be used as the reference capacitor, in which case the interface difference ΔD
Expression (6) for obtaining it is transformed as follows.
【数７】 △Ｄit＝Ｃ1・Ｖin（Ｖout＋Ｖin）／（Ｖout・ｑ） （７）[Equation 7] △ Dit = C1 ・ Vin (Vout + Vin) / (Vout ・ q) (7)
【００１３】以上のように、本発明においては、ウエハ
上のキャパシタの容量が容量測定器の精度以上の微小容
量であっても、ウエハ上の容量の相対分布を得ることが
でき、さらには、誘電率の相対分布、膜厚の相対分布、
界面凖位の分布を簡単に得ることができる。As described above, in the present invention, the relative distribution of the capacitance on the wafer can be obtained even if the capacitance of the capacitor on the wafer is a minute capacitance which is higher than the precision of the capacitance measuring instrument. Relative distribution of dielectric constant, relative distribution of film thickness,
The distribution of interface levels can be easily obtained.
【図１】本発明の半導体絶縁膜の特性測定装置に用いら
れるアナログ反転器の構成を示すブロック図である。FIG. 1 is a block diagram showing a configuration of an analog inverter used in a semiconductor insulating film characteristic measuring apparatus of the present invention.
【図２】特性が相違している２つのキャパシタのＣＶ曲
線の一例を示すグラフであり、界面凖位の差を説明する
ためのグラフである。FIG. 2 is a graph showing an example of CV curves of two capacitors having different characteristics, and is a graph for explaining a difference in interface level.
Claims (6)
気的に評価する装置において、 入力電圧供給手段と、 入力端子が、絶縁膜の第１の測定点における第１の部分
によって形成される第１のキャパシタを介して、入力電
圧供給手段に接続され、出力端子が、絶縁膜の第２の測
定点における第２の部分によって形成される第２のキャ
パシタを介して、入力端子と接続される演算増幅器と、 入力電圧供給手段からの入力電圧と演算増幅器の出力電
圧とに基づいて、絶縁膜の第１及び第２の部分における
絶縁膜の相対的特性を演算する演算手段とからなること
を特徴とする電気的評価装置。1. An apparatus for electrically evaluating the characteristics of an insulating film on a substrate of a semiconductor device, wherein an input voltage supply means and an input terminal are formed by a first portion at a first measurement point of the insulating film. Connected to the input voltage supply means via the first capacitor, and the output terminal connected to the input terminal via the second capacitor formed by the second portion at the second measurement point of the insulating film. And an arithmetic means for calculating the relative characteristics of the insulating film in the first and second portions of the insulating film based on the input voltage from the input voltage supply means and the output voltage of the operational amplifier. An electrical evaluation device characterized by the above.
て、演算手段は、 第１のキャパシタと第２のキャパシタとの比である相対
容量値を、演算増幅器の出力手段と入力電圧供給手段か
らの入力電圧との比として演算する手段を備えているこ
とを特徴とする電気的評価装置。2. The electrical evaluation apparatus according to claim 1, wherein the arithmetic means calculates a relative capacitance value, which is a ratio of the first capacitor and the second capacitor, from the output means and the input voltage supply means of the operational amplifier. An electrical evaluation device comprising means for calculating the ratio of the input voltage to the input voltage.
おいて、演算手段は、 絶縁膜の第１の部分と第２の部分との相対誘電率を、第
１の部分の膜厚と第２の部分の膜厚との比である相対膜
厚が既知である場合に、該相対膜厚と、演算増幅器の出
力電圧と入力電圧供給手段からの入力電圧との比とを乗
算することによって演算する手段を備えていることを特
徴とする電気的評価装置。3. The electrical evaluation apparatus according to claim 1 or 2, wherein the calculating means calculates the relative dielectric constant between the first portion and the second portion of the insulating film and the film thickness of the first portion and the relative dielectric constant. By multiplying the relative film thickness, which is the ratio of the film thickness of the second part, by the ratio of the output voltage of the operational amplifier to the input voltage from the input voltage supply means, An electrical evaluation apparatus comprising means for calculating.
価装置において、演算手段は、 絶縁膜の第１の部分の膜厚と第２の部分の膜厚との比で
ある相対膜厚を、第１の部分と第２の部分との相対誘電
率が既知である場合に、該相対誘電率と、入力電圧供給
手段からの入力電圧と演算増幅器の出力電圧との比とを
乗算することによって演算する手段を備えていることを
特徴とする電気的評価装置。4. The electrical evaluation device according to claim 1, wherein the arithmetic means is a relative film that is a ratio of the film thickness of the first portion and the film thickness of the second portion of the insulating film. If the relative permittivity between the first portion and the second portion is known, the thickness is multiplied by the relative permittivity and the ratio of the input voltage from the input voltage supply means to the output voltage of the operational amplifier. An electrical evaluation apparatus comprising a means for performing an operation by performing.
価装置において、演算手段は、 絶縁膜の第１の部分と第２の部分との界面准位の差を、
絶縁膜の第１の部分の第１のキャパシタが既知である場
合に、該第１のキャパシタと、入力電圧供給手段からの
入力電圧と演算増幅器の出力電圧との比と、該入力電圧
と出力電圧との和と、電気素量の逆数とを乗算すること
によって演算する手段を備えていることを特徴とする電
気的評価装置。5. The electrical evaluation apparatus according to any one of claims 1 to 4, wherein the arithmetic means calculates a difference in interface level between the first portion and the second portion of the insulating film,
When the first capacitor of the first portion of the insulating film is known, the ratio of the first capacitor and the input voltage from the input voltage supply means to the output voltage of the operational amplifier, the input voltage and the output. An electrical evaluation apparatus comprising means for calculating by multiplying the sum of the voltage and the reciprocal of the elementary quantity.
価装置において、演算手段は、 絶縁膜の第１の部分と第２の部分との界面准位の差を、
絶縁膜の第２の部分の第２のキャパシタが既知である場
合に、該第２のキャパシタと、入力電圧供給手段からの
入力電圧と演算増幅器の出力電圧との和と、電気素量の
逆数とを乗算することによって演算する手段を備えてい
ることを特徴とする電気的評価装置。6. The electrical evaluation apparatus according to claim 1, wherein the arithmetic means calculates a difference in interface level between the first portion and the second portion of the insulating film,
When the second capacitor of the second portion of the insulating film is known, the second capacitor, the sum of the input voltage from the input voltage supply means and the output voltage of the operational amplifier, and the reciprocal of the elementary charge. An electrical evaluation apparatus comprising means for calculating by multiplying by and.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19981397A JP3362639B2 (en) | 1997-07-25 | 1997-07-25 | Electrical evaluation system for insulating film of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19981397A JP3362639B2 (en) | 1997-07-25 | 1997-07-25 | Electrical evaluation system for insulating film of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1145918A JPH1145918A (en) | 1999-02-16 |
| JP3362639B2 true JP3362639B2 (en) | 2003-01-07 |
Family
ID=16414077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19981397A Expired - Fee Related JP3362639B2 (en) | 1997-07-25 | 1997-07-25 | Electrical evaluation system for insulating film of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3362639B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007248198A (en) * | 2006-03-15 | 2007-09-27 | Sharp Corp | Feature quantity extraction method of characteristic distribution, and classification method of characteristic distribution |
-
1997
- 1997-07-25 JP JP19981397A patent/JP3362639B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1145918A (en) | 1999-02-16 |
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