JP3561112B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device using a redundancy technique for replacing a normal row / column containing a defective memory cell with a spare row / column.
[0002]
[Prior art]
Recently, it has become more and more difficult to operate all-bit cells due to the increase in memory capacity and miniaturization of cells. In the current memory, a redundancy circuit is provided internally, and among the regular rows / columns, those containing defective cells are replaced with spare rows / columns, and even if all of the regular cells do not operate, good products can be obtained. I am trying to get it. This is a so-called redundancy technology.
[0003]
The redundancy circuit includes a PROM (Programmable ROM) circuit, in which information indicating a defective address is written. The written information is stored in the PROM circuit. The redundancy circuit selects a spare row / column instead of a row / column containing a defective cell according to information stored in the PROM circuit.
There are various types of PROM elements constituting a PROM circuit, and a fuse is widely used in a dynamic RAM (hereinafter referred to as DRAM). The fuse stores information depending on whether it is blown or not. The blow of the fuse is generally performed by laser fusing or current fusing.
[0004]
Hereinafter, a conventional example of the redundancy circuit will be described using a special-purpose DRAM. FIG. 34 is a schematic plan view of a conventional special-purpose 18MDRAM chip, and FIG. 35 is a schematic plan view of the 2M cell array shown in FIG.
[0005]
As shown in FIG. 34, the 18M DRAM chip 101 is provided with eight 2M cell arrays 102 and two 1M cell arrays 103. Four 2M cell arrays 102 are arranged on each of the right (RIGHT) and left (LEFT) sides of the chip 101, and one 1M cell array 103 is arranged on each of the right (RIGHT) and left (LEFT) sides. This achieves a storage capacity of 18M. A pad 104 serving as a contact between the inside and the outside of the chip 101 is arranged along the edge of the chip 101. Since the use of the 18MDRAM shown here is special, the area 105 in which the pads 104 are arranged is set not along each of the four sides of the chip 101 but along three sides. The chip 101 having such a special pad arrangement is housed in a vertical package such as a VSMP (Vertical Surface Mount Package).
[0006]
As shown in FIG. 35, the 2M cell array includes a total of eight 256k sub-arrays 106, four on each of the upper side (TOP) and the lower side (BOTTOM) of the chip 101. In each subarray 106, a word line extending in the X direction and a bit line extending in the Y direction are formed. Further, a dynamic memory cell including a storage capacitor and a transfer transistor connecting the capacitor to a bit line is formed in each sub-array 106 (none is shown). The transfer transistor has a gate connected to the word line, a drain connected to the bit line, and a source connected to the storage capacitor. In a region 107 between each sub-array 106, a sense amplifier (S / A) for amplifying a potential difference between the bit line pairs, an equalizer (EQL) for precharging and equalizing the potential difference between the bit line pairs, a selected bit line A circuit connected to the bit line pair such as a column gate (CG) for connecting the pair to the data line is arranged. In particular, the sense amplifier is a shared type shared by the left and right sub-arrays 106.
[0007]
The row decoder (R / D) is arranged in an area 108 between the 256k sub-array 106 arranged on the upper side (TOP) of the chip 101 and the 256k sub-array 106 arranged on the lower side (BOTTOM).
[0008]
In an 18MDRAM having such a layout, a redundancy circuit (RFUSE) including a fuse is arranged in the same region 108 as a row decoder (R / D). Thus, the redundancy circuit is arranged near the row decoder. The reason is that the redundancy circuit becomes a critical path that determines the time from the input of the row address to the activation of the spare row decoder. That is, by arranging the redundancy circuit near the row decoder, the time difference between the time required to activate the main row decoder and the time required to activate the spare row decoder is reduced.
[0009]
FIGS. 36A and 36B are schematic circuit block diagrams of a 256k sub-array. Hereinafter, an outline of the redundancy operation will be described with reference to a circuit block diagram.
[0010]
First, the address signal A is input to the pad 104 as shown in FIG. The input address signal A is input to the address buffer 114. When an address buffer activating signal (corresponding to a / RAS signal in a general DRAM) becomes a level that activates the address buffer 114, the address signal A is sent from the address buffer 114 to the internal address signal (hereinafter, referred to as an internal signal). , Row address) AR. The row address signal AR is input to the redundancy circuit (RFUSE) 111 shown in FIG. 36A, and is also input to the main row decoder 115 of the row decoder (R / D). The main row decoder 115 selects and drives the word line (WL) arranged in the normal portion 116 of the 256k sub-array 106 according to the logic of the input row address signal AR. If the logic of the input row address signal AR is to select a defective row (defective word line) of the normal portion 116, the output level of the output node N of the redundancy circuit 111 is inverted, and the spare row is inverted. The input level to the decoder 117 is inverted. At this time, the spare row decoder 117 selects and drives the spare word line (SWL) arranged in the spare portion 118 of the 256k sub-array 106. At the same time, the level of the output signal / RSP to the main row decoder 115 is inverted. The function of decoding the row address of the main row decoder 115 is inactive while the level of the output signal / RSP is inverted.
[0011]
FIG. 37 is a specific circuit diagram of the redundancy circuit 111. Here, for simplicity, a circuit that selects four word lines WL1, WL2, WL3, WL4 and one spare word line SWL from the row addresses A0R, / A0R, A1R, / A1R is shown.
[0012]
First, the configuration of the circuit will be described.
[0013]
As shown in FIG. 37, the redundancy circuit 111 includes fuse circuits (FUSE0), (FUSE / 0), (FUSE1), and (FUSE / 1) corresponding to each of the row addresses A0R, / A0R, A1R, and / A1R. )have. Each of these fuse circuits has an N-channel MOSFET (hereinafter referred to as NMOS) 120 receiving a row address at its gate, and a fuse 122. The source of the NMOS 120 is connected to the low-potential power supply Vss (for example, ground potential), and the drain is connected to the output node N via the fuse 122. The spare row decoder 117 has an inverter 124 whose input is connected to the output node N, and an inverter 125 whose input is connected to the output of the inverter 124. Further, a P-channel MOSFET (hereinafter, referred to as PMOS) 126 has a gate receiving the output of the inverter 124, a source receiving the high potential power supply Vdd, and a drain connected to the input of the inverter 124. The output of the inverter 124 is a signal / RSP, which is supplied to the main row decoder 115. The output of inverter 125 is signal RSP, which is supplied to spare word line SWL.
[0014]
Next, the operation will be described.
[0015]
First, the case where the fuse 122 is not blown will be described. At this time, when each of the row addresses A0R, / A0R, A1R, and / A1R attains the "H" level, the NMOS 120 conducts, and the potential of the output node N is discharged to the "L" level. When the potential of output node N attains "L" level, the output of inverter 124 attains "H" level, and signal / RSP attains "H" level. When the signal / RSP goes to “H” level, one of the inputs of the NAND gates 127 included in the main row decoder 115 goes to “H” level, and all the NAND gates 127 are activated. Thereby, the function of decoding the row address of the main row decoder 115 is activated. In the NAND gate 127 in which all inputs are at the "H" level, the output thereof is at the "L" level to select and drive the word line (WL). FIG. 38 shows the relationship between the row address level and the selected word line. Further, since the output of inverter 125 is at "L" level, the spare word line (SWL) is not selected.
[0016]
Further, when the fuse 122 is blown, the NMOS 120 connected to the blown fuse 122 does not discharge the potential of the output node N even if the “H” level row address is supplied. Therefore, the potential of the output node N remains at the “H” level (for example, the precharge potential). When the potential of output node N is at "H" level, the output level of inverter 124 of spare row decoder 117 attains "L" level, and signal / RSP attains "L" level. As a result, one of the inputs of each of the NAND gates 127 included in the main row decoder 115 becomes “L” level, and the outputs of all the NAND gates 127 become “H” level regardless of the level of the row address. Thus, the function of decoding the row address of the main row decoder 115 becomes inactive. At the same time, the output of the inverter 125 becomes "H" level, and the spare word line (SWL) is selected and driven. FIG. 39 shows the relationship between the blow state of the fuse 122 and the word line (WL) replaced with the spare word line (SWL). In FIG. 39, the fuse circuit (FUSE) in which the fuse 122 is blown is denoted by “cut”, and the fuse circuit (FUSE) in which the fuse 122 is not blown is denoted by “no cut”.
[0017]
FIG. 40A is a schematic plan view of the fuse and its vicinity, and FIG. 40B is a cross-sectional view taken along line 40B-40B in FIG.
[0018]
As shown in FIGS. 40A and 40B, in the P-type silicon substrate 181, P-type wells 182-1 and 182-2 biased to the potential Vss, N-type wells 183 biased to the potential Vdd, Further, N-type wells 184-1 to 184-n having potentials floating, which are separated from these wells, are formed. In the P-type wells 182-1 and 182-2 and the N-type well 183, an NMOS and a PMOS constituting a row decoder and a peripheral circuit (for example, a sense amplifier drive circuit) are formed. The fuses 122-1 to 122-n are respectively formed on the N-type wells 184-1 to 184-n via a thick insulating film such as a field oxide film 185. The fuses 122-1 to 122-n are provided one by one in the N-type wells 184-1 to 184-n. When the fuse 122 is blown, a hole reaching the substrate 181 may be formed in the field oxide film 185 by the impact. If a piece of the fuse 122 or a conductive particle enters the hole, the wiring and the substrate 181 are short-circuited. Such a situation is solved by providing a floating N-type well 184 for each of the fuses 122. That is, even if fragments of the fuse 122 enter the hole opened in the field oxide film 185, a short circuit between the wiring and the substrate 181 is prevented by the floating N-type well 184.
[0019]
[Problems to be solved by the invention]
By the way, progress in miniaturization of fuses depends on the accuracy of a laser blower. Even if the fuse is miniaturized, it is meaningless if the laser blower cannot accurately blow the miniaturized fuse. For this reason, miniaturization of fuses does not match the pace of miniaturization of other semiconductor elements such as MOSFETs. Therefore, the difference between the size of the fuse and the size of another semiconductor element is expanding. In particular, in a DRAM row / column decoder, it is required that the element patterns be formed densely in accordance with the arrangement pitch of the memory cells.
[0020]
Further, the absolute number of defective memory cells increases as the storage capacity increases. In order to rescue the increasing number of defective memory cells, the number of fuses must be increased. As the number of fuses increases, the circuit scale of the redundancy circuit including the fuses also increases.
[0021]
As described above, as memory cells are miniaturized at the current pace and storage capacity increases, there is a possibility that fuses will eventually hinder high integration.
[0022]
Since the fuse is blown, nothing can be placed on the fuse. At present, despite the fact that the degree of freedom of the wiring layout has been greatly increased by the multilayer wiring technology, there is a restriction that wiring is performed while avoiding over fuses.
[0023]
In addition, a technique has been reported in which a fuse is replaced with another PROM element, for example, a floating gate type MOSFET used for a memory cell of an EEPROM. In this type of circuit, since there is no fuse, the problem of the redundancy circuit having the fuse is solved. However, a write circuit for writing information of a defective address, a write power supply, and a write wiring are required. For this reason, considering the future increase in integration density, it is not realistic. Further, when the semiconductor memory device is a DRAM, there is no commonality in the manufacturing process, and the manufacturing cost is likely to increase.
[0024]
A semiconductor integrated memory that solves such a situation is disclosed in Japanese Patent Application Laid-Open No. 4-263199. FIG. 41 is a simplified block diagram showing the semiconductor integrated memory.
[0025]
In the semiconductor integrated memory disclosed in Japanese Patent Application Laid-Open No. 4-263199, a PROM element using a fuse or the like is removed from a chip, and a content addressable memory (CAM) is provided instead.
[0026]
In a redundancy circuit having an associative memory, information on a defective address is input from outside the chip before operating the memory, and the information is stored in a RAM circuit of the associative memory. When the memory is operating, the address held in the RAM circuit is compared with the address input from the address line, and only when the addresses match, the spare memory cell array is accessed.
[0027]
This type of redundancy circuit has no fuse and no floating gate type MOSFET. Therefore, any of the above problems can be solved. However, in this type of redundancy circuit, it is necessary to write defective address information to the RAM circuit before operating the memory. Therefore, a test circuit for testing a memory cell and detecting an address of a defective memory cell must be provided outside the system. Alternatively, a dedicated self-test circuit must be provided in the chip separately from the associative memory. Usually, such a test is performed by inspecting many items using a memory tester, and is not a simple test. Therefore, it is difficult to provide such a self-test circuit in a chip.
The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide a more practical configuration in a semiconductor integrated circuit device having a redundancy circuit for storing defective address information by a volatile storage circuit. Have That is, a fuse for storing defective address information can be provided in the defective address storage circuit with a reduced possibility of occurrence of misblow. An object of the present invention is to provide a semiconductor integrated circuit device.
[0028]
A second object of the present invention is to achieve the first object and to reduce the scale of a circuit for storing basic information to be provided to the volatile storage circuit, and to provide a semiconductor having a structure suitable for further high integration. An object of the present invention is to provide an integrated circuit device.
[0031]
Also, the 3 An object of the present invention is to provide a semiconductor integrated circuit device in which a defective address storage circuit included in a semiconductor integrated circuit device according to the present invention can be provided on a semiconductor chip without hindering high integration of the integrated circuit and multilayer wiring. It is in.
[0032]
[Means for Solving the Problems]
In order to achieve the first object, in the invention according to claim 1, a semiconductor chip having a memory function and a memory cell array provided in the chip and including a main row / column and a spare row / column are provided. A defective address storage circuit provided in the chip and storing the defective address information in the main row / column by a nonvolatile storage circuit; and a defective address storage circuit provided in the chip and stored in the defective address storage circuit. A redundancy circuit for storing copy information of the defective address information by a volatile storage circuit, a circuit provided in the chip, for selecting the main row / column according to an address input, and stored in the redundancy circuit. Replaces the spare row / column with the main row / column according to the copy information and selects An address decoder including a spare selection circuit, and transferring the defective address information stored in the defective address storage circuit to a volatile storage circuit of the redundancy circuit in accordance with a transfer timing signal provided in the chip. A transfer circuit for causing the defective address storage circuit to store defective address information. element These fuses element Is the fuse element The laser is arranged so that its major axis direction is aligned with the direction in which the laser for blowing the laser beam moves.
[0033]
According to the first aspect of the present invention, the defective address information is stored in the defective address storage circuit provided in the chip, and the stored defective address information is stored in the volatile storage circuit of the redundancy circuit in accordance with the transfer timing signal. Since the transfer is performed, the defective address information can be easily copied to the volatile storage circuit. Therefore, it has a configuration that can be more practically used than a semiconductor integrated circuit device having a redundancy circuit including a known volatile storage circuit. With this, fuse element By aligning the long axis direction of the fuse with the direction in which the laser for blowing moves, the fuse element Both the length of the blown portions and the distance between the blown portions can be made sufficiently large. For this reason, a fuse for storing defective address information element In addition, it is possible to provide a semiconductor integrated circuit device that can reduce occurrence of misblow.
[0036]
Also, Claim 2 The invention according to Claim 1 In the invention according to the invention, the defective address storage circuit includes a resistor connected in series between power supplies, Said A fourth insulated gate FET including a fuse element and a fourth insulated gate type FET for receiving the transfer timing signal at a gate, except when the transfer timing signal specifies a mode for transferring the defective address information; And turning off the type FET and deactivating the defective address storage circuit.
[0037]
the above Claim 2 According to the invention, the fourth insulated gate FET included in the defective address storage circuit can be turned on only when the transfer timing signal specifies the mode for transferring the defective address information. The current consumption consumed by the defective address storage circuit can be reduced. Therefore, Claim 1 According to the present invention, it is possible to realize a configuration in which current consumption can be further reduced, and to provide a semiconductor integrated circuit device having a configuration that can be more practically used, particularly from the viewpoint of current consumption.
[0038]
Also, Claim 3 The invention according to claim 1 And any one of claims 2 In the present invention, the redundancy circuit compares a potential level of the copy information with a potential level of the address input, as a volatile storage element, and compares a potential level of the copy information with a potential level of the address input. And a comparison circuit for changing an input level to the spare selection circuit.
[0039]
the above Claim 3 According to the invention, the potential level of the copy information is compared with the potential level of the address input, and the input level to the spare selection circuit is changed in accordance with one of the coincidence and the non-coincidence. The spare selection circuit can detect whether or not the copy information stored in the register circuit indicates a defective address.
[0040]
Also, Claim 4 The invention according to Claim 3 In the invention according to the invention, the redundancy circuit is connected to an input of the spare selection circuit via a wiring suspended at a matching potential, and the comparison circuit is configured to output a potential level of the copy information and the address input. A potential level is compared with the potential level, and the potential of the wiring is changed to a potential other than the matching potential depending on whether the potentials match or mismatch.
[0041]
the above Claim 4 According to the invention, the spare selection circuit can detect whether or not the copy information stored in the register circuit indicates a defective address, based on whether or not the input potential is a matching potential. For this reason, the spare selecting circuit changes the spare row / column to the main row / column and selects the spare row / column only when the input potential changes to a potential other than the matching potential (or conversely, the main row / column). / Column is changed to the spare row / column for selection). For this reason, for example, it is determined whether the potential shifted from the precharge potential is the “H” level or the “L” level, and then compared with a spare selection circuit that switches between the spare and the main, the switching operation is more easily performed. Can be done at high speed.
[0042]
Also, Claim 5 The invention according to Claim 3 and Claim 4 In any one of the inventions, the register circuit and the comparison circuit are constituted by MOSFETs. When the register circuit and the comparison circuit include N-channel MOSFETs, these N-channel MOSFETs are connected to the N-channel of the address decoder. When the register circuit and the comparison circuit include P-channel MOSFETs, these P-channel MOSFETs are formed in the wells where the P-channel MOSFETs of the address decoder are formed. It is characterized by having been done.
[0043]
the above Claim 5 According to the invention, the register circuit and the comparison circuit are constituted by MOSFETs, and the register circuit and the comparison circuit are formed in the same well as the MOSFETs constituting the address decoder. This allows Claim 3 and Claim 4 The area occupied by the redundancy circuit in the invention according to the invention can be reduced, and the redundancy circuit can be more compactly integrated on the chip.
[0044]
Also, Claim 6 The invention according to claim 1 to claim 1 Claim 5 In the invention according to any one of the above, the transfer timing signal designates a mode in which the defective address information is transferred in response to a power-on of the semiconductor integrated circuit device, and the failure to the redundancy circuit is specified. After the copying of the address information is completed, the designation of the mode for transferring the defective address information is released.
[0045]
the above Claim 6 According to the present invention, the defective address information stored in the defective address storage circuit can be transferred to the volatile storage circuit of the redundancy circuit every time power is applied to the semiconductor integrated circuit device. Thereby, the defective address information can be stored in the semiconductor integrated circuit device while the defective address information is being supplied to the semiconductor integrated circuit device. Claim 5 One example of obtaining the state stored in the volatile storage circuit of the invention according to the present invention can be realized.
[0046]
In order to achieve the second object, Claim 7 In the invention according to the invention, a semiconductor chip having a memory function, a cell array provided in the chip, a sub-array set in the cell array and including a main row / column and a spare row / column, respectively, A defective address storage circuit provided in the chip for storing the defective information of the sub-array and the defective address information in the main row / column, respectively, and a non-volatile storage of the sub-array information in the chip. A redundancy circuit for storing, by a volatile storage circuit, copy information of the defective address information stored in the defective address storage circuit, and a redundancy circuit provided in the chip, wherein the main row is stored in accordance with an address input. / Column selection circuit and the redundancy circuit And an address decoder including a spare selection circuit for selecting the spare row / column by replacing the spare row / column with the main row / column in accordance with the copy information stored in the chip. Comparing the defect information of the sub-array stored in the defective address storage circuit with the sub-array information stored in the redundancy circuit, and as a result of the comparison, of the redundancy circuits, matches the defect information of the sub-array. A transfer circuit for transferring the defective address information to a volatile storage circuit of the redundancy circuit of the sub-array.
[0047]
the above Claim 7 According to the invention, the defective address information is transferred to the volatile storage circuit of the redundancy circuit of the sub-array that matches the failure information of the sub-array among the redundancy circuits. Therefore, the defective address storage circuit can be shared by several sub-arrays, the size of the defective address storage circuit can be reduced, and a semiconductor integrated circuit device suitable for higher integration can be obtained.
[0054]
In order to achieve the third object, Claim 8 According to the invention, the defective address circuit is arranged along a row of pads.
[0055]
the above Claim 8 According to the invention according to the first aspect, the defective address circuit is arranged along the row of the pads, so that the integrated circuit, for example, the memory Re It can be provided without hindering high integration of a cell array or the like and multilayer wiring.
[0056]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described with reference to embodiments. In this description, common parts are denoted by common reference symbols throughout the drawings.
[0057]
FIG. 1 is a schematic plan view of a special-purpose 18MDRAM chip according to the first embodiment of the present invention, and FIG. 2 is a schematic plan view of the 2M cell array shown in FIG. As shown in FIG. 1, the 18M DRAM chip 1 is provided with eight 2M cell arrays 2 and two 1M cell arrays 3. Four 2M cell arrays 2 are arranged on each of the right (RIGHT) and left (LEFT) sides of the chip 1, and one 1M cell array 3 is arranged on each of the right (RIGHT) and left (LEFT) sides. This achieves a storage capacity of 18M. A pad 4 serving as a contact point with the outside of the integrated circuit formed on the chip 1 is arranged along the edge of the chip 1. Since the use of the 18MDRAM shown here is special, the area 5 where the pads 4 are arranged is not set along each of the four sides of the chip 1 but along three sides. The chip 1 having such a special pad arrangement is accommodated in a vertical package such as a VSMP (Vertical Surface Mount Package).
[0058]
As shown in FIG. 2, the 2M cell array 2 includes a total of eight 256k sub-arrays 6, four on each of the upper side (TOP) and the lower side (BOTTOM) of the chip 1. In each subarray 6, a word line (WL) (not shown) extending in the X direction and a bit line (BL) not shown extending in the Y direction are formed. Further, in each sub-array 6, a dynamic memory cell (M) including a storage capacitor (not shown) and a transfer transistor (not shown) for connecting the capacitor to a bit line is formed. The transfer transistor has a gate connected to the word line, a drain connected to the bit line, and a source connected to the storage capacitor. In a region 7 between the sub-arrays 6, a sense amplifier (S / A) for amplifying the potential difference between the bit line pairs, an equalizer (EQL) for precharging and equalizing the potential difference between the bit line pairs, a selected bit line A circuit connected to the bit line pair such as a column gate (CG) connecting the pair to the data line (DQ) is arranged. In particular, the sense amplifier is of a shared type shared by the left and right sub-arrays 6. The row decoder (R / D) is arranged in a region 8 between the sub-array 6 arranged on the upper side (TOP) of the chip 1 and the sub-array 6 arranged on the lower side (BOTTOM). A redundancy circuit (CAM) including an associative memory is arranged in an area 8 where a row decoder (R / D) is arranged.
[0059]
Further, in the present invention, the chip 1 has a defective address storage circuit (RFUSE) for storing basic information to the redundancy circuit (CAM), that is, defective address information. The defective address storage circuit (RFUSE) stores defective address information using a nonvolatile storage element such as a fuse. Since the defective address storage circuit (RFUSE) includes a fuse, the defective address storage circuit (RFUSE) is arranged in a portion of the chip 1 that does not hinder the miniaturization of the cell array and peripheral circuits. In the device according to the first embodiment, the defective address storage circuit (RFUSE) is provided with an edge (or dicing line) of the chip 1 and an area 5 where the pad 4 is arranged, as shown in FIGS. It is located in the area between.
[0060]
3A to 3C are schematic circuit block diagrams of a 256k sub-array. Hereinafter, an outline of the redundancy operation will be described with reference to a circuit block diagram.
[0061]
According to the present invention, before operating the memory, the defective address information is transferred from the defective address storage circuit (RFUSE) to the redundancy circuit (CAM) including the associative memory and stored in the redundancy circuit (CAM). Therefore, first, the transfer timing signal FDX shown in FIGS. 3A and 3C is changed from the “L” level to the “H” level. When the transfer timing signal FDX is set to “H” level, the defective address storage circuit (RFUSE) 11 shown in FIG. 3C outputs the defective address information F stored therein. The output defective address information F is input to a multiplexer (MUX) 12 shown in FIG. When the transfer timing signal FDX is at “H” level, the multiplex circuit 12 inputs the defective address information F to the redundancy circuit (CAM) 13 including the associative memory in place of the row address AR. When the transfer timing signal FDX is at "H" level, the redundancy circuit 13 switches the mode of the register circuit of the associative memory provided therein from the mode of holding information (write / non-rewritable mode) to the mode of writing information. The mode switches to a mode that allows. As a result, the copy information of the defective address information F stored in the defective address storage circuit 11 is written to the register circuit.
[0062]
Thereafter, when the transfer timing signal FDX is set to the “L” level, the defective address storage circuit 11 is deactivated, and the redundancy circuit 13 switches from the mode in which the register circuit can write to the mode in which the written information is held. Switch to.
[0063]
In this way, the copy information of the defective address information F is transferred to the redundancy circuit 13 and stored therein.
[0064]
The register circuit of the associative memory is a RAM circuit, which is a volatile storage circuit. For this reason, when the power of the apparatus is turned off, the information stored here disappears. This lost information needs to be written again. For this reason, a rewriting function is required. The transfer timing signal FDX shown in FIG. 3 is an "H" pulse signal and is also a trigger signal for instructing rewriting. One example of the signal FDX is to use a power-on reset signal. Another example is that a power-on reset signal is used as a trigger to generate the signal separately. Still another example is to provide a dedicated pad for inputting the signal FDX and to input the signal from the outside. The “H” pulse may be one shot or a plurality of shots.
[0065]
By supplying such a transfer timing signal FDX to the defective address storage circuit 11, the multiplexer 12, and the redundancy circuit 13 at the time of power-on or before the operation of the memory is started, a rewrite function can be realized in the chip 1.
[0066]
After the defective address information F is transferred / held in the redundancy circuit 13, the same operation as in a device having a normal redundancy circuit is performed as follows, for example.
[0067]
First, as shown in FIG. 3B, the address signal A is input to the pad 4. The input address signal A is input to the address buffer 14. When the address buffer activation signal (a signal corresponding to the / RAS signal in a general DRAM) becomes a level for activating the address buffer 14, the address signal A is output from the address buffer 14. , Are output as internal address signals (hereinafter, row addresses) AR. The row address AR is input to the multiplexer 12 shown in FIG. At this time, the transfer timing signal FDX is at the “L” level. The row address AR input to the multiplexer 12 is input to the main row decoder 15 of the redundancy circuit 13 and the row decoder (R / D). The main row decoder 15 selects and drives the word line (WL) arranged in the regular portion 16 of the 256k sub-array 6 shown in FIG. 3A according to the logic of the input row address AR. If the logic of the input row address AR is to select a defective row (defective word line) of the normal portion 16, the redundancy circuit 13 inverts the output level and outputs a spare row decoder 17. Invert the input level to. As a result, the spare row decoder 17 selects and drives the spare word line (SWL) arranged in the spare portion 18 of the 256k subarray 6. At the same time, the redundancy circuit 13 inverts the level of the output signal / RSP to the main row decoder 15. While the level of output signal / RSP is inverted, the function of decoding the address of main row decoder 15 is inactivated.
[0068]
FIG. 4 is a specific circuit diagram of the defective address storage circuit, the redundancy circuit, and the row decoder. Here, for simplicity, a circuit that selects four word lines WL1, WL2, WL3, WL4 and one spare word line SWL from the row addresses A0R, / A0R, A1R, / A1R is shown. Hereinafter, the configuration and operation of the circuit will be described with reference to the circuit diagram.
[0069]
As shown in FIG. 4, the defective address storage circuit 11 included in the device according to the first embodiment includes fuse circuits (FUSE0) and (FUSE0) provided for each row address A0R, / A0R, A1R, / A1R. / F0), (FUSE1) and (FUSE / 1). Each of these fuse circuits (FUSE) has a resistor 20, a fuse 21, and an NMOS 22 whose gate receives a transfer timing signal FDX. The source of the NMOS 22 is connected to a low-potential power supply Vss (for example, a ground potential), and the drain is connected to one end of the fuse 21. The other end of the fuse 21 is connected to one end of a resistor 20, and the other end of the resistor 20 is connected to a high potential power supply Vdd. The defective address information F stored in the fuse circuit (FUSE) is extracted from an interconnection point between one end of the resistor 20 and the other end of the fuse 21. The extracted defective address information F is supplied to the multiplexer 12.
[0070]
The multiplexer 12 has multiplex circuits (MUX0), (MUX / 0), (MUX1), and (MUX / 1) provided for each of the row addresses A0R, / A0R, A1R, and / A1R. Each of these multiplex circuits (MUX) has two inputs and one input, and transmits one of the two inputs to its output according to a transfer timing signal FDX. This is a so-called 2: 1 multiplex circuit. The multiplex circuit (MUX) may be constituted by a conventionally known 2: 1 multiplex circuit. One input of the multiplex circuit (MUX) is supplied with defective address information F, and the other input is supplied with a row address AR. The multiplex circuit (MUX) transmits the defective address information F to its output when the transfer timing signal FDX is at "H" level, and transmits the row address AR to its output when the transfer timing signal FDX is at "L" level. . In the device according to the first embodiment, the output of the multiplex circuit 12 is supplied to the internal address line 19.
[0071]
The redundancy circuit 13 has an associative memory circuit (CAM0), (CAM / 0), (CAM1), (CAM / 1) provided for each row address A0R, / A0R, A1R, / A1R. . Each of these associative memory circuits (CAM) has a register circuit 30 for holding and storing the defective address information F, one end connected to the internal address line 19, the other end connected to the register circuit 30, and a transfer timing signal FDX connected to the gate. A write gate circuit 31 receiving the received address, and a comparison circuit 32 which compares the defective address information F held / stored in the register circuit 30 with the input row address AR and outputs information on whether the address matches or not to the output node N. have. Output node N is suspended at potential MATCH. In the first embodiment, the register circuit 30 is constituted by a so-called cross-coupled latch circuit constituted by two inverters. The write gate circuit 31 includes one NMOS 42 having a current path connected in series between the internal address line 19 and one node 41 of the latch circuit. The comparison circuit 32 has an NMOS 43 having one end connected to the output node N of the redundancy circuit 13 and a gate connected to one node 41 of the latch circuit, and a current path connected to the other end of the current path of the NMOS 43. , An NMOS 44 having a gate connected to the internal address line 19, and the other end of the current path connected to the low potential power supply Vss.
[0072]
The spare row decoder 17 includes an inverter 50 having an input connected to the output node N of the redundancy circuit 13, an inverter 51 having an input connected to the output of the inverter 50, and an inverter 52 having an input connected to the output of the inverter 51. have. The output of inverter 52 is supplied to spare word line SWL. Further, the output of the inverter 51 is supplied to the main row decoder 15 (that is, the signal / RSP).
[0073]
Next, the operation will be described.
[0074]
FIG. 5 shows the relationship between the logic of the row address and the selected word line. FIG. 6 shows the relationship between the state of the fuse and the word line (WL) replaced with the spare word line (SWL). In FIG. 6, the fuse circuit (FUSE) in which the fuse is blown is denoted by “cut”, and the fuse circuit (FUSE) in which the fuse is not blown is denoted by “no cut”.
[0075]
First, an example in which the word line WL1 is replaced with a spare word line SWL will be described.
[0076]
As shown in FIG. 6, when replacing the word line WL1 with the spare word line SWL, the fuses 21 of the fuse circuits (FUSE / 0) and (FUSE / 1) shown in FIG. 4 are blown. In other fuse circuits (FUSE0) and (FUSE1), no fuse is blown.
[0077]
Next, the transfer timing signal FDX is set to the “H” level. At this time, the defective address information (F0), (F / 0), (F1), and (F / 1) are set to levels of "L", "H", "L", and "H", respectively. It is output from the address storage circuit 11. Then, in the associative memories (CAM0), (CAM / 0), (CAM1), and (CAM / 1) shown in FIG. 4, the nodes 41 are set to "L", "H", "L", Copy information at the “H” level is held / stored. With these pieces of copy information, the NMOSs 43 of the associative memories (CAM0), (CAM / 0), (CAM1), and (CAM / 1) are turned "off", "on", "off", and "on", respectively.
[0078]
In this state, it is assumed that an address for setting the row addresses A0R and A1R to the "L" level is input. At this time, the levels of the row addresses A0R, / A0R, A1R, / A1R transmitted to the internal address line 19 are "L", "H", "L", "H", respectively. By these logics, the NMOSs 44 of the associative memories (CAM0), (CAM / 0), (CAM1) and (CAM / 1) are turned "off", "on", "off" and "on", respectively. As a result, the comparing circuits 32 of the associative memories (CAM / 0) and (CAM / 1) become "conductive", and the comparing circuits 32 of the associative memories (CAM0) and (CAM1) become "non-conductive". The potential of the node N drops through the two comparison circuits 32. If the inverter 50 of the spare decoder 17 detects that the potential of the output node N drops through the two comparison circuits 32 as "L" level, the signal / RSP becomes "L" level. Spare decoder 17 inactivates main row decoder 15 and selects and drives spare word line SWL.
[0079]
It is also assumed that, in the above state, an address is input that sets the row address A0R to the “H” level and A1R to the “L” level. At this time, the levels of the row addresses A0R, / A0R, A1R, and / A1R transmitted to the internal address line 19 are "H", "L", "L", and "H", respectively. With these logics, the NMOSs 44 of the associative memories (CAM0), (CAM / 0), (CAM1), and (CAM / 1) are turned "ON", "OFF", "OFF", and "ON", respectively. As a result, the associative memory, (CAM / 1) comparator 32 becomes "conductive", and the associative memories (CAM0), (CAM / 0), (CAM1) comparators 32 become "non-conductive". The potential of the node N drops through one comparison circuit 32. If the inverter 50 of the spare decoder 17 detects that the potential of the output node N drops through one comparison circuit 32 as the "H" level, the signal / RSP becomes the "H" level. Spare decoder 17 activates main row decoder 15 and does not select spare word line SWL. At this time, the main row decoder 15 selects the word line WL2 according to the logic of the row address.
[0080]
Also, when an address is input in which the row address A0R is at the "L" level and A1R is at the "H" level, only one of the comparison circuits 32 of the content addressable memory (CAM / 0) is set to " It becomes a "conduction state". Therefore, signal / RSP attains an "H" level, and spare decoder 17 activates main row decoder 15 and does not select spare word line SWL. Then, the main row decoder 15 selects the word line WL3 according to the logic of the row address.
[0081]
Also, when an address is input that sets both the row addresses A0R and A1R to the "H" level, the comparison circuits 32 of all the associative memories are turned off. Therefore, signal / RSP attains an "H" level, and spare decoder 17 activates main row decoder 15 and does not select spare word line SWL. Then, the main row decoder 15 selects the word line WL4 according to the logic of the row address.
[0082]
Further, when any one of the word lines WL2, WL3, WL4 is replaced with the spare word line SWL, by blowing a fuse as shown in FIG. 6, it can be realized in the same manner as when replacing the word line WL1.
[0083]
Further, when the replacement of the word line WL is not performed, the fuse is not blown in all of the fuse circuits (FUSE0), (FUSE / 0), (FUSE1), and (FUSE / 1) as shown in FIG. At this time, the defective address information (F0), (F / 0), (F1), and (F / 1) are all at the "L" level, and the content addressable memories (CAM0), (CAM / 0), Copy information for setting the node 41 to the “L” level is held / stored in all the register circuits 30 of (CAM1) and (CAM / 1). With these pieces of copy information, the NMOSs 43 of the associative memories (CAM0), (CAM / 0), (CAM1), and (CAM / 1) are all turned off, and the comparison circuits 32 are all turned off regardless of the logic of the row address. It becomes a "non-conductive state". Therefore, signal / RSP is always at "H" level.
[0084]
The redundancy circuit 13 included in the device according to the first embodiment can be variously modified. For example, in the comparison circuit 32, for example, the internal address line 19 may be connected to the gate of the NMOS 43, and the node 41 of the latch circuit may be connected to the gate of the NMOS 44.
[0085]
In addition, in the redundancy circuit 13, the two comparison circuits 32 are in the “conductive state”, and whether the potential of the output node N is discharged by the two comparison circuits 32 depends on whether the output of the redundancy circuit 13 is inverted or not. Non-inversion is detected by the spare decoder 17. That is, the output node N of the redundancy circuit 13 has negative logic. In this case, the gate of the NMOS 43 may be connected to the other node 45 of the latch circuit, and the output node N of the redundancy circuit 13 may be set to positive logic. In this case, for example, the inverter 50 is removed from the spare decoder 17. Alternatively, an odd number of inverters are added between output node N and spare decoder 17.
[0086]
Next, the structure of the device according to the first embodiment will be described.
[0087]
FIG. 7A is a schematic plan view of the redundancy circuit and its vicinity, and FIG. 7B is a cross-sectional view taken along the line 7A-7A in FIG. 7A.
[0088]
As shown in FIGS. 7A and 7B, a P-type well 182 biased to the potential Vss and an N-type well 183 biased to the potential Vdd are formed in the P-type silicon substrate 181. Each of the P-type well 182 and the N-type well 183 has a row decoder (R / D), a memory peripheral circuit (for example, a sense amplifier drive circuit), and a redundancy circuit 13 (register circuit 30, write gate circuit 31, comparison circuit 32). ) Are formed.
[0089]
Conventionally, the fuse included in the redundancy circuit may hinder the high integration of the cell array. However, in the device according to the first embodiment, all of the circuits constituting the redundancy circuit 13 can be constituted by MOSFETs. . Therefore, the redundancy circuit 13 can be formed in the same well as the row decoder (R / D) and the memory peripheral circuit. Therefore, the pace of miniaturization of the redundancy circuit 13 can be matched with that of the row decoder (R / D), the memory peripheral circuit, and the like. For this reason, the redundancy circuit 13 does not hinder high integration of the cell array as in the related art.
[0090]
In addition, by forming the redundancy circuit 13 in the same well as the row decoder (R / D), the redundancy circuit 13 can be arranged closer to the row decoder (R / D). As a result, the difference between the time required to select the spare word line SWL by the spare row decoder 17 and the time required to select the main word line WL by the main row decoder 15 is smaller than before. This helps to further speed up the operation of the memory.
[0091]
Next, the relationship between the defective address storage circuit and the sub-array will be described.
[0092]
In a memory having a large storage capacity, a cell array is divided into several subarrays. For example, as shown in FIG. 2, the 2M cell array 2 is divided into eight 256k sub arrays 6.
[0093]
FIG. 8 is a circuit block diagram showing a first relationship between a defective address storage circuit and a subarray. FIG. 8 shows an example in which the cell array is divided into eight sub-arrays SUB1 to SUB8.
[0094]
As shown in FIG. 8, defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 are provided corresponding to the respective subarrays SUB1 to SUB8. Each of the sub-arrays SUB1 to SUB8 is provided with a multiplexer (MUX) 12 and a redundancy circuit (CAM) 13 including an associative memory.
[0095]
In the device having the first relationship, wiring for transmitting the defective address information F to the multiplexer 12 from each of the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 to the multiplexer 12 of each of the subarrays SUB1 to SUB8. 60 are provided independently of each other.
[0096]
As described above, in the device connecting the multiplexer 12 of each of the sub-arrays SUB1 to SUB8 and each of the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 by the wirings 60 independent of each other, the defective address information F is stored in each defective address. An advantage is that the data can be transferred at a time from the storage circuits (FUSE) 11-SUB1 to 11-SUB8 to the redundancy circuits 13 of the subarrays SUB1 to SUB8.
[0097]
FIG. 9 is a circuit block diagram showing a second relationship between the defective address storage circuit and the sub-array.
[0098]
As shown in FIG. 9, defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 are provided corresponding to the respective subarrays SUB1 to SUB8. Each of the sub-arrays SUB1 to SUB8 is provided with a multiplexer (MUX) 12 and a redundancy circuit (CAM) 13 including an associative memory.
[0099]
In the device having the second relationship, the common wiring 60-TOP is used for the defective address storage circuits 11-SUB1 to 11-SUB4, and the common wiring 60-BOTTOM is used for the defective address storage circuits 11-SUB5 to 11-SUB8. Have. Output wirings 60 of the defective address storage circuits 11-SUB1 to 11-SUB4 are connected to a common wiring 60-TOP via a selector 61. The common wiring 60-TOP is connected to the multiplexers 12 of the sub arrays SUB1 to SUB4. Similarly, output wirings 60 of the defective address storage circuits 11-SUB5 to 11-SUB8 are connected to a common wiring 60-BOTTOM via a selector 61. The common wiring 60-BOTTOM is connected to the multiplexers 12 of the sub-arrays SUB5 to SUB8. When the transfer timing signal FDX (FDX1 to FDX4) becomes “H” level, the selector 61 transfers the defective address information from the defective address storage circuits 11-SUB1 to 11-SUB8 to the common wiring 60-TOP and 60, respectively. -Tell BOTTOM.
[0100]
As described above, in the device in which the multiplexers 12 of the sub-arrays SUB1 to SUB8 and the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 are connected by the common wiring 60-TOP and 60-BOTTOM, the transfer is performed. The timing signals FDX1 to FDX4 are sequentially set to “H” level one by one. As a result, the defective address information F can be transferred from each of the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 to the redundancy circuit 13 of each of the sub-arrays SUB1 to SUB8. An advantage of the device having the second relationship is that the number of wirings 60 can be reduced as compared with the device having the first relationship.
[0101]
FIG. 10 is a circuit block diagram showing a third relationship between the defective address storage circuit and the sub-array.
[0102]
As shown in FIG. 10, defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 are provided corresponding to the respective subarrays SUB1 to SUB8. Each of the sub-arrays SUB1 to SUB8 is provided with a multiplexer (MUX) 12 and a redundancy circuit (CAM) 13 including an associative memory.
[0103]
In the device having the third relationship, all of the defective address storage circuits 11-SUB1 to 11-SUB8 have a common wiring 60-ARRAY. Output wirings 60 of the defective address storage circuits 11-SUB1 to 11-SUB8 are connected to a common wiring 60-ARRAY via a selector 61. The common wiring 60-ARRAY is connected to the multiplexers 12 of the sub-arrays SUB1 to SUB8. When the transfer timing signal FDX (FDX1 to FDX8) becomes “H” level, the selector 61 transmits the defective address information from the defective address storage circuits 11-SUB1 to 11-SUB8 to the common wiring 60-ARRAY. .
[0104]
As described above, in a device in which the multiplexer 12 of each of the sub-arrays SUB1 to SUB8 and each of the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 are connected by the common wiring 60-ARRAY, the transfer timing signals FDX1 to FDX1 The FDXs 8 are sequentially set to “H” level one by one. As a result, the defective address information F can be transferred from each of the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 to the redundancy circuit 13 of each of the sub-arrays SUB1 to SUB8. An advantage of the device having the third relationship is that the number of wirings 60 can be further reduced as compared with the device having the second relationship.
[0105]
FIG. 11 is a circuit block diagram showing a fourth relationship between the defective address storage circuit and the sub-array.
[0106]
As shown in FIG. 11, defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 are provided corresponding to the respective subarrays SUB1 to SUB8. Each of the sub-arrays SUB1 to SUB8 is provided with a redundancy circuit (CAM) 13 including an associative memory.
[0107]
In the device having the fourth relationship, all of the defective address storage circuits 11-SUB1 to 11-SUB8 have a common wiring 60-ARRAY. Output wirings 60 of the defective address storage circuits 11-SUB1 to 11-SUB8 are connected to a common wiring 60-ARRAY via a selector 61. The common wiring 60-ARRAY is connected to the common multiplexer 12-ARRAY in the sub-arrays SUB1 to SUB8. When the transfer timing signal FDX (FDX1 to FDX8) becomes “H” level, the selector 61 transmits the defective address information from the defective address storage circuits 11-SUB1 to 11-SUB8 to the common wiring 60-ARRAY. . The transfer timing signal FDX0 is supplied to the multiplexer 12-ARRAY. The transfer timing signal FDX0 becomes “H” level, for example, when any one of the transfer timing signals FDX1 to FDX8 becomes “H” level.
[0108]
The advantage of the device having the fourth relationship having such a common wiring 60-ARRAY and the common multiplexer 12-ARRAY is that the number of multiplexers 12 can be reduced as compared with the device having the third relationship. That is.
[0109]
Next, a DRAM according to a second embodiment will be described.
[0110]
In the second embodiment, the circuit scale of the redundancy circuit 13 is reduced. More specifically, the circuit scale of the register circuit 30 is made smaller than that of the first embodiment.
[0111]
FIG. 12 is a specific circuit diagram of the defective address storage circuit, the redundancy circuit, and the row decoder included in the device according to the second embodiment. Here, for simplicity, a circuit that selects four word lines WL1, WL2, WL3, WL4 and one spare word line SWL from the row addresses A0R, / A0R, A1R, / A1R is shown. Hereinafter, the configuration and operation of the circuit will be described with reference to the circuit diagram.
[0112]
As shown in FIG. 12, the defective address storage circuit 11 included in the device according to the second embodiment includes fuse circuits (FUSE0) and (FUSE1) provided for each row address A0R and A1R, and a spare word line. It has a fuse circuit (FUSES) for storing information on whether to use or not to use.
[0113]
First, the fuse circuits (FUSE0) and (FUSE1) used for address replacement each include a resistor 20, a fuse 21, and an NMOS 22 whose gate receives a transfer timing signal FDX. The source of the NMOS 22 is connected to a low-potential power supply Vss (for example, a ground potential), and the drain is connected to one end of the fuse 21. The other end of the fuse 21 is connected to one end of a resistor 20, and the other end of the resistor 20 is connected to a high potential power supply Vdd. The defective address information F stored in the fuse circuits (FUSE0) and (FUSE1) is extracted from an interconnection point between one end of the resistor 20 and the other end of the fuse 21. The extracted defective address information F is supplied to the multiplexer 12.
[0114]
The fuse circuit (FUSES) has a resistor 20, a fuse 21, and an NMOS 23. The source of the NMOS 23 is connected to a low-potential power supply Vss (for example, a ground potential), and the drain is connected to one end of the fuse 21. The other end of the fuse 21 is connected to one end of a resistor 20, and the other end of the resistor 20 is connected to a high potential power supply Vdd. The gate is connected to the interconnection point between the other end of the resistor 20 and the high potential power supply Vdd. Spare use information S stored in the fuse circuit (FUSES) is extracted from an interconnection point between one end of the resistor 20 and the other end of the fuse 21. The extracted spare use information S is supplied to the spare row decoder 17.
[0115]
The multiplexer 12 has multiplex circuits (MUX0) and (MUX1) provided for each of the row addresses A0R and A1R. Each of these multiplex circuits (MUX) has two inputs and one input, and transmits one of the two inputs to its output according to a transfer timing signal FDX. This is a so-called 2: 1 multiplex circuit. The multiplex circuit (MUX) may be constituted by a conventionally known 2: 1 multiplex circuit as in the first embodiment. One input of the multiplex circuit (MUX) is supplied with defective address information F, and the other input is supplied with a row address AR. The multiplex circuit (MUX) transmits the defective address information F to its output when the transfer timing signal FDX is at "H" level, and transmits the row address AR to its output when the transfer timing signal FDX is at "L" level. . In the device according to the second embodiment, the output of the multiplex circuit 12 is connected to the internal address line 19.
[0116]
The redundancy circuit 13 has associative memory circuits (CAM0) and (CAM1) provided for each row address pair (A0R, / A0R) and (A1R, / A1R). Each of these associative memory circuits (CAM) has a register circuit 30, a positive-phase write gate circuit 31, a comparison circuit 32, and a negative-phase write gate circuit 33.
[0117]
In the device according to the second embodiment, the register circuit 30 is constituted by a so-called cross-coupled latch circuit constituted by two inverters. Note that the register circuit 30 may be basically a flip-flop circuit having a first output and a second output having an inverted level of the first output.
[0118]
The positive-phase write gate circuit 31 has a current path connected in series between the positive-phase internal address (AR) line 19 and the positive-phase node 41 of the latch circuit, and has a gate receiving the transfer timing signal FDX. And two NMOSs 42.
[0119]
The comparison circuit 32 includes three NMOSs 46, 47, and 48. First, the NMOS 46 has one end of its current path connected to the positive-phase internal address (AR) line 19 and its gate connected to the negative-phase node 45 of the latch circuit. The NMOS 47 has one end of its current path connected to the reverse-phase internal address (/ AR) line 19, the other end connected to the other end of the current path of the NMOS 46, and the gate connected to the positive-phase node 41 of the latch circuit. Connect to Further, the NMOS 48 has one end of the current path connected to the output node N of the redundancy circuit 13 suspended at the potential MATCH, and the other end connected to the low potential power supply Vss.
[0120]
The negative phase write gate circuit 33 has a current path connected in series between the negative phase internal address (/ AR) line 19 and the negative phase node 45 of the latch circuit, and receives a transfer timing signal FDX at its gate. It is composed of one NMOS 49.
[0121]
Spare row decoder 17 has one input connected to output node N of redundancy circuit 13 and the other input has NAND gate 53 receiving spare use information S, and inverter 54 having an input connected to the output of NAND gate 53. And The output of inverter 54 is supplied to spare word line SWL. Also, the output of the NAND gate 53 is supplied to the main row decoder 15 (that is, the signal / RSP).
[0122]
Next, the operation will be described.
[0123]
FIG. 13 shows the relationship between the logic of the row address and the selected word line. FIG. 14 shows the relationship between the state of the fuse and the word line (WL) replaced with the spare word line (SWL). In FIG. 14, the fuse circuit (FUSE) in which the fuse is blown is denoted by "cut", and the fuse circuit (FUSE) in which the fuse is not blown is denoted by "no cut".
[0124]
First, an example in which the word line WL1 is replaced with a spare word line SWL will be described.
[0125]
As shown in FIG. 14, when replacing the word line WL1 with the spare word line SWL, the fuses 21 of the fuse circuits (FUSE0) and (FUSE1) shown in FIG. Blow.
[0126]
Next, the transfer timing signal FDX is set to the “H” level. At this time, the defective address information (F0), (F1), and (S) are set to the “L”, “L”, and “H” levels, respectively, and output from the defective address storage circuit 11. Based on these outputs, copy information that sets the node 41 to the “L” level is held / stored in the register circuits 30 of the associative memories (CAM0) and (CAM1) shown in FIG. According to these pieces of copy information, the NMOSs 46 of the associative memories (CAM0) and (CAM1) are turned "ON" and the NMOS 47 is turned "OFF". The “H” level is supplied to the other input of the NAND gate 53 of the spare row decoder 17. As a result, the NAND gate 53 changes the potential level of its output according to the potential level of the output node input to one input. That is, when the NAND gate 53 is activated, the spare row decoder 17 is activated.
[0127]
In this state, it is assumed that an address for setting the row addresses A0R and A1R to the "L" level is input. At this time, the levels of the row addresses A0R, / A0R, A1R, / A1R transmitted to the internal address line 19 are "L", "H", "L", "H", respectively. By these logics, the NMOSs 48 of the associative memories (CAM0) and (CAM1) are turned off. As a result, the comparison circuits 32 of the associative memories (CAM / 0) and (CAM / 1) become "non-conductive", and the potential of the output node N remains at the potential MATCH. NAND gate 53 of spare decoder 17 detects potential MATCH as "H" level. As a result, signal / RSP attains an "L" level, and spare decoder 17 deactivates main row decoder 15. At the same time, the spare word line SWL is selected and driven.
[0128]
It is also assumed that, in the above state, an address is input that sets the row address A0R to the “H” level and A1R to the “L” level. At this time, the levels of the row addresses A0R, / A0R, A1R, and / A1R transmitted to the internal address line 19 are "H", "L", "L", and "H", respectively. By these logics, the NMOSs 48 of the associative memories (CAM0) and (CAM1) are turned on and off, respectively. As a result, the comparing circuit 32 of the associative memory (CAM0) becomes “conductive”, the comparing circuit 32 of the associative memory (CAM1) becomes “non-conductive”, and the potential of the output node N becomes the comparing circuit of the associative memory (CAM0). Descend through 32. The NAND gate 53 of the spare row decoder 17 detects this lowered potential as “L” level. As a result, signal / RSP attains an "H" level, and spare decoder 17 activates main row decoder 15. At the same time, the spare word line SWL is not selected. The activated main row decoder 15 selects the word line WL2 according to the logic of the row address.
[0129]
Also, when an address is input in which the row address A0R is at the "L" level and A1R is at the "H" level, the comparison circuit 32 of the content addressable memory (CAM1) becomes "conductive" as in the above operation, and the signal is turned on. / RSP attains an "H" level. As a result, spare decoder 17 activates main row decoder 15 and does not select spare word line SWL. The main row decoder 15 selects the word line WL3 according to the logic of the row address.
[0130]
Also, when an address is input that sets both the row addresses A0R and A1R to the "H" level, the comparison circuits 32 of the associative memories (CAM0) and (CAM1) become "conductive" and the signal / RSP becomes "H". Level. Spare decoder 17 activates main row decoder 15 and does not select spare word line SWL. Then, the main row decoder 15 selects the word line WL4 according to the logic of the row address.
[0131]
When replacing any of the word lines WL2, WL3, WL4 with the spare word line SWL instead of the word line WL1, a fuse is blown as shown in FIG. Thereby, each can be replaced with a spare word line SWL.
[0132]
Further, when the replacement of the word line WL is not performed, the fuse 21 of the fuse circuit (FUSES) is not blown as shown in FIG. At this time, the spare use information S becomes "L" level. As a result, the other input of the NAND gate 53 of the spare row decoder 17 is always supplied with the “L” level, and the output of the NAND gate 53 is always “regardless of the potential level of the output node N”. H ”level. Since the output of NAND gate 53 is fixed at "H" level, signal / RSP is always at "H" level. Therefore, the main row decoder 15 selects the word line WL according to the logic of the row address.
[0133]
When the fuse 21 of the fuse circuit (FUSES) is not blown, the fuses 21 of the other fuse circuits (FUSE0) and (FUSE1) may be either blown or not blown.
[0134]
According to the redundancy circuit 13 included in the device according to the second embodiment, the content addressable memory (CAM) is provided not for each row address but for each row address pair. Therefore, the number of associative memories (CAMs) can be reduced by half as compared with the device according to the first embodiment shown in FIG. In particular, the number of register circuits 30 of the content addressable memory (CAM) is halved. For this reason, the circuit scale of the redundancy circuit 13 is reduced, the number of MOSFETs can be reduced as compared with the device according to the first embodiment shown in FIG. 4, and the redundancy circuit 13 including a content addressable memory (CAM) in a chip is provided. Occupied area can be made smaller.
[0135]
Further, since the number of associative memories (CAM) is reduced, the number of fuse circuits (FUSE) of the defective address storage circuit 11 can be reduced as compared with the device according to the first embodiment shown in FIG. Therefore, similarly to the redundancy circuit 13, the area occupied by the defective address storage circuit 11 including the fuse circuit (FUSE) can be reduced. Further, by reducing the number of fuse circuits (FUSE), the number of fuses that are difficult to miniaturize can be reduced from the chip.
[0136]
In addition, the number of defective address information F also decreases as the number of fuse circuits (FUSE) decreases. For this reason, the number of wirings for transferring the defective address information F to the content addressable memory (CAM) can be reduced. Further, by reducing the number of wirings, the number of multiplex circuits (MUX) for inputting the defective address information F to, for example, the internal address line 19 can be reduced.
[0137]
Due to these advantages, the device according to the second embodiment can obtain an effect that higher integration can be achieved than in the first embodiment.
[0138]
Next, a DRAM according to a third embodiment will be described.
[0139]
In the third embodiment, the circuit size of the defective address storage circuit 11 is to be reduced. Specifically, the defective address storage circuit 11 is shared by a plurality of sub-arrays, the number of fuse circuits (FUSE) of the defective address storage circuit 11, particularly, the number of fuses provided on one chip is reduced.
[0140]
For example, as described with reference to FIG. 2, conventionally, in a semiconductor memory having a large-scale storage capacity, a cell array is divided into several sub-arrays. This sub-array is an arbitrary unit that can be divided in a semiconductor memory. In a semiconductor memory divided into several sub-arrays as described above, a redundancy circuit and a spare row (word line) / spare column (bit line) are arranged for each sub-array. Replacement of a defective row (word line) / defective column (bit line) with a spare row / spare column is performed for each sub-array. This is a replacement method generally performed conventionally. For example, as shown in FIG. 35, in a conventional special-purpose 18M DRAM, one 2M cell array is composed of a total of eight 256k sub-arrays (horizontal 4 × vertical 2). A redundancy circuit (RFUSE) is provided for each sub-array, and a fuse is independently provided for each sub-array. In the cell array shown in FIG. 35, a total of eight fuse circuits (hereinafter, referred to as fuse blocks) are arranged. Further, in the whole chip, 8 sets × 9 = 72 fuse blocks are arranged.
[0141]
When such a typical replacement method is used in the present invention, for example, as shown in FIGS. 8 to 11, defective address storage circuits 11-SUB1 to 11-SUB8 including fuse circuits are respectively provided in subarrays SUB1 to SUB8. Set one by one.
[0142]
However, although there are variations depending on the number of sub-arrays and the stage of product development (exploration or maturity), the number of sub-arrays in which defective rows / columns occur is about 20 to 30% of the entire chip. is there. In the other 70-80% of the subarrays, no bad rows / columns have occurred and no spare rows / columns have been used. In these subarrays, the defective address storage circuit 11-SUB including the fuse circuit is not used, and is useless.
[0143]
Therefore, in the third embodiment, noting the above circumstances, the defective address storage circuit 11-SUB is not set one by one in the subarrays SUB1 to SUB8, but is shared by several subarrays. As a result, the number of defective address storage circuits 11-SUB is reduced.
[0144]
FIG. 15 is a circuit block diagram illustrating a relationship between a defective address storage circuit and a subarray included in the device according to the third embodiment.
[0145]
As shown in FIG. 15, the cell array includes eight sub-arrays SUB1 to SUB8. In the third embodiment, only one defective address storage circuit 11 is provided for eight sub-arrays SUB1 to SUB8.
[0146]
The defective address storage circuit 11 has an address fuse circuit (FUSEA) and a sub-array selection fuse circuit (FUSES). The fuse circuit for address (FUSEA) stores the defective address information F similarly to the fuse circuit (FUSE) of the device according to the first and second embodiments. The sub-array selection fuse circuit (FUSES) stores replacement information S indicating which of the eight sub-arrays SUB1 to SUB8 replaces a defective word line with a spare word line. That is, the replacement information S is information for specifying a subarray to be replaced. A transfer timing signal SFDX is supplied to each of the fuse circuits (FUSEA) and (FUSES). When the transfer timing signal SFDX becomes, for example, “H” level, the fuse circuits (FUSEA) and (FUSES) output defective address information F and replacement information S, respectively.
[0147]
Each of the sub-arrays SUB1 to SUB8 has a multiplex circuit (MUX) 12 and a redundancy circuit 13 including an associative memory, similarly to the devices according to the first and second embodiments. Further, in the third embodiment, the redundancy circuit 13 has an associative memory unit (CAMA) for addresses and an associative memory unit (CAMS) for selecting a sub-array.
[0148]
The addressable associative memory unit (CAMA) has a rewritable RAM circuit such as a register circuit, like the associative memory (CAM) of the first and second embodiments. The defective address information F is transferred from the address fuse circuit (FUSEA) to the RAM circuit, and the transferred defective address information is held / stored. The row address AR is input to the address associative memory unit (CAMA). The address associative memory unit (CAMA) holds and stores the input row address AR while the memory is operating, like the associative memory (CAM) of the first and second embodiments. Then, it is determined whether or not the input row address AR designates a defective row.
[0149]
The associative memory unit (CAMS) for selecting a sub-array has a non-rewritable ROM circuit. The sub-array number is written in the ROM circuit. The sub-array number is assigned to each sub-array, and different information is used for each sub-array. Replacement information S is input to the sub-array selection associative memory unit (CAMS) from the sub-array selection fuse circuit (FUSES). The associative memory unit for selecting a sub-array (CAMS) compares the input replacement information S with the written sub-array number during the mode of transferring the defective address information F to the associative memory unit (CAMA). It is determined whether or not the replaced information S specifies its own subarray. Further, in response to this determination result, the content addressable memory unit (CAMS) outputs a local transfer timing signal FDX to the sub-array. For example, the associative memory unit (CAMS) sets the local transfer timing signal FDX to the “H” level only when the input replacement information S specifies its own sub-array, and keeps it at the “L” level otherwise. The local transfer timing signal FDX is supplied to the multiplex circuit 12 and the associative memory unit (CAMA) for addresses in the sub-array. The multiplex circuit 12 receiving the local transfer timing signal FDX at the “H” level supplies the defective address information F to an addressable associative memory unit (CAMA). Then, the RAM circuit of the content addressable memory unit (CAMA) receiving the local transfer timing signal FDX at the "H" level changes from a non-writable mode to a writable mode. The defective address information F is written to the RAM circuit in the writable mode.
[0150]
Conversely, the multiplex circuit 12 receiving the local transfer timing signal FDX at the “L” level does not supply the defective address information F to the addressable associative memory unit (CAMA). Further, the RAM circuit of the content addressable memory unit (CAMA) receiving the local transfer timing signal FDX at the "L" level remains in the non-writable mode.
[0151]
In this way, the defective address information F is written only in the RAM circuit of the sub-array specified by the replacement information S.
[0152]
FIG. 16 is a specific circuit diagram of the redundancy circuit 13 and the row decoder shown in FIG. 15, and FIG. 17 is a specific circuit diagram of the defective address storage circuit 11 shown in FIG. Here, for simplicity, one of the eight sub-arrays is selected by one defective address storage circuit, and four words are selected from the row addresses A0R, / A0R, A1R, / A1R in the selected sub-array. A circuit for selecting the lines WL1, WL2, WL3, WL4 and one spare word line SWL will be described. Hereinafter, the configuration and operation of the circuit will be described with reference to the circuit diagram.
[0153]
As shown in FIG. 17, the defective address storage circuit 11 included in the device according to the third embodiment has a fuse circuit for address (FUSEA) and a fuse circuit for subarray selection (FUSES).
[0154]
The fuse circuit for address (FUSEA) includes fuse circuits (FUSEA0) and (FUSEA1) provided for each of the row addresses A0R and A1R, as in the second embodiment.
[0155]
The sub-array selection fuse circuit (FUSES) includes three fuse circuits (FUSES0), (FUSES1), and (FUSES2) for selecting one sub-array from the eight sub-arrays.
[0156]
First, each of the fuse circuits (FUSEA0), (FUSEA1), (FUSES0), (FUSES1), and (FUSES2) has a resistor 20, a fuse 21, and an NMOS 24 whose gate receives a transfer timing signal SFDX. The source of the NMOS 24 is connected to the low-potential power supply Vss (for example, ground potential), and the drain is connected to one end of the fuse 21. The other end of the fuse 21 is connected to one end of a resistor 20, and the other end of the resistor 20 is connected to a high potential power supply Vdd. The defective address information F0 and F1 stored in the fuse circuits (FUSEA0) and (FUSEA1) are output from the interconnection point between one end of the resistor 20 and the other end of the fuse 21. The replacement information S0, S1, and S2 stored in the fuse circuits (FUSES0), (FUSES1), and (FUSES2) are also output from the interconnection point between one end of the resistor 20 and the other end of the fuse 21.
[0157]
The defective address information F0 and F1 output from the fuse circuits (FUSEA0) and (FUSEA1) are respectively supplied to the multiplex circuits (MUX0) and (MUX1) shown in FIG. The replacement information S0, S1, and S2 output from the fuse circuits (FUSES0), (FUSES1), and (FUSES2) are supplied to a sub-array selection associative memory unit (CAMS) shown in FIG. The associative memory unit (CAMS) includes associative memory circuits (CAMS0), (CAMS1), and (CAMS2) corresponding to the replacement information S0, S1, and S2. The replacement information S0, S1, and S2 are supplied to the content addressable memory circuits (CAMS0), (CAMS1), and (CAMS2), respectively. The associative memory circuits (CAMS0) to (CAMS2) each compare the ROM circuit 70 in which the subarray number is written, and the subarray number written in the ROM circuit 70 with the input replacement information S0, S1, and S2. And a comparison circuit 71. The comparison circuit 71 includes an NMOS 73 connecting one end of a current path to the replacement information line 72, and an NMOS 74 connecting one end of the current path to the inverted replacement information line 72 -INV and connecting the other end to the other end of the current path of the NMOS 73. And an NMOS 75 having one end of a current path connected to the output node NS, the other end connected to the low potential power supply Vss, and a gate connected to an interconnection point between the current paths of the NMOS 73 and 74. Output node NS is suspended at potential MATCHS. The ROM circuit 70 stores information by supplying one of the high-potential power supply Vdd and the low-potential power supply Vss to the gates of the NMOSs 73 and 74 of the comparison circuit 71. That is, the associative memory unit (CAMS) stores the sub-array numbers by eight kinds of combinations of the power supplies Vdd and Vss input to the NMOSs 73 and 74. FIGS. 18A to 18D show the ROM circuits 70 of the sub-arrays SUB1 to SUB4, respectively. Similarly, FIGS. 19A to 19D show the ROM circuits 70 of the sub-arrays SUB5 to SUB8, respectively. FIG. 20 shows the relationship between the contents of the ROM and the subarray numbers.
[0158]
Further, the device according to the third embodiment includes a replacement information register (SREG) that holds / stores the output of the associative memory unit (CAMS), and the content held / stored in the replacement information register (SREG). A local transfer timing signal generator (FDXGEN) for generating a local transfer timing signal FDX.
[0159]
First, the register (SREG) includes a register circuit 80 and a write gate circuit 81 that writes the output of the content addressable memory unit (CAMS) to the register circuit 80 in accordance with the transfer timing signal SFDX. In the third embodiment, the register circuit 80 is constituted by a so-called cross-coupled latch circuit constituted by two inverters. The write gate circuit 81 includes a single NMOS 83 having a current path connected in series between the output node NS and the positive-phase node 82 of the latch circuit, and a gate receiving the transfer timing signal SFDX. The output of the register (SREG) is extracted from the negative node 84 of the latch circuit. The output of the register (SREG) extracted from the negative-phase side node 84 is supplied to the FDX signal generator (FDXGEN) and the spare row decoder 17 after being inverted by the inverter.
[0160]
The FDX signal generator (FDXGEN) receives a transfer timing signal SFDX at one input and receives an inverted output of a register (SREG) at the other input, and inputs an output to the output of the NAND gate circuit 91. It is constituted by the connected inverter 92. The output of the inverter 92 is supplied to the multiplex circuits (MUX0) and (MUX1) and the associative memory circuits (CAMA0) and (CAMA1). (That is, the local transfer timing signal FDX.)
The other configuration is the same as that of the second embodiment, and a description thereof will be omitted.
[0161]
Next, the operation will be described.
[0162]
FIG. 21 shows the relationship between the state of the fuse and the selected sub-array. FIG. 22 shows the relationship between the logic of the row address and the selected word line (WL). FIG. 23 shows the relationship between the state of the fuse and the word line (WL) replaced with the spare word line (SWL). In FIGS. 21 and 23, the fuse circuits (FUSEA) and (FUSES) in which the fuses are blown are denoted by "cut", and the fuse circuits (FUSEA) and (FUSES) in which the fuses are not blown are denoted by "no cut". . Hereinafter, an example will be described in which the sub-array (SUB7) is selected from the eight sub-arrays SUB1 to SUB8, and the word line WL1 of the sub-array (SUB7) is replaced with a spare word line SWL.
[0163]
As shown in FIG. 21, when the sub-array (SUB7) is selected, the fuses 21 of the fuse circuits (FUSES1) and (FUSES2) are blown without blowing the fuse 21 of the fuse circuit (FUSES0) shown in FIG. Further, when replacing the word line WL1 with the spare word line SWL, the fuses 21 of the fuse circuits (FUSEA0) and (FUSEA1) shown in FIG. 17 are not blown.
[0164]
Next, the transfer timing signal SFDX is set to the “H” level. At this time, the defective address information (F0) and (F1) are at the “L” level, and the replacement information (S2), (S1) and (S0) are at the “H”, “H” and “L” levels, respectively. Then, it is output from the defective address storage circuit 11. Based on these outputs, first, signals for setting the replacement information line 72 to "H", "H", and "L" are respectively input to the associative memories (CAMS2), (CAMS1), and (CAMS0) for subarray selection. You. By these inputs, the NMOSs 75 of the associative memories (CAMS2), (CAMS1) and (CAMS0) of the associative memory unit (CAMS) of the subarray SUB7 shown in FIG. 16 are turned off. Therefore, the output node NS of the content addressable memory unit (CAMS) of the sub-array SUB7 becomes the potential MATCHS, that is, the “H” level. In the associative memory unit (CAMS) of the other subarrays SUB1 to SUB6 and SUB8, at least one NMOS 75 of the associative memories (CAMS2), (CAMS1), and (CAMS0) is turned on. Therefore, the output nodes NS of the associative memory unit (CAMS) other than the sub-array SUB7 each fall from the potential MATCHS, and the output nodes NS go to the “L” level. As a result, only the register (SREG) of the sub-array (SUB7) stores the replacement information for setting the negative-phase node 84 to the “L” level. The FDX signal generator (FDXGEN) of the sub-array SUB7 outputs the “H” level transfer timing signal FDX based on the replacement information for setting the negative-phase node 84 to the “L” level. Further, the FDX signal generators (FDXGEN) of the other sub-arrays SUB1 to SUB6 and SUB8 output an "L" level transfer timing signal FDX based on the replacement information for setting the opposite-phase node 84 to an "H" level. As a result, the sub-array SUB7 is selected from the eight sub-arrays, and the "H" level transfer timing signal FDX is generated here.
[0165]
Further, the multiplexer 12 is supplied with a signal for setting the input on the defective address information side of each of the multiplex circuits (MUX0) and (MUX1) to the “L” level. Since the multiplexer 12 of the subarray SUB7 receives the “H” level transfer timing signal FDX, the signal input to the input on the defective address information side is transmitted to the internal address line 19. The multiplexers 12 of the other sub-arrays SUB1 to SUB6 and SUB8 receive the transfer timing signal FDX at the "L" level. In each of these multiplexers 12, the signal input to the input on the defective address information side is not transmitted to the internal address line 19.
[0166]
Of the sub-arrays SUB1 to SUB8, defective address information (F0) and (F1) are transferred from the fuse circuits (FUSEA0) and (FUSEA1) to the associative memory unit (CAMA) of the sub-array SUB7. The copy information for setting the node 41 to the "L" level is held / stored in the register circuits 30 of the associative memories (CAMA0) and (CAMA1). With these pieces of copy information, the NMOSs 46 of the associative memories (CAMA0) and (CAMA1) are turned "ON" and the NMOS 47 is turned "OFF".
[0167]
In the spare row decoder 17 of the subarray SUB7, the inverted value of the output of the register (SREG), that is, the "H" level is supplied to the other input of the NAND gate 53. Thereby, the spare row decoder 17 is activated, as in the second embodiment. On the other hand, in each of the spare row decoders 17 of the other subarrays SUB1 to SUB6 and SUB8, an inverted value of the output of the register (SREG), that is, the “L” level is supplied to the other input of the NAND gate 53. Thereby, spare row decoder 17 is deactivated.
[0168]
In this state, it is assumed that an address for setting the row addresses A0R and A1R to the "L" level is input. At this time, the levels of the row addresses A0R, / A0R, A1R, / A1R transmitted to the internal address line 19 are "L", "H", "L", "H", respectively. By these logics, the NMOSs 48 of the associative memories (CAMA0) and (CAMA1) of the sub-array SUB7 are turned off. As a result, the comparison circuits 32 of the associative memories (CAMA0) and (CAMA1) become "non-conductive", and the potential of the output node N remains at the potential MATCH. NAND gate 53 of spare row decoder 17 detects potential MATCH as "H" level. As a result, similarly to the second embodiment, the signal / RSP becomes the "L" level, and the spare row decoder 17 deactivates the main row decoder 15. At the same time, the spare word line SWL is selected and driven.
[0169]
The operation in other states of the row addresses A0R and A1R is the same as in the second embodiment, and a description thereof will be omitted.
[0170]
As described above, in the device according to the third embodiment, one defective address storage circuit 11 is shared by several sub-arrays by having the associative memory unit (CAMS) for selecting a sub-array for each sub-array. Can be. Thereby, the circuit scale of the defective address storage circuit 11 can be reduced. In particular, the number of fuse circuits (FUSE) of the defective address storage circuit 11 can be reduced, and the number of fuses provided on one chip is reduced even when the storage capacity is increased. Thus, in the device having the defective address storage circuit 11 as in the first and second embodiments, a configuration suitable for higher integration can be obtained.
[0171]
Next, a fourth embodiment of the present invention will be described.
[0172]
The fourth embodiment is another example of a method of transferring defective address information from the defective address storage circuit 11 to the redundancy circuit 13.
[0173]
In the first to third embodiments, defective address information is transferred from the defective address storage circuit 11 to the register circuit 30 of the redundancy circuit 13 via the internal address line 19, respectively.
[0174]
In the fourth embodiment, defective address information is transferred from the defective address storage circuit 11 to the register circuit 30 of the redundancy circuit 13 using a shift register circuit.
[0175]
FIG. 24 is a circuit diagram showing a redundancy circuit, a defective address storage circuit, and a shift register circuit of a semiconductor integrated circuit device according to a fourth embodiment of the present invention, and FIG. 25 is an operation waveform diagram showing a transfer operation.
[0176]
First, referring to FIGS. 24 and 25, using the shift register circuit 91, the defective address information stored in the defective address storage circuit 11 is transferred to the register circuit 30 (R0, R1, R2) of the redundancy circuit 13. The operation to be performed will be described.
[0177]
First, as shown in FIG. 25, the signals φ1 and φ2 are both set to “H” level, and the data set signal Data Set is set to “L” level. As a result, each of the nodes F0, F1, and F2 of the shift register circuit shown in FIG. 24 is initialized to “H” level. Next, after the signals φ1 and φ2 are respectively set to “L” level, the signal Data Set is set to “H” level, and the defective address information is respectively transmitted from the fuse circuits (FUSE0), (FUSE1) and (FUSES) to the respective nodes F0 and F1. , F2.
[0178]
When the fuse of the fuse circuit (FUSE0) is not blown (“No Cut”), the node F0 transitions to “L” level. Conversely, when the fuse of the fuse circuit (FUSE0) is blown ("Cut"), the node F0 maintains the "H" level. The same applies to the fuse circuits (FUSE1) and (FUSES). When the fuse is not blown (“No Cut”), the nodes F1 and F2 transition to the “L” level, and the fuse is blown. During the operation (“Cut”), the nodes F1 and F2 each maintain the “H” level. In this way, the data stored in the fuse circuits (FUSE0), (FUSE1), and (FUSES) are set in the nodes F0, F1, and F2, respectively. Next, the signal Data Set is set to the “L” level, and the nodes F0, F1, and F2 are electrically floated.
[0179]
Note that FIG. 25 shows an example of transfer when the fuse circuits (FUSE0), (FUSE1), and (FUSES) are “Cut”, “No Cut”, and “Cut”, respectively.
[0180]
After the nodes F0, F1, and F2 are electrically floated, the signals φ1 and φ2 are toggled like a two-phase clock. As a result, the data set at the node F0 is shifted in the order of the node F1 and the node F2, and finally shifted to the register circuit 30 (R0) and stored therein. Similarly, the data set at the node F1 is shifted in the order of the node F2 and the register circuit 30 (R0), and finally shifted to the register circuit 30 (R1) and stored therein. Similarly, the data set at the node F2 is shifted in the order of the register circuit 30 (R0) and the register circuit 30 (R1), and finally shifted to the register circuit 30 (R2) and stored therein. You.
[0181]
FIG. 26 shows the relationship between the logic of the row address and the selected word line in the device according to the fourth embodiment. FIG. 27 shows the relationship between the state of the fuse and the replaced word line in the device according to the fourth embodiment.
[0182]
As shown in FIGS. 26 and 27, the relationship between the logic of the row address of the device according to the fourth embodiment and the selected word line, and the relationship between the state of the fuse and the replaced word line are as follows. This is the same as the device according to the embodiment.
[0183]
Further, in the fourth embodiment, a connection method different from those of the first to third embodiments is adopted as a connection method between the redundancy circuit 13 and the spare decoder 17.
[0184]
In other words, the first to third embodiments have a configuration in which the redundancy circuit 13 and the spare decoder 17 are connected via the wiring suspended to the potential MATCH. On the other hand, the fourth embodiment has a configuration in which the redundancy circuit 13 and the spare decoder 17 are connected via the NAND gate circuit 92 to which the outputs of the two comparison circuits 32 are input.
[0185]
As described above, the outputs of the plurality of comparison circuits 32 included in the redundancy circuit 13 may be input to the logic gate circuit, and the output of the logic gate circuit may be input to the spare decoder 17.
[0186]
Next, a fifth embodiment of the present invention will be described.
[0187]
The fifth embodiment relates to the arrangement of fuses included in the defective address storage circuit 11.
[0188]
In the semiconductor integrated circuit device according to the present invention, a defective address storage circuit 11 for storing defective address information is provided in a chip separately from the redundancy circuit 13. The defective address storage circuit 11 has a PROM circuit that stores defective address information. The PROM element included in the PROM circuit is a fuse, for example, a laser blow fuse or a current blow type fuse.
[0189]
The number of fuses can be reduced as compared with other PROM elements such as a variable threshold transistor, because they do not require a write circuit. On the other hand, fuses require a very large space, generate an unwiringable area, and make wiring layout difficult.
[0190]
In order to solve such a situation, the fuse 21 of the defective address storage circuit 11 is not arranged in a region in a cell array or a region near a memory peripheral circuit as in the related art, but is separated from these regions. We are trying to place it in a place. For example, in the first embodiment, the fuse 21 of the defective address storage circuit 11 is arranged near the region 5 where the pad 4 is arranged or on the edge of the chip. Such a region is a region in which the number of circuit elements such as transistors included in an integrated circuit is smaller than that in a region in a cell array or the like. In such a region, there is room in area, and it is possible to devise the arrangement of the fuses.
[0191]
Therefore, the fifth embodiment has an object to realize a fuse arrangement in which blow errors are less likely to occur in the arrangement of fuses blown by a laser as compared with the related art.
[0192]
FIG. 28 is a diagram showing a relationship between a redundancy fuse and a moving direction of a laser beam of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. FIG. 29 is an enlarged view of the redundancy fuse of FIG. FIG. 30 is a diagram showing a relationship between a redundancy fuse and a moving direction of a laser beam of a conventional semiconductor integrated circuit device, and FIG. 31 is an enlarged view of the redundancy fuse of FIG.
[0193]
As shown in FIGS. 28 and 29, the pads 4 are where bonding wires and the like are bonded, and the pads 4 are arranged with a certain distance “d” therebetween.
[0194]
Further, a certain number of pads 4 are required for power supply, input / output, address input, control signals such as a row address strobe signal (/ RAS) and a column address strobe signal (/ CAS). Therefore, the length of the row of pads 4 is sufficiently long. Further, the number of wirings in the periphery of the pad 4 is significantly smaller than that in the region in the cell array or the region near the memory peripheral circuit. For this reason, by arranging the defective address storage circuit 11, particularly, the fuses 21 around the column of the pads 4, there is an advantage that layout restrictions are reduced when arranging the fuses 21. Further, there is an advantage that a sufficient space can be secured around the fuse 21, and the floating well 184 shown in FIG. 40 can be easily provided for each fuse 21.
[0195]
The transfer of the defective address information from the defective address storage circuit 11 may be performed only once before the memory operation, and does not require a high speed. Therefore, the defective address storage circuit 11 can be arranged around the pad 4 far from the row decoder (R / D).
[0196]
Further, in the fifth embodiment, in arranging the fuses 21 along the rows of the pads 4, the device described below is further applied. The contrivance is to arrange the fuses 21 in a line so that the long axis direction of the fuses 21 (the direction in which the blown portion extends) matches the laser movement direction 170, as shown in FIGS. It is. FIGS. 30 and 31 show a conventional example regarding the arrangement of the fuses 21. FIG. In the conventional example, the long axis direction of the fuses 21 is arranged in a line perpendicular to the laser movement direction 170. This is because there is a demand to make the row of fuses 21 compact because the fuses 21 are arranged beside the decoder. In the fuse arrangements shown in FIGS. 30 and 31, the rows of the fuses 21 are compact. On the other hand, the width "d1" of the blown portion of the fuse 21 and the blown width in the laser moving direction 170 are reduced. Since the distance "d0" between the two portions becomes smaller, if the laser moves excessively, another fuse adjacent to the blown fuse may be damaged, that is, a so-called misblow occurs. If a misblow occurs, the product will no longer be rescued, thus reducing the yield. For this reason, the blow position must be adjusted with very high precision. It takes a relatively long time to adjust the blow position with high accuracy. Therefore, speeding up of the blowing process is hindered, and production efficiency is reduced.
[0197]
The fuse arrangement shown in FIGS. 28 and 29 can solve such a problem. According to this arrangement, the width “d1” of the blown portion of the fuse 21 and the distance “d0” between the blown portions can be separated from each other. It is hard to happen. Also, the alignment accuracy of the blow position is not required as much as the apparatus shown in FIGS. Therefore, the speed of the blowing step can be increased, and the production efficiency can be increased as compared with the apparatus shown in FIGS.
[0198]
In the DRAM according to the present invention, the test for detecting the address of the defective cell is performed by setting the transfer timing signal FDX to the “L” level. The defective address information obtained by the test is recorded on the tester at any time during the test. The fuse 21 is blown according to the recorded defective address information, and the defective address information is programmed in the defective address storage circuit 11.
[0199]
Next, a sixth embodiment of the present invention will be described.
[0200]
FIG. 32 is a plan view of a 64MDRAM according to the sixth embodiment, and FIG. 33 is an enlarged plan view showing the vicinity of the 16M core shown in FIG.
[0201]
The area of the defective address storage circuit 11 where the fuse 21 is particularly arranged is not only located at the edge of the chip, but also in the DRAM employing the center pad method, for example, as shown in FIGS. May be modified so as to be arranged in the pad arrangement area 205 existing in the center. 32 and 33, the area where the fuse 21 is arranged is indicated by the reference numeral “RFUSE”. 32 and 33, reference numeral 202 indicates a 1M block of a 64MDRAM.
[0202]
Further, as shown in FIG. 33 in particular, the area where the redundancy circuit 13 including the associative memory is arranged is not set to each of the row decoders (R / D), and two row decoders adjacent to each other are set. (R / D) may be set as a shared area. In this way, by sharing the region where the redundancy circuit 13 is arranged with a plurality of row decoders (R / D) adjacent to each other, the region where the redundancy circuit 13 is arranged can be reduced from above the chip.
[0203]
In the sixth embodiment, as shown in FIG. 33 in particular, a pattern in which a region where the redundancy circuit 13 is arranged and a region where the redundancy circuit 13 is not arranged repeatedly appear for every two row decoders (R / D). ing. Although such a pattern has a low effect of reducing the chip area, other circuits can be arranged in a region where the redundancy circuit 13 is not arranged. In this area, a new circuit can be arranged, for example, when it is necessary to set a new circuit in order to enhance the function of the DRAM.
[0204]
As described above, the arrangement pattern of the sixth embodiment has an effect that a new circuit can be mounted without increasing the chip area.
[0205]
【The invention's effect】
As described above, according to the present invention, a semiconductor integrated circuit device having a redundancy circuit for storing defective address information by a volatile storage circuit has a more practical configuration. That is, a fuse for storing defective address information can be provided in the defective address storage circuit with a reduced possibility of occurrence of misblow. A semiconductor integrated circuit device can be provided.
[0206]
Further, the size of a circuit for storing the basic information given to the volatile storage circuit can be reduced, and a semiconductor integrated circuit device having a configuration suitable for higher integration can be provided.
[0209]
Further, it is possible to provide a semiconductor integrated circuit device in which a defective address storage circuit can be provided in a semiconductor chip without hindering high integration of an integrated circuit and multilayer wiring.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention.
FIG. 2 is a plan view of the 2M cell array shown in FIG.
FIGS. 3A and 3B are diagrams showing the 256k subarray shown in FIG. 1 and its periphery, FIG. 3A is a diagram showing the configuration, FIG. 3B is a diagram showing an address buffer, and FIG. FIG. 4 illustrates an address storage circuit.
FIG. 4 is a circuit diagram showing a redundancy circuit and a defective address storage circuit of the semiconductor integrated circuit device according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating a relationship between logic of a row address and a selected word line;
FIG. 6 is a diagram showing a relationship between a state of a fuse and a word line to be replaced;
7A and 7B are diagrams showing a structure of the redundancy circuit according to the first embodiment of the present invention, wherein FIG. 7A is a plan view of the redundancy circuit and its vicinity, and FIG. 7B is a diagram of FIG. Sectional drawing which follows the 7A-7A line of FIG.
FIG. 8 is a block diagram showing a first relationship between a defective address storage circuit and a subarray of the semiconductor integrated circuit device according to the first embodiment of the present invention.
FIG. 9 is a block diagram showing a second relationship between the defective address storage circuit and the sub-array of the semiconductor integrated circuit device according to the first embodiment of the present invention.
FIG. 10 is a block diagram showing a third relationship between the defective address storage circuit and the sub-array of the semiconductor integrated circuit device according to the first embodiment of the present invention.
FIG. 11 is a block diagram showing a fourth relationship between the defective address storage circuit and the sub-array of the semiconductor integrated circuit device according to the first embodiment of the present invention.
FIG. 12 is a circuit diagram showing a redundancy circuit and a defective address storage circuit of a semiconductor integrated circuit device according to a second embodiment of the present invention.
FIG. 13 is a diagram illustrating a relationship between logic of a row address and a selected word line;
FIG. 14 is a diagram showing a relationship between a state of a fuse and a word line to be replaced;
FIG. 15 is a block diagram showing a relationship between a defective address storage circuit and a sub-array of a semiconductor integrated circuit device according to a third embodiment of the present invention.
FIG. 16 is a circuit diagram showing a redundancy circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention.
FIG. 17 is a circuit diagram showing a defective address storage circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention.
FIGS. 18A to 18D are circuit diagrams showing a ROM circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention.
FIGS. 19A to 19D are circuit diagrams each showing a ROM circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention.
FIG. 20 is a diagram showing the relationship between the contents of a ROM and subarray numbers.
FIG. 21 is a diagram showing a relationship between a state of a fuse and a selected sub-array.
FIG. 22 is a diagram showing a relationship between a logic of a row address and a selected word line;
FIG. 23 is a diagram showing a relationship between a state of a fuse and a word line to be replaced;
FIG. 24 is a circuit diagram showing a redundancy circuit, a defective address storage circuit, and a transfer circuit of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.
FIG. 25 is an operation waveform diagram showing a transfer operation of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.
FIG. 26 is a diagram showing a relationship between a logic of a row address and a selected word line;
FIG. 27 is a diagram showing a relationship between a state of a fuse and a word line to be replaced;
FIG. 28 is a diagram showing a relationship between a fuse for redundancy and a moving direction of a laser beam in a semiconductor integrated circuit device according to a fifth embodiment of the present invention.
FIG. 29 is an enlarged view of the redundancy fuse of FIG. 28;
FIG. 30 is a diagram showing a relationship between a fuse for redundancy and a moving direction of a laser beam in a conventional semiconductor integrated circuit device.
FIG. 31 is an enlarged view of the redundancy fuse of FIG. 30;
FIG. 32 is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.
FIG. 33 is a plan view of the 16M core block shown in FIG. 32;
FIG. 34 is a plan view of a conventional semiconductor integrated circuit device.
FIG. 35 is a plan view of the 2M cell array shown in FIG. 34;
36 is a diagram showing the 256k sub-array shown in FIG. 34 and its periphery, FIG. 36 (A) is a diagram showing the configuration, and FIG. 36 (B) is a diagram showing an address buffer.
FIG. 37 is a circuit diagram showing a conventional redundancy circuit.
FIG. 38 is a diagram showing a relationship between a logic of a row address and a selected word line;
FIG. 39 is a diagram showing a relationship between a state of a fuse and a word line to be replaced;
40A and 40B are diagrams showing the structure of a conventional redundancy circuit. FIG. 40A is a plan view of the redundancy circuit and its vicinity, and FIG. FIG.
FIG. 41 is a diagram showing another conventional semiconductor integrated circuit device.
[Explanation of symbols]
1 ... chips,
2 ... 2M cell array,
3 ... 1M cell array,
4 ... pad,
5 ... Area where pads are arranged,
6 ... 256k subarray,
7 ... Area where the sense amplifier, equalizer and column gate are arranged,
8. An area where a row decoder and a redundancy circuit are arranged,
11: defective address storage circuit,
12 multiplex circuit,
13 ... redundancy circuit,
14 ... address buffer,
15: Main row decoder,
16 ... regular part,
17 Spare row decoder,
18 ... spare part,
19 ... internal address line,
20 ... resistance,
21 ... Fuse,
22 ... NMOS,
24 ... NMOS,
30 ... register circuit,
31 ... write gate circuit (positive-phase side write gate circuit),
32 ... Comparison circuit,
33 ... Negative phase side write gate circuit,
60 ... wiring,
61 ... selector,
70 ... ROM circuit,
71 ... Comparison circuit,
72 ... replacement information line,
80 ... register circuit,
81 Write gate circuit,
181 ... P-type silicon substrate,
182 ... P-type well,
183 ... N-type well,
201 ... chips,
202 ... 1M block,
204 ... pad,
205: Area where pads are arranged.

Claims (8)

A semiconductor chip having a memory function;
A memory cell array provided in the chip and including a main row / column and a spare row / column;
A defective address storage circuit provided in the chip and storing defective address information in the main row / column by a nonvolatile storage circuit;
A redundancy circuit that is provided in the chip and stores, by a volatile storage circuit, copy information of the defective address information stored in the defective address storage circuit; and An address decoder including a circuit for selecting a row / column, and a circuit for spare selection for selecting the spare row / column instead of the main row / column in accordance with the copy information stored in the redundancy circuit;
A transfer circuit provided in the chip, for transferring the defective address information stored in the defective address storage circuit to a volatile storage circuit of the redundancy circuit according to a transfer timing signal,
The defective address storage circuit has a plurality of fuse elements for storing defective address information, and each of these fuse elements has its major axis direction aligned with a direction in which a laser for blowing the fuse element moves. A semiconductor integrated circuit device which is arranged. The defective address storage circuit includes between the power supply, resistors connected in series with each other, the fuse element, and a fourth insulated gate FET for receiving the transfer timing signal to the gate,
Except when the transfer timing signal specifies a mode for transferring the defective address information, a fourth insulated gate FET is turned off, and the defective address storage circuit is deactivated. The semiconductor integrated circuit device according to claim 1 . The redundancy circuit includes:
A register circuit for storing the copy information as a volatile storage element;
A comparison circuit that compares the potential level of the copy information with the potential level of the address input and changes the input level to the spare selection circuit according to whether the potentials match or mismatch. 3. The semiconductor integrated circuit device according to claim 1, wherein: The redundancy circuit is connected to an input of the spare selection circuit via a wiring suspended at a matching potential,
The comparing circuit compares the potential level of the copy information with the potential level of the address input, and changes the potential of the wiring to a potential other than the matching potential in accordance with one of the coincidence and the non-coincidence. 4. The semiconductor integrated circuit device according to claim 3 , wherein said device is changed. The register circuit and the comparison circuit are configured by MOSFETs,
When the register circuit and the comparison circuit include N-channel MOSFETs, these N-channel MOSFETs are formed in a well where the N-channel MOSFETs of the address decoder are formed;
When the register circuit and the comparison circuit comprises a P-channel MOSFET, these P-channel type MOSFET according to claim 3, characterized in that P-channel MOSFET of said address decoder is formed in a well formed 5. The semiconductor integrated circuit device according to claim 4 . The transfer timing signal, with the power of the semiconductor integrated circuit device is turned on as a trigger, designates a mode for transferring the defective address information,
Wherein after terminating the copy of the defective address information to a redundancy circuit, a semiconductor integrated according to claim 1 or any one of claims 5, characterized in that to release the designation of the mode for transferring the defective address information Circuit device. A semiconductor chip having a memory function;
A cell array provided in the chip;
A plurality of sub-arrays set in the cell array, each including a main row / column and a spare row / column;
A defective address storage circuit provided in the chip, for storing defective information of the sub-array and defective address information in the main row / column by a nonvolatile storage circuit, respectively;
A redundancy circuit provided in the chip, for storing sub-array information by a non-volatile storage circuit, and for storing copy information of the defective address information stored in the defective address storage circuit by a volatile storage circuit;
A circuit provided in the chip for selecting the main row / column in accordance with an address input; and replacing the spare row / column with the main row / column according to the copy information stored in the redundancy circuit. An address decoder including a spare selection circuit for selecting
The sub-array information provided in the chip is compared with the sub-array defect information stored in the defective address storage circuit and the sub-array information stored in the redundancy circuit in accordance with a transfer timing signal. As a result of the comparison, the redundancy A semiconductor integrated circuit device, comprising: a transfer circuit that transfers the defective address information to a volatile storage circuit of the redundancy circuit of the subarray that matches the defect information of the subarray among the circuits. The defective address memory circuit, a semiconductor integrated circuit device according to any one of claims 1 to claim 7, characterized in that it is arranged along a column of pads.

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