JPH117793A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a more practical constitution in a semiconductor integrated circuit device comprising a redundancy circuit containing a volatile memory circuit. SOLUTION: An integrated circuit device is provided with a memory cell array 6 which contains a regular part 16 and a spare part 18, with a defective address memory circuit 11 in which defective address information F in the regular part 16 is stored, with a redundancy circuit 13 in which copied information on the defective address information F is stored by a volatile memory circuit, with a main loader decoder 15 which selects the row of the regular part 16 according to an address input AR, with a spare loader decoder 17 which selects the row of the spare part 18 instead of the row of the regular part 16 according to the copied information stored in the redundancy circuit 13, and with a multiplexing circuit 12 by which the defective address information F is transferred to the redundancy circuit 13 according to a transfer timing signal FDX.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a redundancy technique for replacing a normal row / column containing a defective memory cell with a spare row / column.

[0002]

2. Description of the Related Art Recently, it has become more and more difficult to operate all-bit cells due to the increase in memory capacity and miniaturization of cells. In the current memory, a redundancy circuit is provided internally, and among the normal rows / columns, those containing defective cells are replaced with spare rows / columns. I am getting it. This is a so-called redundancy technology.

The redundancy circuit includes a PROM (Progra
mmble ROM) circuit, in which information indicating a defective address is written. The written information is PRO
It is stored in the M circuit. The redundancy circuit selects a spare row / column instead of a row / column containing a defective cell in accordance with the information stored in the PROM circuit. P
There are various types of PROM elements constituting a ROM circuit, and a fuse is widely used in a dynamic RAM (hereinafter referred to as DRAM). The fuse stores information depending on whether it is blown. The blow of the fuse is generally performed by laser fusing or current fusing.

Hereinafter, a conventional example of a redundancy circuit will be described using a special-purpose DRAM. FIG. 34 is a schematic plan view of a conventional special-purpose 18MDRAM chip, and FIG.
FIG. 5 is a schematic plan view of the 2M cell array shown in FIG.

As shown in FIG. 34, an 18M DRAM chip 101 is provided with eight 2M cell arrays 102 and two 1M cell arrays 103. The 2M cell array 102 has a right side (RIGHT) and a left side (LEFHT) of the chip 101.
T) Four of each are arranged, and the 1M cell array 103 is
One is arranged on each of the right side (RIGHT) and the left side (LEFT).
This achieves a storage capacity of 18M. Chip 10
A pad 104 serving as a contact between the inside and the outside of the chip 1 is arranged along the edge of the chip 101. 18 MDR shown here
Since the use of AM is special, the area 105 where the pad 104 is arranged does not follow each of the four sides of the chip 101,
It is set along three sides. The chip 101 having such a special pad arrangement is, for example, a VSMP (Vertical
It is housed in a vertical package such as SurfaceMount Package.

As shown in FIG. 35, in the 2M cell array, a total of eight 256k sub-arrays 106 are provided on the upper side (TOP) and the lower side (BOTTOM) of the chip 101, respectively.
It is included. Each subarray 106 is formed with a word line extending in the X direction and a bit line extending in the Y direction. Further, in each sub-array 106, a dynamic memory cell including a storage capacitor and a transfer transistor connecting the capacitor to a bit line is formed (neither is shown). The transfer transistor has a gate connected to the word line, a drain connected to the bit line, and a source connected to the storage capacitor. In a region 107 between each sub-array 106, a sense amplifier (S / A) for amplifying a potential difference between a pair of bit lines, an equalizer (EQL) for precharging and equalizing a potential difference between a pair of bit lines, a selected bit line A circuit connected to the bit line pair such as a column gate (CG) connecting the pair to the data line is arranged. In particular, the sense amplifier is of a shared type shared by the left and right sub-arrays 106.

The row decoder (R / D) is arranged in an area 108 between the 256k sub-array 106 arranged on the upper side (TOP) of the chip 101 and the 256k sub-array 106 arranged on the lower side (BOTTOM). .

[0008] 18MDRA having such a layout
In M, redundancy circuit including fuse (RFUSE)
Are arranged in the same region 108 as the row decoder (R / D). Thus, the redundancy circuit is arranged near the row decoder. This is because the redundancy circuit becomes a critical path that determines the time from the input of the row address to the activation of the spare row decoder. That is, by arranging the redundancy circuit near the row decoder, the time difference between the time required to activate the main row decoder and the time required to activate the spare row decoder is reduced.

FIGS. 36A and 36B are schematic circuit block diagrams of a 256k sub-array. Hereinafter, an outline of the redundancy operation will be described with reference to a circuit block diagram.

First, as shown in FIG. 36B, an address signal A is input to a pad 104. The input address signal A is input to the address buffer 114. An address buffer activation signal (corresponding to the / RAS signal in a general DRAM) is supplied to the address buffer 114.
Becomes active level, the address signal A
Is output from the address buffer 114 as an internal address signal (hereinafter, row address) AR. The row address signal AR is input to a redundancy circuit (RFUSE) 111 shown in FIG.
(R / D) is input to the main row decoder 115. The main row decoder 115 selects and drives the word line (WL) arranged in the normal portion 116 of the 256k sub-array 106 according to the logic of the input row address signal AR. If the logic of the input row address signal AR is to select a defective row (defective word line) of the normal portion 116, the output level of the output node N of the redundancy circuit 111 is inverted and the spare row is inverted. The input level to the decoder 117 is inverted. At this time, the spare row decoder 117 selects and drives the spare word line (SWL) arranged in the spare portion 118 of the 256k sub-array 106. At the same time, the level of the output signal / RSP to the main row decoder 115 is inverted. The function of decoding the row address of the main row decoder 115 is inactive while the level of the output signal / RSP is inverted.

FIG. 37 is a specific circuit diagram of the redundancy circuit 111. Here, for the sake of simplicity, four word lines WL1, WLA, and A4R, / A0R, A1R, / A1R
A circuit for selecting WL2, WL3, WL4 and one spare word line SWL is shown.

First, the configuration of the circuit will be described.

As shown in FIG. 37, the redundancy circuit 1
11 is a fuse circuit (FUSE0), (FUSE / 0), (FUSE1) corresponding to each row address A0R, / A0R, A1R, / A1R.
, (FUSE / 1). Each of these fuse circuits is an N-channel type M receiving a row address at its gate.
OSFET (hereinafter, NMOS) 120 and fuse 12
And 2. The source of the NMOS 120 is connected to the low potential power supply Vss (for example, ground potential), and the drain is connected to the output node N via the fuse 122. Spare row decoder 117 includes inverter 124 having an input connected to output node N, and inverter 1
And an inverter 125 whose input is connected to 24 outputs. Further, a P-channel MOSFE having a gate receiving the output of the inverter 124, a source receiving the high potential power supply Vdd, and a drain connected to the input of the inverter 124.
T (hereinafter referred to as PMOS) 126. The output of the inverter 124 is the signal / RSP, and the main row decoder 1
15 is supplied. The output of the inverter 125 is the signal RSP
And supplied to the spare word line SWL.

Next, the operation will be described.

First, the case where the fuse 122 is not blown will be described. At this time, the row address A0R,
When each of / A0R, A1R, and / A1R becomes "H" level, N
MOS 120 conducts, and the potential of output node N is discharged to "L" level. When the potential of output node N attains "L" level, the output of inverter 124 attains "H" level, and signal / RSP attains "H" level.
When the signal / RSP goes to "H" level, one of the inputs of the NAND gates 127 included in the main row decoder 115 goes to "H" level, and all the NAND gates 1
27 is activated. Thereby, the function of decoding the row address of the main row decoder 115 is activated. NAND gate 1 in which all inputs are at "H" level
In the case of 27, the output becomes "L" level to select and drive the word line (WL). FIG. 38 shows the relationship between the row address level and the selected word line. Further, since the output of inverter 125 attains an "L" level, spare word line (SWL) is not selected.

When the fuse 122 is blown, the N connected to the blown fuse 122
The MOS 120 does not discharge the potential of the output node N even when the “H” level row address is supplied. Therefore, the potential of the output node N remains at the “H” level (for example, the precharge potential). When the potential of output node N is at "H" level, the output level of inverter 124 of spare row decoder 117 attains "L" level, and signal / RSP attains "L" level. As a result, NAND gate 12 included in main row decoder 115
7, one of the inputs goes to the "L" level, and the outputs of all the NAND gates 127 go to the "H" level regardless of the level of the row address. Thereby, the function of decoding the row address of the main row decoder 115 becomes inactive. At the same time, the output of the inverter 125 becomes "H" level, and the spare word line (SWL) is selected and driven. FIG. 39 shows the blow state of the fuse 122 and the word line replaced with the spare word line (SWL).
(WL). In FIG. 39, fuse 1
“Cut” to the blown fuse circuit (FUSE) 22 and the fuse circuit (FUSE) where the fuse 122 is not blown
To “no cut”.

FIG. 40A is a schematic plan view of the fuse and its vicinity, and FIG. 40B is a plan view of the fuse in FIG.
It is sectional drawing along the 40B-40B line.

As shown in FIGS. 40A and 40B, a P-type silicon substrate 181 has P-type wells 182-1 and 182-2 biased at a potential Vss, and an N-type well biased at a potential Vdd. Wells 183 and N-type wells 184-1 to 184-n separated from these wells and having a floating potential are formed. In each of the P-type wells 182-1 and 182-2 and the N-type well 183, an NMOS and a PMOS constituting a row decoder and a peripheral circuit (for example, a sense amplifier driving circuit) are formed. The fuses 122-1 to 122-n are formed on the N-type wells 184-1 to 184-n via a thick insulating film such as a field oxide film 185, respectively. The fuses 122-1 to 122-n are connected to the N-type well 1
84-1 to 184-n are provided one by one. When the fuse 122 is blown, a hole reaching the substrate 181 may be formed in the field oxide film 185 due to the impact. If there is a piece of fuse 122 in this hole,
When conductive particles enter, wiring and substrate 1
81 is short-circuited. In such circumstances, Hughes 1
Each of the 22 has a floating N-type well 184.
Is eliminated by providing. That is, the fuse 122
Even if fragments of the semiconductor device enter the holes formed in the field oxide film 185, the short circuit between the wiring and the substrate 181 is prevented by the floating N-type well 184.

[0019]

The progress of miniaturization of fuses depends on the accuracy of a laser blower. Even if the fuse is miniaturized, it is meaningless unless the laser blower can blow the miniaturized fuse accurately. For this reason, miniaturization of fuses requires MOSFETs.
It does not match the pace of miniaturization of other semiconductor devices.
For this reason, the difference between the size of the fuse and the size of another semiconductor element is expanding. In particular, in the row / column decoder of the DRAM, it is required that the element pattern be formed densely in accordance with the arrangement pitch of the memory cells.

Further, the absolute number of defective memory cells increases as the storage capacity increases. Naturally, the number of fuses must be increased in order to rescue the increasing number of defective memory cells. As the number of fuses increases, the circuit scale of the redundancy circuit including the fuses also increases.

As described above, as memory cells are miniaturized at the current pace and storage capacity increases, there is a possibility that fuses will eventually hinder high integration.

Since the fuse is blown, nothing can be placed on the fuse. Despite the fact that multi-layer wiring technology has greatly increased the degree of freedom in wiring layout at present, wiring is avoided over fuses.
The restriction has arisen.

A technique has also been reported in which a fuse is replaced with another PROM element, for example, a floating gate type MOSFET used for a memory cell of an EEPROM. In this type of circuit, since there is no fuse, the problem of the redundancy circuit having the fuse is solved. However, a write circuit for writing information of a defective address, a write power supply, and a write wiring are required. For this reason, considering the future increase in integration density, it is not realistic. Further, when the semiconductor memory device is a DRAM, there is no commonality in the manufacturing process, and the manufacturing cost is likely to increase.

A semiconductor integrated memory which solves such a situation is disclosed in Japanese Patent Application Laid-Open No. Hei 4-263199. FIG.
FIG. 1 is a simplified block diagram of the semiconductor integrated memory.

In the semiconductor integrated memory disclosed in Japanese Patent Application Laid-Open No. 4-263199, a PROM element using a fuse or the like is removed from a chip, and a content addressable memory (Contentional memory) is used instead.
ts Addressable Memory (CAM).

In a redundancy circuit having an associative memory, information on a defective address is input from outside the chip before operating the memory, and the information is transferred to the RA of the associative memory.
It is held in the M circuit. When the memory is running,
The address held in the RAM circuit is compared with the address input from the address line, and only when they match,
A spare memory cell array is accessed.

This type of redundancy circuit has neither a fuse nor a floating gate type MOSFET. Therefore, any of the above problems can be solved. However, in this type of redundancy circuit, it is necessary to write defective address information to the RAM circuit before operating the memory. Therefore, test the memory cells,
A test circuit for detecting the address of a defective memory cell must be provided externally as a system. Alternatively, a dedicated self-test circuit must be provided in the chip separately from the associative memory. Usually, such a test is performed by inspecting many items using a memory tester, and is not a simple test. Therefore, it is difficult to provide such a self-test circuit in a chip. The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide a more practical configuration in a semiconductor integrated circuit device having a redundancy circuit for storing defective address information by a volatile storage circuit. It is to provide a semiconductor integrated circuit device having the following.

A second object of the present invention is to achieve the first object and to reduce the scale of a circuit for storing the basic information to be provided to the volatile storage circuit, so as to be suitable for further high integration. It is to provide a semiconductor integrated circuit device having the following.

A third object of the present invention is to provide a semiconductor integrated circuit device having a configuration suitable for further increasing the integration by reducing the scale of an integrated circuit type storage circuit included in the redundancy circuit.

A fourth object of the present invention is to provide a semiconductor integrated circuit device in which a fuse for storing defective address information can be provided in a defective address storage circuit according to the present invention with a reduced possibility of occurrence of misblow. To provide.

A fifth object of the present invention is to provide a defective address storage circuit included in the semiconductor integrated circuit device according to the present invention.
It is an object of the present invention to provide a semiconductor integrated circuit device which can be provided on a semiconductor chip without hindering high integration of an integrated circuit and multilayer wiring.

[0032]

According to a first aspect of the present invention, there is provided a semiconductor chip having a memory function, and a main row / column and a spare provided in the chip. A memory cell array including rows / columns, a defective address storage circuit provided in the chip, and defective address information in the main row / column stored by a nonvolatile storage circuit; and a defective address storage circuit provided in the chip. A redundancy circuit for storing, by a volatile storage circuit, copy information of the defective address information stored in the defective address storage circuit, and a circuit provided in the chip for selecting the main row / column according to an address input , And according to the copy information stored in the redundancy circuit,
An address decoder including a spare selection circuit for selecting a column by changing the column to the main row / column; and the defective address information provided in the chip and stored in the defective address storage circuit in accordance with a transfer timing signal And a transfer circuit for transferring the data to the volatile storage circuit of the redundancy circuit.

According to the first aspect of the present invention, defective address information is stored in a defective address storage circuit provided in a chip, and the stored defective address information is stored in a volatile circuit of a redundancy circuit in accordance with a transfer timing signal. Since the data is transferred to the storage circuit, the defective address information can be easily copied to the volatile storage circuit. Therefore, a semiconductor integrated circuit device having a configuration that can be more practically used can be provided as compared with a semiconductor integrated circuit device having a redundancy circuit including a known volatile memory circuit.

According to a second aspect of the present invention, in the first aspect of the present invention, the defective address storage circuit includes, as the nonvolatile storage element, a fuse element that can be cut by either a laser beam or a current. Features.

According to the second aspect of the present invention, since the defective address storage circuit includes the fuse element, the defective address storage circuit can be formed by a manufacturing process substantially similar to a manufacturing process of a semiconductor integrated circuit device having a current fuse. Therefore, it is possible to provide a semiconductor integrated circuit device having a structure capable of realizing the invention according to claim 1 without largely changing the design of a current semiconductor integrated circuit device, particularly, a manufacturing process.

According to a third aspect of the present invention, in the second aspect of the present invention, the defective address storage circuit comprises a resistor, a fuse element,
And a fourth insulated gate FET that receives the transfer timing signal at its gate, except when the transfer timing signal specifies a mode for transferring the defective address information. And turning off the defective address storage circuit.

According to the third aspect of the present invention, the fourth insulated gate type FET included in the defective address storage circuit is used only when the transfer timing signal specifies the mode for transferring the defective address information. Since it can be turned on, current consumption consumed by the defective address storage circuit can be reduced. Therefore, according to the first or second aspect of the present invention, it is possible to provide a semiconductor integrated circuit device having a configuration capable of reducing current consumption, and particularly having a configuration that can be more practically used from the viewpoint of current consumption. it can.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the redundancy circuit includes a register circuit for storing the copy information as a volatile storage element. A comparison circuit that compares a potential level of the copy information with a potential level of the address input, and changes an input level to the spare selection circuit according to whether the potentials match or mismatch. It is characterized by the following.

According to the fourth aspect of the present invention, the potential level of the copy information is compared with the potential level of the address input. Since the input level is changed, the spare selection circuit can detect whether or not the copy information stored in the register circuit indicates a defective address.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the redundancy circuit is connected to an input of the spare selection circuit via a wiring suspended to a matching potential, The comparing circuit compares the potential level of the copy information with the potential level of the address input, and changes the potential of the wiring to a potential other than the matching potential in accordance with one of these potentials. It is characterized by changing.

According to the fifth aspect of the present invention, the spare selecting circuit determines whether or not the copy information stored in the register circuit indicates a defective address by determining whether the input potential is a matching potential. No, it can be detected. For this reason,
The spare selection circuit selects a spare row / column by changing the spare row / column to the main row / column only when the input potential changes to a potential other than the matching potential (or conversely, the main row / column is switched). Selection is made in place of the spare row / column). For this reason, for example, it is determined whether the potential shifted from the precharge potential is the “H” level or the “L” level, and then compared with a spare selection circuit that switches between the spare and the main, the switching operation thereof is further improved. Can be done at high speed.

According to a sixth aspect of the present invention, in any one of the fourth and fifth aspects, the register circuit and the comparison circuit are constituted by MOSFETs, and the register circuit and the comparison circuit are N-channel. Including these MOSFETs, these N-channel MOS
FET is an N-channel type MOS of the address decoder.
When the register circuit and the comparison circuit include P-channel MOSFETs formed in a well where an FET is formed, these P-channel MOSFETs are formed in a well where the P-channel MOSFET of the address decoder is formed. It is characterized by having.

According to the sixth aspect of the present invention, the register circuit and the comparison circuit are constituted by MOSFETs, and the register circuit and the comparison circuit are formed in the same well as the MOSFET constituting the address decoder. As a result, the area occupied by the redundancy circuit according to the fourth and fifth aspects of the present invention on the chip can be reduced, and the redundancy circuit can be more compactly integrated on the chip.

According to a seventh aspect of the present invention, in the first aspect of the present invention, the transfer timing signal is triggered by turning on the semiconductor integrated circuit device. A mode for transferring the defective address information is specified, and after the copying of the defective address information to the redundancy circuit is completed, the mode for transferring the defective address information is released.

According to the seventh aspect of the present invention, the defective address information stored in the defective address storage circuit can be transferred to the volatile storage circuit of the redundancy circuit every time the semiconductor integrated circuit device is powered on. . Accordingly, it is possible to realize an example of obtaining a state in which the defective address information is stored in the volatile storage circuit according to the first to sixth aspects of the present invention while being supplied to the semiconductor integrated circuit device.

In order to achieve the second object, in the invention according to claim 8, a semiconductor chip having a memory function, a cell array provided in the chip, and a plurality of cells set in the cell array are provided, each of which is a main memory. A sub-array including a row / column and a spare row / column; and a defective address provided in the chip and storing defective information of the sub-array and defective address information of the main row / column in a nonvolatile storage circuit. A memory circuit, and a redundancy circuit provided in the chip for storing sub-array information by a nonvolatile memory circuit and storing, by a volatile memory circuit, copy information of the defective address information stored in the defective address memory circuit Provided in the chip, and the main An address decoder including a circuit for selecting a row / column, and a circuit for selecting a spare for selecting the spare row / column by replacing the spare row / column with the main row / column according to the copy information stored in the redundancy circuit; The defect information of the sub-array provided in the chip and stored in the redundancy circuit according to a transfer timing signal is compared with the sub-array information stored in the redundancy circuit. As a result of the comparison, the redundancy is determined. In the circuit, a transfer circuit for transferring the defective address information to a volatile storage circuit of the redundancy circuit of the sub-array that matches the defective information of the sub-array is provided.

According to the eighth aspect of the present invention, the defective address information is transferred to the volatile storage circuit of the redundancy circuit of the sub-array that matches the defect information of the sub-array among the redundancy circuits. Therefore, the defective address storage circuit can be shared by several sub-arrays, the size of the defective address storage circuit can be reduced, and a semiconductor integrated circuit device suitable for higher integration can be obtained.

In order to achieve the third object, in the invention according to claim 9, a memory cell array provided in the chip and including a main row / column and a spare row / column is provided in the chip. A redundancy circuit provided in the chip, wherein a defective address information in the main row / column is set as information corresponding to an address pair and stored by a flip-flop type storage circuit provided for each address pair; A circuit for selecting the main row / column in accordance with an address input; and a spare selecting circuit for selecting the spare row / column instead of the main row / column in accordance with the copy information stored in the redundancy circuit. And an address decoder including a circuit.

Conventionally, defective address information is stored in a redundancy circuit as information corresponding to an address and its inverted address one by one. For this reason, for example, a fuse that stores defective address information is:
The address is provided for each of the address and its inverted address. In such a storage method for storing defective address information, when the means for storing defective address information is replaced with an integrated circuit type storage circuit, the number of storage circuits increases and the scale of the redundancy circuit increases. There is.

According to the ninth aspect of the present invention, the redundancy circuit is provided for each address pair as information in which the defective address information in the main row / column is associated with the address pair. The problem was solved by storing the data in a flip-flop type storage circuit.

According to the ninth aspect of the present invention, defective address information is stored in association with an address pair consisting of an address and its inverted address. Therefore, the size of the circuit can be reduced by almost half as compared with a storage method in which defective address information is stored in correspondence with an address and its inverted address one by one. As a result, the size of the redundancy circuit can be reduced, and a semiconductor integrated circuit device suitable for higher integration can be obtained.

In order to achieve the fourth object, in the invention according to claim 10, in the invention according to any one of claims 1 to 8, the defective address storage circuit may include:
A plurality of fuses for storing the defective address information are provided, and each of the fuses is arranged so that a major axis direction thereof coincides with a direction in which a laser for blowing the fuse moves.

According to the tenth aspect, by arranging the long axis direction of the fuse so as to coincide with the direction in which the laser for blowing moves, the length of the blown portion of the fuse, and The interval between the blown portions can be made sufficiently large. For this reason, it is possible to reduce the occurrence of misblow in the fuse storing the defective address information.

In order to achieve the fifth object, the invention according to claim 11 is characterized in that the defective address circuits are arranged along a row of pads.

According to the eleventh aspect of the present invention, by arranging the defective address circuits along the rows of the pads, high integration of an integrated circuit, for example, a memory cell array, etc., and multilayer wiring are prevented. It can be provided without.

[0056]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. In this description, common parts are denoted by common reference symbols throughout the drawings.

FIG. 1 is a schematic plan view of a special-purpose 18MDRAM chip according to the first embodiment of the present invention, and FIG. 2 is a schematic plan view of the 2M cell array shown in FIG. As shown in FIG. 1, the 18MDRAM chip 1 includes:
Eight 2M cell arrays 2 and two 1M cell arrays 3
Is provided. Four 2M cell arrays 2 are arranged on each of the right side (RIGHT) and the left side (LEFT) of the chip 1, and 1M
One cell array 3 is arranged on each of the right side (RIGHT) and the left side (LEFT). This achieves a storage capacity of 18M. A pad 4 serving as a contact point with the outside of the integrated circuit formed on the chip 1 is arranged along the edge of the chip 1.
Since the use of the 18MDRAM shown here is special, the region 5 where the pad 4 is arranged is set not along each of the four sides of the chip 1 but along three sides. The chip 1 having such a special pad arrangement is, for example, a VSMP (Ver.
(Surface Mount Package).

As shown in FIG. 2, the 2M cell array 2 has the upper side (TOP) and the lower side (BOTTOM) of the chip 1 respectively.
A total of eight 256k sub-arrays 6 are included, four each. In each subarray 6, a word line (WL) (not shown) extending in the X direction and a bit line (BL) not shown extending in the Y direction are formed. Further, each sub-array 6 includes:
A dynamic memory cell (M) including a storage capacitor (not shown) and a transfer transistor (not shown) for connecting the capacitor to a bit line is formed. The transfer transistor has a gate connected to the word line, a drain connected to the bit line, and a source connected to the storage capacitor. In a region 7 between the sub-arrays 6, a sense amplifier (S / A) for amplifying the potential difference between the bit line pairs, an equalizer (EQL) for precharging and equalizing the potential difference between the bit line pairs, a selected bit line Data line (DQ) pair
A circuit connected to the bit line pair, such as a column gate (CG) connected to the bit line, is arranged. In particular, the sense amplifier is of a shared type shared by the left and right sub-arrays 6. The row decoder (R / D) is arranged in an area 8 between the subarray 6 arranged on the upper side (TOP) of the chip 1 and the subarray 6 arranged on the lower side (BOTTOM). A redundancy circuit (CAM) including an associative memory is arranged in an area 8 where a row decoder (R / D) is arranged.

Further, in the present invention, the redundancy circuit
The chip 1 has a defective address storage circuit (RFUSE) for storing basic information to the (CAM), that is, defective address information. The defective address storage circuit (RFUSE) stores the defective address information using a nonvolatile storage element such as a fuse. Since the defective address storage circuit (RFUSE) includes a fuse, the defective address storage circuit (RFUSE) is arranged in a portion of the chip 1 that does not hinder miniaturization of the cell array and peripheral circuits. In the device according to the first embodiment, a defective address storage circuit (RFUSE)
Are arranged in a region between the edge (or dicing line) of the chip 1 and the region 5 where the pad 4 is arranged, as shown in FIGS.

FIGS. 3A to 3C are schematic circuit block diagrams of a 256k sub-array. Hereinafter, an outline of the redundancy operation will be described with reference to a circuit block diagram.

According to the present invention, before operating the memory,
The defective address information is transferred from the defective address storage circuit (RFUSE) to a redundancy circuit (CAM) including an associative memory,
Store it in the redundancy circuit (CAM). Therefore, first, the transfer timing signal FD shown in FIGS.
X is changed from “L” level to “H” level. When the transfer timing signal FDX is set to "H" level, the defective address storage circuit (RFUSE) 11 shown in FIG. 3C outputs the defective address information F stored therein. The output defective address information F is input to a multiplexer (MUX) 12 shown in FIG. Multiplex circuit 12
When the transfer timing signal FDX is at the “H” level,
Defective address information F is input to a redundancy circuit (CAM) 13 including an associative memory in place of the row address AR. The redundancy circuit 13 outputs the transfer timing signal FD
When X is at the “H” level, the register circuit of the content addressable memory provided therein switches from the mode in which information is held (write / non-rewritable mode) to the mode in which information can be written. Thereby, the defective address information F stored in the defective address storage circuit 11 is obtained.
Is written in the register circuit.

Thereafter, when the transfer timing signal FDX is set to the "L" level, the defective address storage circuit 11 is deactivated, and the redundancy circuit 13 switches the write-in information from the mode in which the register circuit can write, to the redundancy circuit 13. The mode is switched to the hold mode.

In this way, the copy information of the defective address information F is transferred to the redundancy circuit 13 and stored therein.

The register circuit of the associative memory is a RAM.
Circuit and a volatile storage circuit. For this reason, when the power of the apparatus is turned off, the information stored here disappears. This lost information needs to be written again. For this reason, a rewriting function is required. The transfer timing signal FDX shown in FIG. 3 is an "H" pulse signal and is also a trigger signal for instructing rewriting. Signal F
One example of DX is to use a power-on reset signal. Another example is that a power-on reset signal is used as a trigger to generate the signal separately. Still another example is to provide a dedicated pad for inputting the signal FDX,
That is, input from outside. The “H” pulse may be one shot or a plurality of shots.

The transfer timing signal FDX is
The rewriting function can be implemented in the chip 1 by supplying the defective address storage circuit 11, the multiplexer 12, and the redundancy circuit 13 when the power is turned on or before the operation of the memory is started.

After the defective address information F is transferred / held in the redundancy circuit 13, the same operation as that of a device having a normal redundancy circuit is performed as follows, for example.

First, as shown in FIG. 3B, the address signal A is input to the pad 4. The input address signal A is input to the address buffer 14. Address buffer activation signal (comparing to a general DRAM,
This signal is equivalent to the / RAS signal. ) Is at a level that activates the address buffer 14, the address signal A is output from the address buffer 14 as an internal address signal (hereinafter, row address) AR. The row address AR corresponds to the multiplexer 12 shown in FIG.
Is input to At this time, the transfer timing signal FDX
Is at the “L” level. The row address AR input to the multiplexer 12 is supplied to the redundancy circuit 13 and the main row decoder 15 of the row decoder (R / D).
Is input to The main row decoder 15 selects and drives the word line (WL) arranged in the normal part 16 of the 256k sub-array 6 shown in FIG. 3A according to the logic of the input row address AR. If the logic of the input row address AR is to select a defective row (defective word line) in the normal portion 16, the redundancy circuit 13 inverts the output level,
The input level to the spare row decoder 17 is inverted.
Thereby, spare row decoder 17 is connected to spare word line arranged in spare portion 18 of 256k sub-array 6.
Select (SWL) and drive. At the same time, the redundancy circuit 13 outputs the output signal / R to the main row decoder 15.
Invert the level of SP. The main row decoder 15
While the level of the output signal / RSP is inverted, the function of decoding the address is deactivated.

FIG. 4 is a specific circuit diagram of the defective address storage circuit, the redundancy circuit, and the row decoder. Here, for simplicity, the row addresses A0R, / A0R, A1R, / A
The circuit for selecting four word lines WL1, WL2, WL3, WL4 and one spare word line SWL from 1R is shown. Hereinafter, the configuration and operation of the circuit will be described with reference to a circuit diagram.

As shown in FIG. 4, the defective address storage circuit 11 included in the device according to the first embodiment includes a fuse circuit (FUSE0) provided for each row address A0R, / A0R, A1R, / A1R. , (FUSE / 0), (FUSE1), and (FUSE / 1). Each of these fuse circuits (FUSE) has a transfer timing signal FDX connected to a resistor 20, a fuse 21, and a gate.
Receiving NMOS 22. The source of the NMOS 22 is connected to a low-potential power supply Vss (for example, a ground potential), and the drain is connected to one end of the fuse 21. The other end of the fuse 21 is connected to one end of a resistor 20, and the other end of the resistor 20 is connected to a high potential power supply Vdd. The defective address information F stored in the fuse circuit (FUSE) is extracted from an interconnection point between one end of the resistor 20 and the other end of the fuse 21. The extracted defective address information F is supplied to the multiplexer 12.

The multiplexer 12 controls each row address A0
It has multiplex circuits (MUX0), (MUX / 0), (MUX1), and (MUX / 1) provided for each of R, / A0R, A1R, and / A1R. Each of these multiplex circuits (MUX) has two inputs and one input, and transmits one of the two inputs to its output according to a transfer timing signal FDX. This is a so-called 2: 1 multiplex circuit. The multiplex circuit (MUX) may be constituted by a conventionally known 2: 1 multiplex circuit. One input of the multiplex circuit (MUX) is supplied with defective address information F, and the other input is supplied with a row address AR.
Is supplied. The multiplex circuit (MUX) transmits the defective address information F to its output when the transfer timing signal FDX is at "H" level, and transmits the row address AR to its output when the transfer timing signal FDX is at "L" level. . In the device according to the first embodiment, the output of the multiplex circuit 12 is supplied to the internal address line 19.

The redundancy circuit 13 is provided for each row address.
It has associative memory circuits (CAM0), (CAM / 0), (CAM1), and (CAM / 1) provided for each of A0R, / A0R, A1R, and / A1R.
Each of these associative memory circuits (CAM) has a register circuit 30 for holding and storing the defective address information F, one end connected to the internal address line 19, the other end connected to the register circuit 30, and a transfer timing signal FDX connected to the gate. And a comparison circuit 32 that compares the defective address information F held / stored in the register circuit 30 with the input row address AR, and outputs information on the match or mismatch to the output node N. have. Output node N
Are suspended at the potential MATCH. In the first embodiment, the register circuit 30 is constituted by a so-called cross-coupled latch circuit constituted by two inverters. In addition, the write gate circuit 31
Is the internal address line 19 and one node 4 of the latch circuit.
One NMOS with a current path connected in series between
42. The comparison circuit 32 includes an NMOS 43 having one end connected to the output node N of the redundancy circuit 13 and a gate connected to one node 41 of the latch circuit, and a current path connected to the other end of the current path of the NMOS 43. , An NMOS 44 having a gate connected to the internal address line 19, and the other end of the current path connected to the low potential power supply Vss.

The spare row decoder 17 has an inverter 50 whose input is connected to the output node N of the redundancy circuit 13, an inverter 51 whose input is connected to the output of the inverter 50, and an input connected to the output of the inverter 51. And an inverter 52. Inverter 52
Is supplied to the spare word line SWL. Also,
The output of the inverter 51 is supplied to the main row decoder 15 (ie, the signal / RSP).

Next, the operation will be described.

FIG. 5 shows the relationship between the logic of the row address and the selected word line. Also, in FIG.
The relationship between the state of the fuse and the word line (WL) replaced with the spare word line (SWL) is shown. In FIG. 6, "cut" is given to the fuse circuit (FUSE) where the fuse is blown, and "nocu" is given to the fuse circuit (FUSE) where the fuse is not blown.
t ”.

First, an example in which the word line WL1 is replaced with a spare word line SWL will be described.

As shown in FIG. 6, when replacing the word line WL1 with the spare word line SWL, the fuses 21 of the fuse circuits (FUSE / 0) and (FUSE / 1) shown in FIG. 4 are blown. Fuse is not blown in other fuse circuits (FUSE0) and (FUSE1).

Next, the transfer timing signal FDX is set to "H".
Level. At this time, the defective address information (F0), (F /
0), (F1) and (F / 1) are “L”, “H”,
The signals are set to the “L” and “H” levels and output from the defective address storage circuit 11. Then, the associative memory shown in FIG.
Register circuit 3 of (CAM0), (CAM / 0), (CAM1), (CAM / 1)
0, the node 41 is set to “L”, “H”,
Copy information at the “L” and “H” levels is held / stored. Based on these copy information, the associative memory (CAM0), (C
AM / 0), (CAM1), and (CAM / 1) NMOS 43
"OFF", "ON", "OFF", "ON".

In this state, it is assumed that an address for setting the row addresses A0R and A1R to the "L" level is input. At this time, the levels of the row addresses A0R, / A0R, A1R, / A1R transmitted to the internal address line 19 are respectively
"L", "H", "L", "H". By these logics, the associative memories (CAM0), (CAM / 0), (CAM1), (CAM /
1) NMOS 44 is “off”, “on”,
“Off” and “On”. As a result, the associative memory (CAM
/ 0) and (CAM / 1) are in the “conductive state”, the associative memories (CAM0) and (CAM1) are in the “non-conductive state”, and the potential of the output node N is 2
Through two comparison circuits 32. If the inverter 50 of the spare decoder 17 detects that the potential of the output node N drops through the two comparison circuits 32 as the “L” level, the signal / RSP goes to the “L” level. Spare decoder 17 includes main row decoder 15
Are deactivated, and the spare word line SWL is selected and driven.

It is also assumed that, in the above state, an address is input that sets the row address A0R to "H" level and A1R to "L" level. At this time, the levels of the row addresses A0R, / A0R, A1R, and / A1R transmitted to the internal address line 19 are "H", "L", "L", and "H", respectively. With these logics, the associative memories (CAM0), (CAM / 0), (CAM
1) and (CAM / 1) NMOS 44 are “ON”,
"Off", "Off", and "On". As a result, the comparing circuit 32 of the associative memory and (CAM / 1) becomes "conductive", and the comparing circuits 32 of the associative memories (CAM0), (CAM / 0) and (CAM1) become "non-conductive". The potential of the node N is 1
Through two comparison circuits 32. If the inverter 50 of the spare decoder 17 detects that the potential of the output node N drops through one comparison circuit 32 as the "H" level, the signal / RSP becomes the "H" level. Spare decoder 17 includes main row decoder 15
And the spare word line SWL is not selected. At this time, the main row decoder 15 selects the word line WL2 according to the logic of the row address.

Further, the row address A0R is set to the "L" level,
When an address for setting A1R to the "H" level is input, only one of the comparison circuits 32 of the associative memory (CAM / 0) becomes "conductive" as in the above operation. Therefore,
The signal / RSP becomes “H” level, and the spare decoder 17
Activates the main row decoder 15 and does not select the spare word line SWL. Then, the main row decoder 15 selects the word line WL3 according to the logic of the row address.

When an address which sets both the row addresses A0R and A1R to the "H" level is input, the comparison circuits 32 of all the associative memories enter the "non-conductive state". Therefore, signal / RSP attains an "H" level, and spare decoder 17 activates main row decoder 15 and does not select spare word line SWL. Then, the main row decoder 15 selects the word line WL4 according to the logic of the row address.

When any one of the word lines WL2, WL3, WL4 is replaced with a spare word line SWL, the fuse can be blown as shown in FIG. 6 to realize the same as in the case of replacing the word line WL1. .

Further, when the replacement of the word line WL is not performed, as shown in FIG. 6, the fuse circuits (FUSE0),
Do not blow the fuse in all of (FUSE / 0), (FUSE1) and (FUSE / 1). At this time, the defective address information (F0), (F
/ 0), (F1), and (F / 1) are all at the "L" level, and the register circuits of the associative memories (CAM0), (CAM / 0), (CAM1), and (CAM / 1) shown in FIG. Copy information for setting the node 41 to the “L” level is held / stored in all of the 30. Based on these copy information, associative memories (CAM0), (CAM / 0), (CAM1), (CAM /
All of the NMOSs 1) are turned off, and the comparison circuits 32 are all turned off regardless of the logic of the row address. Therefore, signal / RSP is always at "H" level.

The redundancy circuit 13 included in the device according to the first embodiment can be variously modified. For example, in the comparison circuit 32, for example, the internal address line 19 may be connected to the gate of the NMOS 43, and the node 41 of the latch circuit may be connected to the gate of the NMOS 44.

In the redundancy circuit 13, the 2
The inversion / non-inversion of the output of the redundancy circuit 13 is detected by the spare decoder 17 depending on whether the two comparison circuits 32 are in the “conductive state” and the potential of the output node N is discharged by the two comparison circuits 32. I did it. That is, the output node N of the redundancy circuit 13 has negative logic. This is connected to the other node 45 of the latch circuit by connecting the gate of the NMOS 43 to the redundancy circuit 1.
The output node N of No. 3 may be of positive logic. In this case, for example, the inverter 50 is removed from the spare decoder 17. Alternatively, output node N and spare decoder 1
7 and an odd number of inverters are added.

Next, the structure of the device according to the first embodiment will be described.

FIG. 7A is a schematic plan view of the redundancy circuit and its vicinity, and FIG. 7B is a cross-sectional view taken along the line 7A-7A in FIG. 7A.

As shown in FIGS. 7A and 7B, a P-type silicon substrate 181 has a P-type bias voltage of Vss.
A mold well 182 and an N-type well 183 biased to the potential Vdd are formed. P-type well 182 and N
Each of the mold wells 183 has an NMO that constitutes a row decoder (R / D), a memory peripheral circuit (for example, a sense amplifier driving circuit, etc.), and a redundancy circuit 13 (register circuit 30, write gate circuit 31, comparison circuit 32).
S and PMOS are formed.

Conventionally, the fuse included in the redundancy circuit may hinder the high integration of the cell array. However, in the device according to the first embodiment, all the circuits constituting the redundancy circuit 13 are replaced by MOSFETs. Can be configured. Therefore, the redundancy circuit 13 can be formed in the same well as the row decoder (R / D) and the memory peripheral circuit. Therefore, the pace of miniaturization of the redundancy circuit 13 can be matched with that of the row decoder (R / D), the memory peripheral circuit, and the like. For this reason, the redundancy circuit 13
There is no hindrance to the high integration of the cell array as in the prior art.

Further, by forming the redundancy circuit 13 in the same well as the row decoder (R / D), the redundancy circuit 13 can be arranged closer to the row decoder (R / D). As a result, the difference between the time required for selecting the spare word line SWL by the spare row decoder 17 and the time required for selecting the main word line WL by the main row decoder 15 is smaller than before. This helps to further speed up the operation of the memory.

Next, the relationship between the defective address storage circuit and the sub-array will be described.

In a memory having a large storage capacity, a cell array is divided into several subarrays. For example, as shown in FIG. 2, the 2M cell array 2 is divided into eight 256k sub arrays 6.

FIG. 8 is a circuit block diagram showing a first relationship between a defective address storage circuit and a subarray. FIG. 8 shows an example in which the cell array is divided into eight sub-arrays SUB1 to SUB8.

As shown in FIG. 8, each of the sub-arrays SUB1-SU
A defective address storage circuit (FUSE) 1 corresponding to each of B8
1-SUB1 to 11-SUB8 are provided. Each subarray
Each of SUB1 to SUB8 has a multiplexer (MUX) 12,
A redundancy circuit (CAM) 13 including an associative memory is provided.

In the device having the first relation, the defective address information F is transferred from each of the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 to the multiplexer 12 of each of the subarrays SUB1 to SUB8.
Wirings 60 for transmitting up to 2 are provided independently of each other.

As described above, in the device connecting the multiplexer 12 of each of the subarrays SUB1 to SUB8 and each of the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 by the wirings 60 independent of each other, the defective address information F is This has the advantage that data can be transferred at one time from the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 to the redundancy circuits 13 of the subarrays SUB1 to SUB8.

FIG. 9 is a circuit block diagram showing a second relationship between the defective address storage circuit and the subarray.

As shown in FIG. 9, each of the sub-arrays SUB1-SU
A defective address storage circuit (FUSE) 1 corresponding to each of B8
1-SUB1 to 11-SUB8 are provided. Each subarray
Each of SUB1 to SUB8 has a multiplexer (MUX) 12,
A redundancy circuit (CAM) 13 including an associative memory is provided.

In the device having the second relation, the common wiring 60 is used for the defective address storage circuits 11-SUB1 to 11-SUB4.
-TOP and defective address storage circuits 11-SUB5 to 11-SUB8
And a common wiring 60-BOTTOM. Output wirings 60 of the defective address storage circuits 11-SUB1 to 11-SUB4 are connected to a common wiring 60-TOP via a selector 61, respectively. The common wiring 60-TOP is connected to the sub-array SU
It is connected to the multiplexers B1 to SUB4. Similarly, output wirings 60 of the defective address storage circuits 11-SUB5 to 11-SUB8 are connected to a common wiring 60-BOTTOM via a selector 61. Common wiring 60-B
OTTOM is a multiplexer 12 for subarrays SUB5 to SUB8.
It is connected to the. When the transfer timing signals FDX (FDX1 to FDX4) attain the "H" level, the selectors 61 respectively operate the defective address storage circuits 11-SUB1 to 1-SUB1.
The defective address information from 1-SUB8 is transferred to the common wiring 60-T.
OP, tell 60-BOTTOM.

As described above, the common wirings 60-TOP and 60-B
According to the OTTOM, the multiplexer 12 of each of the sub-arrays SUB1 to SUB8 and each of the defective address storage circuits (FUSE) 11-SUB1 to
In the device connected to the 11-SUB8, the transfer timing signals FDX1 to FDX4 are sequentially set to "H" level one by one. As a result, the defective address information F is transmitted from each of the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8.
The data can be transferred to the redundancy circuits 13 of the sub-arrays SUB1 to SUB8. An advantage of the device having the second relationship is that the number of wirings 60 can be reduced as compared with the device having the first relationship.

FIG. 10 is a circuit block diagram showing a third relationship between a defective address storage circuit and a subarray.

As shown in FIG. 10, each of sub-arrays SUB1 to SUB1
A defective address storage circuit (FUSE) corresponding to each of SUB8
11-SUB1 to 11-SUB8 are provided. Each of the sub-arrays SUB1 to SUB8 has a multiplexer (MUX) 1
2. A redundancy circuit (CAM) 13 including an associative memory is provided.

In the device having the third relationship, all of the defective address storage circuits 11-SUB1 to 11-SUB8 have a common wiring 60-ARRAY. Bad address storage circuit 11
The output wirings 60 of -SUB1 to 11-SUB8 are each connected to a common wiring 60-ARRAY via a selector 61. The common wiring 60-ARRAY is connected to the multiplexers 12 of the sub-arrays SUB1 to SUB8. The selectors 61 respectively transfer the transfer timing signals FDX (FDX1 to FD
When X8) becomes "H" level, the defective address information from the defective address storage circuits 11-SUB1 to 11-SUB8 is transmitted to the common wiring 60-ARRAY.

As described above, in a device in which the multiplexer 12 of each of the sub-arrays SUB1 to SUB8 and the defective address storage circuits (FUSE) 11-SUB1 to 11-SUB8 are connected by the common wiring 60-ARRAY, the transfer timing Signal FDX
1 to FDX8 are sequentially set to “H” level one by one. As a result, the defective address information F is transferred from each defective address storage circuit (FUSE) 11-SUB1 to 11-SUB8 to each sub-array.
The data can be transferred to the redundancy circuits 13 of SUB1 to SUB8. Third
The advantage of the device having the above relationship is that the number of wirings 60 can be further reduced as compared with the device having the second relationship.

FIG. 11 is a circuit block diagram showing a fourth relationship between the defective address storage circuit and the sub-array.

As shown in FIG. 11, each of the sub-arrays SUB1-SUB
A defective address storage circuit (FUSE) corresponding to each of SUB8
11-SUB1 to 11-SUB8 are provided. Each of the sub-arrays SUB1 to SUB8 is provided with a redundancy circuit (CAM) 13 including an associative memory.

In the device having the fourth relationship, all of the defective address storage circuits 11-SUB1 to 11-SUB8 have a common wiring 60-ARRAY. Bad address storage circuit 11
The output wirings 60 of -SUB1 to 11-SUB8 are each connected to a common wiring 60-ARRAY via a selector 61. The common wiring 60-ARRAY is connected to the common multiplexer 12-ARRAY in the sub-arrays SUB1 to SUB8. The selectors 61 respectively transfer the transfer timing signal FDX (F
DX1 to FDX8) attain the "H" level, the defective address information from the defective address storage circuits 11-SUB1 to 11-SUB8 is transmitted to the common wiring 60-ARRAY. The multiplexer 12-ARRAY has a transfer timing signal FDX0
Is supplied. The transfer timing signal FDX0 goes to “H” level, for example, when one of the transfer timing signals FDX1 to FDX8 goes to “H” level.

The advantage of the device having the fourth relationship having the common wiring 60-ARRAY and the common multiplexer 12-ARRAY is that the number of multiplexers 12 is smaller than that of the device having the third relationship. , It can be reduced.

Next, a DRAM according to the second embodiment will be described.

In the second embodiment, the circuit scale of the redundancy circuit 13 is to be reduced. More specifically, the circuit scale of the register circuit 30 is
It is smaller than that of the first embodiment.

FIG. 12 is a specific circuit diagram of the defective address storage circuit, the redundancy circuit, and the row decoder included in the device according to the second embodiment. Here, for the sake of simplicity, a circuit for selecting four word lines WL1, WL2, WL3, WL4 and one spare word line SWL from the row addresses A0R, / A0R, A1R, / A1R is shown. Hereinafter, the configuration and operation of the circuit will be described with reference to a circuit diagram.

As shown in FIG. 12, the defective address storage circuit 11 included in the device according to the second embodiment includes a fuse circuit (FUSE0) provided for each of the row addresses A0R and A1R.
(FUSE1) and a fuse circuit (FUSES) for storing information on whether or not to use the spare word line.

First, each of the fuse circuits (FUSE0) and (FUSE1) used for address replacement has a resistor 20, a fuse 21, and an NMOS 22 whose gate receives a transfer timing signal FDX. The source of the NMOS 22 is connected to a low-potential power supply Vss (for example, a ground potential), and the drain is connected to one end of the fuse 21. The other end of the fuse 21 is connected to one end of a resistor 20, and the other end of the resistor 20 is connected to a high potential power supply Vdd. The defective address information F stored in the fuse circuits (FUSE0) and (FUSE1) includes one end of the resistor 20 and the fuse 2
1 from the interconnection point with the other end. The extracted defective address information F is supplied to the multiplexer 12.

Further, the fuse circuit (FUSES)
0, a fuse 21, and an NMOS 23.
The source of the NMOS 23 is connected to a low-potential power supply Vss (for example, a ground potential), and the drain is connected to one end of the fuse 21. The other end of the fuse 21 is connected to a resistor 2
0, and the other end of the resistor 20 is connected to a high potential power supply Vdd. The gate is connected to the interconnection point between the other end of the resistor 20 and the high potential power supply Vdd. Spare use information S stored in the fuse circuit (FUSES) is extracted from an interconnection point between one end of the resistor 20 and the other end of the fuse 21. The extracted spare use information S is
It is supplied to a spare row decoder 17.

The multiplexer 12 has a row address A0R.
, A multiplex circuit (MUX0) provided for each A1R,
(MUX1). These multiplex circuits (MU
X) each have two inputs and one input, and transmit any one of the two inputs to its output according to a transfer timing signal FDX. This is a so-called 2: 1 multiplex circuit. Multiplex circuit (MUX)
As in the first embodiment, a conventionally known 2: 1 ratio is used.
It may be constituted by a multiplex circuit. One input of the multiplex circuit (MUX) has defective address information F
And the other input is supplied with a row address AR. The multiplex circuit (MUX) transmits the defective address information F to its output when the transfer timing signal FDX is at "H" level, and transmits the row address AR to its output when the transfer timing signal FDX is at "L" level. . In the device according to the second embodiment, the output of the multiplex circuit 12 is connected to the internal address line 19.

The redundancy circuit 13 has associative memory circuits (CAM0) and (CAM1) provided for each row address pair (A0R, / A0R) and (A1R, / A1R). Each of these associative memory circuits (CAM) has a register circuit 30, a normal phase write gate circuit 31, a comparison circuit 32, and a negative phase write gate circuit 33.

In the device according to the second embodiment, the register circuit 30 is constituted by a so-called cross-coupled latch circuit constituted by two inverters. The register circuit 30
May be basically a flip-flop type circuit having a first output and a second output having an inverted level of the first output.

The positive phase write gate circuit 31 is connected to the positive phase internal address (AR) line 19 and the positive phase node 4 of the latch circuit.
1, a current path is connected in series, and one NMOS 42 receives a transfer timing signal FDX at a gate.

The comparison circuit 32 includes three NMOSs 46, 4
7, 48. First, the NMOS 46
Connects one end of the current path to the positive-phase internal address (AR) line 1
9 and the gate is connected to the negative-phase node 45 of the latch circuit. The NMOS 47 has one end of the current path connected to the reverse-phase internal address (/ AR) line 19 and the other end connected to the N-side.
The other end of the current path of the MOS 46 is connected, and the gate is connected to the positive-phase node 41 of the latch circuit. NMOS4
8, one end of the current path is connected to the output node N of the redundancy circuit 13 suspended at the potential MATCH, and the other end is connected to the low potential power supply Vss.

The negative-phase write gate circuit 33 has a current path connected in series between the negative-phase internal address (/ AR) line 19 and the negative-phase node 45 of the latch circuit. It is composed of one NMOS 49 receiving FDX.

Spare row decoder 17 has one input connected to output node N of redundancy circuit 13 and the other input receives NAND gate 53 receiving spare use information S.
And an inverter 54 whose input is connected to the output of the NAND gate 53. The output of inverter 54 is supplied to spare word line SWL. Also, NAN
The output of the D gate 53 is supplied to the main row decoder 15 (that is, the signal / RSP).

Next, the operation will be described.

FIG. 13 shows the relationship between the logic of the row address and the selected word line. FIG. 14 shows the relationship between the state of the fuse and the word line (WL) replaced with the spare word line (SWL). In FIG.
“Cut” is added to the fuse circuit (FUSE) where the fuse is blown.
”, Fuse circuit with no blown fuse (FUS
E) is marked with “no cut”.

First, an example in which word line WL1 is replaced with spare word line SWL will be described.

As shown in FIG. 14, the word line WL1 is
When replacing with the spare word line SWL, the fuses 21 of the fuse circuits (FUSES) and (FUSE1) shown in FIG. 12 are not blown, but the fuses 21 of the fuse circuit (FUSES) are blown.

Next, the transfer timing signal FDX is set to "H".
Level. At this time, the defective address information (F0), (F
1) and (S) are set to “L”, “L”, and “H” levels, respectively, and output from the defective address storage circuit 11.
With these outputs, the associative memory (CAM0) shown in FIG.
Each of the register circuits 30 of (CAM1) holds / stores copy information for setting the node 41 to the “L” level. Based on these copy information, N of the associative memories (CAM0) and (CAM1)
The MOS 46 is turned "ON" and the NMOS 47 is turned "OFF". In addition, N of spare row decoder 17
The “H” level is supplied to the other input of the AND gate 53. As a result, the NAND gate 53 changes the potential level of its output according to the potential level of the output node input to one input. That is, N
When the AND gate 53 is activated, the spare row decoder 17 is activated.

In this state, it is assumed that an address for setting the row addresses A0R and A1R to the "L" level is input. At this time, the levels of the row addresses A0R, / A0R, A1R, / A1R transmitted to the internal address line 19 are respectively
"L", "H", "L", "H". By these logics, the NMOSs 48 of the associative memories (CAM0) and (CAM1) are turned off. As a result, the associative memory (CAM / 0)
, (CAM / 1) are in the “non-conductive state”, respectively.
, And the potential of the output node N remains at the potential MATCH. NAND gate 53 of spare decoder 17 has a potential
MATCH is detected as "H" level. As a result, the signal / RSP becomes “L” level, and the spare decoder 17
The main row decoder 15 is deactivated. At the same time, the spare word line SWL is selected and driven.

It is also assumed that, in the above state, an address is input that sets the row address A0R to "H" level and A1R to "L" level. At this time, the levels of the row addresses A0R, / A0R, A1R, and / A1R transmitted to the internal address line 19 are "H", "L", "L", and "H", respectively. By these logics, the NMO of the associative memories (CAM0) and (CAM1)
S48 is "ON" and "OFF", respectively. As a result, the comparison circuit 32 of the associative memory (CAM0) becomes “conductive”,
The comparison circuit 32 of the associative memory (CAM1) becomes “non-conductive”, and the potential of the output node N drops through the comparison circuit 32 of the associative memory (CAM0). N of spare row decoder 17
AND gate 53 detects this lowered potential as an “L” level. As a result, the signal / RSP becomes "H" level, and the spare decoder 17 activates the main row decoder 15. At the same time, the spare word line SW
Do not select L. The activated main row decoder 15 outputs the word line W according to the logic of the row address.
Select L2.

Further, the row address A0R is set to the "L" level,
When an address for setting A1R to the "H" level is input, the comparison circuit 32 of the associative memory (CAM1) becomes "conductive" and the signal / RSP becomes the "H" level, as in the above operation. As a result, spare decoder 17 activates main row decoder 15 and spare word line SWL.
Do not select The main row decoder 15 selects the word line WL3 according to the logic of the row address.

When an address which sets both the row addresses A0R and A1R to the "H" level is input, the comparing circuits 32 of the associative memories (CAM0) and (CAM1) become "conductive" and the signal / RSP becomes It becomes "H" level. Spare decoder 17 activates main row decoder 15 and does not select spare word line SWL. Then, the main row decoder 15 selects the word line WL4 according to the logic of the row address.

In place of word line WL1, one of word lines WL2, WL3, WL4 is connected to spare word line S.
When replacing with WL, a fuse is blown as shown in FIG. Thereby, each can be replaced with a spare word line SWL.

Further, when the replacement of the word line WL is not performed, as shown in FIG.
Is not blown. At this time, the spare use information S becomes "L" level. As a result, the "L" level is always supplied to the other input of the NAND gate 53 of the spare row decoder 17, and the NAN
The output of D gate 53 is always fixed at "H" level regardless of the potential level of output node N. By fixing the output of the NAND gate 53 to the “H” level, the signal
/ RSP is always at "H" level. Therefore, the main row decoder 15 selects the word line WL according to the logic of the row address.

Note that the fuse 2 of the fuse circuit (FUSES)
When 1 is not blown, another fuse circuit (FUSE0)
, (FUSE1) fuses 21 blow /
Either may or may not be.

According to the redundancy circuit 13 of the device according to the second embodiment, the associative memory (CAM) is provided not for each row address but for each row address pair. For this reason, the number of associative memories (CAM) can be reduced by half as compared with the device according to the first embodiment shown in FIG. In particular, the number of register circuits 30 in the associative memory (CAM) is halved. For this reason, the circuit scale of the redundancy circuit 13 is reduced, the number of MOSFETs can be reduced as compared with the device according to the first embodiment shown in FIG. 4, and the redundancy circuit 1 including an associative memory (CAM) in a chip is provided.
3 can be smaller.

Further, since the number of associative memories (CAM) is reduced, compared with the device according to the first embodiment shown in FIG.
The number of fuse circuits (FUSEs) in the defective address storage circuit 11 can also be reduced. Therefore, the redundancy circuit 1
Similarly to 3, the area occupied by the defective address storage circuit 11 including the fuse circuit (FUSE) can be reduced. Further, by reducing the number of fuse circuits (FUSE), the number of fuses that are difficult to miniaturize can be reduced from on the chip.

In addition, the number of defective address information F also decreases as the number of fuse circuits (FUSE) decreases. Therefore, the number of wirings for transferring the defective address information F to the content addressable memory (CAM) can be reduced. Further, by reducing the number of wirings, the number of multiplexing circuits (MUX) for inputting the defective address information F to the internal address line 19 can be reduced.

Due to these advantages, the device according to the second embodiment can obtain an effect that higher integration can be achieved than in the first embodiment.

Next, a DRAM according to the third embodiment will be described.

In the third embodiment, the circuit scale of the defective address storage circuit 11 is to be reduced. More specifically, the defective address storage circuit 11 is shared by a plurality of sub-arrays, the number of fuse circuits (FUSE) of the defective address storage circuit 11, particularly, the number of fuses provided in one chip is reduced.

For example, as described with reference to FIG. 2, conventionally, in a semiconductor memory having a large-scale storage capacity, a cell array is divided into several sub-arrays. This sub-array is an arbitrary unit that can be divided in a semiconductor memory. In a semiconductor memory divided into several sub-arrays as described above, a redundancy circuit and a spare row (word line) / spare column (bit line) are arranged for each sub-array. The replacement of a defective row (word line) / defective column (bit line) with a spare row / spare column is performed for each sub-array. This is a replacement method generally performed conventionally. For example, as shown in FIG. 35, in a conventional special purpose type 18M DRAM, one 2M cell array is composed of a total of eight 256k sub-arrays (4 × 2 = 2). A redundancy circuit (RFUSE) is provided for each sub-array, and a fuse is independently provided for each sub-array. In the cell array shown in FIG. 35, a total of eight fuse circuits (hereinafter, referred to as fuse blocks) are arranged. Further, in the whole chip, 8 sets × 9 = 72 fuse blocks are arranged.

When such a typical replacement method is used in the present invention, for example, as shown in FIGS.
Defective address storage circuit 11-SUB1 including fuse circuit
11-SUB8 is set in each of the subarrays SUB1 to SUB8.

However, although there are variations depending on the number of subarrays and the stage of product development (exploration or maturity), the number of subarrays in which defective rows / columns occur is 20 to 30 of the entire chip. %. Other 70 ~
In 80% of the sub-arrays, no bad rows / columns occurred and no spare rows / columns were used. In these subarrays, the defective address storage circuit 11-SUB including the fuse circuit is not used, and is useless.

Therefore, in the third embodiment, noting the above circumstances, the defective address storage circuit 11-SUB is not set one by one in the subarrays SUB1 to SUB8, but is shared by several subarrays. . Thereby, the number of defective address storage circuits 11-SUB is reduced.

FIG. 15 is a circuit block diagram showing the relationship between the defective address storage circuit and the sub-array of the device according to the third embodiment.

As shown in FIG. 15, the cell array is composed of eight sub-arrays SUB1 to SUB8. In the third embodiment, only one defective address storage circuit 11 is provided for eight sub-arrays SUB1 to SUB8.

The defective address storage circuit 11 has an address fuse circuit (FUSEA) and a sub-array selection fuse circuit (FUSES). The address fuse circuit (FUSEA) stores the defective address information F, similarly to the fuse circuits (FUSE) of the devices according to the first and second embodiments. Also, a fuse circuit (FUSES) for selecting a sub-array
Stores replacement information S indicating which of the eight sub-arrays SUB1 to SUB8 replaces a defective word line with a spare word line. That is, the replacement information S is information for specifying a subarray to be replaced. Each of these fuse circuits (FUSEA) and (FUSES) is supplied with a transfer timing signal SFDX.
When the transfer timing signal SFDX becomes, for example, "H" level, the fuse circuits (FUSEA) and (FUSES) output defective address information F and replacement information S, respectively.

Each of the sub-arrays SUB1 to SUB8 has a multiplex circuit (MUX) 12 and a redundancy circuit 13 including an associative memory, similarly to the devices according to the first and second embodiments. Further, in the third embodiment, the redundancy circuit 13 has an associative memory unit (CAMA) for addresses and an associative memory unit (CAMS) for selecting a sub-array.

The address associative memory unit (CAMA) has a rewritable RAM circuit such as a register circuit, like the associative memory (CAM) of the first and second embodiments.
The defective address information F is transferred from the address fuse circuit (FUSEA) to the RAM circuit, and the transferred defective address information is held / stored. The row address AR is input to the address associative memory unit (CAMA).
The address associative memory unit (CAMA) holds and stores the input row address AR while the memory is operating, similarly to the associative memory (CAM) of the first and second embodiments. Then, it is determined whether or not the input row address AR designates a defective row.

The associative memory section (C
AMS) has a non-rewritable ROM circuit. ROM
The sub-array number is written in the circuit. A subarray number is assigned to each subarray, and different information is used for each subarray. The associative memory section (CAMS) for subarray selection has a fuse circuit for subarray selection.
(FUSES), the replacement information S is input. The associative memory section (CAMS) for selecting a sub-array includes the defective address information F
During the mode of transferring the data to the associative memory unit (CAMA), the input replacement information S is compared with the written sub-array number, and whether the input replacement information S designates its own sub-array is determined. Judge. Further, in response to this determination result, the associative memory unit (CAMS) outputs a local transfer timing signal FDX to the sub-array. For example, the associative memory unit (CAMS) sets the local transfer timing signal FDX to the “H” level only when the input replacement information S specifies its own sub-array, and keeps it at the “L” level otherwise. The local transfer timing signal FDX is supplied to a multiplex circuit 12 and an addressable associative memory unit (CAMA) in the subarray. "H" level local transfer timing signal F
The multiplex circuit 12 receiving the DX supplies the defective address information F to an addressable associative memory unit (CAMA). Then, the RAM circuit of the content addressable memory unit (CAMA) receiving the local transfer timing signal FDX at the "H" level changes from a non-writable mode to a writable mode. The defective address information F is written into the RAM circuit in the writable mode.

Conversely, multiplex circuit 1 receiving local transfer timing signal FDX at "L" level
2 does not supply the defective address information F to the addressable associative memory unit (CAMA). Further, the associative memory unit (C) receiving the local transfer timing signal FDX at "L" level
The RAM circuit of AMA) remains in the non-writable mode.

In this manner, the defective address information F is written only in the RAM circuit of the sub-array specified by the replacement information S.

FIG. 16 is a specific circuit diagram of the redundancy circuit 13 and the row decoder shown in FIG. 15, and FIG.
FIG. 6 is a specific circuit diagram of the defective address storage circuit 11 shown in FIG. Here, for simplicity, one of the eight sub-arrays is selected by one defective address storage circuit, and the row address A0 is selected in the selected sub-array.
From R, / A0R, A1R, / A1R, four word lines WL1, WL2
, WL3, WL4 and one spare word line SWL will be described. Hereinafter, the configuration and operation of the circuit will be described with reference to a circuit diagram.

As shown in FIG. 17, the defective address storage circuit 11 included in the device according to the third embodiment has an address fuse circuit (FUSEA) and a sub-array selection fuse circuit (FUSES). ing.

The fuse circuit for address (FUSEA) includes fuse circuits (FUSEA0) and (FUSEA1) provided for each of the row addresses A0R and A1R, as in the second embodiment.

Further, the fuse circuit (F
USES) has three fuse circuits (FUSES0), (FUSS0), and (FUSS0) for selecting one subarray from eight subarrays.
ES1) and (FUSES2).

First, the fuse circuits (FUSEA0), (FUSEA1),
(FUSES0), (FUSES1), and (FUSES2) respectively represent the transfer timing signal SFDX to the resistor 20, the fuse 21, and the gate.
And an NMOS 24 for receiving the signal. The source of the NMOS 24 is connected to a low potential power supply Vss (for example, ground potential), and the drain is connected to one end of the fuse 21. The other end of the fuse 21 is connected to one end of a resistor 20, and the other end of the resistor 20 is connected to a high potential power supply Vdd. The defective address information F0 and F1 stored in the fuse circuits (FUSEA0) and (FUSEA1) are output from an interconnection point between one end of the resistor 20 and the other end of the fuse 21, respectively.
The replacement information S0, S1, and S2 stored in the fuse circuits (FUSES0), (FUSES1), and (FUSES2)
Is output from an interconnection point between one end of the fuse 21 and the other end of the fuse 21.

The defective address information F0 and F1 output from the fuse circuits (FUSEA0) and (FUSEA1) are supplied to the multiplex circuits (MUX0) and (MUX1) shown in FIG. 16, respectively. The replacement information S0, S1, and S2 output from the fuse circuits (FUSES0), (FUSES1), and (FUSES2) are supplied to the sub-array selection associative memory unit (CAMS) shown in FIG. The associative memory unit (CAMS) has associative memory circuits (CAMS0), (CAMS1), and (CAMS2) corresponding to the replacement information S0, S1, and S2. The replacement information S0, S1, and S2 are supplied to the associative memory circuits (CAMS0), (CAMS1), and (CAMS2), respectively.
The associative memory circuits (CAMS0) to (CAMS2) are respectively a ROM circuit 70 in which a subarray number is written, and a ROM
A comparison circuit 71 compares the sub-array number written in the circuit 70 with the input replacement information S0, S1, S2. The comparison circuit 71 connects one end of the current path to the replacement information line 72 and one end of the current path to the inverted replacement information line 72-INV, and connects the other end to NM
An NMOS 74 connected to the other end of the current path of the OS 73;
One end of the current path is connected to the output node NS, the other end is connected to the low potential power supply Vss, and the gates of the NMOSs 73 and 7 are connected.
4 NMOS connected to the interconnection point of each current path
75. Output node NS is suspended at potential MATCHS. The ROM circuit 70 includes a comparison circuit 7
The high potential power supply Vdd,
Information is stored by supplying one of the low-potential power supplies Vss. In other words, the associative memory unit (CAMS)
The sub array numbers are stored by eight combinations of the power supplies Vdd and Vss input to 3, 74. FIG.
(A) to (D) show the R of the subarrays SUB1 to SUB4, respectively.
The OM circuit 70 is shown. Similarly, FIGS. 19A to 19D show the ROM circuits 70 of the subarrays SUB5 to SUB8, respectively. FIG. 20 shows the relationship between the contents of the ROM and the subarray numbers.

The device according to the third embodiment further includes a replacement information register (SREG) for holding / storing the output of the associative memory unit (CAMS), and contents held / stored in the replacement information register (SREG). And a local transfer timing signal generator (FDXGEN) for generating a local transfer timing signal FDX.

First, the register (SREG) is a register circuit 8
0 and a write gate circuit 81 that writes the output of the associative memory unit (CAMS) to the register circuit 80 in accordance with the transfer timing signal SFDX. In the third embodiment, the register circuit 80 is constituted by a so-called cross-coupled latch circuit constituted by two inverters. The write gate circuit 81 has a current path connected in series between the output node NS and the positive-phase node 82 of the latch circuit, and has a transfer timing signal S
It comprises one NMOS 83 that receives FDX. The output of the register (SREG) is extracted from the negative-phase node 84 of the latch circuit. The output of the register (SREG) extracted from the negative-phase node 84 is supplied to the FDX signal generator (FDXGEN) and the spare row decoder 17 after being inverted by the inverter.

Also, an FDX signal generator (FDXGEN)
Receives the transfer timing signal SFDX at one input,
NAN receiving inverted output of register (SREG) at the other input
It comprises a D gate circuit 91 and an inverter 92 whose input is connected to the output of the NAND gate circuit 91. The output of the inverter 92 is a multiplex circuit (M
UX0), (MUX1), and associative memory circuits (CAMA0), (CAMA1). (That is, the local transfer timing signal FD
X. The other configuration is the same as that of the second embodiment, and a description thereof will be omitted.

Next, the operation will be described.

FIG. 21 shows the relationship between the state of the fuse and the selected sub-array. FIG. 22 shows the relationship between the logic of the row address and the selected word line (WL). FIG. 23 shows the state of the fuse and the word line (WL) replaced with the spare word line (SWL).
Is shown. In FIGS. 21 and 23, the fuse circuits (FUSEA) and (FUSES)
, “FUSEA” and “FUSES” with no fuse blown by “no cut”. In the following, of the eight sub-arrays SUB1 to SUB8,
(SUB7) and the word line WL1 of the sub-array (SUB7).
Is replaced with a spare word line SWL.

As shown in FIG. 21, when the sub-array (SUB7) is selected, the fuse circuit (FUSES0) shown in FIG.
Fuse circuit (FUSES1) without blowing fuse 21
(FUSES2) Each fuse 21 is blown. When replacing the word line WL1 with the spare word line SWL, the fuse circuits (FUSEA0) and (FUSEA1) shown in FIG.
Do not blow each fuse 21.

Next, the transfer timing signal SFDX is set to "H" level. At this time, the defective address information (F
0) and (F1) are the “L” level, respectively, the replacement information (S2),
(S1) and (S0) are at the “H”, “H”, and “L” levels, respectively, and are output from the defective address storage circuit 11. Based on these outputs, first, the associative memories (CAMS2), (CAMS1), and (CAMS0) for subarray selection are
A signal for setting the replacement information line 72 to “H”, “H”, “L” is input. By these inputs, the associative memory (CAMS) of the associative memory section (CAMS) of the sub-array SUB7 shown in FIG.
2) The NMOS 75 of (CAMS1) and (CAMS0) are turned off. For this reason, the associative memory unit (CAMS) of the subarray SUB7
Output node NS attains the potential MATCHS, that is, "H" level. In the associative memory units (CAMS) of the other subarrays SUB1 to SUB6 and SUB8, the associative memories (CAMS2), (CAMS1), (CAMS)
S0), at least one NMOS 75 turns on. For this reason, the associative memory section (CAM
Each of the output nodes NS of S) falls from the potential MATCHS, and the output node NS becomes the “L” level. As a result, only the register (SREG) of the sub-array (SUB7) stores the replacement information for setting the opposite-phase node 84 to the “L” level. FDX signal generator (FDXGE
N) is an “H” level transfer timing signal FDX according to the replacement information for setting the opposite-phase node 84 to “L” level.
Is output. The FDX signal generators (FDXGEN) of the other sub-arrays SUB1 to SUB6 and SUB8
A low level transfer timing signal FDX is output in accordance with the replacement information for setting the “H” level. As a result, the sub-array SUB7 is selected from the eight sub-arrays, and the "H" level transfer timing signal FDX is
Is generated.

Each of the multiplexers 12 has
A signal for setting the input on the defective address information side of each of the multiplex circuits (MUX0) and (MUX1) to the “L” level is input. The multiplexer 12 of the sub-array SUB7 is "H"
Level transfer timing signal FDX,
A signal input to the input on the defective address information side is transmitted to the internal address line 19. Other sub arrays SUB1 to SUB
6. On the contrary, the multiplexer 12 of SUB8 receives the transfer timing signal FDX at "L" level. In each of these multiplexers 12, the signal input to the input on the defective address information side is not transmitted to the internal address line 19.

[0166] Of the subarrays SUB1 to SUB8, the subarray
The associative memory section (CAMA) of SUB7 has a fuse circuit (FUSEA
0) and (FUSEA1), defective address information (F0) and (F1) are transferred. Then, copy information for setting the node 41 to the "L" level is held / stored in the register circuits 30 of the associative memories (CAMA0) and (CAMA1). With these pieces of copy information, the NMOSs 46 of the associative memories (CAMA0) and (CAMA1) are turned "ON" and the NMOS 47 is turned "OFF".

In the spare row decoder 17 of the subarray SUB7, the other input of the NAND gate 53
The inverted value of the output of the register (SREG), that is, the “H” level is supplied. As a result, the spare row decoder 17 is activated as in the second embodiment. On the other hand, in each of the spare row decoders 17 of the other subarrays SUB1 to SUB6 and SUB8, the inverted value of the output of the register (SREG), that is, the “L” level is supplied to the other input of the NAND gate 53. Thereby, spare row decoder 17 is deactivated.

In this state, it is assumed that an address for setting the row addresses A0R and A1R to the "L" level is input. At this time, the levels of the row addresses A0R, / A0R, A1R, / A1R transmitted to the internal address line 19 are respectively
"L", "H", "L", "H". Based on these logics, the associative memories (CAMA0), (CAMA0)
Each of the NMOSs 1) is turned off. As a result, the comparison circuits 32 of the associative memories (CAMA0) and (CAMA1) become “non-conductive”, and the potential of the output node N becomes
The potential remains at MATCH. N of spare row decoder 17
AND gate 53 detects potential MATCH as "H" level. As a result, similarly to the second embodiment, the signal
/ RSP becomes “L” level, and the spare row decoder 17
Makes the main row decoder 15 inactive. At the same time, the spare word line SWL is selected and driven.

The operation in the other states of the row addresses A0R and A1R is the same as that of the second embodiment, and the description is omitted.

As described above, in the device according to the third embodiment, the associative memory section for selecting a sub-array is provided for each sub-array.
By having (CAMS), one defective address storage circuit 11 can be shared by several sub-arrays. Thereby, the circuit scale of the defective address storage circuit 11 can be reduced. In particular, the number of fuse circuits (FUSE) of the defective address storage circuit 11 can be reduced, and the number of fuses provided on one chip can be reduced even if the storage capacity is increased. Thus, in the device having the defective address storage circuit 11 as in the first and second embodiments, a configuration suitable for higher integration can be obtained.

Next, a fourth embodiment of the present invention will be described.

The fourth embodiment is another example of a method of transferring defective address information from the defective address storage circuit 11 to the redundancy circuit 13.

In the first to third embodiments, defective address information is transferred from the defective address storage circuit 11 to the register circuit 30 of the redundancy circuit 13 via the internal address line 19, respectively.

In the fourth embodiment, the defective address information is stored in the redundancy circuit 1 from the defective address storage circuit 11.
3 to the register circuit 30 using a shift register circuit.

FIG. 24 is a circuit diagram showing a redundancy circuit, a defective address storage circuit, and a shift register circuit of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.
FIG. 25 is an operation waveform diagram showing the transfer operation.

First, referring to FIGS. 24 and 25, using the shift register circuit 91, the defective address information stored in the defective address storage circuit 11 is stored in the register circuit 30 (R0, R1, R2) of the redundancy circuit 13. ) Will be described.

First, as shown in FIG. 25, signals φ1, φ
2 at the “H” level, and the data set signal Data S
Let et be the “L” level. As a result, each of the nodes F0, F1, and F2 of the shift register circuit shown in FIG. 24 is initialized to "H" level. Then, the signal φ1,
After φ2 is set to “L” level, the signal Data Set is set to “H” level, and the fuse circuits (FUSE0), (FUSE1),
(FUSES) from each node F
Read to 0, F1, F2.

When the fuse of the fuse circuit (FUSE0) is not blown (“No Cut”), the node F0 transitions to “L” level. Conversely, fuse circuit (FUSE0)
When the fuse is blown ("Cut"), the node F0 maintains the "H" level. Fuse circuit (FUS
The same applies to E1) and (FUSES). When the fuse is not blown (“No Cut”), the nodes F1 and F
2 change to the "L" level, and when the fuse is blown ("Cut"), the nodes F1 and F2 each maintain the "H" level. In this manner, the fuse circuits (FUSE) are respectively connected to the nodes F0, F1, and F2.
Set the data stored in (0), (FUSE1) and (FUSES). Next, the signal Data Set is set to the “L” level, and the nodes F0, F1, and F2 are electrically floated.

In FIG. 25, the fuse circuit (FUSE0)
, (FUSE1) and (FUSES) are “Cut” and “No Cu
An example of transfer when “t” and “Cut” are shown.

After the nodes F0, F1, and F2 are electrically floated, the signals φ1 and φ2 are toggled like a two-phase clock. Thereby, the node F0
Is shifted in the order of the node F1 and the node F2, and finally, the register circuit 30 (R0)
And stored here. Similarly, node F
The data set to 1 is shifted in the order of the node F2 and the register circuit 30 (R0), and finally shifted to the register circuit 30 (R1) and stored therein.
Similarly, the data set at the node F2 is shifted in the order of the register circuit 30 (R0) and the register circuit 30 (R1), and finally shifted to the register circuit 30 (R2) and stored therein. You.

FIG. 26 shows the relationship between the logic of the row address and the selected word line in the device according to the fourth embodiment. FIG. 27 shows the relationship between the state of the fuse and the replaced word line in the device according to the fourth embodiment.

As shown in FIGS. 26 and 27, the relationship between the logic of the row address of the device according to the fourth embodiment and the selected word line, and the relationship between the state of the fuse and the replaced word line are as follows. This is the same as the device according to the second embodiment.

Further, in the fourth embodiment, the connection method between the redundancy circuit 13 and the spare
A connection method different from that of the third embodiment is employed.

That is, in the first to third embodiments, the redundancy circuit 13 and the spare decoder 17 use the potential MATC
H is connected via a wire suspended to H. On the other hand, in the fourth embodiment, the redundancy circuit 13 and the spare decoder 17 include two comparison circuits 3
NAND gate circuit 92 to which the outputs of the two are respectively input
Is connected via the.

As described above, the outputs of the plurality of comparison circuits 32 included in the redundancy circuit 13 may be input to the logic gate circuit, and the output of the logic gate circuit may be input to the spare decoder 17.

Next, a fifth embodiment of the present invention will be described.

The fifth embodiment relates to the arrangement of fuses included in defective address storage circuit 11.

In the semiconductor integrated circuit device according to the present invention,
In addition to the redundancy circuit 13, a defective address storage circuit 11 for storing defective address information is provided in a chip. The defective address storage circuit 11 has a PROM circuit that stores defective address information. The PROM element included in the PROM circuit is a fuse, for example, a laser blow fuse or a current blow type fuse.

The number of fuses can be reduced as compared with other PROM elements such as a variable threshold type transistor because a write circuit is not required. On the other hand, the fuse requires a very large space, generates an area where wiring is impossible, and makes wiring layout difficult.

In order to solve such a situation, the fuse 21 of the defective address storage circuit 11 is not disposed in a region in a cell array or a region near a memory peripheral circuit as in the related art. To be placed away from For example, in the first embodiment, the fuse 21 of the defective address storage circuit 11 is arranged near the region 5 where the pad 4 is arranged or at the edge of the chip. Such a region is a region where the number of circuit elements such as transistors included in an integrated circuit is smaller than that of a region in a cell array or the like. In such a region, there is room in area, and it is possible to devise the arrangement of the fuse.

Therefore, the fifth embodiment has an object to realize a fuse arrangement in which blow errors are less likely to occur in the arrangement of fuses blown by a laser as compared with the related art.

FIG. 28 is a diagram showing the relationship between the fuse for redundancy and the moving direction of the laser beam in the semiconductor integrated circuit device according to the fifth embodiment of the present invention, and FIG.
8 is an enlarged view of a redundancy fuse, FIG. 30 is a diagram showing a relationship between a redundancy fuse of a conventional semiconductor integrated circuit device and a moving direction of a laser beam, and FIG. 31 is FIG.
FIG. 3 is an enlarged view of a fuse for redundancy of 0.

As shown in FIGS. 28 and 29, the pads 4 are where bonding wires and the like are bonded, and the pads 4 are separated from each other by a certain distance “d”.
Is arranged.

The pad 4 is for power supply, input / output,
For address input, row address strobe signal (/ RA
S) and a certain number for control signals such as a column address strobe signal (/ CAS). Therefore, the length of the row of pads 4 is sufficiently long. Further, the number of wirings in the periphery of the pad 4 is significantly smaller than that in the region in the cell array or the region near the memory peripheral circuit. Therefore, the defective address storage circuit 11, especially the fuse 21
Is arranged around the row of the pads 4, there is an advantage that layout restrictions are reduced when the fuses 21 are arranged. Furthermore, a sufficient space can be secured around the fuse 21, and for each fuse 21,
There is also an advantage that the floating well 184 shown in FIG. 40 can be easily provided.

The transfer of the defective address information from the defective address storage circuit 11 only needs to be performed once before the memory operation, and the speed is not required. Therefore, the defective address storage circuit 11 can be arranged around the pad 4 far from the row decoder (R / D).

Further, in the fifth embodiment, the arrangement described below is further applied to the arrangement of the fuses 21 along the rows of the pads 4. Fig. 2
8. As shown in FIG. 29, the long axis direction of the fuse 21 (the direction in which the blown portion extends) corresponds to the laser movement direction 17.
That is, the fuses 21 are arranged in a line so as to match 0. FIGS. 30 and 3 show a conventional example relating to the arrangement of the fuse 21. FIG.
It is shown in FIG. In the conventional example, the long axis direction of the fuses 21 is arranged in a line perpendicular to the laser movement direction 170.
This is because there is a demand to make the row of the fuses 21 compact because the fuses 21 are arranged beside the decoder. In the fuse arrangements shown in FIGS. 30 and 31, the rows of the fuses 21 are compact. On the other hand, the width "d1" of the blown portion of the fuse 21 and the blown width in the laser moving direction 170 are reduced. Since the distance "d0" between the portions becomes smaller, if the laser moves excessively, another fuse adjacent to the blown fuse is damaged, that is, a so-called misblow occurs. If a misblow occurs, the product will no longer be rescued, thus reducing the yield. For this reason, the blow position must be adjusted with very high accuracy. It takes a relatively long time to adjust the blow position with high accuracy. Therefore, speeding up of the blowing process is hindered, and production efficiency is reduced.

FIG. 2 shows that such a problem can be solved.
8, the fuse arrangement shown in FIG. According to this arrangement, the width “d1” of the blown portion of the fuse 21 and the distance “d0” between the blown portions can be separated from each other, so that even if the laser moves excessively, the misblow will not occur. Less likely to happen. Also, the alignment accuracy of the blow position is not required as much as the apparatus shown in FIGS. Therefore, the speed of the blowing step can be increased, and the production efficiency can be increased as compared with the apparatus shown in FIGS.

In the DRAM according to the present invention, the test for detecting the address of the defective cell is performed with the transfer timing signal FDX set to the "L" level. The defective address information obtained by the test is recorded on the tester at any time during the test. The fuse 21 is blown according to the recorded defective address information, and the defective address information is programmed in the defective address storage circuit 11.

Next, a sixth embodiment of the present invention will be described.

FIG. 32 shows a 64MD according to the sixth embodiment.
FIG. 33 is an enlarged plan view showing the vicinity of the 16M core shown in FIG. 32.

The area of the defective address storage circuit 11 where the fuse 21 is particularly arranged is not only located at the edge of the chip but also in a DRAM employing the center pad method, as shown in FIGS. 32 and 33, for example. , Chip 2
01 may be modified so as to be arranged in the pad arrangement area 205 existing in the center. 32 and 33, the region where the fuse 21 is arranged is indicated by reference numeral “RFUS”.
32. In FIG. 32 and FIG. 33, reference numeral 202 indicates a 1M block of a 64MDRAM.

Further, as shown in FIG. 33, the area where the redundancy circuit 13 including the associative memory is arranged is not required to be set for each row decoder (R / D), and is not adjacent to each other. It may be set as a shared area between two row decoders (R / D). As described above, by sharing the area where the redundancy circuit 13 is arranged with a plurality of row decoders (R / D) adjacent to each other, the area where the redundancy circuit 13 is arranged can be reduced from above the chip.

In the sixth embodiment, as shown in FIG. 33, a region where the redundancy circuit 13 is disposed and a region where the redundancy circuit 13 is not disposed repeatedly appear for every two row decoders (R / D). It has a pattern. Although such a pattern has a low effect of reducing the chip area, other circuits can be arranged in a region where the redundancy circuit 13 is not arranged. In this area, for example, DR
This new circuit can be arranged, for example, when it is necessary to set up a new circuit for advanced functions of the AM.

As described above, the arrangement pattern of the sixth embodiment has an effect that a new circuit can be mounted without increasing the chip area.

[0205]

As described above, according to the present invention, a semiconductor integrated circuit device having a redundancy circuit for storing defective address information by a volatile storage circuit has a more practical configuration. Can be provided.

Further, the size of a circuit for storing the basic information given to the volatile storage circuit can be reduced, and a semiconductor integrated circuit device having a configuration suitable for higher integration can be provided.

Further, the size of the integrated circuit type storage circuit included in the redundancy circuit can be reduced, and a semiconductor integrated circuit device having a configuration suitable for higher integration can be provided.

Further, it is possible to provide a semiconductor integrated circuit device in which a fuse for storing defective address information can be provided in the defective address storage circuit with a reduced possibility of occurrence of misblow.

Further, it is possible to provide a semiconductor integrated circuit device in which a defective address storage circuit can be provided in a semiconductor chip without hindering high integration of an integrated circuit and multilayer wiring.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the 2M cell array shown in FIG.

FIG. 3 is a diagram showing the 256k sub-array shown in FIG. 1 and its periphery, and FIG. 3 (A) is a configuration diagram showing the configuration;
3B is a diagram illustrating an address buffer, and FIG. 3C is a diagram illustrating a defective address storage circuit.

FIG. 4 is a circuit diagram showing a redundancy circuit and a defective address storage circuit of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a relationship between a logic of a row address and a selected word line;

FIG. 6 is a diagram illustrating a relationship between a state of a fuse and a word line to be replaced;

7A and 7B are diagrams showing a structure of the redundancy circuit according to the first embodiment of the present invention, wherein FIG. 7A is a plan view of the redundancy circuit and its vicinity, and FIG. 7B is a diagram of FIG. 7A
Sectional drawing which follows the -7A line.

FIG. 8 is a block diagram showing a first relationship between a defective address storage circuit and a subarray of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 9 is a block diagram showing a second relationship between the defective address storage circuit and the sub-array of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 10 is a block diagram showing a third relationship between the defective address storage circuit and the subarray of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 11 is a block diagram showing a fourth relationship between the defective address storage circuit and the sub-array of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 12 is a circuit diagram showing a redundancy circuit and a defective address storage circuit of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 13 is a diagram illustrating a relationship between logic of a row address and a selected word line;

FIG. 14 is a diagram showing a relationship between a state of a fuse and a word line to be replaced;

FIG. 15 is a block diagram showing a relationship between a defective address storage circuit and a sub-array of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 16 is a circuit diagram showing a redundancy circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 17 is a circuit diagram showing a defective address storage circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIGS. 18A to 18D are circuit diagrams each showing a ROM circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIGS. 19A to 19D are circuit diagrams each showing a ROM circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 20 is a diagram showing the relationship between the contents of a ROM and subarray numbers.

FIG. 21 is a diagram showing a relationship between a state of a fuse and a selected sub-array.

FIG. 22 is a diagram showing a relationship between a logic of a row address and a selected word line;

FIG. 23 is a diagram showing a relationship between a state of a fuse and a word line to be replaced;

FIG. 24 is a circuit diagram showing a redundancy circuit, a defective address storage circuit, and a transfer circuit of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 25 is an operation waveform diagram showing a transfer operation of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

FIG. 26 is a diagram showing the relationship between the logic of a row address and a selected word line;

FIG. 27 is a diagram showing a relationship between a state of a fuse and a word line to be replaced;

FIG. 28 is a view showing a relationship between a fuse for redundancy and a moving direction of a laser beam in a semiconductor integrated circuit device according to a fifth embodiment of the present invention;

FIG. 29 is an enlarged view of the redundancy fuse of FIG. 28;

FIG. 30 is a diagram showing a relationship between a fuse for redundancy and a moving direction of a laser beam in a conventional semiconductor integrated circuit device.

FIG. 31 is an enlarged view of the redundancy fuse of FIG. 30;

FIG. 32 is a plan view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 33 is a plan view of the 16M core block shown in FIG. 32;

FIG. 34 is a plan view of a conventional semiconductor integrated circuit device.

FIG. 35 is a plan view of the 2M cell array shown in FIG. 34;

FIG. 36 is a diagram showing the 256k sub-array shown in FIG. 34 and its periphery, FIG. 36 (A) is a diagram showing the configuration, and FIG.

FIG. 37 is a circuit diagram showing a conventional redundancy circuit.

FIG. 38 is a diagram showing the relationship between the logic of a row address and a selected word line;

FIG. 39 is a diagram showing a relationship between a state of a fuse and a word line to be replaced;

40A and 40B are diagrams showing the structure of a conventional redundancy circuit. FIG. 40A is a plan view of the redundancy circuit and its vicinity, and FIG. 40B is a cross section taken along line 40B-40B in FIG. FIG.

FIG. 41 is a diagram showing another conventional semiconductor integrated circuit device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Chip, 2 ... 2M cell array, 3 ... 1M cell array, 4 ... Pad, 5 ... Area where pad is arranged, 6 ... 256k sub-array, 7 ... Area where sense amplifier, equalizer, column gate is arranged, 8 ... Row Decoder, area where redundancy circuit is arranged, 11: defective address storage circuit, 12: multiplex circuit, 13: redundancy circuit, 14: address buffer, 15: main row decoder, 16: regular part, 17: spare row decoder , 18 spare parts, 19 internal address line, 20 resistance, 21 fuse, 22 NMOS, 24 NMOS, 30 register circuit, 31 write gate circuit (positive phase write gate circuit), 32 ... Comparison circuit, 33: anti-phase side write gate circuit, 60: wiring, 61: selector 70: ROM circuit, 71: comparison circuit, 72: replacement information line, 80: register circuit, 81: write gate circuit, 181: P-type silicon substrate, 182: P-type well, 183: N-type well, 201: chip, 202: 1M block; 204: pad; 205: area where pads are arranged.

Claims (11)

[Claims] A semiconductor chip having a memory function; a memory cell array provided in the chip and including a main row / column and a spare row / column; and a main row / column provided in the chip. A defective address storage circuit that stores therein defective address information by a non-volatile storage circuit; and a copy of the defective address information provided in the chip and stored in the defective address storage circuit. A redundancy circuit for storing, a circuit provided in the chip, for selecting the main row / column in accordance with an address input, and the spare row / column in accordance with the copy information stored in the redundancy circuit; Deco including a spare selection circuit to select a row / column instead of a row And a transfer circuit provided in the chip and configured to transfer the defective address information stored in the defective address storage circuit to a volatile storage circuit of the redundancy circuit in accordance with a transfer timing signal. A semiconductor integrated circuit device characterized by the above-mentioned. 2. The semiconductor integrated circuit device according to claim 1, wherein the defective address storage circuit includes, as a nonvolatile storage element, a fuse element that can be cut by any one of a laser beam and a current. 3. The defective address storage circuit includes a resistor, a fuse element, and a fourth insulated gate FET connected in series between power supplies, the gate having the gate receiving the transfer timing signal. 3. The method according to claim 2, wherein a fourth insulated gate type FET is turned off and the defective address storage circuit is deactivated except when a signal designates a mode for transferring the defective address information. 3. The semiconductor integrated circuit device according to 1. 4. The redundancy circuit, as a volatile storage element, compares a register circuit storing the copy information with a potential level of the copy information and a potential level of the address input, and determines whether these potentials match. 4. The semiconductor integrated circuit device according to claim 1, further comprising: a comparison circuit that changes an input level to the spare selection circuit in response to one of the mismatches. 5. 5. The redundancy circuit is connected to an input of the spare selection circuit via a wiring suspended to a matching potential, and the comparison circuit is configured to determine a potential level of the copy information and an address of the address input. 5. The semiconductor integrated circuit according to claim 4, wherein a potential level is compared with the potential level, and the potential of the wiring is changed to a potential other than the matching potential in accordance with one of these potentials. apparatus. 6. The register circuit and the comparison circuit are constituted by MOSFETs, and the register circuit and the comparison circuit are of an N-channel type.
When an OSFET is included, these N-channel MOSFETs
T is an N-channel MOSFE of the address decoder.
T is formed in a well where T is formed, and the register circuit and the comparison circuit are P-channel type M
When an OSFET is included, these P-channel MOSFETs
T is a P-channel MOSFE of the address decoder.
The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is formed in a well in which T is formed. 7. The transfer timing signal is triggered by turning on the power of the semiconductor integrated circuit device.
4. A mode for transferring the defective address information is designated, and after the copying of the defective address information to the redundancy circuit is completed, the designation of the mode for transferring the defective address information is released. The semiconductor integrated circuit device according to claim 6. 8. A semiconductor chip having a memory function, a cell array provided in the chip, a sub-array set in the cell array and including a main row / column and a spare row / column, respectively, A defective address storage circuit provided in the chip for storing the defective information of the sub-array and the defective address information in the main row / column respectively, and a non-volatile storage of the sub-array information provided in the chip. Circuit, and copy information of the defective address information stored in the defective address storage circuit,
A redundancy circuit stored in a volatile storage circuit, a circuit provided in the chip, for selecting the main row / column according to an address input, and the spare row according to the copy information stored in the redundancy circuit. An address decoder including a spare selection circuit for selecting a row / column by changing the row / column to the main row / column; and an address decoder provided in the chip and stored in the defective address storage circuit according to a transfer timing signal. The failure information is compared with the sub-array information stored in the redundancy circuit, and as a result of the comparison, of the redundancy circuits, in the volatile storage circuit of the redundancy circuit of the sub-array that matches the failure information of the sub-array, A transfer circuit for transferring the defective address information; The semiconductor integrated circuit device characterized by comprising. 9. A semiconductor chip having a memory function, a memory cell array provided in the chip and including a main row / column and a spare row / column, and the main row / column provided in the chip A redundancy circuit provided in the chip for storing defective address information therein as information corresponding to an address pair and storing the information by a flip-flop type storage circuit provided for each address pair; A circuit for selecting a column, and an address decoder including a spare selection circuit for selecting the spare row / column by replacing the spare row / column with the main row / column in accordance with the copy information stored in the redundancy circuit. A semiconductor integrated circuit device characterized by the above-mentioned. 10. The defective address storage circuit includes a plurality of fuses for storing defective address information, and each of the fuses has a major axis direction corresponding to a direction in which a laser for blowing the fuse moves. 9. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged so as to be arranged. 11. The semiconductor integrated circuit device according to claim 1, wherein said defective address circuit is arranged along a row of pads.