JP3560428B2 - Output buffer circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an output buffer circuit. In particular, the present invention relates to an output buffer circuit having improved signal transfer characteristics.
[0002]
[Prior art]
When configuring an electronic device, a technique of configuring an electronic device by mounting a plurality of semiconductor chips on a predetermined board and connecting the plurality of semiconductor chips by wiring on the board is widely used. I have.
[0003]
As described above, when a plurality of semiconductor chips are mounted on a board, a signal line connection using so-called bus wiring is used in wiring between each semiconductor chip and each chip or between a certain board and another boat. May be used. Such a bus wiring is also used between electronic devices.
[0004]
Such a bus wiring is often used for multi-bit data lines and the like, and in such a bus wiring, it is desirable that the signal transmission characteristics of each signal line constituting the bus be the same. FIG. 5 is a conceptual diagram showing such a bus wiring. As shown in FIG. 5, a plurality of semiconductor chips, for example, LSI-1, LSI-2, and LSI-3 are mounted on the board 10. These semiconductor chips are mutually connected by a signal line of a bus 12.
[0005]
[Problems to be solved by the invention]
There is a case where a part of a signal line constituting such a bus line is pulled up or down by an external resistance element. FIG. 6 shows an example in which a part of the bus wiring is pulled up by the resistance element, for example, as described above. In the example of FIG. 6, one wiring constituting the bus is pulled up by the pull-up resistor 14.
[0006]
As described above, only some of the signal lines are pulled up, depending on the bus standard, there may be a case where it is required to pull up one signal line based on the purpose of detecting an operation state or the like. Because. Such standards include a PCI bus standard, an ISA bus standard, and other standards. In such a standard, as shown in FIG. 6, only some of the bus lines are pulled up for the purpose of identifying the operation state (often called a mode) of the electronic device. There are cases where provisions have been made to require the user to pull down or pull down.
[0007]
On the other hand, as described above, it is desirable that the wires constituting the bus have the same signal transmission characteristics. However, as shown in FIG. 6, when only a part of the signal line constituting the bus wiring is pulled up by an external resistor, the transmission characteristic of the signal line depends on the presence or absence of the external resistance element. There is a problem that the signal wiring is different from the signal wiring.
[0008]
The manner in which the signal transfer characteristic changes depending on the presence or absence of the external resistance element will be described below.
[0009]
For example, a circuit diagram of a conventional typical output buffer is shown in FIG. As shown in FIG. 7, the output buffer 20 has two inverters 22 and 24 for receiving an input signal. The output signal of the inverter 22 is supplied to the gate terminal of the PMOS transistor M1, and the output signal of the inverter 24 is supplied to the gate terminal of the NMOS transistor M2. The PMOS transistor M1 is connected to the power supply Vdd side, and the NMOS transistor M2 is connected to the ground side. The output signal is extracted from the connection point between the PMOS transistor M1 and the NMOS transistor M2. Further, the two transistors M1 and M2 have a so-called CMOS configuration.
[0010]
The output signal of the output buffer 20 is supplied to an external bus. In FIG. 7, an external capacitor C1 and a pull-up resistor R1 are shown as an equivalent circuit of a signal line of the bus.
[0011]
The signal waveform of each part in the output buffer 22 as shown in FIG. 7 is shown in the graph of FIG. Hereinafter, the operation of the output buffer 20 will be described with reference to FIGS.
[0012]
Normally, in order to extract a large output current from the output buffer 20, a large transistor is used for both the PMOS transistor M1 and the NMOS transistor M2. Since both transistors M1 and M2 have a large current, it is necessary to prevent a case where both transistors are simultaneously turned on. This is because if the PMOS transistor M1 and the NMOS transistor M2 are simultaneously turned on, an extremely large through current will flow from the power supply Vdd to the ground, causing noise and malfunction. In particular, since both transistors M1 and M2 are large in size, the influence is large.
[0013]
Therefore, when the output signal of the output buffer 20 changes from "L" to "H", the NMOS transistor M2 shifts from the ON operation to the OFF operation, and then the PMOS transistor M1 shifts from the OFF operation to the ON operation. Must transition. That is, when the output signal Vout of the output buffer 20 changes from “L” to “H”, a moment occurs when both the PMOS transistor M1 and the NMOS transistor M2 are turned off. Therefore, when the pull-up resistor R1 is connected to the output terminal 26 of the output buffer 20, the following waveform changes occur as compared with the case where the pull-up resistor R1 is not connected. I will.
[0014]
First, as shown in the graph of FIG. 8A, the input signal Vin changes from “L” to “H” with time. In this graph, the horizontal axis represents time, and the vertical axis represents signal voltage. Similarly, in the following graphs, the horizontal axis represents time, and the vertical axis represents voltage. The time axes of the graphs (1) to (4) in FIG. 8 are all aligned and displayed. As the input signal changes from “L” to “H” as shown in the graph of FIG. 8A, the output signal of the inverter 24 is changed as shown in the graph of FIG. Changes from “H” to “L”. Accordingly, the NMOS transistor M2 which has supplied the output level "L" of the output buffer 20 shifts to the OFF operation.
[0015]
The timing at which the NMOS transistor M2 is turned off is represented by "M2OFF" in FIG. 8 (2). At the timing when the NMOS transistor M2 turns off, the PMOS transistor M1 has not yet turned on. The timing at which the PMOS transistor M1 shifts to the ON operation is shown in the graph of FIG.
[0016]
The graph of FIG. 8C shows a change in the output signal Vn1 of the inverter 22. The output signal Vn1 of the inverter 22 shifts from "H" to "L" later than the output signal Vn1 of the inverter 24. As a result, as can be understood from FIGS. 8 (2) and (3), the PMOS transistor M1 shifts to the ON operation with a predetermined time delay after the NMOS transistor M2 shifts to the OFF operation.
[0017]
However, when the pull-up resistor R1 is connected to the output terminal 26 and the NMOS transistor M2 is turned off, the PMOS transistor M1 is turned on by the charging current from the pull-up resistor R1 to the external capacitor C1. Even if it is not operating, the potential of the output terminal 26 rises. Therefore, when there is a pull-up resistor R1 as indicated by A in FIG. 8D, the signal waveform rises before the PMOS transistor M1 turns on. When a predetermined time has elapsed and the PMOS transistor M1 shifts to the ON operation, the charging current to the external capacitor C1 is supplied not only from the pull-up resistor R1 but also from the PMOS transistor M1. Therefore, as shown by B in FIG. 8 (4), the slope (change rate) of the signal waveform at the output terminal 26 changes.
[0018]
Therefore, as a result, as shown in the graph of FIG. 8D, when there is the pull-up resistor R1, there is a problem that a step occurs in the output waveform of the output buffer 20. In FIG. 8D, the signal waveform when there is no pull-up resistor R1 is shown by a solid line, and the signal waveform when there is a pull-up resistor R1 is shown by a broken line.
[0019]
As described above, since the timing at which the NMOS transistor M2 turns off and the timing at which the PMOS transistor M1 turns on do not completely match, the charging current to the external capacitor C1 is determined only by the pull-up resistor R1. Two periods, that is, the case where the charge is performed by both the up resistor R1 and the PMOS transistor M1, occur, and the change rate of the waveform, that is, the slope is changed in both periods. As a result, as described in the graph of FIG. 8D, a step occurs in the output waveform.
[0020]
As described above, in the circuit configuration of the conventional output buffer, there has been a problem that the signal transmission characteristic changes depending on the presence or absence of the external resistance element.
[0021]
The present invention has been made in view of such a problem, and an object of the present invention is to provide an output buffer circuit capable of substantially simultaneously performing signal transmission characteristics regardless of the presence or absence of an external resistance element connected to an output terminal. That is.
[0022]
[Means for Solving the Problems]
Basically, the present invention solves the above-mentioned problem by turning off an NMOS (or PMOS) transistor at the moment when a PMOS (NMOS) transistor in a final output stage is turned on, thereby reducing external resistance. The present invention proposes a method for making the difference in transmission characteristics substantially the same depending on the presence or absence of an element.
[0023]
In order to realize such a thing, various measures can be considered. First, it is conceivable to take measures to compensate for the change in the electrical characteristics in anticipation of the change in the electrical characteristics of the transistor due to the insertion of the pull-up resistor. However, it is difficult to accurately predict what kind of change in electrical characteristics will occur.
[0024]
The present invention employs the following means in order to perform the ON operation of the PMOS transistor almost simultaneously with the OFF operation of the NMOS transistor.
[0025]
The present invention provides a positive-side final-stage transistor, a negative-side final-stage transistor,
An output buffer circuit including a driver circuit for exclusively driving the positive-side last-stage transistor includes the following configuration.
[0026]
That is, the present invention relates to a transistor having a threshold value similar to that of the positive-side final-stage transistor, wherein the positive-side monitoring transistor driven by the driver circuit in the same manner as the positive-side final-stage transistor; Negative-side last-stage transistor control means for permitting the negative-side last-stage transistor to be turned off only when it is detected that the monitoring transistor is turned on, and operation similar to that of a normal output buffer in the case of on-operation An output buffer circuit characterized by including a negative-side final-stage transistor control means for performing the following.
[0027]
The positive-side monitoring transistor is a transistor of the same type as the positive-side final-stage transistor. By driving this positive-side monitoring transistor with a driver circuit in the same manner as the positive-side final-stage transistor, the same as the positive-side final-stage transistor is used. The operation can be performed by the positive side monitoring transistor.
[0028]
Therefore, if the positive-side monitoring transistor is turned on, it is determined that the positive-side last-stage transistor is also turned on. Therefore, if the negative last stage transistor is turned off after the positive monitoring transistor is turned on, the ON operation of the positive last stage transistor and the OFF operation of the negative last stage transistor can be performed at the same timing.
[0029]
Further, the present invention provides a positive-side final-stage transistor, a negative-side final-stage transistor,
An output buffer circuit including a driver circuit that exclusively drives the negative-side last-stage transistor includes the following configuration.
[0030]
That is, the present invention provides a transistor having a threshold value similar to that of the negative-side last-stage transistor, wherein the negative-side monitoring transistor driven by the driver circuit in the same manner as the negative-side last-stage transistor; Positive-side last-stage transistor control means for permitting the positive-side last-stage transistor to turn off only when it detects that the monitoring transistor is to be turned on; An output buffer circuit characterized by including a positive-side final-stage transistor control means for performing the following.
[0031]
In the above invention, the monitoring transistor is provided on the positive side, but it may be provided on the negative side. In the present invention, a monitoring transistor is provided on the negative side, and the operation and effects thereof are substantially the same as those of the present invention described above, except that the polarity is different.
[0032]
Further, the present invention is characterized in that the output buffer circuit including the positive-side last-stage transistor and the negative-side last-stage transistor includes the following configuration.
[0033]
That is, the present invention relates to a transistor having a threshold value similar to that of the positive-side final-stage transistor, wherein the positive-side monitoring transistor is driven in the same manner as the positive-side final-stage transistor; A negative-side monitoring transistor that has a similar threshold value and is driven in the same manner as the negative-side last-stage transistor; and the negative-side monitoring transistor only when it is detected that the positive-side monitoring transistor is turned on. Negative-side final-stage transistor control means for permitting the last-stage transistor to perform an OFF operation; negative-side last-stage transistor control means for performing the same operation as a normal output buffer in the case of an ON operation; Only when the ON-operation is detected, the positive-side last-stage transistor that permits the OFF operation of the positive-side last-stage transistor is enabled. A stage transistor control means, an output buffer circuit which comprises a positive-side final-stage transistor control means for the normal output buffer and the same operation in the case of ON operation.
[0034]
The present invention described above has a monitoring transistor provided on the positive side, and the present invention further provides a monitoring transistor on the negative side. The present invention provides a monitoring transistor on both the positive side and the negative side, and achieves all the functions and effects of the present invention at the same time.
[0035]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0036]
FIG. 1 is a circuit diagram of an output buffer circuit according to a preferred embodiment of the present invention. The input signal Vin is inverted by the inverter 32 to generate Vn1. The inverted signal Vn1 is further inverted by the inverter 34 to become Vn2. This signal Vn2 is again inverted by the inverter formed by the transistors M3 and M4, and a signal of Vn3 is generated, and this Vn3 is supplied to the PMOS transistor M1 on the positive side. Therefore, a signal inverted from the input signal Vin is basically applied to the PMOS transistor M1. This is the same as the conventional output buffer circuit 20 shown in FIG.
[0037]
A characteristic of the present embodiment is that Vn3, which is a signal supplied to the PMOS transistor M1, is also applied to the PMOS transistor M7. The transistor M7 is a PMOS transistor having the same characteristics as the transistor M1. The transistor M7 has the same characteristics as the transistor M1 which is the last transistor on the positive side, and corresponds to the positive monitoring transistor in the present invention.
[0038]
What is characteristic in this embodiment is that a transistor having the same characteristics as the last-stage transistor is separately provided as described above, and that the monitoring transistor (PMOS transistor M7) is turned on to detect the ON state of the transistor. This is to indirectly detect that M1 has been turned ON. Then, after the monitoring transistor (PMOS transistor M7) is turned ON, the NMOS transistor M2, which is the last transistor on the negative side, is turned OFF. Therefore, the ON operation of the transistor M1 and the OFF operation of the transistor M2 can be performed at substantially the same timing, and the change in waveform between when the external pull-up resistor R1 is connected and when it is not connected is small. It is possible to do. FIG. 2 shows a graph of main signal waveforms of the output buffer circuit 30 shown in FIG.
[0039]
The operation of the output buffer circuit 30 shown in FIG. 1 will be described in detail with reference to the signal waveform graph shown in FIG.
[0040]
The operation when the output signal Vin changes from “L” to “H” as shown in the graph of FIG. 2A will be described. In the graph of FIG. 2A, the vertical axis represents the signal voltage, and the horizontal axis represents time. The same applies to other graphs included in FIG.
[0041]
When the input signal becomes “H”, the output signal of the inverter 32 changes from “H” to “L” accordingly. A graph of the output signal Vn1 of the inverter 32 is shown in FIG. As described above, when the signal Vn1 changes from “H” to “L”, the PMOS transistor M8 is turned on and the NMOS transistor M9 is turned off. That is, the transistors M8 and M9 constitute an inverter. However, at the timing when the signal Vn1 changes to “L”, since the transistor M7 is in the OFF operation, the output signal Vn4 of the inverter including the transistors M8 and M9 still maintains “L”. It is not "H". Next, the output signal of the inverter 34 changes from "L" to "H" as Vn1 becomes "H". The graph of Vn2, which is the output signal of the inverter 34, is shown in FIG. Thus, as the signal Vn2 becomes “H”, the PMOS transistor M5 is turned off. Similarly, the PMOS transistor M3 turns off and the NMOS transistor M4 turns on. The transistors M3 and M4 form an inverter, and the output signal Vn3 of the inverter is a signal obtained by inverting the signal Vn2. Therefore, when the signal Vn2 becomes "H", the signal of "L" becomes Become. A graph of the signal Vn3 is shown in FIG.
[0042]
Thus, when the signal Vn3 changes from “H” to “L”, both the PMOS transistor M1 as the last transistor on the positive side and the transistor M7 as a transistor of the same type as the transistor M1 are turned on.
[0043]
When the PMOS transistor M7 is turned on, the signal Vn4 changes from "L" to "H" immediately after that. The transistor M8 is turned on in advance as described above, and the transistor M9 is turned off in advance as described above. As a result, the signal Vn4 quickly changes from "L" to "H" as the transistor M7 turns on. A graph showing such a change in the signal Vn4 is shown in FIG. It can be understood from this graph that the rising of the signal Vn4 is fast. As the signal Vn4 becomes “H”, the transistor M6 shifts to the ON operation.
[0044]
As described above, since the transistor M5 has already been turned off, the signal Vn5 quickly changes from "H" to "L" as the transistor M6 is turned on. A graph showing the change of the signal Vn5 is shown in FIG. The signal Vn5 is a combined output of the transistor M5 and the transistor M6, but since the transistor M5 has been turned off in advance, the waveform has a rapidly falling waveform as shown in FIG.
[0045]
When the signal Vn5 falls and its value becomes "L", the NMOS transistor M2, which is the last transistor on the negative side, is turned off for the first time.
[0046]
A characteristic of this embodiment is that a transistor M7 of the same type as the transistor M1 which is the last transistor on the positive side is provided. Then, after the transistor M7 is turned on, the negative-side last-stage transistor M2 is turned off. Therefore, in the conventional output buffer circuit, the transistor M2 is turned off before the transistor M1 is turned on. However, in the output buffer circuit 30 of the present embodiment, it is confirmed that the transistor M1 is turned on. Thus, the OFF operation of the transistor M2 is permitted.
[0047]
As a result, in the output buffer circuit 30 according to the present embodiment, the case where the transistors M1 and M2 are simultaneously turned off does not occur. Therefore, even when the pull-up resistor R1 is connected to the output terminal of the output buffer circuit 30, the ON resistance of the NMOS transistor M2, which is the last transistor on the negative side, is much smaller than the pull-up resistor R1. The output signal Vout does not increase until the last transistor M2 on the side performs the OFF operation. This situation is shown in the graph of FIG.
[0048]
As described above, the output buffer circuit 30 according to the present embodiment does not turn off the negative-side transistor M2 immediately after the rise of the input signal, but waits for the positive-side transistor M1 to turn on. It was turned off. Therefore, when only the charging current from the pull-up resistor R1 is supplied to the external capacitor C1 as in a conventional output buffer circuit, the external capacitor C1 is charged from both the pull-up resistor R1 and the positive-side last-stage transistor M1. There is no two periods, and a current always flows into the external capacitance C1 from both the pull-up resistor R1 and the PMOS transistor M1. Therefore, as shown in FIG. 2 (7), it is possible to always maintain the same signal waveform regardless of the presence or absence of the pull-up resistor R1.
[0049]
As described above, in the present embodiment, since the last-stage transistor M2 is not turned off and then the positive-side last-stage transistor M1 is turned on, the case where both the transistors M1 and M2 are momentarily turned on. Occurs. However, at such a moment, since the ON resistance of the transistor M1 is still large, it is considered that the through current flowing through the transistors M1 and M2 can be suppressed to a not so large value.
[0050]
As described above, the gate signal Vn3 of the PMOS transistor M1 at the output final stage is also supplied to the gate of the transistor M7, which is a transistor similar to the transistor M1, and the operation of the transistor M7 causes the negative final stage. The gate signal of the transistor M2 which is the output transistor is controlled.
[0051]
Therefore, it is possible to keep the through current flowing through both the transistor M1 and the transistor M2 to a minimum value and to suppress a change in the output waveform due to the pull-up resistor R1.
[0052]
In the embodiment described above, even if the pull-up resistor R1 is connected to the output terminal, the gate signal of the negative last transistor M2 is controlled by the gate signal of the PMOS last transistor M1 in the output last stage. By doing so, it is possible to obtain an effect that the transmission characteristics are made almost simultaneously regardless of the presence or absence of the pull-up resistor R1.
[0053]
Another embodiment of the present invention
In the above-described embodiment, a transistor M7 similar to the PMOS transistor M1 which is the last transistor on the positive side is provided, and the ON operation of the last transistor M2 on the negative side is maintained until the transistor M1 is turned ON. Things. It is also conceivable that a transistor having the same operation as that of the last transistor M2 on the negative side is separately provided, and the transistor M2 is turned on before the transistor M1 on the positive side is turned off. Such an operation is effective when the input signal changes from "H" to "L", contrary to the graph shown in FIG. FIG. 3 shows a circuit diagram of the output buffer when such a configuration is employed. The circuit diagram shown in FIG. 3 has a configuration in which the positive side and the negative side are reversed from the circuit diagram shown in FIG. 1, and the operation is exactly the same in principle. However, the circuit shown in FIG. 3 is particularly effective when there is a pull-down resistor R1 unlike the circuit shown in FIG.
[0054]
Still another embodiment of the present invention
The output buffer circuit shown in FIG. 1 includes a monitoring transistor M7 having the same characteristics as the transistor M1 on the positive side. On the other hand, the output buffer circuit shown in FIG. 3 is provided with a transistor having characteristics similar to those of the last transistor on the negative side as a monitoring transistor.
[0055]
Therefore, a circuit configuration that simultaneously includes the configurations shown in FIGS. 1 and 3 is also conceivable. FIG. 4 shows a circuit diagram of an output buffer circuit in which monitoring transistors are provided on both the positive side and the negative side. As shown in FIG. 4, a transistor M10 is provided as a transistor having the same electric characteristics as the positive-side final-stage transistor M1, and a monitoring transistor having the same electric characteristics as the negative-side final-stage transistor M2. A transistor M9 is provided.
[0056]
As described above, since both the monitoring transistor on the positive side and the monitoring transistor on the negative side are provided, the output buffer circuit shown in FIG. 4 has a case where there is a pull-up resistor and a case where a pull-down resistor is connected. Can be supported. That is, the output buffer circuit shown in FIG. 4 can be said to be a circuit having the features and effects of the output buffer circuits shown in FIGS.
[0057]
【The invention's effect】
As described above, according to the present invention, the positive-side monitoring transistor having the same threshold value as that of the positive-side final-stage transistor is provided. Can be turned off, and an output buffer circuit capable of realizing constant transfer characteristics regardless of the presence or absence of an external resistance element can be obtained.
[0058]
According to the present invention, since the negative-side monitoring transistor having the same threshold value as the negative-side final-stage transistor is provided, the positive-side final-stage transistor is turned off at the moment when the negative-side final-stage transistor is turned on. It is possible. As a result, it is possible to make the transfer characteristics substantially the same regardless of the presence or absence of the external resistance element.
[0059]
According to the present invention, since all of the configurations of the present invention are included, substantially the same transfer characteristics are obtained in both the case where the pull-up resistor is connected to the output terminal and the case where the pull-down resistor is connected. Can be obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an output buffer circuit according to a preferred embodiment of the present invention.
FIG. 2 is a graph showing signal waveforms at various parts of the output buffer circuit shown in FIG.
FIG. 3 is a circuit diagram of an output buffer circuit having a polarity opposite to that of the output buffer circuit shown in FIG. 1 and corresponding to a pull-down resistor.
FIG. 4 is a circuit diagram of an output buffer circuit including both the configurations shown in FIGS. 1 and 3;
FIG. 5 is an explanatory diagram illustrating bus wiring of a semiconductor chip on a board.
FIG. 6 is an explanatory diagram illustrating an example in which one signal line in a bus line is pulled up by a pull-up resistor.
FIG. 7 is a circuit diagram of a conventional output buffer circuit.
8 is a graph showing signal waveforms at various parts of the conventional output buffer circuit shown in FIG.
[Explanation of symbols]
10 boards, 12 buses, 14 pull-up resistors, 20, 30 output buffer circuits, 22, 24, 32, 34 inverters, 26 output terminals.

Claims (3)

In an output buffer circuit including a positive-side final-stage transistor and a negative-side final-stage transistor, a driver circuit for driving the positive-side final-stage transistor and a transistor having a threshold value similar to that of the positive-side final-stage transistor A positive-side monitoring transistor driven by the driver circuit in the same manner as the positive-side final transistor, and the negative-side last-stage transistor is turned off immediately after detecting that the positive-side monitoring transistor is turned on. And a driver circuit for driving the negative-side last-stage transistor having a control function to perform the above operation. In an output buffer circuit including a positive-side final-stage transistor and a negative-side final-stage transistor, a driver circuit for driving the negative-side final-stage transistor and a transistor having a threshold value similar to that of the negative-side final-stage transistor A negative-side monitoring transistor driven by the driver circuit in the same manner as the negative-side last-stage transistor; and the positive-side final-stage transistor is turned off immediately after detecting that the negative-side monitoring transistor is turned on. And a driver circuit for driving the positive-side final-stage transistor having a control function to perform the above operation. An output buffer circuit including a positive-side final-stage transistor and a negative-side final-stage transistor, wherein the transistor has a threshold value similar to that of the positive-side final-stage transistor and is driven in the same manner as the positive-side final-stage transistor. And a driver for driving the negative last stage transistor having a control function of turning off the last negative stage transistor immediately after detecting that the positive side monitoring transistor is turned on. A circuit, a transistor having a threshold value similar to that of the negative-side last-stage transistor, wherein the negative-side monitor transistor is driven in the same manner as the negative-side last-stage transistor, and the negative-side monitor transistor is turned on. Immediately after detecting the above, before having a control function such that the positive-side final-stage transistor is turned off. Output buffer circuit which comprises a driver circuit for driving the positive side final-stage transistors.

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