JP3559599B2 - Signal processing device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a signal processing device, and more particularly to a signal processing device such as a digital filter with improved frequency characteristics.
[0002]
[Prior art]
At present, digital filters are widely used as filter circuits for audio devices, and band-limiting filter circuits such as FIR filters and IIR filters used in the field of TV cameras and VTRs.
[0003]
FIG. 11 shows an example of an N-order FIR digital filter. The sampled discrete input data X (nT) is delayed by one sample time (T) in each of the delay units 101, 102,..., 103. The input data and the outputs of the delay units 101, 102,..., 103 are respectively multiplied by predetermined multiplier coefficients h (0T), h (1T), h (2T) by multipliers 111, 112, 113,. ,..., H ((N−1) T), the outputs of the multipliers 111 and 112 are added by the adder 121, and the addition result is further added by the adder 122 to the output of the multiplier 113. . Then, the output of the multiplier 114 is added to the output of the immediately preceding adder to obtain an output y (nT). The frequency characteristic of the digital filter can be changed by changing the multiplication coefficient of the multiplier.
[0004]
FIG. 12 shows an example of an Nth-order IIR digital filter. The discrete input data X (nT) is delayed by one sampling time in each of the delay units 201, 202,..., 203, and the input data and the output of each of the delay units 201, 202,. , 212, 213,... 214 are multiplied by predetermined multiplication coefficients, respectively, added by the adder 221 and output to one input terminal of the adder 222. The output of the adder 222 is delayed by one sampling time in delay units 231, 232,..., 233, and each delayed output is multiplied by a predetermined multiplication coefficient in multipliers 241, 242,. After that, the signal is output to another input terminal of the adder 222. Thus, the output of the adder 222 is obtained as the digital filter output y (nT).
[0005]
The target performance items of the above-mentioned conventional digital filter include: (1) gain characteristics: increase the attenuation rate of a stop band, and steepen the approach of a pass band or a stop band (narrow the width of a transition band). (2) phase characteristics: reducing delay time difference between frequencies in a pass band; and (3) ringing characteristics: reducing the level and convergence time of ringing (false signal) generated at a frequency transition point of an input signal. There is.
[0006]
Generally, in a digital filter, it is necessary to add a differential component of an input signal to obtain an ideal gain characteristic, and a coefficient at a discrete time position corresponding to a desired frequency is set to a relatively large negative value. There is a disadvantage that the ringing level becomes large at the continuous points. For example, FIG. 14 shows an example of an output signal of a digital filter for the input signal shown in FIG.
[0007]
The input signal in FIG. 13 is represented by 12-bit digital data of 000H to FFFH, and the frequency is changed every predetermined time. For example, after a signal having a frequency of fs / 2 for a certain period of time is inputted, a signal of an intermediate level 800H is inputted, and subsequently, a signal having a slightly lower Fs / 3 is inputted. Similarly, a signal having a frequency of Fs / 4, Fs / 6, and Fs / 8 and a signal having an intermediate level of 800H inserted between the frequencies is input. In FIG. 13, at the frequency of Fs / 8, discrete levels such as 000H level L1, 300H level L2, 800H level L4, D00H level L6, and FFFH level L7 are output in order. 8 are repeatedly input. At the frequency Fs / 6, the level changes at a repetition frequency determined by Fs / 6 in the order of 000H level L1, 500H level L3, A00H level L5, and FFFH level L7.
[0008]
FIG. 14 shows an output obtained when the input signal shown in FIG. 13 is input to the digital filter. As is apparent from FIG. 14, a so-called rampage occurs in which the output level largely changes around a frequency change point, for example, an intermediate value (800H) inserted during the change from Fs / 8 to Fs / 6. ing. This rampage is called ringing. Similarly, similar ringing occurs between Fs / 8 and Fs / 6 and between Fs / 6 and Fs / 4.
[0009]
FIG. 15 shows an example of frequency characteristics (gain characteristics and delay characteristics) of a conventional FIR filter. In the vicinity of the band critical frequency f0, the gain and the delay amount sharply decrease. FIG. 16 also shows an example of the step response characteristic of the filter shown in FIG. This step response characteristic indicates a change in an output signal when a signal that changes from level 0 to level 1 and continues at level 1 is input.
[0010]
In FIG. 16, the portion that fluctuates before and after the timing at which the signal level changes is ringing. The magnitude of this ringing is expressed as a peak-to-peak. In this example, the ringing occurs at three sampling intervals for a peak from high to low.
[0011]
FIG. 17 shows an example of the multiplication coefficients H (0) to H (30) set in each of the 31 multipliers constituting the conventional FIR filter. H (0) indicates the multiplication coefficient at the input end, H (15) indicates the center multiplication coefficient, and H (30) indicates the multiplication coefficient at the output end. As shown in FIG. 17, the center multiplication coefficient has a positive value, but the three multiplication coefficients centered on positions four sampling times away therefrom are set to negative values. It causes ringing.
[0012]
Next, a design example of the IIR filter will be described. In general, an IIR filter can obtain good gain characteristics with a smaller number of taps and a lower-order configuration than an FIR filter. FIGS. 18 and 19 show frequency characteristics (gain characteristics and delay characteristics) and step response characteristics of the IIR filter similar to FIGS. 15 and 16.
[0013]
[Problems to be solved by the invention]
As shown in FIG. 18, in the IIR type filter, when the gain characteristic is improved, the delay characteristic is changed in a manner that the delay characteristic changes at every frequency. Such rampage causes ringing as shown in FIG. The IIR filter has a problem that ringing occurs and the time until convergence basically lasts indefinitely. That is, there is a problem that the convergence time of the ringing becomes long.
[0014]
On the other hand, since the FIR filter has a higher-order configuration than the IIR filter, that is, the number of taps increases, the differential coefficients are also arranged over other taps, and as a result, the convergence time of ringing becomes longer. There is a similar drawback.
[0015]
Conversely, if the ringing characteristic is emphasized, the gain characteristic is degraded. Therefore, even if the circuit scale is increased, it is inconsistent to bring both these characteristics close to ideal, and it is necessary to set a proper balance between the two characteristics. The current state of design.
[0016]
Therefore, an object of the present invention is to provide a signal processing device that suppresses the ringing level and shortens the convergence time during which the ringing fluctuation converges to improve the frequency characteristics.
[0017]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the signal processing device according to the present invention employs the following characteristic configuration.
(1) Digital filter means for performing a filtering process on an input digital signal, detection means for detecting the degree of change in the output signal of the digital filter means, and digital processing based on the output of the detection means. A ringing suppression unit configured to adaptively change a multiplier and perform a multiplication process on an output of the filter unit to suppress ringing related to an output of the digital filter unit.
(2) The detection means detects the degree of change in the signal to be detected based on the degree of change in the signal level of the output signal of the digital filter means at different points in time. 1) The signal processing device.
(3) Digital filter means for performing filtering processing on the input digital signal, detection means for detecting whether or not the frequency of the output signal of the digital filter means corresponds to the frequency of ringing to be suppressed, and this detection Ringing suppression means adapted to adaptively change the multiplier to the output of the digital filter means based on the output of the means and to perform a multiplication process to suppress ringing relating to the output of the digital filter means. Signal processing device.
(4) Digital filter means for performing a filtering process on the input digital signal, first detection means for detecting the degree of change in the signal level at different points in the output signal of the digital filter means, and the digital filter Second detection means for detecting whether or not the frequency of the output signal of the means corresponds to the frequency of ringing to be suppressed; and the digital filter means based on the output of the first detection means and the second detection means. A ringing suppressing means adapted to adaptively change the multiplier to perform a multiplication process to suppress ringing relating to the output of the digital filter means.
[0019]
[Action]
According to the present invention, ringing is suppressed by detecting a change in output signal of the digital filter and performing a multiplication process by adaptively changing a multiplier on the output of the digital filter based on the detection result. ing.
[0020]
【Example】
Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration block diagram of a signal processing device according to a first embodiment of the present invention.
[0021]
The input is represented by 12-bit digital data represented by two's complement to represent a negative number, and this input is inputted to the digital filter 1 having the above-described configuration. The multiplication coefficient set in the multiplier constituting the digital filter 1 is supplied from the coefficient setting circuit 2. The timing controller 3 supplies a clock fck for setting the discrete time axis and reference timing of the digital filter 1 to the multiplying circuit 5, multiplier decoder 6, and level difference detecting circuit 7, which will be described later, in addition to the digital filter 1.
[0022]
The output of the digital filter 1 is sent to the delay circuit 4 and the level difference detection circuit 7. The level difference detection circuit 7 detects a level difference at a different time every sampling time, and detects a level difference at each sampling interval corresponding to the frequency of the generated ringing. When the detected level difference is equal to or less than the maximum value at which ringing occurs (the maximum value of the ringing level), the level difference detection circuit 7 determines that the level difference has been detected to obtain a desired suppression level. To the multiplier decoder 6 to output the multiplier (constant) to the multiplier 5. For example, when the ringing level to be suppressed is suppressed to about 1/2, the constant output from the multiplier decoder 6 is 0.5. Here, at the time of detection, the reason that the level difference is equal to or less than the maximum value is that if the level difference is equal to or greater than the maximum value, the original signal component may be suppressed at a frequency lower than the ringing frequency.
[0023]
The output from the digital filter 1 is delayed by the delay circuit 4 by a time corresponding to the processing time in the level difference detection circuit 7 and sent to the multiplication circuit 5. The multiplication circuit 5 multiplies the signal delayed by the delay circuit 4 by the multiplier from the multiplier decoder 6 and outputs a signal in which the level difference of the ringing unit is suppressed as a digital signal.
[0024]
Next, a second embodiment of the signal processing device according to the present invention will be described with reference to FIG. In the drawings to be referred to hereinafter, components denoted by the same reference numerals as those in FIG. 1 are components having the same function.
[0025]
In the embodiment shown in FIG. 1, the level difference is detected by the level difference detection circuit 7 as a reference of the degree of suppression, whereas in the present embodiment, the changing frequency is detected by the frequency detection circuit 8. . More specifically, the frequency detection circuit 8 counts the number of clocks from the changing peak to the peak of the input signal to detect the changing frequency of the signal output from the digital filter 1, and counts the number of clocks counted. Is a code representing a frequency. The frequency detection circuit 8 also outputs to the multiplier decoder 6 when the detected frequency is the same as the frequency of the ringing to be suppressed. The multiplier decoder 6 receives the output from the frequency detection circuit 8 and supplies a multiplier (for example, 0.5 when suppressed to １ ／) to the multiplication circuit 5. The multiplier decoder 6 supplies a constant (for example, 1.0) when the output from the frequency detection circuit 8 is not received.
[0026]
A third embodiment of the signal processing device according to the present invention will be described with reference to FIG. In this embodiment, a frequency & level difference detection circuit 9 having both the level difference detection circuit 7 and the frequency detection circuit 8 in the first and second embodiments is provided. The frequency & level difference detection circuit 9 detects whether or not the change in the input signal is equal to or less than the maximum value of the level of the ringing to be suppressed and whether or not the change corresponds to the frequency of the ringing to be suppressed. Supplies the result of
[0027]
Next, a specific configuration example of the level difference detection circuit 7 and the multiplier decoder 6 shown in FIG. 1 will be described with reference to FIG.
[0028]
The output from the digital filter 1 is latched by sampling flip-flops 31 and 32 one sampling time interval in response to the reference clock fck. The subtraction circuit 33 subtracts the outputs from the D flip-flops 31 and 32 as data which is temporally adjacent to each other and shifted by one clock. This assumes that the frequency of the ringing to be suppressed occurs for each pixel. The absolute value of the subtraction output is output from the subtraction circuit 33, sampled and held by the D flip-flop 34 in response to the reference clock, and supplied to the ROM 35 corresponding to the multiplier decoder 6. In the ROM 35, suppression data for each level difference data, such as whether the level difference data exceeds the maximum value of the ringing and whether the level difference data is equal to or less than the ringing level, are coded and recorded. . The multiplier data to be supplied to the suppression level multiplying circuit 5 read from the ROM 35 is sampled and held again by the D flip-flop 36 in response to the reference clock fck, and then output as multiplied digital data.
[0029]
FIG. 5 shows a specific configuration block diagram of the frequency detection circuit 8 and the multiplication circuit 5 in FIG. D flip-flops 41, 42, and 46 in FIG. 5 have the same functions as D flip-flops 31, 32, and 36 in FIG.
[0030]
In this circuit, the data which is temporally adjacent to each other and shifted by one clock is compared in the comparison circuit 43, and it is determined whether the slope of the data change is positive or negative based on the sign of the subtraction result of both data, and which data is larger. That is, it is determined whether the level is changing in the same direction. The comparison circuit 43 observes the sign (flag) change as a result of the subtraction, and sends a flag change signal to the change clock counter 44 as a counter reset signal. The change clock counter 44 counts the number of clocks from the time when the slope changes from positive to negative and from negative to positive, based on the output from the comparison circuit 43, to the time when the slope next changes from positive to negative and from negative to positive. That is, the number of clocks in the period from peak to peak is counted.
[0031]
The output from the change clock counter 44 is frequency information indicating how many clocks have changed (the number of clocks at which the output of the counter changes, but indicates a time interval). This information is supplied to the ROM 45. In the ROM 45, multiplier digital data to be suppressed is stored in advance as an input address of a frequency to be suppressed. In the ROM 45, frequency information is input, and it is determined whether or not the frequency corresponds to the frequency of the ringing to be suppressed. If the frequency corresponds to the frequency, the frequency to be suppressed and the ringing frequency are: A multiplier to be supplied to the multiplication circuit 5 is generated as a coefficient in a direction for suppressing digital data.
[0032]
FIG. 6 shows a specific configuration block diagram of the level difference & frequency detection circuit 9 and the multiplier decoder 6 in FIG. 6, D flip-flops 51, 52 and 58 have the same function as D flip-flops 31, 32 and 36 in FIG.
[0033]
Adjacent data output from the D flip-flops 51 and 52 and shifted by one clock are input to a subtraction circuit 53 and a comparison circuit & change clock counter 54. The subtraction circuit 53 has the same function as the subtraction circuit 33 of FIG. 4. The obtained level difference data is sampled and held by the D flip-flop 55 in response to the reference clock fck, and is supplied to the ROM 57. The comparison circuit & change clock counter 54 has the functions of the comparison circuit 43 and the change clock counter 44 shown in FIG. 5, and the obtained frequency information is similarly sampled and held by the D flip-flop 56 and supplied to the ROM 57. You. From the ROM 57 to which the level difference data and the frequency information supplied from the D flip-flops 55 and 56 are input, multiplier digital data for suppressing ringing is output via the D flip-flop 58.
[0034]
The ringing suppression effect according to the above embodiment will be described below.
As shown in FIG. 7, when the full range of the input signal is set to 100%, the peak to peak of the ringing level is assumed to be 10% as the input signal. Consider a signal in which the ringing changes as shown and finally rises above the ringing level to a higher level.
[0035]
FIG. 8 shows a temporal change of the output signal after ringing suppression according to the embodiment shown in FIG. Assuming that the set suppression level in the multiplier decoder 6 is set to 50% (1/2), the ringing level of the input signal is 10%, so that the output ringing level is 5%.
[0036]
FIG. 9 shows an example of an output signal after ringing suppression according to the embodiment shown in FIG. As in FIG. 8, the ringing level is suppressed by half and becomes 5%.
[0037]
FIG. 10 shows gain characteristics for explaining the ringing suppression effect according to the embodiment of FIG. In the figure, A shows the gain characteristic obtained by the embodiment of FIG. 3, and B shows the gain characteristic at the ringing detection frequency when only the frequency information without level detection is used. Further, when the ringing level is similarly suppressed only by the filter design, the level starts to decrease from a low frequency as indicated by the gain characteristic C in which the ringing characteristic has priority.
[0038]
The effects of the gist configuration of the above-described embodiment will be enumerated below in comparison with the related art.
[0039]
(1) Digital filter means (FIR type filter or IIR type filter) for performing a filtering process on an input digital signal, and detection means (frequency, frequency) for detecting the degree of change in the output signal of the digital filter means Level difference, frequency & level difference detecting means), and based on the output of the detecting means, the output of the digital filter means is adaptively changed in multiplier to perform a multiplication process to perform ringing on the output of the digital filter means. And a ringing suppression unit configured to suppress the ringing.
In a conventional digital filter circuit, it is necessary to take into account the differential component of the input signal as the ideal gain characteristic is obtained, so that the ringing level increases at the discontinuous point of the signal, and the convergence time of the ringing increases. Although there was a problem, according to this configuration, the ringing level can be suppressed to a small value, and the convergence time of the ringing can be shortened. In addition, since the degree of affecting the signal level change other than the ringing component is very small, good gain characteristics can be obtained. be able to.
[0040]
(2) The detection means detects the degree of change in the signal to be detected based on the degree of change in the signal level of the output signal of the digital filter means at different points in time. ) Signal processing device.
The ringing level is determined by the ringing characteristic of the filter, and if the ringing level is suppressed to a low level, the gain characteristic deteriorates. However, according to this configuration, the ringing detection circuit can be realized with a simple configuration and is generated by the filter. Since it does not affect a signal level change equal to or more than the maximum level of ringing, deterioration of gain characteristics is small.
[0041]
(3) Digital filter means for performing filtering processing on the input digital signal, detection means for detecting whether or not the frequency of the output signal of the digital filter means corresponds to the frequency of ringing to be suppressed, and this detection Ringing suppression means adapted to adaptively change the multiplier to the output of the digital filter means based on the output of the means and to perform a multiplication process to suppress ringing relating to the output of the digital filter means. Signal processing device.
This is the same as (2), and it is possible to selectively suppress only a high-level frequency among the frequency components in which ringing occurs, so that the frequency at which the gain characteristic is degraded is limited and the degree of influence is small.
[0042]
(4) digital filter means for performing a filtering process on the input digital signal, first detection means for detecting the degree of change in the signal level at different points in the output signal of the digital filter means, and the digital filter Second detecting means for detecting whether or not the frequency of the output signal of the means corresponds to the frequency of the ringing to be suppressed; and the digital filter means based on the output of the first detecting means and the second detecting means. A ringing suppressing means adapted to adaptively change the multiplier to perform a multiplication process to suppress ringing relating to the output of the digital filter means.
This is the same as (2), and since the frequency and the maximum level at which ringing occurs can be specified by the detection circuit, ringing can be suppressed reliably. Furthermore, since the frequency at which the gain characteristic deteriorates is limited and does not affect the signal level higher than the maximum level of ringing, the deterioration of the gain characteristic is extremely small.
[0043]
【The invention's effect】
As described above, according to the signal processing device of the present invention, it is possible to suppress the ringing level, shorten the convergence time during which the ringing fluctuation converges, and improve the frequency characteristics.
[Brief description of the drawings]
FIG. 1 is a configuration block diagram of a signal processing device according to a first embodiment of the present invention.
FIG. 2 is a configuration block diagram of a signal processing device according to a second embodiment of the present invention.
FIG. 3 is a configuration block diagram of a signal processing device according to a third embodiment of the present invention.
FIG. 4 is a specific configuration block diagram of a level difference detection circuit 7 and a multiplier decoder 6 shown in FIG.
FIG. 5 is a specific configuration block diagram of a frequency detection circuit 8 and a multiplier decoder 6 shown in FIG. 2;
FIG. 6 is a specific configuration block diagram of a level difference & frequency detection circuit 9 and a multiplier decoder 6 in FIG. 3;
FIG. 7 is a diagram illustrating an input signal for explaining a ringing suppression effect according to an embodiment of the present invention.
8 is a diagram showing a temporal change of an output signal after ringing suppression according to the embodiment shown in FIG. 1;
9 is a diagram showing a temporal change of an output signal after ringing suppression according to the embodiment shown in FIG. 2;
FIG. 10 is a diagram showing gain characteristics for explaining a ringing suppression effect according to the embodiment of FIG. 3;
FIG. 11 is a diagram illustrating an example of an N-order FIR digital filter.
FIG. 12 is a diagram illustrating an example of an Nth-order IIR digital filter.
FIG. 13 is a diagram showing an example of an input signal for explaining a conventional problem.
14 is a diagram illustrating an example of an output signal of a digital filter with respect to the input signal illustrated in FIG. 13;
FIG. 15 is a diagram illustrating an example of frequency characteristics (gain characteristics and delay characteristics) of a conventional FIR filter.
16 is a diagram showing an example of a step response characteristic of the filter shown in FIG.
FIG. 17 is a diagram showing an example of multiplication coefficients H (0) to H (30) set in each of 31 multipliers constituting a conventional FIR filter.
18 is a diagram illustrating frequency characteristics (gain characteristics and delay characteristics) of an IIR filter similar to FIG.
FIG. 19 is a diagram illustrating an example of a step response characteristic of an IIR filter similar to FIG. 16;
[Explanation of symbols]
REFERENCE SIGNS LIST 1 digital filter 2 coefficient setting circuit 3 timing controller 4 delay circuit 5 multiplier circuit 6 multiplier decoder 7 level difference detection circuit 8 frequency detection circuit 9 frequency & level difference detection circuit

Claims (4)

Digital filter means for performing a filtering process on an input digital signal; detection means for detecting the degree of change in the output signal of the digital filter means; and digital filter means based on the output of the detection means. A ringing suppressing unit configured to adaptively change a multiplier to perform a multiplication process to suppress ringing related to an output of the digital filter unit. 2. The apparatus according to claim 1, wherein the detecting means detects a degree of change in the signal to be detected based on a degree of change in the signal level of the output signal of the digital filter means at different times. Signal processing device. Digital filter means for performing a filtering process on an input digital signal, detection means for detecting whether or not the frequency of the output signal of the digital filter means corresponds to the frequency of ringing to be suppressed, and output of the detection means Ringing suppression means adapted to adaptively change the multiplier of the output of the digital filter means to perform a multiplication process on the basis of the multiplication processing to suppress ringing relating to the output of the digital filter means. A signal processing device characterized by the above-mentioned. Digital filter means for performing a filtering process on an input digital signal, first detection means for detecting the degree of change in signal level at different points in the output signal of the digital filter means, and output of the digital filter means A second detector for detecting whether or not the frequency of the signal corresponds to the frequency of the ringing to be suppressed; an output of the digital filter based on an output of the first detector and an output of the second detector. A ringing suppression unit adapted to adaptively change a multiplier to perform a multiplication process to suppress ringing related to an output of the digital filter unit.

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