JP3546425B2 - Transport stream generator - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a transport stream generator which is highly reliable and can immediately output a transport stream.
[0002]
[Prior art]
The MPEG (Moving Picture Coding Experts Group) 2 standard, which is an international standard, is used for compression encoding and multiplexing of digital broadcasting. There is a transport stream generator as a test apparatus for the digital broadcast receiving equipment of the MPEG2 standard. Such an apparatus is described in, for example, Japanese Patent Application Laid-Open No. 10-257487. This transport stream generator is shown and described in FIG.
[0003]
In the figure, a hard disk 11 stores transport stream data. A FIFO (First In First Out) memory 12 inputs and outputs transport stream data of the hard disk 11 based on a write signal and a read signal. The driver 13 outputs the transport stream data from the FIFO memory 12. The CPU 14 reads the transport stream data of the hard disk 11 in response to the permission signal, and provides the FIFO memory 12 with the transport stream data and the write signal. The transmission clock generator 15 generates a transmission clock, which is a system clock of the transport stream, and supplies the transmission clock to the FIFO memory 12 as a read signal. The FIFO controller 16 adds “1” to the counter value according to the write signal from the CPU 14, subtracts “1” from the counter value according to the transmission clock from the transmission clock generator 15, and sets the counter value to a predetermined value. In the following cases, a permission signal for permitting writing is given to the CPU 14.
[0004]
The operation of such a device is described below.
When receiving the permission signal from the FIFO controller 16, the CPU 14 reads the transport stream data from the hard disk 11, gives the transport stream data and the write signal to the FIFO memory 12, and sends the transport stream data to the FIFO memory 12. Write. Such an operation is repeated and read from the beginning to the end of the transport stream data stored in the hard disk 11. At this time, the FIFO controller 16 receives the write signal from the CPU 14 and adds “1” to the counter value.
[0005]
Further, the transmission clock generator 15 outputs a transmission clock. Using this transmission clock as a read signal, the FIFO memory 12 reads the transport stream data and supplies it to the driver 13. The driver 13 outputs this transport stream data as a transport stream. At this time, the FIFO controller 16 receives the transmission clock of the transmission clock generator 15 and subtracts “1” from the counter value.
[0006]
Then, the FIFO controller 16 adds or subtracts the counter value based on the write signal of the CPU 14 and the transmission clock of the transmission clock generator 15, and gives a permission signal to the CPU 14 if the counter value is equal to or less than a predetermined value. When the counter value exceeds a predetermined value, a permission signal is not given to the CPU 14 and the CPU 14 is prohibited from writing to the FIFO memory 12.
[0007]
As described above, since the transmission clock has a fixed frequency, the read timing of the FIFO memory 12 is fixed. However, when writing to the FIFO memory 12 by the CPU 14, a seek or the like occurs depending on the position where the data on the hard disk 11 is written. Therefore, the timing for reading the transport stream data from the hard disk 11 is random, and the timing for writing to the FIFO memory 12 is also random. That is, the fact that the read timing and output from the hard disk 11 are asynchronous is absorbed by the FIFO memory 12.
[0008]
When (transmission clock)> (writing time of the CPU 14 to the FIFO memory 12) is satisfied by the FIFO controller 16, the counter value keeps a constant value, and the FIFO memory 12 operates as a buffer.
[0009]
However, in such an apparatus, the hard disk 11 is constantly accessed, and the disk and the head are always in contact with each other, and the risk of crash is extremely high. In addition, when writing and erasing are repeatedly performed on the hard disk 11, fragmentation frequently occurs. If the fragmentation occurs continuously, the reading speed of the hard disk 11 decreases, the transport stream data in the FIFO memory 12 becomes empty, and the transport stream data cannot be output continuously.
[0010]
Then, an apparatus as shown in FIG. 3 can be considered.
In the figure, a transmission clock generator 21 generates a transmission clock. The address counter 22 sequentially outputs an address for each transmission clock of the transmission clock generator 21. The main memory 23 stores the transport stream data and outputs the transport stream data according to the address of the address counter 22. The driver 24 receives the transport stream data from the main memory 23 and outputs it as a transport stream. The hard disk 25 stores transport stream data. The CPU 26 reads the transport stream data from the hard disk 25 and writes it to the main memory 23.
[0011]
The operation of such a device is described below.
The CPU 26 reads the transport stream data from the hard disk 25 and stores it in the main memory 23. In some cases, the CPU 26 creates transport stream data by calculation and writes it to the main memory 23.
[0012]
Then, the transmission clock generator 21 generates a transmission clock. For each transmission clock, the address counter 22 counts up the address and outputs it. This address is input to the main memory 23 and the transport stream data is output. This transport stream data is output as a transport stream via the driver 24. Such an operation is repeated.
[0013]
As described above, since the transport stream data is sequentially output after the data is stored in the main memory 23, no loss due to the data transfer speed occurs. Further, since the hard disk is not always used, the reliability is high.
[0014]
However, in such an apparatus, it takes time for the CPU 26 to write the transport stream data to the main memory 23, and the transport stream cannot be output immediately. For example, it takes about 30 minutes to write a 10-minute transport stream of a satellite broadcast from the hard disk 25 to the main memory 23 by the CPU 26. Also, it takes about 5 minutes for a 10-minute transport stream of DVD video.
[0015]
[Problems to be solved by the invention]
Therefore, an object of the present invention is to realize a transport stream generator which has high reliability and can immediately output a transport stream.
[0016]
[Means for Solving the Problems]
The present invention
In a transport stream generator that outputs transport stream data of a hard disk,
A main memory for storing transport stream data of the hard disk,
A selector for selecting the transport stream data of the hard disk until the transport stream data of the hard disk is stored in the main memory, and selecting and outputting the transport stream data of the main memory after storing the transport stream data.
Is provided.
Also, the present invention
A transmission clock generator for generating a transmission clock;
A hard disk that stores and outputs transport stream data,
In the transport stream generator, the transport stream data of the hard disk is inputted, and the transport stream generator has a FIFO memory for outputting the transport stream data for each transmission clock of the transmission clock generator.
A main memory for storing transport stream data from the FIFO memory;
A selector is provided for selecting the transport stream data in the FIFO memory until the transport stream data is stored in the main memory, and selecting and outputting the transport stream data in the main memory after storage. Is what you do.
[0017]
In the present invention, the transport stream data of the hard disk is output via the selector and stored in the main memory. After storing in the main memory, the transport stream data is output from the main memory via the selector.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram showing one embodiment of the present invention. Here, the same components as those in FIG.
[0019]
In the figure, a buffer 31 temporarily holds transport stream data from the FIFO memory 12. The main memory 32 stores the transport stream data from the buffer 31. The selector 33 selects the transport stream data from the FIFO memory 12 and the transport stream data from the main memory 32 and outputs them to the driver 13. The main memory controller 34 receives the transmission clock of the transmission clock generator 15, controls input / output of the main memory 32, and switches the selector 33.
[0020]
The operation of such a device is described below.
When receiving the permission signal from the FIFO controller 16, the CPU 14 reads the transport stream data from the hard disk 11, gives the transport stream data and the write signal to the FIFO memory 12, and sends the transport stream data to the FIFO memory 12. Write. Such an operation is performed from the beginning to the end of the transport stream data stored on the hard disk 11. At this time, the FIFO controller 16 receives the write signal from the CPU 14 and adds “1” to the counter value.
[0021]
Further, the transmission clock generator 15 outputs a transmission clock. Using this transmission clock as a read signal, the FIFO memory 12 reads the transport stream data and supplies it to the buffer 31 and the selector 33. Then, the buffer 31 temporarily holds the transport stream data. At this time, the FIFO controller 16 receives the transmission clock of the transmission clock generator 15 and subtracts “1” from the counter value.
[0022]
Then, the FIFO controller 16 adds or subtracts the counter value based on the write signal of the CPU 14 and the transmission clock of the transmission clock generator 15, and gives a permission signal to the CPU 14 if the counter value is equal to or less than a predetermined value. When the counter value exceeds a predetermined value, permission is not given to the CPU 14 and writing to the FIFO memory 12 is prohibited.
[0023]
The main memory controller 34 makes the selector 33 select the transport stream data from the FIFO memory 12. Further, the main memory controller 34 changes the address according to the transmission clock of the transmission clock generator 15 and gives the address, and writes the transport stream data of the buffer 31 to the main memory 32. Then, the transmission clock of the transmission clock generator 15 is input and counting is performed. Based on this count, the main memory controller 34 detects one cycle of the transport stream data and causes the selector 33 to select the transport stream data from the main memory 32. Then, the main memory controller 34 changes the address according to the transmission clock of the transmission clock generator 15 and gives the address. The main memory 32 outputs the transport stream data to the selector 33.
[0024]
Then, the driver 13 inputs the transport stream data selected by the selector 33 and outputs the transport stream.
[0025]
As described above, the transport stream data is output from the hard disk 11 and stored in the main memory 32 until the transport stream makes one round, and the transport stream data is output from the main memory 32 after one round. A transport stream can be output immediately. Further, since it is only necessary to access the hard disk 11 up to one round, the reliability can be increased.
[0026]
The present invention is not limited to this, and a configuration without the FIFO controller 16 may be used. However, it goes without saying that it is preferable to provide the FIFO controller 16 because the reliability is reduced.
[0027]
Further, the apparatus shown in FIG. 1 may be used like the apparatus shown in FIGS. That is, the transport stream data of the hard disk 11 may be output while the selector 33 remains selected in the FIFO memory 12. Alternatively, the transport stream data of the hard disk 11 may be stored in the main memory 32 while the selector 33 remains selected in the main memory 32, and then the transport stream data of the main memory 32 may be output.
[0028]
【The invention's effect】
According to the present invention, the transport stream data of the hard disk is output and stored in the main memory, and after the storage, the transport stream data is output from the main memory, so that the transport stream can be output immediately. . Further, since it is only necessary to access the hard disk until the data is stored in the main memory, the reliability can be improved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing one embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a conventional transport stream generator.
FIG. 3 is a diagram showing another configuration of a conventional transport stream generator.
[Explanation of symbols]
11 Hard Disk 12 FIFO Memory 15 Transmission Clock Generator 32 Main Memory 33 Selector

Claims (2)

In a transport stream generator that outputs transport stream data of a hard disk,
A main memory for storing transport stream data of the hard disk,
A selector for selecting the transport stream data of the hard disk until the transport stream data of the hard disk is stored in the main memory, selecting the transport stream data of the main memory after storing, and outputting the selector.
A transport stream generator comprising: A transmission clock generator for generating a transmission clock;
A hard disk that stores and outputs transport stream data,
In the transport stream generator, the transport stream data of the hard disk is inputted, and the transport stream generator has a FIFO memory for outputting the transport stream data for each transmission clock of the transmission clock generator.
A main memory for storing transport stream data from the FIFO memory;
A selector is provided for selecting the transport stream data in the FIFO memory until the transport stream data is stored in the main memory, and selecting and outputting the transport stream data in the main memory after storage. A transport stream generator.

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