KR100640913B1 - Apparatus of Storing/Reproducing Data Stream Received at Digital Broadcasting Receiver and Method Thereof - Google Patents

Abstract

The present invention relates to a data stream storage / playback apparatus and method capable of storing and playing only data streams desired by a user.

A data stream storage / reproducing apparatus of a digital broadcasting receiver according to the present invention includes a program identification information detector for detecting identification information of a program selected by a user from an input data stream, and only a valid packet having the program identification information is stored in the storage apparatus. It is characterized in that it is provided with a control unit for controlling to be stored and reproduced at the same time.

According to the present invention, since only the program having the PID desired by the user among the received data streams is stored in the HDD, the bus occupancy ratio of the system can be lowered and the amount of data stored in the HDD is reduced, thereby increasing the storage time.

Description

Apparatus of Storing / Reproducing Data Stream Received at Digital Broadcasting Receiver and Method Thereof}             

1 is a block diagram showing a conventional digital broadcast receiver.

FIG. 2 is a block diagram showing a detailed configuration of the stream controller shown in FIG.

3 is a block diagram showing a detailed configuration of a stream controller of a digital broadcast receiver according to an embodiment of the present invention.

FIG. 4 is a driving timing diagram of corresponding elements when data is stored in the stream controller of FIG.

FIG. 5 is a driving timing diagram of corresponding elements when data is reproduced by the stream controller of FIG.

6 is a flowchart illustrating a method of storing / reproducing a received data stream according to an exemplary embodiment of the present invention.

7 is a flowchart specifically illustrating a storage operation included in FIG. 6.

8 is a flowchart specifically illustrating a reproducing operation included in FIG. 6.

<Brief description of symbols for the main parts of the drawings>

2: Tuner / Demodulator 4: Stream Controller

6: Demux / MPEG Decoder 8: MPEG Memory

10: system bus 12: RAM

14: CPU 16: ROM

18: user interface 20: HDD

22, 30, 44: MUX 24: Receive (RX) FIFO

26, 58: host interface 28: transmit (TX) FIFO

32: program identification information detector 34: control logic

36: reception counter 38: transmission counter

40: FIFO 42: Counter

46, 48: Receive buffer 60, 62: Transmit buffer

50, 54, 64, 68, 72: data director

52, 56, 66, 70: address director

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast receiver, and more particularly, to an apparatus and method for storing and reproducing a data stream capable of storing and playing only a desired data stream among input data.

Digital broadcast receivers generally use a hard disc drive (HDD) as a storage medium when the received data stream is stored and reproduced or reproduced. In order to realize this, the digital broadcast receiver includes a stream controller for controlling the path of the transport stream as shown in FIG.

The digital broadcast receiver of FIG. 1 is a tuner / demodulator 2 for receiving a broadcast signal from an arbitrary service medium and outputs digital data, and a transmission path of a data stream from the tuner / demodulator 2. A stream controller (4) for controlling a signal, a demultiplexer (DEMUX) / moving picture expert group (MPEG) decoder (6) connected to an output terminal of the stream controller (4), and a demux / MPEG decoder (6). And an MPEG memory 8 connected to the system, a RAM 12, a CPU 14, a ROM 16, a user interface 18, and an HDD 20, which are commonly connected to the system bus 10. The tuner / demodulator 2 converts and outputs a broadcast signal input through an input line 1 from any service medium into a digital data stream under the control of the CPU 14 via the system bus 10. The stream controller 4 outputs and stores the data stream from the tuner / demodulator 2 to the HDD 20 under the control of the CPU 14 via the system bus 10 or to the demux / MPEG decoder 6. Output to play In addition, the stream controller 4 outputs and reproduces the data stream input from the HDD 20 through the system bus 10 to the demux / MPEG decoder 6 under the control of the CPU 14. To this end, the stream controller 4 has a detailed configuration as shown in FIG.

The stream controller 4 of FIG. 2 has a MUX (Multiplxer) 22 for switching the path of the input data stream TP_datain and a host interface (first-in-first-out) for the data stream input from the MUX 22. A receive (RX) FIFO 24 for output to the 26), a transmit (TX) FIFO 28 for outputting the data stream input through the host interface 26 in a first-in first-out manner, the CPU 16, It has a host interface 26 for the interface. The mux 22 outputs the data stream TP_datain input from the tuner / demodulator 2 to the receiving FIFO 24 under the control of the CPU 14 through the host interface 26 or the demux / MPEG decoder 6. Will be printed on The reception FIFO 24 outputs the data stream input from the MUX 22 to the host interface 26 in a first-in first-out manner so that it can be stored in the HDD 20 through the system bus 10. The transmission FIFO 28 outputs the data stream input from the HDD 20 through the host interface 26 to the demux / MPEG decoder 6 in a first-in first-out manner so that it can be reproduced. In this case, the host interface 26 transmits the data stream together with the input clock signal TP_clkin or the output clock signal TP_clkout.

In FIG. 1, the demux / MPEG decoder 6 selects a data stream TP_dataout input from the stream controller 4 under the control of the CPU 14, stores it in the MPEG memory 8, and reads the stored data stream. And decodes the data through the output line 7. The CPU 14 performs a control operation corresponding to a user command input from the user interface 18 via the system bus 10. For example, the CPU 14 converts a channel at the tuner / demodulator 2 according to a user command and converts a data stream transmission path at the stream controller 4. In addition, the CPU 16 controls the demux / MPEG decoder 6 to select an input data stream according to a user command. The RAM 12 and the ROM 16 are used during the control operation of the CPU 14.

As described above, the conventional digital broadcasting receiver stores the received data stream using the HDD 20 and reproduces or reproduces the data stream. In this case, the received data stream usually includes a plurality of broadcast programs, but the user selects only a desired broadcast program without seeing the received multiple broadcast programs at the same time. If you want to see more than one program, you need to have as many MPEG decoders as there are programs. By the way, the user sees only the desired program among a plurality of received programs, but the digital broadcast receiver stores all received data streams in the HDD 20. In this case, since the amount of data streams is enormous, the performance of the CPU 14 and the bus speed between components are inevitably problematic in order to store and reproduce the data streams on the HDD 20 without loss.

For example, in the case of terrestrial 8VSB broadcasting, the data stream is input at 19.4Mbps (2.425Mbytes / Sec), and in order to store and play the data stream, 'Read time of the RX FIFO 24 + HDD 20' Write time + read time of HDD 20 + write time of TX FIFO 28 + etc. = 30ns + 30ns + 3ns + 30ns + etc. = 120ns' processing time is required . In this case, the input time of the data stream is 1 / 2.425 Mhz = 412 ns, which is larger than the 120 ns. However, this assumes that the capacity of the receive (RX) and transmit (TX) FIFOs 24, 28 is large enough, and the speed of all the buses is 33Mhz and all of them are processing time when DMA processing is possible. If all of these conditions are not satisfied, the processing time is greater than 120 ns. In addition, in other service media such as satellite and cable, the input of the transmission data stream goes up to 40 Mbps, and the processing time of the data stream in the digital broadcasting receiver takes about 200 ns. In this case, the CPU 14 hardly performs other processing.

In addition, in the conventional digital broadcasting receiver, all the received broadcast programs are stored, so the capacity of the HDD 20 becomes a problem. For example, when storing a data stream input at 19.4 Mbps (2.425 Mbytes / Sec) for 1 hour, the capacity of 2.425 × 3600 = 8.73 Gbytes is required, and when the capacity is 40 Mbps, the capacity of the HDD 20 is required. This situation is lacking.

Accordingly, an object of the present invention is to provide an apparatus and method for data stream storage / reproduction of a digital broadcast receiver which can reduce a bus occupancy and HDD capacity by detecting a program ID and storing only a program desired by a user.

In order to achieve the above objects, a data stream storage / reproducing apparatus of a digital broadcasting receiver according to the present invention includes a program identification information detector for detecting identification information of a program selected by a user from an input data stream, and the program identification information. The branch is characterized in that it comprises a control unit for controlling only the effective packet is stored in the storage device and reproduced at the same time.

A data stream storage / reproduction method of a digital broadcasting receiver according to the present invention comprises the steps of setting program identification information corresponding to a program selected by a user in a program identification information detector, and detecting and storing only an effective packet having the set program identification information. And storing and reproducing the data stream stored in the storage device.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 8.

3 illustrates a stream controller of a digital broadcast receiver according to an embodiment of the present invention. The stream controller 4 of FIG. 3 includes a mux 30 for switching the transmission path of the input data stream TP_datain and a PID for detecting a selected program ID (hereinafter referred to as PID) connected to the mux 30. The detector 32, the FIFO 40 for PID detection, the counter 42 for counting the number of unnecessary PID packets, and the second mux 42 for switching the outputs of the FIFO 40 and the counter 42. And first and second receive (RX) buffers 46 and 48 connected between the second mux 42 and the host interface 58 to temporarily store the quantity of unnecessary PID packets and the selected PID, and the host interface ( And first and second transmit (TX) buffers 60 and 62 for temporary storage of the written data stream, and a host interface 58 for interfacing with the CPU 14. 4 and 5 show the input and output signal timing of each component.

In FIG. 3, the first mux 30 switches the path of the data stream TP_datain input from the tuner / demodulator 2. In this case, the first mux 30 inputs the control signal TP_con of the control logic unit 34 according to the control of the CPU 14 through the host interface 58 to convert the data stream TP_datain into the PID detector 32. ) And FIFO 40 or to the demux / MPEG decoder 6. As shown in FIG. 4, the data stream is transmitted in units of a transmission packet (TP). The transmission packet TP is usually composed of a PID and a data stream corresponding to the PID. As illustrated in FIG. 4, the PID detector 32 detects the synchronization signal Sync from the data stream TP_datain input through the first mux 30 and sets PID information set in the control logic unit 34. PID is detected in response to (PID_d). When the desired PID is detected, the PID detector 32 outputs the PID detection signal PID_mch to the control logic unit 34 as shown in FIG. 4. The FIFO 40 stores and outputs only the transmission packet TP having the effective PID detected by the PID detector 32 among the transmission packets TP output from the first mux 30 under the control of the control logic unit 34. Done. Specifically, the FIFO 40 stores the transmission packet TP having an effective PID when the control logic unit 34 supplies the write signal W_fifo by the PID detection signal PID_mch. As shown in FIG. 4, the FIFO 40 outputs the stored transmission packet when the read signal R_fifo is supplied from the control logic unit 34. The counter 42 counts the number of unnecessary transmission packets according to the clock signal CT_clk supplied from the control logic unit 34 as shown in FIG. In addition, the counter 42 outputs the value counted by the reset signal CT_rst supplied from the control logic unit 34 and is reset. As illustrated in FIG. 4, the control logic unit 34 generates the reset signal CT_rst of the counter 42 when the PID detection signal PID_mch is input from the PID detector 32. As shown in FIG. 4, the second mux 44 transmits a packet or a counter from the FIFO 40 according to the control signal MUX_con outputted in synchronization with the PID detection signal PID_mch from the control logic unit 34. The unnecessary transfer packet count value from 42 is output. As a result, the output data RX_data of the second mux 44 has a form in which the count value of the unnecessary transmission packet is added to the front end of the valid transmission packet as shown in FIG. The first and second receive (RX) buffers 46 and 48 store the output data RX_data of the second mux 44 under the control of the control logic unit 34 and output the stored data to the host interface 10. Done. In this case, the control logic unit 34 checks the data access amounts of the first and second reception (RX) buffers 46 and 48 by using the built-in reception counter 36 to control input / output of data. The data input / output paths of the first and second receive (RX) buffers 46 and 48 are switched by the data directors 50 and 54 connected to each other. In addition, the address input / output paths of the first and second receive (RX) buffers 46 and 48 are switched by the address directors 52 and 56 connected to each other. As shown in FIG. 4, the control logic unit 34 supplies the first reception control signal RX_con1 in the high state to the first data and the first address directors 50 and 52 and outputs the control logic unit 34. The output data RX_data of the second mux 44 is stored in the first reception RX buffer 46 according to the address signal RX_addr. Subsequently, when the output logic RX_data fills the first reception buffer RX 46, the control logic unit 34 is in a high state to the CPU 14 through the host interface 58 as shown in FIG. 4. The interrupt signal (HOST_con) (int) is supplied. At the same time, the control logic section 34 supplies the second reception control signal RX_con2 in the high state to the second data and address directors 54 and 56 and outputs it from the control logic section 34 as shown in FIG. The output data RX_data of the second mux 44 is stored in the second reception RX buffer 48 according to the address signal RX_addr. When the output data RX_data fills the second reception RX buffer 46, the control logic unit 34 interrupts the host 14 with an interrupt signal HOST_con ( int). In this case, the control logic unit 34 counts the number of transmission packets stored in each of the first and second reception (RX) buffers 46 and 48 by using the reception counter 36. When the interrupt signal HOST_con (int) is supplied, the CPU 14 reads data stored in the first or second receive (RX) buffers 46 and 48 according to the read address RD_addr and stores the data in the HDD 20. Done. In this case, the CPU 14 reads the count value of the reception counter 36 and reads out data RD_data corresponding to the quantity.

When the user applies a reproduction command of the data stored in the HDD 20, the CPU 14 reads the data stored in the HDD 20 and transmits the first and second transmit (TX) buffers through the host interface 58. Will be stored at (60, 62). The control logic unit 34 reads the transmission packets stored in the first and second transmission (TX) buffers 60 and 62 and outputs them to the demux / MPEG decoder 6. In this case, the data input / output paths of the first and second transmission (TX) buffers 60, 62 are switched by the data directors 64, 68 connected to each. In addition, the address input / output paths of the first and second transmission (TX) buffers 60 and 62 are switched by the address directors 66 and 70 connected to the respective ones. In detail, the CPU 14 first transmits the first write control signal W_con1 in the high state as shown in FIG. 5 to the third data, the third address directors 64 and 66, and the first transmit TX buffer. 60, the write data W_data read from the HDD 20 is stored in the first transmission TX buffer 60 according to the write address W_addr. In this case, the CPU 14 sets the number of transmission packets written to the first transmission TX buffer in the transmission counter of the control logic unit 34. Then, the CPU 14 supplies the second write control signal W_con2 in the high state to the fourth data and the address directors 68 and 70 so that the write data W_data is second transmitted in accordance with the address signal W_addr. (TX) to be stored in the buffer 62. In this case, the CPU 14 sets the number of transmission packets written to the first and second transmission (TX) buffers 60 and 62 in the transmission counter 38 of the control logic unit 34. Accordingly, when a value greater than or equal to 0 is set in the transmission counter 38, the control logic unit 34 reads data stored in the first transmission buffer 60 according to the transmission address TX_addr. At this time, the control logic unit 34 reads the first byte of the transmission packet by supplying the D0_con signal to the fifth data director 72 as shown in FIG. When the read value is '0', as shown in FIG. 5, an output clock signal TP_clkout in an active state is generated, and from the first transmission buffer 60 according to the output clock signal TP_clkout. The read transmission data TX_data is transmitted to the demux / MPEG decoder 6. On the other hand, if the first byte value of the transmission packet is greater than '0', as shown in FIG. 5, the output clock signal TP_clkout is output in the non-active state by the first byte value. In this case, the output clock signal TP_clkout has the same frequency as the input clock signal TP_clkout. The value of the transmission counter 38 of the control logic unit 34 is to count down the set value per transmission packet when the valid packet is output as the output data TP_dataout. Accordingly, since the first transmission buffer 60 is empty when the count value is '0', the interrupt signal HOST_con (int) of the first transmission buffer 60 is shown in the host interface 58 as shown in FIG. 5. At the same time, the transmission packet stored in the second transmission (TX) buffer 62 by the transmission counter 38 is outputted to the output data TP_dataout in the same manner as described above to be reproduced by the demux / MPEG decoder. do. The CPU 14 receives the first transmission buffer 60 interrupt signal HOST_con (int) through the host interface 58 to the first transmission buffer 60 and the second transmission buffer 62 interrupt signal HOST_con. (int), the data read from the HDD 20 is written to the second transmission buffer 62.

6 is a flowchart illustrating a step-by-step method of storing / reproducing a received data stream of a digital broadcast receiver according to an embodiment of the present invention.

In step 2 (S2), information about the data stream received through the demux / MPEG decoder 6 is obtained. In other words, during the initial operation, the first mux 30 of the stream controller is controlled toward the demux / MPEG decoder 6 and receives system information on the data stream currently selected and received through the demux / MPEG decoder 6. It is obtained and stored in the RAM 12 through the CPU (14). In step 4 (S4), if the user selects the operation mode of the digital broadcast receiver through the user interface 18 as the storage and playback mode, the process proceeds to step 8 (S8); when the user selects the playback mode, step 10 (S10) The process proceeds to the normal operation and the reproduction operation. In step 8 (S8), when the user views the system information and selects a data stream for the desired program (i.e., the desired movie, etc.), the corresponding PID passes through the host interface 58 and the control logic unit 34 and the PID detector 32. Will be set to). In this case, the PID set in the PID detector 32 may be a number such as a video PID, an audio PID, and a PID for system decoding. Next, in step 10 (S10), the first mux 30 is switched from the normal mode to the storage mode by the control signal of the control logic unit 34. Accordingly, an effective transmission packet having a PID set in the PID detector 32 is stored in the first or second reception buffers 46 and 48. In this case, the effective transmission packet is stored in a form in which the unnecessary transmission packet number is added to the front end thereof. In step 12 (S12), if the first or second receive buffers 46 and 48 become full, and the receive interrupt signal is generated in the control logic unit 34, the process proceeds to step 14 (S14) and the first or second 2 The valid transmission packets stored in the reception buffers 46 and 48 are read and stored in the HDD 20. This storage operation is described in detail as shown in FIG.

In step 22 (S22), if the first receive buffer 46 becomes full and the first receive buffer interrupt is generated through the control logic unit 34, the process proceeds to step 24 (S24) and the receiving counter 36 The first reception counter value is read. Thereafter, in step 26 (S26), the transmission packet stored in the first reception buffer 46 is read out as much as the first reception counter value and stored in the HDD 20. In step 28 (S28), the first reception counter value is cleared. In operation 30 (S30), when the transmission packet becomes full in the second reception buffer 48 and a second reception buffer interrupt occurs through the control logic unit 34, the process proceeds to step 32 (S32) and the reception counter 36 Leads to a second receive counter value. Next, in step 32 (S32), the transmission packet stored in the second reception buffer 48 is read out as much as the second reception counter value and stored in the HDD 20. In operation 34 (S34), the second reception counter value is cleared.

In this way, while the effective transmission packet is stored in the HDD 20, the stored transmission packet is first read and reproduced. In other words, when the transmission interrupt signal is generated in the control logic unit 34 in step 14 (S16), the flow advances to step 18 (S18) to read the transmission packet stored in the HDD 34 to read the first or second transmission buffer ( 60, 62). Then, the transmission packets stored in the first or second transmission buffers 60, 62 are read out to be reproduced. This regeneration operation is described in detail as shown in FIG.

When the first transmission buffer interrupt is generated in step 40 (S40), the process proceeds to step 42 (S42), where the transmission packet is read from the HDD 20 and written to the first transmission buffer 60. In step 44 (S44), the transmission counter 38 of the control logic unit 34 updates the count value while counting the number of transmission packets written to the first transmission buffer 60 (Up date). The transmission packet stored in the first transmission buffer 60 is read and output while down counting the first transmission counter value. When the second transmit buffer interrupt is generated in step 46 (S46), the process proceeds to step 48 (S48) to read the transmission packet from the HDD 20 and write it to the second transmit buffer 62. In step 50 (S50), the transmission counter 38 of the control logic unit 34 updates the count value while counting the number of transmission packets written to the second transmission buffer 62 (Up date). Then, the transmission packet stored in the second transmission buffer 62 is read and output while down counting the second transmission counter value.

As described above, while repeating steps 12 (S12) and 18 (S18), only the data stream desired by the user is stored / played back, and when the end command is received from the user in step 20 (S20), the storage / playback operation is terminated. .

As described above, according to the apparatus and method for storing / reproducing a received data stream of a digital broadcast receiver according to the present invention, only a program having a PID desired by a user among the received data streams is stored in the HDD, thereby reducing the bus occupancy rate of the system. . In addition, since only the desired program is stored in the HDD, the amount of data stored in the HDD is reduced, thereby increasing the storage time. In addition, it is possible to extend the life of the HDD by writing and reading unnecessary data.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

A program identification information detector for detecting identification information of a program selected by a user from an input data stream; A control unit for adding and storing a quantity of unnecessary packets to a valid packet having the program identification information, and controlling reproduction and reproduction; and And a storage device for storing an effective packet to which the quantity of unnecessary packets has been added. The method of claim 1, And a counter for counting and adding a quantity of unnecessary packets located between the valid packets to each of the valid packets. The method of claim 2, A reception buffer for temporarily storing a valid packet to which the quantity of unnecessary packets is added; And a transmission buffer for temporarily storing data read from the storage device. The method of claim 1, The control unit And a counter for detecting data access amounts of the transmission and reception buffers to control the transmission and reception buffers. In the method of simultaneously storing the data input from the digital broadcast receiver to the storage device, Setting program identification information corresponding to a program selected by the user in the program identification information detector; Adding a quantity of unnecessary packets to a valid packet having the set program identification information and storing the quantity of unnecessary packets in the storage device; Receiving and reproducing the data stream stored in the storage device. The method of claim 5, The storing of the valid packet is And detecting a quantity of unnecessary packets located between the valid packets and adding the detected number of unnecessary packets to the front end of the valid packet. The method of claim 5, Reproducing the data stream Detecting a quantity of unnecessary packets added to the front end of the transmission packet read from the storage device; And selectively activating a clock signal in response to the number of unnecessary packets detected in the step and outputting the transmission packet to reproduce the received data stream.

Images