JP3541338B2 - HIPPI input / output device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
According to the present invention, when a start instruction of a multi-channel program is issued to a source channel, transfer data from a memory is transferred at a very high speed of 800 M to 1.6 Gbit / sec from HIPPI (High performance parallel interface). HIPPI input / output device for sending to an interface developed for this purpose.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a HIPPI input / output device, input / output control between a memory and a HIPPI is performed by executing a channel program in accordance with an instruction of an operating system (hereinafter, referred to as an OS).
[0003]
Here, the channel program is a program for performing input / output control between the memory and the HIPPI, and exists on the memory. The input / output device has a physically existing physical channel for performing data transfer between the memory and the HIPPI, and the physical channel has a source channel on the transmission side and a destination channel on the reception side. The physical channel has a plurality of logical channels as a unit for starting and ending the channel program. As a result, the OS can issue an instruction to activate a plurality of channel programs.
[0004]
When an instruction to start a multi-channel program is issued to the source channel, the contents of the plurality of channel programs are used as data transfer instructions from the memory to the HIPPI in the conventional method.
[0005]
The control of the channel program is performed by firmware (hereinafter, referred to as FW) of the input / output device. When receiving the instruction to execute the channel program, the FW decodes the contents of the channel program and instructs the execution contents to the transfer control hardware (hereinafter, referred to as HW) of the input / output device.
[0006]
The transfer data from the memory is taken into the transfer buffer of the input / output device by the transfer control HW of the input / output device, and the taken data is then transferred to the channel transfer buffer of the source channel and transferred to the HIPPI by the buffer. Is done.
[0007]
FIG. 3 shows a specific configuration of a conventional HIPPI input / output device. The HIPPI input / output device 300 performs input / output control between the memory 200 and the HIPPI 400 by executing a channel program according to an instruction from the OS 100.
[0008]
Here, the memory 200 stores a channel program 201 for controlling input / output between the memory 200 and the HIPPI 400, and transfer data 202 input / output to / from the HIPPI 400.
[0009]
The input / output device 300 includes an FW 301 and a transfer control HW 302 for controlling a channel program in accordance with an instruction from the OS 100, a transfer buffer 303 for receiving transfer data from the memory 200, and sends the transfer data captured in the transfer buffer 303 to the HIPPI 400. A physical channel (source channel) 310, a physical channel (destination channel) 320 for receiving the transfer data from the HIPPI 400, and a transfer buffer 304 for sending the transfer data captured by the physical channel 320 to the memory 200.
[0010]
The transfer control HW 302 receives a channel program execution instruction issued for each logical channel from the OS 100 and reports it to the FW 301, a unit that reads the channel program 201 on the memory 200 in accordance with the instruction from the FW 301, and a memory in accordance with the instruction from the FW 301. Means for taking in the transfer data 202 from the 200 into the transfer buffer 303, means for taking in the transfer data from the physical channel 320 into the transfer buffer 304 in accordance with an instruction from the FW 301, and causing data to be transferred from the transfer buffer 304 to the memory 200 in accordance with an instruction from the FW 301 Have a means.
[0011]
The physical channels 310 and 320 perform data transfer between the memory 200 and the HIPPI 400, and the transmission side is a source channel (310) and the reception side is a destination channel (320).
[0012]
Each of the physical channels 310 and 320 has a plurality of logical channels as units for starting and ending the channel program.
[0013]
The source channel 310 includes a channel transfer buffer 312 and a channel control HW 311. The channel transfer buffer 312 takes in the transfer data from the transfer buffer 303 and sends it to the HIPPI 400. The channel control HW 311 includes means for controlling the data fetch and transfer of the channel transfer buffer 312 in response to an instruction from the FW 301, and means for detecting the end of the transfer data and reporting the transfer end to the FW 301.
[0014]
The destination channel 320 includes a channel transfer buffer 321 and a channel control HW 322. The channel transfer buffer 321 captures the transfer data from the HIPPI 400 and sends it to the transfer buffer 304. The channel control HW 322 includes means for controlling the data fetch and transfer of the channel transfer buffer 321 in response to an instruction from the FW 301, and means for detecting the end of the data to be transferred and reporting the transfer end to the FW 301.
[0015]
The FW 301 controls the channel program 201 in the memory 200 through the transfer control HW 302 to decode the channel program 201, instructs the transfer control HW 302 to perform an operation of loading the channel program 201, and completes execution of the channel program to the OS 100. Is provided.
[0016]
The operation of the above configuration will be described with reference to the time schedule shown in FIG. Here, a case will be described in which the activation instruction of the multi-channel program is issued to the source channel 310.
[0017]
Execution instructions for a plurality of channel programs are issued for each logical channel unit, and execution is performed on physical channels 310 and 320. The channel program is a program that controls input and output between the memory 200 and the HIPPI 400, and exists on the memory 200. Here, a channel program (1) and a channel program (2) are prepared.
[0018]
The contents of the channel program (1) and the channel program (2) include a transfer instruction from the memory 200 to the HIPPI 400, information of an address of transfer source data on the memory 200, and information of a transfer data length. The transfer data (1) and the transfer data (2) are transfer data to the HIPPI 400 on the memory 200.
[0019]
In the data transfer control method between the memory 200 and the HIPPI 400 in the source channel 310, first, the execution instruction (111) of the channel program (1) is issued from the OS 100 to the logical channel (1).
[0020]
In the input / output device 300 that has received the instruction to execute the channel program (1), the channel program (1) is read (391) and decoded (392) by the FW 301, and the operation content of the decoded channel program (1) is transferred. An instruction is given to the HW 302 (393).
[0021]
Upon receiving the operation content instruction (393), the transfer control HW 302 takes in the transfer data (1) from the specified address on the memory 200 by the specified data length into the transfer buffer 303 (394), and sets the channel transfer buffer. Transfer to 312 (395). The data sent to the channel transfer buffer 312 is transferred to the HIPPI 400 (396).
[0022]
The source channel 310 under execution of the channel program (1) is occupied by the channel program under execution (1) until the execution of the channel program ends.
[0023]
When the execution instruction (112) of the channel program (2) is issued from the OS 100 to the logical channel (2) of the source channel in the physical channel occupation state, the FW 301 reads (381) and decodes the channel program (2) (382). ). The execution of the channel program (2) is awaited by the FW 301 (383) until the transfer end report (397) of the channel program (1) being executed is received.
[0024]
When the transfer end report (397) of the channel program (1) is made, the FW 301 reports the execution end (113) of the channel program (1) to the OS 100.
[0025]
Next, the process of executing the channel program (2) is started, and the operation content of the decoded channel program (2) is instructed to the transfer control HW 302 (384). Thus, the transfer to the memory-HIPPI is performed by executing the channel program (2).
[0026]
After the transfer of the data (2) is completed, an end report (386) is made to the FW 301. The FW 301 reports the end of execution of the channel program (2) to the OS 100 (114), and a series of operations ends.
[0027]
Here, as a prior art relating to a HIPPI input / output device for transmitting transfer data from a memory to a HIPPI when an instruction to start a multi-channel program is issued to a source channel, (1) Japanese Patent Laid-Open No. 5-120008 discloses There is a "register access method", (2) a "DMA transfer control table look-ahead method" in JP-A-64-88669, and (3) a "DMA transfer queue control method" in JP-A-61-282965.
[0028]
According to the invention of the prior art (1), a temporary register is provided, and when a write request for control data is issued from an external CPU to an internal register of an operating channel, the write request data is stored in the temporary register. Once the writing and the writing of the control data based on the result of the internal processing of the channel to the internal register are completed, the writing control unit controls the data of the temporary register to be transferred to the internal register. It significantly reduces waiting time.
[0029]
In the invention of the prior art (2), a waiting time is required for the input / output device to perform a mechanical operation at the time of reading over a sector or a track. At this time, the DMA transfer request of the input / output device becomes inactive, the control of the bus is transferred to the transfer control table read channel, and the next transfer control table is read. After the end of the waiting time, data transfer from the input / output device is performed again. In this way, a vacant time during data transfer is found and the transfer control table is pre-read to prevent a waiting time from being inserted between the first data transfer and the second data transfer.
[0030]
In the invention of the prior art (3), when there is an initial transfer request from a channel, the central processing unit performs preprocessing for transfer by a microprogram. At that time, it is checked whether or not a DMA transfer process is being performed.
[0031]
However, the conventional HIPPI input / output device is a transfer method to the memory-HIPPI when the start instruction of the multi-channel program is issued to the source channel, including the method described in the above publication, and the source channel is If the channel program is being executed, the execution of the channel program for which another start instruction has been issued is made to wait by the FW until a transfer end report of the channel program being executed is received from the channel control device. For this reason, execution waiting of the channel program occurs, and transfer efficiency is reduced.
[0032]
[Problems to be solved by the invention]
As described above, the conventional HIPPI input / output device has a drawback in that when an instruction to start a multi-channel program is issued to the source channel, the execution of the channel program is waited, and the transfer efficiency is reduced.
[0033]
The present invention solves the above-described problem, and can execute a channel program continuously without waiting for the execution of a channel program even when an instruction to start a multi-channel program is issued to a source channel. It is an object to provide a HIPPI input / output device capable of improving efficiency.
[0034]
[Means for Solving the Problems]
In order to solve the above problems, a HIPPI input / output device according to the present invention is configured as follows.
[0035]
(1) In a HIPPI input / output device which is controlled by an instruction from an operating system and transfers data from a memory to a HIPPI by executing a channel program, a first transfer buffer for taking in transfer data from the memory, and the first transfer A physical channel including a source channel for capturing the transfer data captured in the buffer for each channel and transferring the data to the HIPPI and a destination channel for capturing the transfer data from the HIPPI for each channel; and a transfer captured in the destination channel A second transfer buffer for transferring data to the memory, transfer control hardware for controlling transfer of the first and second transfer buffers in accordance with an instruction from the operating system, ; And a firmware for controlling the transfer control hardware and physical channels in accordance with an instruction from the stem, the transfer control hardware incorporating a data length of instruction from the firmware from the memory to the first transfer buffer After sending the request to the source channel , the firmware notifies the firmware of an operation instruction request of the next channel program waiting to be executed, and the firmware waits for execution upon receiving an operation request instruction from the transfer control hardware. and select and execute the channel programs, sends an operation instruction to the transfer control hardware, the transfer control hardware, the transfer data from the memory so as to take into the first transfer buffer in accordance with an operation instruction from the firmware did.
[0036]
(2) In the configuration of (1), the transfer control hardware is a means for receiving a channel program activation in units of logical channels from an operating system and reporting to the firmware, and a channel program on the memory according to an instruction from the firmware. Means for reading data, means for taking in transfer data from the memory in accordance with an instruction from the firmware into the first transfer buffer, means for transferring data from the second transfer buffer to the memory in accordance with an instruction from the firmware, In addition to the means for transferring data from the destination channel to the second transfer buffer, when the transfer data is completely transmitted from the first transfer buffer 303 to the source channel, a next operation instruction request is made to the firmware. hand Means for receiving the execution instruction of the channel program, decoding the contents of the channel program, and instructing the transfer control hardware of the execution contents, and performing the next operation from the transfer control hardware. In response to the instruction request, a means for decoding the contents of the next channel program and instructing the execution contents to the transfer control hardware is provided.
[0037]
That is, in the HIPPI input / output device according to the present invention, in the data transfer by executing the channel program, when the transfer data is completely transmitted from the first transfer buffer to the source channel, the transfer control hardware executes the channel program waiting for execution. Notify the firmware of the execution request.
[0038]
In particular, in a data transfer method between a memory and a HIPPI when a start instruction of a multi-channel program is issued to a source channel, a memory for executing a channel program is used to avoid a decrease in transfer efficiency due to a wait for execution of a channel program. In the transfer method to the HIPPI, the transfer control hardware fetches the data length instructed by the firmware from the memory and sends the data length to the source channel transfer buffer. Notify. The firmware that has received the operation request instruction executes the channel program waiting to be executed, and issues an operation instruction to the transfer control hardware. In response, the transfer control hardware fetches the transfer data from the memory to the first transfer buffer according to the operation content. As a result, the next channel program can be executed without waiting for the transfer completion report of the executing channel program from the channel control, so that the transfer efficiency can be improved.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS.
[0040]
FIG. 1 shows a configuration of a HIPPI input / output device according to an embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 3 are denoted by the same reference numerals.
[0041]
In the HIPPI input / output device illustrated in FIG. 1, input / output control between the memory 200 and the HIPPI 400 is performed by executing a channel program according to an instruction from the OS 100.
[0042]
The channel program 201 is a program for controlling input / output between the memory 200 and the HIPPI 400. A channel program (1) and a channel program (2) are prepared on the memory 200.
[0043]
The contents of the channel program (1) and the channel program (2) include a transfer instruction from the memory 200 to the HIPPI 400, an address of transfer source data on the memory 200, and a transfer data length.
[0044]
The transfer data (1) and the transfer data (2) are transfer data to the HIPPI 400 on the memory 200.
[0045]
The input / output device 300 performs data transfer between the memory 200 and the HIPPI 400 by having a FW 301 for controlling a channel program, a transfer control HW 302 for transfer control, transfer buffers 303 and 304 for taking in transfer data, and physical channels 310 and 320. .
[0046]
The transfer control HW 302 receives a channel program execution instruction issued for each logical channel from the OS 100 and reports it to the FW 301, reads the channel program 201 in the memory 200 according to the FW instruction, and transfers data from the memory 200 according to the FW instruction. In addition to the means for taking the data 202 into the transfer buffer 303, the means for transferring data from the transfer buffer 304 to the memory 200 in response to the FW instruction, the means for transferring data from the channel transfer buffer 321 to the transfer buffer 304, and further the transfer data Has a means 371 for making a request for the next operation instruction to the FW 301 when all the data has been transmitted from the to the channel transfer buffer 312.
[0047]
The physical channel physically exists for performing data transfer between the memory 200 and the HIPPI 400, and includes a source channel 310 on the transmission side and a destination channel 320 on the reception side. The physical channel has a plurality of logical channels as a unit for starting and ending the channel program.
[0048]
The source channel 310 has a channel transfer buffer 312 and a channel transfer control HW 311. The channel transfer buffer 312 fetches transfer data of the transfer buffer 303 of the input / output device, and the channel control HW 311 sends data of the transfer buffer to the HIPPI 400. When the end of the data to be transferred is transmitted, a means for reporting the end of transfer to the FW 301 is provided.
[0049]
The destination channel 320 has a channel transfer buffer 321 and a channel control HW 322. The channel transfer buffer 321 fetches transfer data from the HIPPI 400, and the channel control HW 322 sends data of the channel transfer buffer 321 to the transfer buffer 304. When the end of the data to be transmitted is transmitted, a means for reporting the completion of transfer to the FW 301 is provided.
[0050]
The operation of the above configuration will be described with reference to the time schedule shown in FIG. Here, a case will be described in which the activation instruction of the multi-channel program is issued to the source channel 310.
[0051]
The contents of the plurality of channel programs are programs for input / output control between the memory 200 and the HIPPI 400, and exist on the memory 200, and a channel program (1) and a channel program (2) are prepared.
[0052]
The contents of the channel program (1) and the channel program (2) include a transfer instruction from the memory 200 to the HIPPI 400, an address of transfer source data on the memory 200, and a transfer data length. The transfer data (1) and the transfer data (2) are transfer data to the HIPPI 400 on the memory 200.
[0053]
In the data transfer control method between the memory 200 and the HIPPI 400 in the source channel 310, first, the execution instruction (111) of the channel program (1) is issued from the OS 100 to the logical channel (1).
[0054]
In the input / output device 300 that has received the instruction to execute the channel program (1), the FW 301 is controlled by the FW 301. The FW 301 reads (391), decodes (392) the channel program (1), and executes the decoding of the decoded channel program (1). The operation content is instructed to the transfer control HW 302 (393).
[0055]
Upon receiving the operation content instruction (393), the transfer control HW 302 takes in the transfer data (1) into the transfer buffer 303 from the specified address on the memory 200 by the specified data length (394), and performs channel transfer. The data is transferred to the buffer 312 (395). The data sent to the channel transfer buffer 312 is transferred to the HIPPI 400 (396).
[0056]
When the execution of the channel program (2) is instructed to the logical channel (2) of the source channel under execution of the channel program (1) (112), the FW 301 reads (381) and decodes (382) the channel program (2). . When all the transfer data by the channel program (1) is transmitted from the transfer buffer 303 to the channel transfer buffer 312, the transfer control HW 302 issues an operation instruction request to the FW 301 by the next channel program (371).
[0057]
Upon receiving the operation instruction request, the FW 301 instructs the operation contents of the channel program (2) to the transfer control HW 302 (384). Upon receiving the operation content instruction (384), the transfer control HW 302 fetches the transfer data (2) of the specified data length from the specified address on the memory 200 into the transfer buffer 303 (385). ). The transfer of the channel program (2) is performed.
[0058]
When the transfer data (1) is sent from the channel transfer buffer 312 to the HIPPI 400, a transfer completion report of the channel program (1) is made (397). Upon receiving the report (311), the FW 301 reports the execution end of the channel program (1) to the OS 100 (113).
[0059]
When all the transfer data by the channel program (2) is sent from the transfer buffer 303 to the channel transfer buffer 312, an operation instruction request is made to the FW 301 by the next channel program (372).
[0060]
After completion of the transfer of the data (2), when a completion report is made to the FW 301 (386), the FW 301 reports an execution completion of the channel program (2) to the OS 100 (114).
[0061]
As is apparent from the above operation, in the HIPPI input / output device according to the configuration of the present embodiment, in the transfer to the memory-HIPPI by executing the channel program, the transfer control HW 302 fetches the data length instructed from the FW 301 from the memory 200. When it is sent to the channel transfer buffer 312, the FW 301 is notified of the operation instruction request of the next channel program waiting to be executed. Upon receiving the operation request instruction, the FW 301 executes the waiting channel program, sends an operation instruction to the transfer control HW 302, and the transfer control HW 302 transfers the transfer data from the memory 200 according to the operation content to the transfer buffer of the input / output device 300. Capture to 303.
[0062]
As a result, the next channel program can be executed without waiting for the transfer completion report of the currently executed channel program from the channel control HW 311. Therefore, the transfer efficiency can be improved as compared with the conventional device.
[0063]
【The invention's effect】
As described above, according to the present invention, even when an instruction to start a multi-channel program is issued to the source channel, the channel program can be continuously executed without waiting for the execution of the channel program, and the transfer efficiency can be improved. Can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a HIPPI input / output device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a processing flow for explaining the operation of the embodiment.
FIG. 3 is a block diagram showing a configuration of a conventional HIPPI input / output device.
FIG. 4 is a diagram showing a processing flow for explaining the operation of the conventional device.
[Explanation of symbols]
100 OS
200 Memory 201 Channel program storage unit 202 Transfer data storage unit 300 HIPPI input / output device 301 Firmware 302 Transfer control hardware 303, 304 Transfer buffer 310 Source channel 311 Channel transfer control hardware 312 Channel transfer buffer 320 Destination channel 321 Channel transfer buffer 322 channel control hardware 400 HIPPI

Claims (2)

In a HIPPI input / output device controlled by an instruction from an operating system and transferring data from a memory to a HIPPI by executing a channel program,
A first transfer buffer for receiving transfer data from the memory;
A physical channel having a source channel for taking in the transfer data taken into the first transfer buffer for each channel and transferring the data to the HIPPI, and a destination channel for taking in the transfer data from the HIPPI for each channel;
A second transfer buffer for transferring the transfer data captured by the destination channel to the memory;
Transfer control hardware for controlling transfer of the first and second transfer buffers according to an instruction from the operating system;
Comprising a firmware that controls the transfer control hardware and a physical channel according to an instruction from the operating system,
The transfer control hardware reads the data length instructed by the firmware from the memory into the first transfer buffer , sends the data to the source channel , and then executes the next channel program waiting for execution by the firmware. Notify the operation instruction request of
The firmware executes the channel program waiting to be executed in response to the operation request instruction from the transfer control hardware, sends an operation instruction to the transfer control hardware,
It said transfer control hardware, HIPPI output apparatus characterized by incorporating the transfer data from the memory according to the operation instruction from the firmware to the first transfer buffer. The transfer control hardware is a means for receiving a channel program activation in units of logical channels from the operating system and reporting to the firmware, a means for reading a channel program on the memory according to an instruction from the firmware, and an instruction from the firmware. Means for taking in transfer data from the memory into the first transfer buffer, means for transferring data from the second transfer buffer to the memory in accordance with instructions from the firmware, and means for transferring the data from the destination channel to the second transfer buffer Means for transmitting a next operation instruction request to the firmware at a point in time when all of the transfer data has been transmitted from the first transfer buffer to the source channel,
The firmware receives the instruction to execute the channel program, decodes the content of the channel program, and instructs the transfer control hardware to execute the content, and issues a next operation instruction request from the transfer control hardware. 2. The HIPPI input / output device according to claim 1, further comprising means for decoding the contents of the next channel program upon receipt, and instructing the transfer control hardware of the contents of execution.

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