JP3541331B2 - Ferroelectric memory cell - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile memory using a ferroelectric.
Semiconductor memories are indispensable electronic components along with CPUs in the electronics industry, from large computers to home appliances.
In recent years, in particular, the speed of increasing the capacity of memories, mainly DRAMs, has been increasing, and memories having a storage capacity of 256M have been prototyped.
[0002]
However, in the conventional memory configuration, it is considered that the limit will be reached in one or two generations in view of the complexity of the structure and the number of steps, and it is urgently necessary to develop a new memory configuration method. Has become.
In addition, non-volatile memories called EPROMs and flash memories, which do not require a power supply for storing and storing data, are attracting attention as a replacement for magnetic memories such as hard disks, in contrast to memories requiring a power supply for storing and storing data such as DRAM and SRAM. (Fujio Masuoka, "Leaping Flash Memory").
[0003]
In addition, a capacitor using a ferroelectric can secure several tens of times the capacity of a conventional capacitor using a dielectric and can be made non-volatile. (Metal Ferroelectric Semiconductor (MFS) transistors), which are unnecessary and can be read non-destructively, are attracting attention as candidate technologies for large-capacity memories after ICs (Yasuo Tarui, Nikkei Micro Devices, July 1993).
[0004]
[Prior art]
One of applications of ferroelectrics to memories is an MFS transistor structure.
This is a structure in which the gate insulating film of a conventional FET is replaced with a ferroelectric material. Carriers are induced in the semiconductor of the channel by the remanent polarization of the ferroelectric material, and the change in the lateral charge in the semiconductor due to the polarization charge is suppressed. To use.
[0005]
At present, a single crystal TGS (Trigricine Sulfate) is used as a ferroelectric and a CdS thin film is formed as a semiconductor channel thereon to form a transistor, or an insulating film of a Si MOS transistor is used as a ferroelectric. There is a report on the operation of a ferroelectric memory in the structure of the above.
[0006]
Also, a diode type memory cell having a metal / ferroelectric / semiconductor structure has been proposed (Japanese Patent Laid-Open No. 7-14990). This is a method of accumulating data using a current-voltage characteristic having hysteresis caused by spontaneous polarization of a ferroelectric substance.
[0007]
[Problems to be solved by the invention]
In order to realize the MFS transistor as described above, a junction between a semiconductor channel and a ferroelectric is required. However, ferroelectrics such as PZT and BaTiO ₃ are oxide materials, and have problems in matching with semiconductor materials such as Si and GaAs. For example, in the case where oxygen diffuses from a ferroelectric oxide to a semiconductor of a channel, the operation becomes unstable due to trapping of electric charge at an interface, or the characteristics of a transistor are deteriorated.
[0008]
Further, when the leakage current of the ferroelectric thin film used for the gate is large, the characteristics of the memory or the transistor are deteriorated and the operation is unstable.
In order to solve such a problem, a diode type memory cell having a metal / dielectric / semiconductor structure has been proposed as described above.
[0009]
FIG. 1 is a diagram illustrating the principle of the current-voltage characteristics of the memory diode and the memory operation.
This memory diode has the current-voltage characteristics of a Schottky diode with the metal (electrode) side in the forward direction.
First, when a voltage (V _W0 or V _W1 ) higher than the inversion voltage (threshold voltage) of the ferroelectric polarization is applied to both sides of the diode, hysteresis occurs in the current-voltage characteristics depending on the polarity of the voltage.
This hysteresis is used for writing data.
[0010]
Further, the threshold voltage below the forward voltage (V _R) is applied, for detecting a current (I _R0 or I _R1) flowing through the diodes (i.e., detects the conductance of the diode) reading data by I do.
[0011]
However, in the above-described memory diode, when writing is performed by biasing in the forward direction of the diode, it is necessary to drive the memory diode with a relatively large current, which increases the load on the transistor for driving the diode. In addition, since a large current flows in the forward direction during writing, power consumption is also a problem.
An object of the present invention is to realize a non-volatile memory which is easy to operate and consumes low power by reducing a current flowing in a write operation in a memory diode using a ferroelectric substance.
[0012]
[Means for Solving the Problems]
FIG. 2 is an explanatory diagram of the ferroelectric memory cell according to the first embodiment of the present invention.
In this figure, 1 is an electrode, 2 is a ferroelectric layer, 3 is a semiconductor substrate, 4 is an ohmic or low contact resistance electrode, and 5 is a Schottky electrode.
[0013]
The principle of the ferroelectric memory cell of the present invention will be described with reference to FIG.
In this ferroelectric memory cell, a ferroelectric layer 2 is formed on an upper surface of a semiconductor substrate 3, an electrode 1 is formed on an upper surface of the ferroelectric layer 2, and a Schottky electrode 5 is formed on an upper surface of the semiconductor substrate 3. An ohmic or low contact resistance electrode 4 is formed on the lower surface of the semiconductor substrate 3.
[0014]
The ohmic or low contact resistance electrode 4 forms a low resistance or ohmic contact resistance with the semiconductor substrate 3, and the ferroelectric layer 2 and the semiconductor substrate between the electrode 1 and the ohmic or low contact resistance electrode 4 are formed. 3 constitutes a memory diode.
[0015]
A read operation is performed between the electrode 1 and the ohmic or low contact resistance electrode 4 by applying a forward bias voltage to the electrode 1 side.
Further, a data write operation is performed by applying a bias voltage between the electrode 1 and the Schottky electrode 5.
[0016]
In addition to the above configuration, the ohmic or low contact resistance electrode and the Schottky electrode can both be formed on the upper surface of the semiconductor substrate, and the semiconductor substrate can be a semiconductor layer formed on the substrate. Also, the ohmic or low contact resistance electrode and the Schottky electrode can be formed on the same surface of the semiconductor layer formed on the substrate.
[0017]
As described above, in the writing operation, it is necessary to apply a voltage higher than the threshold value for inverting the polarization of the ferroelectric layer to the ferroelectric layer.
Assuming that the write voltage is constant, in order to reduce the current during the write operation, an electrode that forms a high-resistance contact resistance with the semiconductor substrate (layer) is used, and the current flowing by increasing the resistance between the electrodes is used. It is necessary to lower.
[0018]
Since the voltage applied to the write electrode is divided into the ferroelectric layer and the semiconductor substrate (layer) connected in series, the voltage must be efficiently applied to the ferroelectric layer in order to reduce the write voltage. There is.
Since the division ratio at this time is determined by the dielectric constant of the ferroelectric layer and the semiconductor substrate (layer), it is desirable that the semiconductor substrate (layer) has a higher dielectric constant in order to lower the writing voltage.
Therefore, when there is a high-resistance layer having a low dielectric constant between the semiconductor substrate (layer) and the write electrode, the applied voltage is applied to the high-resistance layer by the capacitance ratio between the ferroelectric layer and the semiconductor substrate (layer). It will be absorbed.
[0019]
As shown in FIG. 2, when a semiconductor substrate (layer) and an electrode for forming a Schottky are used as the writing electrodes, when a forward voltage is applied to the diode, the Schottky acts as a barrier to generate a current. Will be suppressed.
Furthermore, when a Schottky is used as a barrier, since the dielectric constant of the barrier is the same as that of the semiconductor substrate (layer), the voltage absorbed by the barrier is small and the operating voltage does not increase.
[0020]
On the other hand, in reading, when considering the operation of the sense amplifier, it is desired to increase the reading current. In order to increase the read current at a constant voltage, the resistance between the electrodes is reduced and the contact resistance between the read electrode and the semiconductor substrate (layer) is reduced (an ohmic contact is desirable).
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
(First Embodiment)
The ferroelectric memory cell according to the first embodiment will be described again with reference to FIG. 2 which has been used in describing the principle of the ferroelectric memory cell of the present invention.
FIG. 2 is an explanatory diagram of the ferroelectric memory cell according to the first embodiment of the present invention.
In this figure, 1 is an electrode, 2 is a ferroelectric layer, 3 is a semiconductor substrate, 4 is an ohmic or low contact resistance electrode, and 5 is a Schottky electrode.
[0022]
In the ferroelectric memory cell of this embodiment, a ferroelectric layer 2 made of PZT, PTO or the like is formed on an upper surface of a semiconductor substrate 3 made of SrTiO ₃ or the like, and Pt or Pt is formed on an upper surface of the ferroelectric layer 2. An electrode 1 made of Au is formed, and a low-resistance ohmic or low-contact resistance electrode 4 made of Y, Nb or the like for reading is formed on an upper surface of the semiconductor substrate 3, and a lower surface of the semiconductor substrate 3 for writing is formed on the lower surface of the semiconductor substrate 3. A Schottky electrode 5 made of Pt, Au or the like is formed.
The ferroelectric layer 2 and the semiconductor substrate 3 between the electrode 1 and the ohmic or low contact resistance electrode 4 constitute a memory diode.
[0023]
A read operation is performed by applying a forward bias voltage to the electrode 1 between the electrode 1 and the ohmic or low contact resistance electrode 4, and a bias voltage is applied between the electrode 1 and the Schottky electrode 5. Data writing operation.
[0024]
As described above, in order to lower the writing voltage, it is preferable that the semiconductor substrate (layer) has a higher dielectric constant. For example, when an oxide semiconductor having a dielectric constant of approximately 200 is used, the operating voltage is reduced to approximately 1 V. It becomes possible.
[0025]
Further, in order to increase the read current, it is necessary to reduce the resistance of the diode between the electrode 1 and the ohmic or low contact resistance electrode 4. To this end, it is desirable to reduce the contact resistance between the ohmic or low contact resistance electrode 4 and the semiconductor substrate (layer) by doping the semiconductor at a high concentration.
[0026]
(Second embodiment)
FIG. 3 is an explanatory diagram of a ferroelectric memory cell according to the second embodiment of the present invention.
In this figure, 1 is an electrode, 2 is a ferroelectric layer, 3 is a semiconductor substrate, 4 is an ohmic or low contact resistance electrode, and 5 is a Schottky electrode.
[0027]
In the ferroelectric memory cell of this embodiment, a ferroelectric layer 2 is formed on an upper surface of a semiconductor substrate 3, an electrode 1 is formed on an upper surface of the ferroelectric layer 2, and a shot is formed on the upper surface of the semiconductor substrate 3. A key electrode 5 is formed, and a low-resistance ohmic or low-contact-resistance electrode 4 is formed on the lower surface of the semiconductor substrate 3.
The ferroelectric layer 2 and the semiconductor substrate 3 between the electrode 1 and the ohmic or low contact resistance electrode 4 constitute a memory diode.
[0028]
As described above, a read operation is performed by applying a forward bias voltage to the electrode 1 between the electrode 1 and the ohmic or low contact resistance electrode 4, and a read operation is performed between the electrode 1 and the Schottky electrode 5. A data write operation is performed by applying a bias voltage to the memory cell.
[0029]
(Third embodiment)
FIG. 4 is an explanatory diagram of a ferroelectric memory cell according to the third embodiment of the present invention.
In this figure, 6 is a support substrate, 7 is an electrode, 8 is a ferroelectric layer, 9 is a semiconductor thin film, 10 is an ohmic or low contact resistance electrode, and 11 is a Schottky electrode.
[0030]
The feature of the ferroelectric memory cell of this embodiment is that a semiconductor thin film is used as a semiconductor, and the ferroelectric memory cell is formed on a support substrate 6 made of a Si substrate, an MgO substrate, a non-doped SrTiO ₃ or the like on which an SiO ₂ layer is formed. A Schottky electrode 11 is formed, a semiconductor thin film 9 is formed thereon, a ferroelectric layer 8 is formed on a part thereof, and an electrode 7 is formed on the ferroelectric layer 8. An ohmic or low contact resistance electrode 10 is formed on the thin film 9.
[0031]
Also in this embodiment, the read operation is performed by applying a forward bias voltage to the electrode 7 side between the electrode 7 and the ohmic or low contact resistance electrode 10 as described above. A data write operation is performed by applying a bias voltage between the Schottky electrodes 11.
[0032]
(Fourth embodiment)
FIG. 5 is an explanatory diagram of a ferroelectric memory cell according to a fourth embodiment of the present invention.
In this figure, 6 is a support substrate, 7 is an electrode, 8 is a ferroelectric layer, 9 is a semiconductor thin film, 10 is an ohmic or low contact resistance electrode, and 11 is a Schottky electrode.
[0033]
The feature of the ferroelectric memory cell of this embodiment is that, similarly to the fourth embodiment, a semiconductor thin film is used as a semiconductor, and a Si substrate on which an SiO ₂ layer is formed, a MgO ₂ substrate, a non-doped An ohmic or low contact resistance electrode 10 is formed on a support substrate 6 made of SrTiO ₃ or the like, a semiconductor thin film 9 is formed thereon, and a ferroelectric layer 8 is formed on a part thereof. The electrode 7 is formed on the ferroelectric layer 8, and the Schottky electrode 11 is formed on the semiconductor thin film 9.
[0034]
Also in this embodiment, the read operation is performed by applying a forward bias voltage to the electrode 7 side between the electrode 7 and the ohmic or low contact resistance electrode 10 as described above. A data write operation is performed by applying a bias voltage between the Schottky electrodes 11.
[0035]
FIG. 6 is an explanatory diagram of a ferroelectric memory cell according to a fifth embodiment of the present invention.
In this figure, 1 is an electrode, 2 is a ferroelectric layer, 3 is a semiconductor substrate, 4 is an ohmic or low contact resistance electrode, and 5 is a Schottky electrode.
[0036]
The basic structure of the ferroelectric memory cell of this embodiment is the same as the ferroelectric memory cell of the first embodiment described with reference to FIG. 2, except that the ferroelectric layer 2 is formed on the upper surface of the semiconductor substrate 3. The electrode 1 is formed on the upper surface of the ferroelectric layer 2, and the ohmic or low contact resistance electrode 4 having low resistance and the Schottky electrode 5 are formed on the upper surface of the semiconductor substrate 3.
[0037]
Also in this embodiment, a read operation is performed by applying a forward bias voltage to the electrode 1 side between the electrode 1 and the ohmic or low contact resistance electrode 4 as described above. A data write operation is performed by applying a bias voltage between the Schottky electrodes 5.
[0038]
FIG. 7 is an explanatory diagram of a ferroelectric memory cell according to a sixth embodiment of the present invention.
In this figure, 1 is an electrode, 2 is a ferroelectric layer, 3 is a semiconductor substrate, 4 is an ohmic or low contact resistance electrode, and 5 is a Schottky electrode.
[0039]
The basic structure of the ferroelectric memory cell of this embodiment is the same as the ferroelectric memory cells of the first and fifth embodiments described with reference to FIGS. A ferroelectric layer 2 is formed on the upper surface of the semiconductor substrate 3, an electrode 1 is formed on the upper surface of the ferroelectric layer 2, and a low-resistance ohmic or low-contact resistance electrode 4 and a Schottky electrode 5 are formed on the lower surface of the semiconductor substrate 3. Is formed.
[0040]
Also in this embodiment, a read operation is performed by applying a forward bias voltage to the electrode 1 side between the electrode 1 and the ohmic or low contact resistance electrode 4 as described above. A data write operation is performed by applying a bias voltage between the Schottky electrodes 5.
[0041]
(Seventh embodiment)
FIG. 8 is an explanatory diagram of a ferroelectric memory cell according to a seventh embodiment of the present invention.
In this figure, 6 is a support substrate, 7 is an electrode, 8 is a ferroelectric layer, 9 is a semiconductor thin film, 10 is an ohmic or low contact resistance electrode, and 11 is a Schottky electrode.
[0042]
The basic structure of the ferroelectric memory cell of this embodiment is the same as that of the ferroelectric memory cell of the third embodiment described with reference to FIG. 4, except that a semiconductor thin film 9 is formed on a support substrate 6, A ferroelectric layer 8 is formed on a part of the ferroelectric layer 8, an electrode 7 is formed on the ferroelectric layer 8, and an ohmic or low contact resistance electrode 10 and a Schottky electrode 11 are formed on the semiconductor thin film 9. Is formed.
[0043]
Also in this embodiment, the read operation is performed by applying a forward bias voltage to the electrode 7 side between the electrode 7 and the ohmic or low contact resistance electrode 10 as described above. A data write operation is performed by applying a bias voltage between the Schottky electrodes 11.
[0044]
(Eighth embodiment)
FIG. 9 is an explanatory diagram of a ferroelectric memory cell according to an eighth embodiment of the present invention.
In this figure, 6 is a support substrate, 7 is an electrode, 8 is a ferroelectric layer, 9 is a semiconductor thin film, 10 is an ohmic or low contact resistance electrode, and 11 is a Schottky electrode.
[0045]
The basic structure of the ferroelectric memory cell of this embodiment is the same as that of the ferroelectric memory cell of the third embodiment described with reference to FIG. 10 and a Schottky electrode 11 are formed at an interval, a semiconductor thin film 9 is formed thereon, a ferroelectric layer 8 is formed thereon, and an electrode 7 is formed on the ferroelectric layer 8. ing.
[0046]
Also in this embodiment, the read operation is performed by applying a forward bias voltage to the electrode 7 side between the electrode 7 and the ohmic or low contact resistance electrode 10 as described above. A data write operation is performed by applying a bias voltage between the Schottky electrodes 11.
[0047]
(Ninth embodiment)
FIGS. 10A and 10B are explanatory diagrams of a ferroelectric memory according to a ninth embodiment of the present invention, wherein FIG. 10A is a sectional view and FIG. 10B is an enlarged view of a part of FIG.
6 is a supporting substrate, 7 is an electrode, 8 is a ferroelectric layer, 9 is a semiconductor thin film, 10 is an ohmic or low contact resistance electrode, 11 is a Schottky electrode, 12 is a number of ferroelectric memory cells. A memory cell array chip, 13 is a peripheral circuit for driving the memory cell array, and 14 is a bump.
[0048]
In the ferroelectric memory of this embodiment, the ferroelectric memory cell of the fifth embodiment described with reference to FIG. 6 or the ferroelectric memory cell of the seventh embodiment described with reference to FIG. Thus, a ferroelectric memory cell array chip 12 in which electrodes of a large number of ferroelectric memory diodes are formed only on one side of a semiconductor substrate or a support substrate, and a peripheral circuit 13 for driving a memory cell array are bonded.
[0049]
An example using the ferroelectric memory cell of the seventh embodiment described with reference to FIG. 8 will be described. A semiconductor thin film 9 is formed on a support substrate 6, and a ferroelectric layer 8 is formed on a part of the thin film. A ferroelectric memory cell chip in which an electrode 7 is formed on the ferroelectric layer 8 and an ohmic or low contact resistance electrode 10 and a Schottky electrode 11 are formed on the semiconductor thin film 9; Peripheral circuits 13 for driving the memory cell array are connected and bonded by the bumps 14.
[0050]
The ferroelectric or semiconductor used for the ferroelectric memory cell of the present invention is often an oxide material, and a ferroelectric memory cell made of such an oxide is usually used as a memory composed of an integrated circuit of Si. When manufactured together with the peripheral circuit of the above, mutual contamination and the like become a problem in the manufacturing process. However, according to the ferroelectric memory of this embodiment, the circuit element which does not want to be contaminated can be manufactured separately. , Can eliminate the problem of contamination.
[0051]
【The invention's effect】
As described above, according to the present invention, in a memory cell using a ferroelectric memory diode, an effect of reducing a current flowing at the time of writing is exhibited, which is effective in realizing a high-density ferroelectric memory with low power consumption. It is.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating current-voltage characteristics of a memory diode and the principle of a memory operation.
FIG. 2 is an explanatory diagram of a ferroelectric memory cell according to the first embodiment of the present invention.
FIG. 3 is an explanatory diagram of a ferroelectric memory cell according to a second embodiment of the present invention.
FIG. 4 is an explanatory diagram of a ferroelectric memory cell according to a third embodiment of the present invention.
FIG. 5 is an explanatory diagram of a ferroelectric memory cell according to a fourth embodiment of the present invention.
FIG. 6 is an explanatory diagram of a ferroelectric memory cell according to a fifth embodiment of the present invention.
FIG. 7 is an explanatory diagram of a ferroelectric memory cell according to a sixth embodiment of the present invention.
FIG. 8 is an explanatory diagram of a ferroelectric memory cell according to a seventh embodiment of the present invention.
FIG. 9 is an explanatory diagram of a ferroelectric memory cell according to an eighth embodiment of the present invention.
FIGS. 10A and 10B are explanatory diagrams of a ferroelectric memory according to a ninth embodiment of the present invention, wherein FIG. 10A is a sectional view and FIG. 10B is an enlarged view of a part of FIG.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 electrode 2 ferroelectric layer 3 semiconductor substrate 4 ohmic or low contact resistance electrode 5 Schottky electrode 6 support substrate 7 electrode 8 ferroelectric layer 9 semiconductor thin film 10 ohmic or low contact resistance electrode 11 Schottky electrode 12 ferroelectric Cell array chip 13 in which a large number of body memory cells are arranged 13 Peripheral circuit 14 for driving a memory cell array 14 Bump

Claims (5)

In a diode type ferroelectric memory cell composed of a semiconductor substrate, a ferroelectric layer and a metal,
A data write electrode arranged on the semiconductor substrate and in Schottky contact;
A ferroelectric memory cell comprising: a data read electrode disposed on the semiconductor substrate and in contact with a low resistance or ohmic contact. In a diode type ferroelectric memory cell composed of a semiconductor thin film , a ferroelectric layer and a metal,
A support substrate;
A data reading electrode which is disposed on the supporting substrate and has a low resistance or ohmic contact,
It said semiconductor thin film disposed on the data read electrode,
A ferroelectric memory cell comprising: a data write electrode disposed on the semiconductor thin film and in Schottky contact. In a diode type ferroelectric memory cell composed of a semiconductor thin film , a ferroelectric layer and a metal,
A support substrate;
It said semiconductor thin film disposed on the support substrate,
A data reading electrode which is disposed on the semiconductor thin film and has a low resistance or ohmic contact;
A ferroelectric memory cell comprising: a data write electrode disposed on the semiconductor thin film and in Schottky contact. The ferroelectric memory cell of any one of claims 1 to 3 semiconductor substrate or a semiconductor thin film is characterized in that it consists of SrTiO _3. Bonding a memory cell array in which a plurality of ferroelectric memory cells are arranged and a peripheral circuit chip for driving the memory cell array
The ferroelectric memory cell according to claim 3, wherein:

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