JP3535905B2 - COB memory module and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a COB (Chip On Boar)
d) A memory module and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a memory module has a structure in which a large number of memory ICs, which are plastic-sealed for surface mounting, are soldered to a glass epoxy substrate or the like on one side or both sides. After soldering, wash the flux and then check the electrical characteristics. Then, after that, the defective IC is replaced, the electric characteristic is checked again, and the defective memory is eliminated, and the completed memory module is manufactured.

[0003]

However, the conventional memory module and the manufacturing method thereof have the following problems. (1) Since a plastic-encapsulated memory IC is used, cost reduction due to modularization cannot be obtained.

(2) The package size of the plastic encapsulation is standardized, and the degree of freedom in design is small with respect to miniaturization and thinning of the module.

(3) When trying to make the memory module into a COB, it has been difficult to achieve both quality assurance and cost reduction.

(4) It is difficult to reduce the weight because a plastic-encapsulated memory IC is used.

[0007]

In order to solve the above-mentioned problems, in the first invention of the present invention, a COB memory memory is used.
Wiring pattern and multiple recesses on the main surface of the joule
And a metal film formed on the bottom surface of the recess.
And a plurality of pads having a pad and mounted on the metal film.
A memory chip (hereinafter referred to as "bare chip"),
A button for electrically connecting the pad and the wiring pattern.
Bonding wire and a sealing tree for sealing the bare chip
It has fat.

In the second invention, the COB conversion method of the first invention is used.
In the memory module, the metal film is formed in another recess.
It is not electrically connected to the formed metal film. Third
In the invention, in the COB memory module of the first invention,
In addition, the metal film is a copper foil. In the fourth invention,
In the COB-ized memory module according to the first invention,
A memory IC is mounted on the resin.

According to a fifth aspect of the invention, a COB memory module is provided.
The main surface has a wiring pattern and multiple recesses.
And the wiring pattern mounted on the plurality of recesses.
A plurality of first bare chips electrically connected to the
The wiring pattern mounted on the first bare chip
A second bare chip electrically connected to the first bare chip;
And a sealing resin that seals the second bare chip.
It

According to a sixth aspect of the invention, the COB conversion method of the fifth aspect is used.
In the memory module, a metal film is formed on the bottom of the recess.
And the first bare chip is mounted on the metal film.
It In the seventh invention, the COB memory module of the sixth invention is used.
In the tool, the metal film is a copper foil.

According to an eighth aspect of the invention, a COB memory module is provided.
In the manufacturing method of a film, a front surface and a back surface facing the front surface.
Prepare a substrate having and facing from the front surface to the back surface.
Then, scrape the substrate and make a recess so that it does not reach the back surface.
Then, a metal film is formed on the bottom surface of the recess. And
Form a wiring pattern on the surface and bond it on the metal film
Forming a layer, mounting a memory chip on the adhesive layer,
The memory chip and the wiring pattern are bonded together.
Electrically connect using ear to seal the memory chip
Seal with resin.

According to a ninth aspect of the invention, the COB conversion method of the eighth aspect is used.
In the method for manufacturing a memory module, the adhesive layer is
After mounting the memory chip, the electrical
When the characteristic is judged to be defective by the characteristic inspection,
In this case, another memory chip is mounted on the memory chip.

According to a tenth aspect of the invention, there is provided a first COB memory.
The second COB memory module is installed in the module
A COB memory module configured as
The first COB memory module has a main surface and a back surface.
And having a first wiring pattern and a plurality of first recesses on the main surface.
And a first portion penetrating the main surface and the back surface.
A first substrate having a through hole, a first pad, and
The plurality of first bare chips mounted in the plurality of first recesses
And the first pad and the first wiring pattern
A first bonding wire electrically connected to the first bonding wire;
Consists of a first sealing resin for sealing one bare chip
Has been done. Further, the second COB memory module
Has a main surface and a back surface, and has a second surface on the main surface.
A line pattern and a plurality of second recesses are formed, and the main surface and
A second substrate having a second through hole penetrating the back surface
And a second pad, which is mounted in the plurality of second recesses
A plurality of second bare chips and the second pad
A second button for electrically connecting to the second wiring pattern.
The bonding wire and the second bare chip
It is composed of a second sealing resin. And said
First COB conversion memory module and the second COB conversion
The memory module includes the first through hole and the second through hole.
It is electrically connected by a connecting pin penetrating the through hole.
According to an eleventh invention, a COB memory module of the tenth invention is provided.
In the tool, the connection pin is a non-chlorine type flux.
It is solder containing solder.

[0014]

According to the present invention , a bare memo is formed in the concave portion on the substrate side.
A bare chip, which is a rechip, is mounted , the bare chip is electrically connected to the wiring pattern on the substrate side, and then is sealed with resin. Input / output can be performed with respect to the bare chip by the wiring pattern on the substrate side.

[0015]

EXAMPLES (First Embodiment) FIG. 1 is a perspective view of the COB memories model <br/> module showing a first embodiment of the present invention. COB of main of the first embodiment
The difference between the memory module and the conventional memory module is that the bare chip, which is a bare memory chip, is adhered to the glass epoxy substrate 1 and is connected to the wiring pattern of the glass epoxy substrate 1 by the bonding wire, and the bare chip is sealed by the epoxy sealing resin. That is, it is a tightly sealed COB memory module.

That is, in the COB memory module of FIG. 1, the dam frame 2 is bonded onto the glass epoxy substrate 1. The dam frame 2 is for increasing the mounting density of the modules and ensuring the bending strength of the modules while keeping the outer dimension (thickness dimension) at a constant value. The holding portions 7a, 7 when the substrates are stacked in any of three directions other than the I / O terminal direction of the dam frame 2
b is formed. The holding portions 7a and 7b are for facilitating the manufacture of the substrate and improving the bending strength of the module.

FIG. 2 is a sectional view taken along line AA in FIG. As shown in FIG. 2, a plurality of recesses are provided on the glass epoxy substrate 1 in the dam frame 2 for mounting the bare chips 3a to 3d. The depth of the recess is the same as the thickness of the bare chips 3a to 3d mounted therein, or deeper by about 100 μm. A copper foil 6, which is an electrically independent metal film, is formed on the entire inner surface of each recess. Since the specific heat of copper is smaller than that of the glass epoxy substrate 1, the copper foil 6 reduces the thermal resistance due to the heat generated during the operation of the bare chips 3a to 3d and improves the heat dissipation.

In the recess, bare chips 3a to 3d (for example, memory chips each having a capacity of 1M and a total of 4M) are formed.
The longitudinal direction is fixed in a direction perpendicular to the longitudinal direction of the glass epoxy substrate 1 by an epoxy adhesive which is an adhesive layer.

Each pad of the bare chips 3a to 3d is connected by a bonding wire 4 to a wiring pattern formed on the glass epoxy substrate 1. The wiring pattern is electrically connected to the I / O terminal 9 provided at the end portion in the longitudinal direction of the glass epoxy substrate 1. External CAS lines, RAS lines, address lines, etc. are connected to the I / O terminal 9. Then, the I / O terminals 9 pass through the wiring pattern and the body wire 4 and CA of the bare chips 3a to 3d.
It is connected to the S terminal, the RAS terminal, the address terminal, and the like.
As a result, the bare chips 3a to 3d can be accessed from the outside.

Further, since the depth of the concave portion of the glass epoxy substrate 1 is made equal to or deeper than the thickness of the bare chips 3a to 3d, the bare chips 3c and 3e can be stacked. This is because when a bare chip 3c is detected to be a defective chip in an intermediate inspection to be described later, a defective non-defective bare chip 3e is mounted on the defective bare chip 3c and re-wire bonding is performed, and the defective non-defective bare chip 3e is defective. The function of the bare chip 3c is replaced.

The bare chips 3a to 3e are hermetically sealed with an epoxy sealing resin 5. The epoxy sealing resin 5 is α
A black resin having a radioisotope content of 0.1 ppb or less is used in order to prevent occurrence of bit errors of the bare chips 3a to 3e due to lines and malfunction of the bare chips 3a to 3e due to photoelectric effect. A plurality of decoupling capacitors 8 are mounted on the glass epoxy substrate 1 by soldering in order to further improve the noise margin.

[0022] As described above, according to the first embodiment has the following advantages. (A) The total thickness of the conventional memory module when the plastic-encapsulated memory IC is mounted on one side is about 4.8 mm.
On the other hand, in the case of the first embodiment to which the COB technology is applied, there is an advantage that the thickness is about 1.9 mm, which is 2/5 thinner than the conventional one. Similarly, in terms of weight, the conventional memory module weighs 17.5 g, while the first
The COB memory module of the above embodiment has an advantage of being 11.5 g, which is 2/3 lighter than the conventional one.

(B) A recess is formed in the glass epoxy substrate 1 on which the bare chips 3a to 3d are mounted, and the bonding pad surfaces of the bare chips 3a to 3d and the ponding pad of the glass epoxy substrate 1 are lowered on the same surface or the bare chip side by about 100 μm. As a method of repairing when a defective bare chip is found, replenishment good bare chips 3e are stacked in two stages on top of the defective bare chip 3c and re-wire bonding becomes possible. In consideration of mass productivity, the wire length of the bonding wire 4 needs to be 4 times or more of the height difference. Therefore, when the epoxy substrate 1 is not provided with a recess, the mounting design should be performed assuming a doubled chip thickness. This hinders downsizing and thinning, but
In the first embodiment, since the concave portion is provided, downsizing and thinning can be easily realized.

(C) By providing the copper foil 6 on the entire inner surface of the recess, the thermal resistance is reduced and the heat dissipation effect is improved.

The (d) The by chip long side and COB memories Mo <br/> was perpendicular Joule long side direction mounting,
It is possible to improve the warp resistance of the module by minimizing the stress applied to the module on the bare chips 3a to 3e.

[0026] Figure 3 (method for manufacturing a COB of the memory module of FIG. 1) is a diagram of a manufacturing process flow illustrating a method of manufacturing COB of the memory module of FIG. Hereinafter, a method of manufacturing the COB memory module of FIG. 1 will be described with reference to FIG.

First, the glass epoxy substrate of the concave portion is die-cut. In order to make the recess deeper than the thickness of the bare chip to be mounted, the glass epoxy substrate is made thicker than the bare chip. Then, the die-cut glass epoxy substrate and another glass epoxy substrate having a copper foil formed on the surface are laminated by a hot press ( hereinafter referred to as "multilayer substrate lamination method").
Say. ). Next, a wiring pattern of soft gold plating for wire bonding, an I / O terminal 9 and the like are formed on the surface layer.
Then, the die-cut glass epoxy substrate 1 is bonded to the glass epoxy substrate 1 by the method of laminating a multilayer substrate.

Next, in step S1 in FIG. 3, an adhesive is applied to the concave surface of the glass epoxy substrate 1. In step S2, bare chips 3a to 3d are mounted in the recesses of the glass epoxy substrate 1 coated with the adhesive. In step S3, the adhesive is thermoset. In step S4, the pads of the bare chips 3a to 3d and the wiring pattern of the glass epoxy substrate 1 are connected by the bonding wires 4. In step S5, the electrical connection check, the actual operation timing check, and the high temperature operation check of the bare chips 3a to 3d are performed to detect a defective bare chip (for example, 3c) in the initial stage of the manufacturing process.

FIG. 4 is a sectional view of the main part of the bare chip inspection apparatus. Hereinafter, referring to FIG. 4, step S5
The intermediate inspection of the bare chips 3a to 3d will be described in detail.

After the steps S1 to S4, the test module 50 has the Teflon insulating plate 5 on the heater 54.
5 is mounted. The test module 50 is covered with a light shielding plate 51 for preventing soft errors of the bare chips 3a to 3d. Test module 5
0 I / O terminal 9 has test probe pins 52a, 52
touching b. Test probe pins 52a, 52b
Is connected to the tester.

First, the heater 54 heats the test module 50 to a temperature of 70 ° C. Then, a predetermined voltage is applied to the I / O terminal 9 from the test probe pins 52a and 52b, and a functional test, an electrical characteristic test, and the like are performed by a tester to detect a defective bare chip. If there is no defective bare chip, the process proceeds to step S6. If there is a defective bare chip (for example, 3c), the process proceeds to step S11.

At step S6, bare chips 3a ...
3d is hermetically sealed with an epoxy sealing resin 5 which is a black resin having no thixotropy. In step S7, the amount of warpage of the glass epoxy substrate 1 is measured and set in a jig so as to be warped in the opposite direction by the same amount as the amount of warpage, and at 150 ° C which exceeds the glass transition temperature of the epoxy sealing resin 5. After heating for 10 minutes or more, it is cooled at room temperature to balance the curing shrinkage stress of the epoxy sealing resin 5 and the warp of the glass epoxy substrate 1 to correct the warp. The amount of reverse warp is increased in proportion to the weight of the epoxy sealing resin.

In step S8, the decoupling capacitor 8 is solder-mounted (SMT: surface mount technology) using a chlorine-containing flux-containing solder. In step S9, a completion inspection is performed.
Results of the completed test, discard the COB memories modular <br/> Yuru if fail, if the path to the completion of the COB memories module <br/> Lumpur.

If a defective bare chip (for example, 3c) is found by the intermediate inspection in step S5, in step S11, the bonding wire 4 of the defective bare chip 3c and the gold ball on the pad of the defective bare chip 3c are removed to obtain the defective bare chip. Surface flatness of 50μ
m or less. In step S12, the adhesive is applied again on the defective bare chip 3c. In step S13, the alternative bare chip 3e is mounted.

In step S13, the adhesive is thermoset. In step S14, re-wire bonding is performed on the alternative bare chip 3e. After that, step S
The process proceeds to the intermediate inspection of No. 5, and steps S6 to S8 or steps S11 to S15 are repeated according to the inspection result.

As described above, this embodiment has the following advantages. (A) Since the method of forming a through hole, which is a through hole, is applied to the formation of the recess, there are advantages of improving the flatness and parallelism of the bottom surface of the recess and suppressing the cost, as compared with the conventional technique of spot facing.

(B) Since the chlorine-free flux-containing solder is used, it is not necessary to clean the entire COB memory module.

[0038] (Second Embodiment) FIG. 5 is a perspective view of the COB memories model <br/> module showing a second embodiment of the present invention, B-B cross section in FIG. 6 5 It is a figure.

[0039] The COB of memory modules, a main memory module <br/> Le a first COB of memory modules, sub-note is a second COB of memory modules
And the re module is a superimposed structure. The main memory module has a substantially similar structure as the COB of the memory module of FIG. 1, the first glass epoxy substrate 11
The first dam frame 112, the first bare chip 113,
It is composed of a first epoxy sealing resin 115, a first decoupling capacitor, an I / O terminal 119 and the like. The first wiring pattern on the first glass epoxy substrate 111 and the pad of the first bare chip 113 are electrically connected by the first bonding wire 114.

The sub- memory module is also C in FIG.
It has the same structure as the OB memory module.
On the glass epoxy substrate 131, the second dam frame 132, the second bare chip 133, the second epoxy sealing resin 135, the second decoupling capacitor 138 and the like are formed. The second wiring pattern on the second glass epoxy substrate 131 and the pad of the second bare chip 133 are electrically connected by the second bonding wire 134. Sub-memory module, in order to share I / O pins 119 of the main memory module, the sub-memory Mogi <br/> Yuru I / O pins is not provided.

Positioning reference holes 121a and 121b are formed in the left and right ends of the glass epoxy substrate 111, respectively. Positioning reference holes 141a and 141b are also formed in the left and right ends of the glass epoxy substrate 131, respectively. Then, the glass epoxy substrates 111 and 131 are stacked so that the positioning reference holes 121a and 141a and the positioning reference holes 121b and 141b are aligned with each other.

As shown in FIG. 6, the first I / O terminal 119 of the glass epoxy board 111 of the main memory module is connected to the first memory module.
A through hole 122, which is a through hole, is opened.
Further, the glass epoxy substrate 131 of the sub memory module on the I / O terminal 119 is also provided with a through hole 142 which is a second through hole. Through holes 122, 14
2, the connection pins 151 from the sub memory module side
There is pressed, a main memory module and the sub-memory modular <br/> Yuru is electrically and mechanically connected. Connection pin 15
1 has projections 153 and 152 at the contact portions with the glass epoxy substrates 111 and 131.

The dimensions of the protrusions 152 and 153 are stepwise different from each other by 120% and 110% of the diameter of the connecting pin 151. The hole diameters of the through holes 142 and 122 are also
113% of the pin diameter, 112%, respectively
It is different from%. The connection strength is secured at 1 Kgf / pin or more and stability is maintained.

In the recesses of the glass epoxy substrates 111 and 131,
Bare chips 113 and 133 are mounted. For example,
The main memory module is equipped with eight memory chips each having a 4-bit capacity of 0.5M (32-bit structure having a total capacity of 4M), and the sub- memory module similarly has a 32-bit structure having a total capacity of 4M. Has become. On the glass epoxy board 111 of the main memory module, I /
An O terminal 119 is provided, and this I / O terminal 119
Connector is connected to.

The sub memory module is not provided with an I / O terminal and is connected to the outside by the I / O terminal 119. Therefore, the connection pin 151 has the I / O terminal 11
9 and the sub memory module are electrically connected. I /
A pin number is specified for the O terminal 119.
Data line, address line, and CAS at O terminal 119
Line, RAS line, etc. are connected. The main memory module and the sub memory module share the data line, the address line, and the CAS line, and
Only the S line is provided separately.

The connection pins 151 are connected to the bare chip 11 by the wiring patterns of the main memory module and the sub memory module and the bonding wires 114 and 134.
3, 133 are electrically connected to address terminals and the like.
Thus, main memory modules and sub-menu from the external
It becomes accessible to the bare chip 113 and 133 of the memory module.

As described above, the difference in the wiring pattern between the main memory module and the sub memory module is that the RAS is different.
Only the wiring pattern of the line is made, and the glass epoxy substrates 111 and 131 in which the wiring pattern of this part is changed are made, and 2
By stacking and connecting with connecting pin 151, 2
Times (e.g., 4M memory module is a memory module 2 Tsude 8M) becomes the capacity of the memory modules.

As described above, the second embodiment has the following advantages. (A) a memory module of the first embodiment as the main memory <br/> module, COB of small and memory modules to change slightly the wiring patterns by a sub memory modules, more than double the capacity The memory module can be manufactured at low cost.

(B) The assembly cost such as wire bonding / molding of the conventional plastic-sealed product is not included in the COB memory module, and the encapsulation is performed by the memory module collectively. Therefore, the manufacturing cost is higher than that of the conventional product. Can be reduced by 20% or more.

(C) Plastic-encapsulated memory I
In the conventional memory module in which C is mounted, the manufacturing process is assembled on the assumption that the mounted IC memory is a good product, and the completion inspection yield of the memory module is also good. On the other hand, in the COB memory module,
It is important to set up the manufacturing process on the assumption that there is a defective bare chip, and the mounting structure of this embodiment can perform the inspection required for the module in the intermediate inspection process and easily repair the defective bare chip found there. Depending on the manufacturing method, C
The OB memory module can be realized at low cost.

[0051] (Manufacturing method of COB of the memory module of FIG. 5) FIG. 7 is a diagram of a manufacturing process flow illustrating a method of manufacturing COB of the memory module of FIG. Hereinafter, a method of manufacturing the COB memory module of FIG. 5 will be described with reference to FIG. 7.

First, a good product of the main memory module and a good product of the sub memory module that have passed the completion inspection through the steps S1 to S15 of FIG. 3 are prepared. However, the main memo in the previous process of step S1 of FIG.
Glass-epoxy board 1 for re- module and sub- memory module
Reference holes 121a, 121b for positioning in 11, 131,
141a, 141b and through holes 122, 142 are opened.

In step S21, the reference holes 121a and 121b for positioning the main memory module and the sub holes
Reference holes 141a, 141 for positioning the memory module
After vertically overlapping with b, the connection pin 151 is press-fitted into the through holes 122 and 142 of both modules from above to perform electrical / mechanical connection between both modules. In step S22, a completion inspection is performed. If the result of the completion inspection is failure, it is discarded, and if it is a pass, it is regarded as a completed memory module.

As described above, in this embodiment, since the chlorine-free flux-containing solder is used and the connection bin 151 is press-fitted and connected, it is not necessary to wash the entire COB memory module.

(Third Embodiment) FIG. 8 is a sectional view of a COB type memory module according to a third embodiment of the present invention. In the COB memory module of the third embodiment, the glass epoxy substrate in which a wiring pattern is formed on the bottom surface (B surface) of the recess, with the depth of the recess being 2-3 times the thickness of the bare chip to be mounted. 201 is used. The bare chip 203 is fixed to the concave portion of the glass epoxy substrate 201 with an epoxy adhesive, and the bare chip 203 and the wiring pattern are electrically connected by the bonding wire 204. The bare chip 203 is made of the epoxy sealing resin 20.
5, the surface of the epoxy sealing resin 205 is sealed so as not to project from the upper surface (A surface) of the glass epoxy substrate 201.

A wiring pattern is also formed on the surface A of the glass epoxy substrate 201. The leads of the plastic-encapsulated memory IC 206 mounted on the surface A and the land (wiring pattern) on the surface are connected by soldering. Connection between the pad of the bare chip 203 and the wiring pattern by the bonding wire 204, and the memory IC 206
The bare chip 203 and the memory IC 206 are electrically connected to each other by soldering the leads and the wiring pattern.

The bare chip 203 and the memory IC 206 are
Any type can be used depending on the purpose of implementation. It is only necessary to change the wiring pattern on the A side and the wiring pattern on the B side. For example, the control lines such as the address line, the RAS line, the CAS line, and the WE line are the bare chip 203 and the memory IC 2
It is also possible to share it with 06 and separate only the data line.

Further, in a 1M × 36 (4Mb) configuration, bits 0 to 31 are configured by bare chips 203 mounted on the glass epoxy substrate 201, and memory IC 206 is used when parity bits of bits 32 to 35 are required. You can Accordingly, the same glass epoxy substrate 201 can be changed to another type of memory module by post-processing.

As described above, the third embodiment has the following advantages. (A) By adopting a structure in which the bare chip 203 is embedded in the concave portion, surface mounting components can be mounted because there is no convex portion such as the epoxy sealing resin 205 on the substrate surface, and the memory IC 206 of the same substrate size is plastic-sealed. By implementing, it is possible to realize double the memory capacity.

(B) By sharing the parity bit with the surface-mounted memory IC 206, the parity bit can be added with the same substrate size.

[0061] (Fourth Embodiment) FIG. 9 is a cross-sectional view of the COB memories model <br/> module showing a fourth embodiment of the present invention. In this COB memory module, recesses having a depth of 2 to 3 times the bare chip thickness are provided on the upper surface (A surface) and the lower surface (C surface) of the glass epoxy substrate 211. Wiring patterns are formed on the surfaces of the concave portions on the A surface and the B surface. Bare chips 213a and 213b are fixed in the recesses on the A and B sides with an epoxy adhesive, and the bare chips 213a and 213b and the wiring pattern are electrically connected by bonding wires 214a and 214b.

The epoxy sealing resins 215a and 215b are used to seal the glass epoxy substrate 211 so as not to project from the A and B surfaces. Wiring patterns are also formed on the A and B surfaces of the glass epoxy substrate 211. On sides A and B,
Memory ICs 216a and 216 that are plastic-sealed
The lead of b and the land (wiring pattern) are connected by soldering.

As described above, the fourth embodiment has the following advantages. (A) Bare chips 213 on both surfaces of the glass epoxy substrate 211
Since a, 213b and memory ICs 216a, 216b are mounted, a memory capacity four times larger can be realized with the same substrate size. (B) The glass epoxy substrate size can be reduced by making the capacities the same.

(Fifth Embodiment) FIG. 10 is a sectional view of a COB type memory module showing a fifth embodiment of the present invention. COB conversion of the fifth embodiment
The memory module, the upper surface and the lower surface of the glass epoxy substrate 211 in the COB memories <br/> module of the fourth embodiment are reduced in thickness without mounting a memory IC that sealed plastic seal.

According to the fifth embodiment, it is possible to reduce the thickness dimension, and similarly to the second embodiment, by press-fitting and connecting two or more modules with the connection pins 151, it is easy to increase the capacity. There is an advantage that can be realized.

(Sixth Embodiment) FIG. 11 shows a sixth embodiment of the present invention.
FIG. 3 is a perspective view of a COB-ized memory module showing the embodiment of FIG. 12 is a sectional view taken along line CC in FIG. 11, and FIG. 13 is FIG.
FIG.

In the COB-implemented memory module of the sixth embodiment, the two memory modules are the ones that have been inspected by the individual modules, and are stacked so as to have a front-back symmetrical structure. ing.

The lower memory module is composed of the first glass epoxy substrate 301 and the components on the back surface thereof. The upper memory module is the second glass epoxy substrate 3
21 and parts on its surface. On the back surface of the glass epoxy substrate 301, as in the first embodiment, the first bare chip mounted in the recess and connected to the first wiring pattern by the first bonding wire,
The epoxy sealing resin, the first I / O terminal 309, the first decoupling capacitor, and the like.

On the surface of the glass epoxy substrate 321, as in the first embodiment, the second bare chip 323 mounted in the recess and connected to the second wiring pattern by the second bonding wire, and the second bare chip 323. It is composed of an epoxy sealing resin 325, a second I / O terminal 329, a second decoupling capacitor 328, and the like.

In order to overlap the upper and lower memory modules, the reference holes 33 are formed at the ends of the glass epoxy substrates 301 and 321.
1a and 331b are opened, and the upper and lower reference holes 331
two glass epoxy substrates 30 so that a and 331b are matched.
1, 321 are overlapped.

Further, semi-cylindrical end face through holes 332a, 332b, 332c are opened at the end portions of the glass epoxy substrate 321 in the lateral direction and the longitudinal direction in order to electrically and mechanically connect to the glass epoxy substrate 301. Has been.

End face through holes 332a, 332b, 3
Solder 333a that has been welded inside 32c and has a skirt extending outward
The land (wiring pattern) of the glass epoxy substrate 301 and the land (wiring pattern) of the glass epoxy substrate 321
And are electrically and mechanically connected.

Since different signals are input to the I / O terminals 309 and 319 of the glass epoxy boards 301 and 321, the bare chips 32 mounted on the glass epoxy boards 301 and 321 are input.
3, ... are end face through holes 332a, 332b, 33
Electrical connection is made through the solder 333a in 2c and the wiring pattern.

As described above, in the sixth embodiment, CO
This is effective when the board thickness (connector section) of the B memory module is specified and you want to reduce the thickness.
There is an advantage that a memory card or the like can be easily realized at low cost.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the COB memory module of FIG.
In the through hole 122 and the sub-memory mode <br/> module of the through hole 142 of the memory module has been mechanically connected by press-fitting the connecting pin 151, the through hole 122 of the I / O terminals 119 of the main memory modules Connection pin 1
The sub memory module can be easily attached and detached by press-fitting 51 and providing a female socket on the sub memory module side. Thus, by replacing the sub-memory model <br/> module, the capacity of the memory modules can be easily changed, without wasting the cost of the main memory modules end-user investment once,
The memory capacity can be easily increased by the end user himself.

(2) The third and fourth embodiments are applied to the memory module, but there are many application examples by combining the bare chip ICs in the substrates 201 and 211 with the surface mount components. For example, plastic encapsulation ICs are digital ICs such as gate arrays and CPUs.
By using the bare chip as an analog IC such as an operational amplifier and a comparator and mounting surface mounting components such as resistors and capacitors, it is possible to realize a functional module with a high mounting density. In addition, surface mount parts are EPROM,
If the bare chip is applied to an MCM or the like by using a custom circuit such as a CPU or G / A, it can be realized as a user programmable function module.

(3) In the embodiment, the construction using the dam frames 2, ... Is described. However, when the epoxy sealing resin 5, .. It is possible to seal the bare chips 3a, ...

[0078]

As described above in detail, the first to the fourth
According to the invention, a wiring pattern and a plurality of recesses are formed on the main surface.
And a metal film formed on the bottom surface of the recess
And a bare chip that is a bare memory chip
Since it is mounted on the metal film on the bottom surface of the recess and connected to the wiring pattern on the substrate side, it is resin-sealed to form a COB memory module, so it is possible to easily realize miniaturization and thinning, and reduce cost. it can. Moreover, a metal film is formed on the bottom of the recess.
Since it is formed, the thermal resistance is reduced and the heat dissipation effect is improved. First
According to the fifth to seventh inventions, the concave portion formed on the substrate is
A stack of first and second bare chips, which are memory chips
Then, seal the first and second bare chips with resin.
Since it is a COB memory module, it is smaller and thinner.
Can be easily realized, and the cost can be reduced. It
In addition, for example, as a repair method when finding a defective bare chip
The defective bare chip on top of the defective bare chip in two stages
Overlapping and reconnection is possible. According to the eighth invention, a substrate
To form a recess on the bottom surface of the recess,
The memory chip was mounted on the metal film via the adhesive layer.
After that, it is sealed with resin, so it is small and thin and radiates heat.
COB memory module with excellent effect can be installed at low cost.
Easy to manufacture. According to the ninth invention, the metal on the bottom surface of the recess is
Mount the memory chip on the film via the adhesive layer,
The electrical characteristics of the rechip were inspected, and it was determined that the chip was defective.
In this case, install a good memory chip on the memory chip.
As a result, defective memory chips can be easily repaired.
To improve the manufacturing yield of non-defective products and reduce the manufacturing cost.
Wear. According to the tenth and eleventh aspects, the recess is formed in the substrate.
A bare chip, which is a memory chip, is mounted and sealed with resin.
The first COB memory module stopped and the recess of the substrate
Bare chip, which is a bare memory chip, is mounted on the
Stacked with the second COB memory module that is resin-sealed
And the first and second COB-based memory modules
Memory is connected electrically by connecting pins
Capacity can be easily increased at low cost. Moreover, for example,
When a defective bare chip is found in the intermediate inspection process,
This defective bare chip can be easily repaired and the yield of good products can be improved.
A low cost COB memory module with improved
realizable.

[Brief description of drawings]

1 is a perspective view of the COB memories model <br/> module showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA in FIG.

3A to 3D are manufacturing process diagrams showing a manufacturing method of the COB memory module of FIG.

FIG. 4 is a cross-sectional view showing a main part of the inspection device.

5 is a perspective view of the COB memories model <br/> module showing a second embodiment of the present invention.

6 is a sectional view taken along line BB in FIG.

7A to 7C are manufacturing process diagrams showing a manufacturing method of the COB memory module of FIG.

8 is a cross-sectional view of the COB memories model <br/> module showing a third embodiment of the present invention.

9 is a cross-sectional view of the COB memories model <br/> module showing a fourth embodiment of the present invention.

FIG. 10 is a cross-sectional view of a COB type memory module showing a fifth embodiment of the present invention.

FIG. 11 is a sectional view of a COB type memory module showing a sixth embodiment of the present invention.

12 is a cross-sectional view taken along line CC of FIG.

FIG. 13 is a perspective view of FIG.

[Explanation of symbols]

1,111,131,201,211,301,321
Laepo board 2, 112, 132
Dam frames 3a to 3e, 113, 133, 203, 213a, 21
3b, 323 bare chip 4, 114, 134, 204, 214a, 214b
Bonding wires 5,115,135,205,215a, 215b, 3
25 epoxy sealing resin 6
Copper foil 7a, 7b
Holding parts 9, 119, 309, 329
I / O terminals 121a, 121b, 141a, 141b, 331a,
331b Reference holes 122 and 142
Through hole 151
Connection pins 152,153
Protrusions 206, 216a, 216b
Memory ICs 332a, 332b, 332c
End face through hole 333a
solder

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-3-211763 (JP, A) JP-A-6-29422 (JP, A) JP-A-6-45517 (JP, A) JP-A-2- 58356 (JP, A) JP-A-2-63141 (JP, A) JP-A-1-144664 (JP, A) JP-A-1-293555 (JP, A) JP-A-3-185753 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 25/04 H01L 25/18

Claims (3)

(57) [Claims] 1. A substrate having a front surface and a back surface facing the front surface is prepared, the substrate is ground from the front surface toward the back surface, and a recess is formed so as not to reach the back surface. A metal film is formed on a bottom surface, a wiring pattern is formed on the surface, an adhesive layer is formed on the metal film, a first memory chip is mounted on the adhesive layer, and an electrical property of the first memory chip is formed. Characteristic test,
If the first memory chip is determined to be defective, the first memory chip is
A second memory chip is mounted on a memory chip, and when the second memory chip is mounted, the second memory chip and the wiring pattern are electrically connected using a bonding wire. Then, the second memory chip is encapsulated with an encapsulating resin to produce a COB memory module. 2. A COB configured by mounting a second COB-ized memory module on a first COB-ized memory module.
An integrated memory module, wherein the first COB-based memory module has a main surface and a back surface, a first wiring pattern and a plurality of first recesses are formed on the main surface, and the main surface and the back surface are formed. A first substrate having a first through hole penetrating the back surface; a plurality of first bare memory chips having a first pad and mounted in the plurality of first recesses; A first bonding wire that electrically connects the first pad and the first wiring pattern, and a first sealing resin that seals the first bare memory chip, The second COB memory module has a main surface and a back surface, a second wiring pattern and a plurality of second recesses are formed on the main surface, and penetrates the main surface and the back surface. A second substrate having a second through hole, a second pad, and A plurality of second bare memory chips mounted in a plurality of second recesses; a second bonding wire electrically connecting the second pad and the second wiring pattern; And a second encapsulation resin for encapsulating the bare memory chip of the first COB memory module and the second CO
The B-type memory module includes the first through hole and the second through hole.
A COB type memory module, which is electrically connected by a connecting pin penetrating through the through hole. 3. The COB type memory module according to claim 2, wherein the connection pin is a solder containing chlorine-free flux.