JP3530438B2 - Overdrive prevention drive circuit - Google Patents
Overdrive prevention drive circuitInfo
- Publication number
- JP3530438B2 JP3530438B2 JP34562699A JP34562699A JP3530438B2 JP 3530438 B2 JP3530438 B2 JP 3530438B2 JP 34562699 A JP34562699 A JP 34562699A JP 34562699 A JP34562699 A JP 34562699A JP 3530438 B2 JP3530438 B2 JP 3530438B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- voltage
- collector
- drive circuit
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Amplifiers (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は駆動回路、特にマイ
コン等の信号を受けてバスラインに一定電圧以下での駆
動信号を供給するオーバードライブ防止駆動回路に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit, and more particularly to an overdrive prevention drive circuit which receives a signal from a microcomputer or the like and supplies a drive signal at a constant voltage or less to a bus line.
【０００２】[0002]
【従来の技術】モバイル機器の普及に伴い、マイコン等
の信号をバスラインに供給する際にできる限り内蔵二次
電池の電源電圧に近い値の出力信号を供給できる電圧ロ
スの少ないオーバードライブ防止駆動回路が求められて
いる。図２に従来のオーバードライブ防止駆動回路を示
す。従来のオーバードライブ防止駆動回路ではオペアン
プと基準電圧との組み合わせた回路構成が一般的であっ
た。まずオペアンプの＋入力端子と電源端子Ｖｃｃ間に
基準電圧ＶＲＥＦを接続し、オペアンプの−入力端子は
出力端子ＶＯＵＴに接続される帰還ループを作ってい
る。マイコン等からのオン/オフ信号はＮＰＮトランジ
スタＱ１のベースに印加され、エミッタはアース端子Ｇ
ＮＤに、コレクタはオペアンプの出力端子に抵抗Ｒ１を
介して接続されている。ＮＰＮトランジスタＱ２はベー
スをトランジスタＱ１のコレクタに接続され、エミッタ
はアース端子ＧＮＤに接続され、コレクタは抵抗Ｒ２を
介して電源端子Ｖｃｃに接続されている。負荷のドライ
ブをするＰＮＰトランジスタＱ３はコレクタを電源端子
Ｖｃｃに接続され、ベースは抵抗Ｒ２とトランジスタＱ
２のコレクタの接続点に接続され、コレクタは出力端子
ＶＯＵＴに接続されている。次に、このオーバードライ
ブ防止駆動回路の動作について説明する。この回路では
出力端子ＶＯＵＴには電源電圧Ｖｃｃから基準電圧ＶRE
Fを減じた電圧が出力されて、負荷が電源電圧以上まで
オーバードライブされることを防止している。2. Description of the Related Art With the spread of mobile devices, an overdrive prevention drive with a small voltage loss that can supply an output signal of a value as close as possible to the power supply voltage of a built-in secondary battery when supplying a signal of a microcomputer or the like to a bus line A circuit is needed. FIG. 2 shows a conventional overdrive prevention drive circuit. In the conventional overdrive prevention drive circuit, a circuit configuration in which an operational amplifier and a reference voltage are combined is common. First, the reference voltage VREF is connected between the + input terminal of the operational amplifier and the power supply terminal Vcc, and the-input terminal of the operational amplifier forms a feedback loop connected to the output terminal VOUT. The on / off signal from the microcomputer is applied to the base of the NPN transistor Q1, and the emitter is the ground terminal G.
The collector is connected to the output terminal of the operational amplifier via the resistor R1. The NPN transistor Q2 has a base connected to the collector of the transistor Q1, an emitter connected to the ground terminal GND, and a collector connected to the power supply terminal Vcc via the resistor R2. A PNP transistor Q3 for driving a load has a collector connected to the power supply terminal Vcc, and a base having a resistor R2 and a transistor Q2.
It is connected to the connection point of the two collectors, and the collector is connected to the output terminal VOUT. Next, the operation of this overdrive prevention drive circuit will be described. In this circuit, the power supply voltage Vcc is changed to the reference voltage VRE at the output terminal VOUT.
A voltage less F is output to prevent the load from being overdriven to the power supply voltage or higher.
【０００３】すなわち、出力端子ＶＯＵＴの電圧が上昇
すると、オペアンプの出力は帰還ループの働きで減少方
向に動く。この結果、トランジスタＱ１を流れる電流は
減少し、トランジスタＱ２を流れる電流も減少する。こ
れにより抵抗Ｒ２の電圧降下が減少し、ドライブ用のト
ランジスタＱ３がオフ方向に動き、出力端子ＶＯＵＴの
電圧が下がるように動いて、出力端子ＶＯＵＴの電圧を
一定に保つように動作する。That is, when the voltage of the output terminal VOUT rises, the output of the operational amplifier moves in the decreasing direction by the action of the feedback loop. As a result, the current flowing through the transistor Q1 decreases and the current flowing through the transistor Q2 also decreases. As a result, the voltage drop of the resistor R2 is reduced, the driving transistor Q3 moves in the OFF direction, the voltage of the output terminal VOUT decreases, and the voltage of the output terminal VOUT keeps constant.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上述し
た従来のオーバードライブ防止駆動回路ではオペアンプ
を利用しているので、基準電圧ＶＲＥＦを通常は０．２
Ｖ程度に設定されるのが一般的であり、そうすると電源
電圧Ｖｃｃを３．３Ｖとすれば、出力端子ＶＯＵＴには
３．１Ｖの出力しかでてこない課題があった。このため
に二次電池駆動のモバイル機器では非常に電源効率が悪
くなるので、できる限り基準電圧をＶＲＥＦを小さくし
て出力電圧をできる限り電源電圧に近づけたオーバード
ライブ防止駆動回路の実現を求められている。However, since the above-mentioned conventional overdrive prevention drive circuit uses the operational amplifier, the reference voltage VREF is usually 0.2.
It is generally set to about V, and if the power supply voltage Vcc is set to 3.3V, there is a problem that the output terminal VOUT outputs only 3.1V. For this reason, the power supply efficiency is extremely poor in the secondary battery driven mobile device. Therefore, it is required to realize an overdrive prevention drive circuit in which the reference voltage is made as small as possible and VREF is made as close as possible to the output voltage. ing.
【０００５】[0005]
【課題を解決するための手段】本発明はかかる課題に鑑
みてなされ、カレントミラー回路の持つ電流比の特性を
利用して極めて少ない検出電圧で電源電圧に近い出力電
圧を提供できるオーバードライブ防止駆動回路を実現す
るものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and utilizes the characteristics of the current ratio of a current mirror circuit to provide an overdrive prevention drive capable of providing an output voltage close to the power supply voltage with an extremely small detection voltage. It realizes a circuit.
【０００６】[0006]
【発明の実施の形態】本発明の一実施形態を図面を参照
して説明する。図１は、本発明のオーバードライブ防止
駆動回路を説明する回路図である。図１において、ＮＰ
ＮトランジスタＱ１のベースにはマイコン等からのオン
/オフ信号が印加され、エミッタはアース端子ＧＮＤに
接続され、コレクタは定電流源を介して電源端子Ｖｃｃ
に接続されている。ＮＰＮトランジスタＱ２のベースは
トランジスタＱ１のコレクタに接続され、エミッタはア
ース端子ＧＮＤに接続され、コレクタは抵抗Ｒ１を介し
て電源端子Ｖｃｃに接続されている。バスライン等の負
荷ドライブ用のＰＮＰトランジスタＱ３はべースを抵抗
Ｒ１とトランジスタＱ２のコレクタとの接続点に接続
し、エミッタは電源端子Ｖｃｃに接続され、コレクタは
出力端子ＶＯＵＴに接続されている。トランジスタＱ４
とトランジスタＱ５は本発明の特徴とするカレントミラ
ー回路を構成しており、ＰＮＰトランジスタＱ４はエミ
ッタを電源端子Ｖｃｃに接続し、コレクタは抵抗Ｒ２を
介してアース端子ＧＮＤに接続され、ベースはカレント
ミラー回路を構成しているのでベースコレクタを接続し
かつ両トランジスタＱ４Ｑ５のベースは直結されてい
る。ＰＮＰトランジスタＱ５のエミッタは出力端子ＶＯ
ＵＴに接続され、コレクタは抵抗Ｒ3を介してアース端
子ＧＮＤに接続されている。ＮＰＮトランジスタＱ６は
コレクタをトランジスタＱ１のコレクタに接続され、エ
ミッタはアース端子ＧＮＤに接続され、ベースはトラン
ジスタＱ５のコレクタと抵抗Ｒ３の接続点に接続されて
いる。かかる回路構成によれば、カレントミラー回路を
構成するトランジスタＱ４とＱ５とを１：Ｎ の比の大
きさに作ることに特徴がある。従ってトランジスタＱ４
に対してトランジスタＱ５はＮ倍の電流が流れる。トラ
ンジスタＱ６はこの電流を抵抗Ｒ３の電圧降下で検知
し、定電流源の電流を奪うように動作する。すなわち、
ＶＯＵＴ＝Ｖｃｃ− (ｋＴ/ｑ)ｌｎ(Ｎ）で表せる。こ
こで、ｑは電子の電荷量、ｋはボルツマン定数であり、
ｋＴ／ｑは約２６ｍＶ(Ｔ＝３００Ｋ)である。DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram illustrating an overdrive prevention drive circuit of the present invention. In FIG. 1, NP
The base of N-transistor Q1 is turned on by a microcomputer or the like.
/ OFF signal is applied, emitter is connected to ground terminal GND, collector is power supply terminal Vcc through constant current source
It is connected to the. The base of the NPN transistor Q2 is connected to the collector of the transistor Q1, the emitter is connected to the ground terminal GND, and the collector is connected to the power supply terminal Vcc via the resistor R1. A PNP transistor Q3 for driving a load such as a bus line connects the base to a connection point between the resistor R1 and the collector of the transistor Q2, the emitter is connected to the power supply terminal Vcc, and the collector is connected to the output terminal VOUT. . Transistor Q4
And the transistor Q5 constitute a current mirror circuit which is a feature of the present invention. The PNP transistor Q4 has its emitter connected to the power supply terminal Vcc, its collector connected to the ground terminal GND through the resistor R2, and its base connected to the current mirror. Since the circuit is formed, the base and collector are connected and the bases of both transistors Q4 and Q5 are directly connected. The emitter of the PNP transistor Q5 is the output terminal VO.
It is connected to the UT and the collector is connected to the ground terminal GND through the resistor R3. The NPN transistor Q6 has a collector connected to the collector of the transistor Q1, an emitter connected to the ground terminal GND, and a base connected to a connection point between the collector of the transistor Q5 and the resistor R3. This circuit configuration is characterized in that the transistors Q4 and Q5 forming the current mirror circuit are made to have a size of 1: N. Therefore, transistor Q4
On the other hand, N times the current flows through the transistor Q5. The transistor Q6 detects this current by the voltage drop of the resistor R3, and operates so as to rob the current of the constant current source. That is,
It can be expressed by VOUT = Vcc- (kT / q) ln (N). Where q is the amount of electron charge, k is the Boltzmann constant,
kT / q is about 26 mV (T = 300K).
【０００７】本実施形態では、Ｎ=４で設定すると、
(ｋＴ/ｑ)ｌｎ(Ｎ）＝（２６ｍＶ）ｌｎ(4)＝３６．０
４ｍＶとなる。従って、ＶＯＵＴ＝Ｖｃｃ−３６．０４
ｍＶとなり、出力端子ＶＯＵＴの電圧は電源電圧Ｖｃｃ
より３６．０４ｍＶだけ少ない電圧に設定でき、電源電
圧Ｖｃｃにより近づけることができる。In this embodiment, if N = 4 is set,
(kT / q) ln (N) = (26 mV) ln (4) = 36.0
It becomes 4 mV. Therefore, VOUT = Vcc-36.04
mV, and the voltage of the output terminal VOUT is the power supply voltage Vcc.
It can be set to a voltage lower by 36.04 mV and can be brought closer to the power supply voltage Vcc.
【０００８】次に、動作原理について説明する。今,出
力端子ＶＯＵＴの電圧が増加すると、カレントミラー回
路のトランジスタＱ５を流れる電流が増加し、抵抗Ｒ３
の電圧降下が増加するする。これによりトランジスタＱ
６は深くバイアスされて電流が増加し、定電流源の電流
を多く奪ってしまう。このためトランジスタＱ２はオフ
方向に働き電流が減少し、抵抗Ｒ１の電圧降下が減少す
る。この結果、トランジスタＱ３はオフ方向に働き、出
力端子ＶＯＵＴの電圧を減少させる様に動き、出力電圧
を一定に保持する。Next, the operating principle will be described. Now, when the voltage of the output terminal VOUT increases, the current flowing through the transistor Q5 of the current mirror circuit increases and the resistor R3
Voltage drop increases. This allows the transistor Q
6 is deeply biased to increase the current, and robs the constant current source of a large amount of current. Therefore, the transistor Q2 works in the OFF direction, the current decreases, and the voltage drop of the resistor R1 decreases. As a result, the transistor Q3 works in the OFF direction, moves so as to decrease the voltage of the output terminal VOUT, and holds the output voltage constant.
【０００９】[0009]
【発明の効果】以上に説明したように、本発明に依れば
出力端子ＶＯＵＴの電圧検出を出力端子ＶＯＵＴとアー
ス端子ＧＮＤ間に接続したカレントミラー回路のトラン
ジスタＱ５を流れる電流検出で行っているので、従来の
ように基準電圧が出力電圧を引き下げることが無くなる
利点がある。As described above, according to the present invention, the detection of the voltage of the output terminal VOUT is performed by the detection of the current flowing through the transistor Q5 of the current mirror circuit connected between the output terminal VOUT and the ground terminal GND. Therefore, there is an advantage that the reference voltage does not lower the output voltage as in the conventional case.
【００１０】また、このカレントミラー回路のトランジ
スタＱ４とＱ５を１：Ｎの大きさに作ることにより、ト
ランジスタＱ５を流れる電流をトランジスタＱ４のＮ倍
に大きくできるので、抵抗Ｒ３の検出電位を大きくでき
て出力電圧の電源電圧からの減少分を約３６ｍＶ(Ｎ＝4
のとき)までにでき、電圧ロスを最小限にできる利点も
有する。Further, by making the transistors Q4 and Q5 of this current mirror circuit to have a size of 1: N, the current flowing through the transistor Q5 can be increased to N times that of the transistor Q4, so that the detection potential of the resistor R3 can be increased. The output voltage is reduced by about 36 mV (N = 4
It also has the advantage that the voltage loss can be minimized.
【００１１】さらに出力端子ＶＯＵＴの電圧をトランジ
スタＱ３の飽和直前まで電源電圧Ｖｃｃに近づけられる
ので、この回路は発振しにくい特徴も併せ持つ。Furthermore, since the voltage of the output terminal VOUT can be brought close to the power supply voltage Vcc until just before the saturation of the transistor Q3, this circuit also has a characteristic that it is difficult to oscillate.
【図１】本発明のオーバードライブ防止駆動回路を説明
する回路図である。FIG. 1 is a circuit diagram illustrating an overdrive prevention drive circuit of the present invention.
【図２】従来のオーバードライブ防止駆動回路を説明す
る回路図である。FIG. 2 is a circuit diagram illustrating a conventional overdrive prevention drive circuit.
Ｑ１、Ｑ２、Ｑ３、Ｑ４、Ｑ５、Ｑ６ トランジス
タ
Ｒ１、Ｒ２、Ｒ３ 抵抗
Ｖｃｃ 電源端子
ＶＯＵＴ 出力端子
ＧＮＤ アース端子Q1, Q2, Q3, Q4, Q5, Q6 Transistors R1, R2, R3 Resistance Vcc Power supply terminal VOUT Output terminal GND Ground terminal
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) G05F 1/00 - 1/70 G05F 3/00 - 3/30 H03F 1/00 - 3/52 H03F 3/50 - 3/64 H03F 3/62 - 3/64 H03F 3/68 - 3/72 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) G05F 1/00-1/70 G05F 3/00-3/30 H03F 1/00-3/52 H03F 3 / 50-3/64 H03F 3/62-3/64 H03F 3/68-3/72
Claims (2)
ンジスタと、前記 第１のトランジスタジスタのコレクタに接続される
定電流源と、前記 第１のトランジスタのコレクタ及び前記定電流源の
接続点にベースが接続される第２のトランジスタと、 電源端子と出力端子間に接続され、前記第２トランジス
タのコレクタ電圧によりドライブされる第３のトランジ
スタと、 第４および第５のトランジスタで構成されたカレントミ
ラー回路と、前記第５のトランジスタのコレクタに接続される検出抵
抗と、 前記検出抵抗の電圧降下による電圧がベースに印加さ
れ、コレクタが前記第１のトランジスタのコレクタ及び
前記定電流源の接続点に接続される第６のトランジスタ
と、を備え、前記第６のトランジスタで前記定電流源の
電流を奪うことにより前記第２のトランジスタの電流を
減少させてコレクタに接続された検出抵抗の電圧降下を
減少させて前記第３のトランジスタの電流を制御させて
出力電圧を安定に保持することを特徴とするオーバード
ライブ防止駆動回路。A first transistor which is input an ON / OFF signal [1 claim], a constant current source connected to the collector of the first transistor register, the collector and the constant current source of the first transistor
A second transistor having a base to the connection point is connected, is connected between the power supply terminal and an output terminal, said second transistor
A third transistor driven by the collector voltage of the transistor, a current mirror circuit composed of fourth and fifth transistors, and a detection resistor connected to the collector of the fifth transistor.
And anti, the voltage due to the voltage drop of the detection resistor is applied to the base, the collectors of said first transistor and
A sixth transistor connected to a connection point of the constant current source , wherein the sixth transistor is connected to the constant current source.
By stealing the current, the current of the second transistor is
Reduce the voltage drop across the sense resistor connected to the collector
Decrease and control the current in the third transistor
An overdrive prevention drive circuit characterized by stably holding an output voltage .
および第５のトランジスタの大きさを１：Ｎに形成する
ことを特徴とする請求項１記載のオーバードライブ防止
駆動回路。2. A fourth constituting the current mirror circuit.
2. The overdrive prevention drive circuit according to claim 1, wherein the size of the fifth transistor is set to 1: N.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34562699A JP3530438B2 (en) | 1999-12-06 | 1999-12-06 | Overdrive prevention drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34562699A JP3530438B2 (en) | 1999-12-06 | 1999-12-06 | Overdrive prevention drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001166838A JP2001166838A (en) | 2001-06-22 |
| JP3530438B2 true JP3530438B2 (en) | 2004-05-24 |
Family
ID=18377885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34562699A Expired - Fee Related JP3530438B2 (en) | 1999-12-06 | 1999-12-06 | Overdrive prevention drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3530438B2 (en) |
-
1999
- 1999-12-06 JP JP34562699A patent/JP3530438B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001166838A (en) | 2001-06-22 |
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