JP3526542B2 - Data transfer device and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to transfer of data stored in storage means, and more particularly to a technique of transferring a plurality of data in parallel.

[0002]

2. Description of the Related Art Data containing an error is detected and ECC
A parity bit is added to digital data in order to perform an error correction process based on (error-correcting code). The parity bit makes it less susceptible to noise on the recording medium and the transmission line during communication.
It is necessary not to appear continuously, and it is arranged so as to appear discretely by having a certain regularity.

Further, when a data series for error correction by a parity bit is sequentially stored in a storage device which designates a data storage position by a row address and a column address, the data in the data series has the row address and the column address. In some cases, the addresses are sequentially mapped and stored in a diagonal direction so that they are sequentially different by one. Also,
A plurality of such data series exist independently, and each data series is adjacent to each other on the memory map.

Conventionally, when data of such a data series is read from a memory and error correction processing is performed by an ECC circuit, data is read one by one while simultaneously changing a row address and a column address.

[0005]

In recent years, semiconductor technology has made remarkable progress, and a DRAM embedded technology has been established in which a logic circuit and a DRAM (dynamic random-access memory) are formed on the same chip in order to facilitate timing design. Has come to be. DRAM embedded LSI (large-scale in
In addition to the ease of timing design, it is not limited by the number of I / O pins as in packaged LSIs, so the width of the data bus on the chip can be increased and data It is possible to increase the bit width when accessing.

However, when reading a data series which is diagonally mapped on the memory map, if one data series is read out one by one, the wide width of the data bus in the DRAM embedded LSI can be utilized. There wasn't. Further, since it is necessary to change the row address and the column address at the same time for each data, the data cannot be read out from the memory at high speed.

The present invention is directed to a data transfer device for transferring data of a plurality of data series in parallel at a high speed when a plurality of data series mapped diagonally on a memory map are stored in a storage means. The challenge is to provide.

[0008]

Means for Solving the Problems In order to solve the above-mentioned problems, the means according to the invention of claim 1 is a data transfer device, wherein a data series in which a row address and a column address each have different data by one And a storage means for reading out a set of data in which each of the data having the same row address is sequentially set for every m (m is an integer of 2 or more) according to a certain rule. In each of the read control means for controlling the data set and the data set read by the storage means, the data belonging to the m series of the data series is arranged at a position determined for each data series. Sorting is performed according to the reading order of the data set, and sorting means for outputting the sorted data set, and the sorted data set are used to select the data belonging to the m series. Selected according to data on the reading order, in which a data extracting means for outputting.

According to a second aspect of the present invention, in the data transfer apparatus according to the first aspect, the read control means provides a row address and a column address for a data set including one m-series data each. Let X and Y (X and Y are integers), respectively, and set the data set from the row of row address X-m + 1 to the row of row address X in the column of the data set of column addresses Y-1 and Y to a row address of a small row address. It is characterized in that the storage means is controlled so as to read the data in order from the one.

Further, in the invention of claim 3, in the data transfer apparatus according to claim 1, the read control means controls the storage means so as to read only a set of data including data belonging to the m series. It is characterized by doing.

According to a fourth aspect of the present invention, in the data transfer apparatus according to the third aspect, the read control means provides a row address and a column address for a data set including one m-series data each. X and Y respectively, and from the row of row address X-m + 1 to the row of row address X-1 in the column of the data set of column address Y-1, and the row address X- in the column of the data set of column address Y. The storage means is controlled so that the data set from the row of m + 1 to the row of the row address X is read in order from the row having the smallest row address.

According to a fifth aspect of the present invention, as a data transfer method, the same row address is provided from the storage means that stores a plurality of data series having data in which the row address and the column address are sequentially different by one. Data belonging to the m-series of the data series in each of the reading step of reading out a set of data for every m pieces in sequence according to a certain rule and the set of data read in the reading step. A rearrangement step of rearranging the data sets according to the reading order of the data sets so that the data sets are arranged at positions determined for each data series, and the data belonging to the m series is read from the data sets after the rearrangement. And a data extraction step of selecting according to the order.

According to the first and fifth aspects of the present invention, the data is arranged in the bit position determined for each data series in the data set read from the storage means, and unnecessary data is not output. The series data can be transferred in parallel for each series.

Further, the invention of claim 6 is the data transfer method according to claim 5, wherein in the reading step, a row address and a column address are respectively set for data sets each including one m-series data. X and Y, and a set of data from the row of the row address X-m + 1 to the row of the row address X in the column of the data set of the column addresses Y-1 and Y is read in order from the row with the smallest row address. To do.

According to the second and sixth aspects of the present invention, since the column address Y of the data set to be read can be regularly changed, the column address Y can be easily generated. Particularly, according to the invention of claim 2, the structure of the read control means for generating the column address Y can be simplified. Further, since reading of unnecessary data sets is small and row addresses are sequentially read and read, efficient data transfer can be performed without disturbing the order of data in each data series.

Further, the invention of claim 7 is the data transfer method according to claim 5, wherein in the reading step, only a set of data including data belonging to the m-series is read.

According to the third and seventh aspects of the present invention, since unnecessary data reading is avoided, the time required for data reading can be shortened.

The invention of claim 8 is the data transfer method according to claim 7, wherein in the reading step, a row address and a column address are respectively set for a data set including one m-series data each. X and Y, the row address X-m + 1 to the row address X-1 in the column of the data set of the column address Y-1 to the row of the row address X-1 and the row address X of the column of the data set of the column address Y.
It is characterized in that a data set from the row of -m + 1 to the row of the row address X is read in order from the row having the smallest row address.

According to the fourth and eighth aspects of the present invention, since there is no reading of an unnecessary data set and the row address is sequentially read and read, the efficient data transfer disturbs the order of the data in each data series. Can be done without.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data transfer device and an ECC device for receiving output data of the data transfer device according to an embodiment of the present invention. The data transfer device 10 of FIG. 1 includes a memory 11 as a storage unit, a memory control circuit 12 as a read control unit, and a rearrangement circuit 13.
A rearrangement control circuit 14, a data extraction circuit 15,
And a data extraction control circuit 16. The sorting circuit 13 and the sorting control circuit 14 serve as sorting means,
The data extraction circuit 15 and the data extraction control circuit 16 operate as data extraction means. A control signal is input from the outside to the memory control circuit 12, the rearrangement control circuit 14, and the data extraction control circuit 16 so that they can operate in synchronization.

In addition, the ECC device 20 of FIG.
CC circuit 21, second ECC circuit 22, and third EC
A C circuit 23, a fourth ECC circuit 24, and an ECC control circuit 25 are provided. The data output by the data transfer device 10 is transferred to the ECC device 20 via the bus.

In the following, as an example, a CD-ROM (comp
A case where the data transfer device 10 of FIG. 1 transfers the data read from the act disk read only memory) to the ECC device 20 will be described. In the memory 11, an address for selecting a word line is a row address, an address for selecting a bit line is a column address, and one byte has 8 bits.

In the CD-ROM, 1 of the recorded data
A block is composed of 2352 bytes, and ECC is defined for 2340 bytes excluding the synchronization pattern at the head. The ECC divides these 2340 bytes of data into 16-bit units and divides each into 8 bits of data on the LSB side and the MSB side. For each 1170 bytes of data on the LSB side and the MSB side, P
It is applied in two directions, the sequence and the Q sequence. The P series has 24 bytes of data and 26 bytes of parity 2 bytes, and the Q series has 43 bytes of data and 45 bytes of 2 bytes of parity as one series, and error correction is performed in each series.

In FIG. 1, the memory 11 is composed of a DRAM, and data can be output in units of 4 bytes. It is assumed that 1170 bytes of LSB-side data read from the CD-ROM is stored in the memory 11 according to a predetermined rule.

FIG. 2 shows the C of each data of the data read from the CD-ROM and stored in the memory 11.
It is explanatory drawing which showed the correspondence of the reading order from D-ROM, and a storage position on a memory map. In FIG. 2, one 4-digit number (0000 to 1169) represents 1-byte data (hereinafter, 1-byte data is referred to as unit data), and each number represents the unit data stored in that position. Regarding the reading order in the 1170-byte data from the CD-ROM. x and y are a row address and a column address for the unit data, respectively, and these addresses are data "00" at the upper left of FIG.
This is a relative address with respect to 00 ".
Some data are omitted. In the following, a case of transferring the data “0000” to “1117” from the memory 11 to the ECC device 20 will be described.

Sequences of P series and Q series can be represented by P _j = 43i + j (1) Q _i = (43i + 44j) mod 1118 (2) in FIG. Here, i = 0 to 25, j = 0 to
42, and i and j are integers. FIG. 2 shows an example of the Q series. As described above, the data of each Q series is arranged diagonally on the memory map so that the row address x and the column address y are sequentially different by one, and one Q series data is arranged. It is necessary to change the row address x and the column address y of the memory at the same time in order to read only the data.

In the following, m-byte data in which adjacent unit data m (m is an integer of 2 or more) in each row are grouped in order from the unit data of column address y = 0 will be referred to as a data set. . In the same data set, the unit data with the smaller column address y is the upper byte.

FIG. 3 is an explanatory diagram showing a part of the data stored in the memory 11. FIG. 3 shows the upper left portion (x
= 0 to 7 in 8 rows and y = 0 to 7 in 8 columns) are extracted and displayed. Here, it is assumed that m = 4, four unit data are treated as one data set, and four series of data are read from the memory 11. In FIG. 3, unit data is represented by one circle, and four circles are surrounded by lines to represent data sets DA1 to DA12. An address is assigned to each data set, the row address and the column address of the data set are respectively X and Y, and the address of the data set DA1 at the upper left of FIG. 3 is (X, Y) = (0, 0 ).

The data of the first Q series (Q ₀ ) is
The order of reading from the CD-ROM is from A to A
0, A1, A2, ..., Similarly, the data of the second Q series (Q ₁ ) is B0, B1, B2, ..., The data of the third Q series (Q ₂ ) is C0, C1, C2 ,. Fourth Q series (Q ₃ )
Data is represented as D0, D1, D2, ...
The Q series will be referred to as A series, B series, C series, and D series, respectively.

Here, 4 of the A to D series from the memory 11 is used.
The case where the data of the series is read will be described, and the data that does not belong to these series is represented by “Z”. For example, the A-series data A0, A1, and A2 in FIG. 3 are “0000”, “0044”, and “0088” in FIG. 2, and the B-series data B0, B1, and B2 in FIG. 3 are “0043”. , “0087” and “0131”. Data Z in FIG. 3 is data represented by “0001”, “0172”, etc. in FIG. 2 and belongs to a Q series other than Q _{0 to} Q ₃ .

FIG. 4 is an explanatory diagram showing a read rule when reading four series of data A to D from the memory 11. FIG. 4 shows the correspondence between the reading order n of the data set from the memory 11 and the addresses X, Y, etc. of the data set to be read. In this figure, s and t are integers of 0 or more.

Although not shown in FIG. 4, when reading the data of the CD-ROM stored in the memory as shown in FIG. 2, the row address X needs to be the remainder obtained by dividing X by 26. . In addition, the range of the row address X of the data set is 0 to 25, and the range of the column address Y is 0 to 11.
The data corresponding to the column address y = 43 to 47 of the unit data in is also read from the memory 11. Therefore, s changes in the range of 0-10. A ~
When reading out a data set of Q _{0 to} Q ₃ series as the D series, t = 0 in FIG.

The memory control circuit 12 stores the data set in FIG.
The addresses X and Y are generated in accordance with the reading order n so that the memory 11 is controlled so that the memory 11 is read according to the rule defined in 1.
The memory 11 reads the 4-byte data of the data set and outputs it to the rearrangement circuit 13.

The rule of FIG. 4 is that the reading order is n = 1 to 4.
The column address Y of the data set is 0 and the row address X is
4t, 1 + 4t, 2 + 4t and 3 + 4t respectively
It For the read order n = 5 and thereafter, 4 of A to D series
A set of data that contains one series of data each (for example,
For example, the row of DA12 in FIG. 3, reading order n = 12 + 8s)
Address X₀, Column address Y₀When the column address
Y₀-1 and Y₀Address in the column of the data set of the
X₀-3 (= X₀-M + 1) to row address X ₀Row of
Of the 8 data sets up to, the data set is
It is specified that the pages are read in order from the smallest one. Ingredient
Physically, X₀= 7 + 4 (s + t), Y₀= S + 1
There is. Which data set has the same row address first
You may read it.

As described above, the memory control circuit 12 controls data reading from the memory 11 according to a certain rule, and a logic circuit for generating the addresses X and Y of the data set according to the reading order n and ROM (read-only
memory).

FIG. 5 is an explanatory diagram showing input / output data of the rearrangement circuit 13. FIG. 5A is an explanatory diagram in which the sets of data DA1 to DA12 read by the memory 11 and input to the rearrangement circuit 13 according to the rule of FIG. 4 are arranged in the order of reading from the top.

FIG. 6 is a circuit diagram showing the configuration of the rearrangement circuit 13. The rearrangement circuit 13 of FIG. 6 includes four selectors 131 to 134, and each of the selectors 131 to 134 includes four input terminals a to d.

Input a of selector 131, selector 132
The lower 8-bit data of the 32-bit data of the data set output from the memory 11 is input to the input d, the input c of the selector 133, and the input b of the selector 134.

Input b of selector 131, selector 132
To the input a of the selector 133, the input d of the selector 133, and the input c of the selector 134, the data of the 9th to 16th bits of the 32-bit data of the data set output from the memory 11 is counted. There is.

Input c of selector 131, selector 132
The input b, the input a of the selector 133, and the input d of the selector 134 are the 17th to 24th bits of the 32-bit data of the data set output from the memory 11, counted from the least significant. There is.

Input d of selector 131, selector 132
The upper 8 bits of the 32-bit data of the data set output from the memory 11 are input to the input c, the input b of the selector 133, and the input a of the selector 134.

The transfer of A, B, C and D series data will be described. First, the case of s = 0 in FIG. 4, that is, the case of reading order n = 1 to 12 will be described.
The memory control circuit 12 reads the data sets DA1 to DA12 in the reading order n = 1 to 12 and selects the selectors 131 to 131.
The memory 11 is controlled to output to 134.

The rearrangement control circuit 14 selects one of the four inputs a to d according to the display of the column of the shift amount SH defined for the reading order n as shown in FIG.
The selectors 131 to 134 are controlled. That is, the selectors 131 to 134 input the input a when the shift amount SH is 0, input b when the shift amount SH is 1, and the shift amount S.
When H is 2, the input c is selected, and when the shift amount SH is 3, the input d is selected, and the input data is selected.
The output is controlled to 5.

Then, the rearrangement circuit 13 sets the data sets DA1 to DA12 output from the memory circuit 11 to the shift amount SH shown in FIG. 4 in the respective data sets.
The unit data of each byte is shifted to the right (to the lower bit side) by the number of bytes of (the byte overflowing to the right is the most significant byte) and then output.

FIG. 5B is an explanatory diagram showing the data output by the rearrangement circuit 13. Selector 131-134
5 shifts the unit data in each of the data sets DA1 to DA12 of FIG.
The data is output as the data sets DB1 to DB12 in (b).
Here, the A-series data is included only in the data SA1 output by the selector 131. Similarly, the BD series data is included only in the data SB1, SC1 and SD1 output by the selectors 132 to 134, respectively.

FIG. 7 is a block diagram showing the structure of the data extraction circuit 15. The data extraction circuit 15 of FIG. 7 includes four FIFO (first-in, first-out) buffers 151 to 15
4 and a decoding circuit 155. Also, FIG.
FIG. 4 is an explanatory diagram showing input / output data of the data extraction circuit 15. FIG. 8A shows data output from the rearrangement circuit 13 and input to the data extraction circuit 15 (same as FIG. 5B).

Data SA1 and SB output from the selectors 131 to 134 are stored in the FIFO buffers 151 to 154, respectively.
1, SC1 and SD1 are input respectively. The write circuit WR output from the data extraction control circuit 16 and the data request signal RQ output from the ECC control circuit 25 are input to the decode circuit 155.

The decode circuit 155 outputs the F signal designated by the write signal WR output from the data extraction control circuit 16.
The write enable signal WE of the IFO buffers 151 to 154 is asserted. FIFO buffers 151-154
Are the data SA1 and SB output from the selectors 131 to 134 when the write enable signal WE is asserted.
1, SC1 and SD1 are stored respectively.

The data extraction control circuit 16 controls the writing to the FIFO buffers 151 to 154 according to the display of the column of the write signal WR defined for the reading order n as shown in FIG. That is, the write signal WR of FIG.
Similarly, when the display of the column of A includes A, the FIFO buffer 151 stores the data SA1.
FIFO buffers 152 to 1 when D is included
54 decodes the write signal WR instructing to store the data SB1, SC1 and SD1 respectively.
Output to 5. The decode circuit 155 asserts the write enable signal WE of the FIFO buffers 151 to 154, which is designated by the write signal WR.

Then, of the unit data of the sets DB1 to DB12 of each data output by the rearrangement circuit 13, A to D are selected.
The data Z other than the series is stored in the FIFO buffers 151 to 154.
Are not written to the FIFO buffers 151 to 15
In No. 4, only the A to D series data are selected and sequentially stored.

As described above, the rearrangement control circuit 14 and the data extraction control circuit 16 control the data operations in the rearrangement circuit 13 and the data extraction circuit 15, respectively, according to the read order n according to a certain rule. Yes, it can be configured with a ROM or a logic circuit that generates the shift amount SH and the write signal WR according to the reading order n.

FIG. 8B shows the FIFO buffers 151 to 1
5 is an explanatory diagram showing data stored and output by 54, that is, output data of a data extraction circuit 15. FIG. The FIFO buffers 151 to 154 are the data set DB of FIG.
1-DB12 does not store the data Z other than the A-D series, the data sets DC1-DC8 of FIG.
The data of the series A to D are stored without any gap as shown in FIG. “W” in FIG. 8B indicates the FIFO buffers 151 to 151.
The data to 154 represents a portion that has not been input.

The ECC control circuit 25 determines the availability of the bus used for data transfer and the ECC in the ECC circuits 21 to 24.
The data request signal RQ is asserted when the ECC circuits 21 to 24 can receive data depending on the availability of processing.

The decode circuit 155, when the data request signal RQ is asserted, the FIFO buffer 151.
~ 154 read enable signal RE is asserted and F
The IFO buffers 151 to 154 store the oldest stored data as data SA2, SB2, S, respectively.
Simultaneously output as C2 and SD2 to the ECC circuits 21-24.

At the time when the memory 11 reads the data set of the reading order n = 1 to 12, the FIFO buffer 15
1 to 154 can transfer the data sets DC1 to DC5 including the data of A to D series one by one to the ECC circuits 21 to 24.

Similarly, for the reading order n = 13 and thereafter, by setting s = 1, 2, ..., 10 in FIG. 4, the memory 11 reads the data set by 4 bytes,
The FIFO buffers 151 to 154 can transfer a set of data including one piece of A to D series data.

FIG. 9 shows transfer data SA2, SB2, SC2 and SD from the data transfer device 10 to the ECC device 20.
It is explanatory drawing which showed 2 in the order of transfer. The four-digit number in Figure 9 is
This corresponds to the order of reading data from the CD-ROM shown in FIG. As described above, the data transfer device 10 of the present embodiment can transfer the four Q series data in parallel to the ECC device 20.

In the present embodiment, Q ₀ represented by the equation (2)
The four Q series of ~Q ₃ was described as A~D series. Similarly, Q _4t with i = _{4t to 4t} + 3 in Expression (2)
.., Q _{4t +3} are treated as A to D sequences, and t = 1, 2, ..., 6 in FIG. 4, other Q sequences can be described. When the value of t is changed and new Q-series data is read out, the reading order n is increased from 1 again.

As described above, according to the present embodiment, for the data series in which the unit data is diagonally arranged on the memory map, four unit data are read and four unit data are read by the ECC device. Since the data is transferred, it is possible to transfer the data at high speed by utilizing the wide width of the bit when accessing the data. Therefore, the occupation time of the bus for data transfer can be shortened.

The data set in the reading order n = 11 + 8s, for example, the data set DA11 in FIG. 3 includes only the data Z which is data other than the A to D series. The memory control circuit 1 is designed so that the relationship between the read order n and the addresses X and Y of the data set shown in FIG. 4 is as regular as possible.
In order to simplify the configuration of No. 2, such a data set is also read out, but it may not be read out. That is, the data series (A
It is also possible to read out only a set of data including at least one unit data belonging to (~ D series). in this case,
Since unnecessary data reading can be avoided, higher speed data transfer can be performed.

In this embodiment, m = 4 and four unit data are treated as one data set, but the value of m may be another value (an integer of 2 or more). Good. In this case, m unit data are set as one data set, the number of selectors of the rearrangement circuit 13 and the number of FIFO buffers of the data extraction circuit 15 are set to m, and
As shown in FIG. 4, a FIFO for asserting the write enable signal WE based on the addresses X and Y of the set of data to be read corresponding to the reading order n, the shift amount SH, and the write signal WR may be obtained in advance. The size of the unit data may be other than 8 bits.

Further, as an example, the case where the data read from the CD-ROM to the memory is transferred has been described.
Not limited to this, the unit data of the same series are arranged diagonally according to a predetermined rule on the memory map so that the row address and the column address are sequentially different by one, and a plurality of series exist. If so, the present invention can be similarly applied. Therefore, the address range of the memory for storing the data and the storage order may be other than those shown in this embodiment.

[0064]

As described above, according to the present invention, the DRA
In the case where the bit width of the data bus can be widened as in an M-embedded LSI, the data series data mapped diagonally on the memory map by utilizing the size of the bit width when accessing the data Can be transferred in parallel. Therefore, the time required for data transfer can be shortened and high-speed data transfer can be performed. Further, since the occupied time of the data bus can be shortened, the performance of the entire system sharing the data bus can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a data transfer device and an ECC device that receives output data of the data transfer device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing, on a memory map, the correspondence between the reading order of each data from the CD-ROM and the storage position of the data read from the CD-ROM and stored in the memory.

FIG. 3 is an explanatory diagram showing a part of data stored in a memory.

FIG. 4 is an explanatory diagram showing a read rule when reading data of four series of A to D series from a memory.

FIG. 5 is an explanatory diagram showing input / output data of a rearrangement circuit.

FIG. 6 is a circuit diagram showing a configuration of a rearrangement circuit.

FIG. 7 is a block diagram showing a configuration of a data extraction circuit.

FIG. 8 is an explanatory diagram showing input / output data of the data extraction circuit.

FIG. 9 is an explanatory diagram showing transfer data from a data transfer device to an ECC device in a transfer order.

[Explanation of symbols]

10 Data transfer device 11 memory (storage means) 12 Memory control circuit (readout control means) 13 Sorting circuit (sorting means) 14 Sorting control circuit (sorting means) 15 data extraction circuit (data extraction means) 16 Data extraction control circuit (data extraction means) 20 ECC device 21-24 ECC circuit 25 ECC control circuit 131-134 Selector 151-154 FIFO buffer 155 decode circuit Row address for x unit data Column address for y unit data n Data set read order Row address for the X data set Column address for Y data set SH shift amount WR write signal

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-5-324646 (JP, A) JP-A-62-288930 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 7/24

Claims (8)

(57) [Claims] 1. A row address and a column address are both 1
Storage means for storing and reading a plurality of data series each having different data sequentially, and the data having the same row address are sequentially m (m is 2
In each of the read control means for controlling the storage means so as to read out a set of data for each of the above integers) according to a certain rule, and the data set read out by the storage means. Rearrangement means for rearranging the data belonging to the m series of the series according to the reading order of the data sets so as to be arranged at the position determined for each data series, and outputting the rearranged data sets. A data transfer device comprising: a data extraction unit that selects and outputs data belonging to the m-series from the sorted data set according to the reading order. 2. The data transfer device according to claim 1, wherein the read control means sets a row address and a column address for a set of data each including one m-series data to X and Y, respectively.
(X and Y are integers), the data sets from the row of the row address X-m + 1 to the row of the row address X in the column of the data set of the column addresses Y-1 and Y are read in order from the smallest row address. A data transfer device, wherein the storage means is controlled as described above. 3. The data transfer device according to claim 1, wherein the read control unit controls the storage unit to read only a set of data including data belonging to the m series. Transfer device. 4. The data transfer device according to claim 3, wherein the read control unit includes a row address and a column address for a set of data each including one m-series data as X and Y, respectively.
From the row of row address X-m + 1 to the row of row address X-1 in the column of the data set of column address Y-1.
And the storage means is controlled so that the data sets from the row of the row address X-m + 1 to the row of the row address X in the column of the data set of the column address Y are read out in ascending order of the row address. Data transfer device. 5. A row address and a column address are both 1
A read step of reading a set of m data sets each having the same row address in order from a storage means that stores a plurality of data series each having different data according to a certain rule; In each of the data sets read in step S, the data that belongs to the m series of the data series is rearranged according to the reading order of the data sets so as to be arranged at a position determined for each data series. A data transfer method comprising: a rearrangement step; and a data extraction step of selecting data belonging to the m series from the rearranged data set according to the reading order. 6. The data transfer method according to claim 5, wherein in the reading step, a row address and a column address for a set of data each including one m-series data are X and Y, respectively.
And a data transfer in which the data sets from the row of row address X-m + 1 to the row of row address X in the column of the data set of column addresses Y-1 and Y are read in order from the smallest row address. Method. 7. The data transfer method according to claim 5, wherein in the reading step, only a set of data including data belonging to the m series is read. 8. The data transfer method according to claim 7, wherein in the reading step, a row address and a column address for a set of data each including one m-series data are X and Y, respectively.
From the row of row address X-m + 1 to the row of row address X-1 in the column of the data set of column address Y-1.
And a data transfer method in which the data sets from the row of the row address X-m + 1 to the row of the row address X in the column of the data set of the column address Y are read in order from the smallest row address.