JP3524525B2 - Mounting board for semiconductor device - Google Patents
Mounting board for semiconductor deviceInfo
- Publication number
- JP3524525B2 JP3524525B2 JP2001242645A JP2001242645A JP3524525B2 JP 3524525 B2 JP3524525 B2 JP 3524525B2 JP 2001242645 A JP2001242645 A JP 2001242645A JP 2001242645 A JP2001242645 A JP 2001242645A JP 3524525 B2 JP3524525 B2 JP 3524525B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- device mounting
- pilot hole
- mounting board
- strip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置実装用
基板およびこれを用いた半導体装置の製造方法にかか
り、特に、リードフレーム、ＴＡＢ（Tape Automated
Bonding）テープを使用するＴＢＧＡ、フレキシブルな
プリント基板を使用するＰＢＧＡやＣＳＰに用いられる
実装用基板におけるパイロット穴の形成に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting substrate and a method of manufacturing a semiconductor device using the same, and more particularly to a lead frame and a TAB (Tape Automated).
Bonding) TBGA using a tape, PBGA using a flexible printed board, and formation of pilot holes in a mounting board used in a CSP.
【０００２】[0002]
【従来の技術】近年、電子機器に装着される半導体装置
は、携帯電話、ＰＤＡなどの携帯用端末等に採用される
ため、小型化、薄型化、軽量化が求められている。2. Description of the Related Art In recent years, semiconductor devices to be mounted on electronic equipment have been adopted for portable terminals such as mobile phones and PDAs, and therefore have been required to be smaller, thinner and lighter.
【０００３】そしてその小型化、薄型化および軽量化、
さらには高集積化を実現すべく、半導体装置の実装にお
いては種々の提案がなされており、ＴＡＢ（テープオー
トメイティドボンディング）、ＢＧＡ（ボールグリッド
アレイ）、最近ではＣＳＰ（チップサイズパッケージ）
と呼ばれる、チップのサイズと同等のウェハスケールＣ
ＳＰ、またはチップサイズよりも若干大きいサイズのＣ
ＳＰなどが開発されている。[0003] And downsizing, thinning and weight reduction,
Furthermore, various proposals have been made in mounting semiconductor devices in order to realize high integration, such as TAB (tape automated bonding), BGA (ball grid array), and recently CSP (chip size package).
Called wafer scale C, which is equivalent to the chip size
SP or C slightly larger than the chip size
SP etc. are being developed.
【０００４】ところで、このような実装方法に用いられ
るＴＡＢ基板は、ポリイミドテープなどのフレキシブル
テープに配線パターンを形成してなるもので、条材とし
て連続的に形成される。By the way, the TAB substrate used in such a mounting method is one in which a wiring pattern is formed on a flexible tape such as a polyimide tape, and is continuously formed as a strip material.
【０００５】このような条材には通常、図１０に示すよ
うに位置決めのためにパイロット穴４が設けられている
ことが多い。Usually, such a strip is often provided with pilot holes 4 for positioning as shown in FIG.
【０００６】通常、ＢＧＡ（Ball Grid Array）基板
の場合、図１０に示すように、複数の半導体装置用実装
基板領域１が、所定の間隔を隔てて連続的に配設せしめ
られた条材２から形成され、この条材２の両サイドに設
けられたサイドレール３に設けられたパイロット穴４に
よって順次この条材を搬送しながら、パターニングし、
テープの貼着、半田ボールの実装などの工程が実施され
る。Generally, in the case of a BGA (Ball Grid Array) substrate, as shown in FIG. 10, a plurality of semiconductor device mounting substrate regions 1 are continuously arranged at predetermined intervals with a strip member 2. And patterning while sequentially transporting the strip material by pilot holes 4 provided in side rails 3 provided on both sides of the strip material 2,
Processes such as tape attachment and solder ball mounting are performed.
【０００７】例えばこのような基板の場合、４０ｍｍか
ら５０mm程度の条材を用いて、幅方向に２列の半導体装
置用実装基板領域１が配列されている。しかしながら、
このサイドレール３は半導体装置の完成後、切除される
領域であり、実際の有効幅は３０ｍｍ程度であり、材料
の無駄が多いという問題があった。For example, in the case of such a substrate, two rows of semiconductor device mounting substrate regions 1 are arranged in the width direction using a strip material of about 40 mm to 50 mm. However,
The side rail 3 is a region that is cut off after the semiconductor device is completed, and the actual effective width is about 30 mm, which causes a problem that much material is wasted.
【０００８】このような状況の中で、ＢＧＡのみなら
ず、リードフレームあるいはフィルムキャリアにおいて
も、パターンの微細化が進むにつれ、板厚も薄型化して
きており、サイドレールに設けられたパイロット穴で搬
送する場合、余分な力が加わり、変形や破断を生じ易い
という問題があった。Under such circumstances, not only BGA but also lead frames or film carriers have become thinner as the pattern becomes finer, and the pilot holes provided in the side rails are becoming thinner. When it is transported, there is a problem that excessive force is applied and deformation or breakage is likely to occur.
【０００９】またリードフレームの場合、銅などの条材
をプレス加工することにより形成されるが図９に示すよ
うに、サイドレール１３に設けられたパイロット穴１４
で搬送しつつ形成される。Further, in the case of a lead frame, it is formed by pressing a strip material such as copper, but as shown in FIG. 9, pilot holes 14 provided in the side rails 13 are formed.
It is formed while being transported.
【００１０】そこで近年、パイロット穴による搬送に替
え、グリッパーと指称する搬送ローラを用いた搬送方法
が広く用いられるようになってきている。この場合、搬
送に際してはサイドレールもパイロット穴も不要である
が、樹脂封止や固片化の際の位置決めに際し、パイロッ
ト穴が必要であることから、図９および図１０に示した
ようなサイドレールおよびパイロット穴付きの条材が用
いられていた。Therefore, in recent years, instead of carrying by a pilot hole, a carrying method using a carrying roller called a gripper has been widely used. In this case, neither side rails nor pilot holes are required for transportation, but pilot holes are required for positioning during resin sealing or solidification. Therefore, the side rails shown in FIGS. 9 and 10 are required. Strips with rails and pilot holes were used.
【００１１】[0011]
【発明が解決しようとする課題】このように、従来のリ
ードフレーム、ＢＧＡ用基板などの基板はサイドレール
およびパイロット穴付きの条材を用いて形成されてお
り、材料歩留まりという観点では無駄が多く、コストの
低減を阻む大きな問題となっていた。また、環境改善と
いう観点からも廃棄物の増大という問題もあった。As described above, the substrates such as the conventional lead frame and BGA substrate are formed by using the side rail and the strip material with the pilot hole, and there is much waste from the viewpoint of material yield. However, it was a big problem that prevented cost reduction. There was also the problem of increased waste from the perspective of environmental improvement.
【００１２】本発明は前記実情に鑑みてなされたもの
で、材料の無駄を低減し、小型でかつ収率の高い半導体
装置実装用基板、およびこれを用いた半導体装置の製造
方法を提供することを目的とする。The present invention has been made in view of the above circumstances, and provides a substrate for mounting a semiconductor device which reduces waste of material, is small in size and has a high yield, and a method of manufacturing a semiconductor device using the same. With the goal.
【００１３】[0013]
【課題を解決するための手段】そこで本発明の半導体装
置用実装基板は、複数の半導体装置用実装基板領域が、
所定の間隔を隔てて連続的に配設せしめられた条材と、
前記条材の長手方向に沿って隣接する前記半導体装置用
実装基板領域間に相当する領域に配設せしめられたパイ
ロット穴とを具備し、前記パイロット穴が前記半導体装
置用実装基板領域間の破断線の一部として半導体装置用
実装基板としての有効幅の範囲内に設けられていること
を特徴とする。Therefore, in the semiconductor device mounting board of the present invention, a plurality of semiconductor device mounting board regions are provided.
A strip material continuously arranged at a predetermined interval,
A pilot hole arranged in a region corresponding to the semiconductor device mounting substrate regions adjacent to each other along the longitudinal direction of the strip, the pilot hole being a break between the semiconductor device mounting substrate regions. It is characterized in that it is provided within a range of an effective width as a mounting substrate for a semiconductor device as a part of the line .
【００１４】かかる構成によれば、パイロット穴が、半
導体装置用実装基板としての有効幅の範囲内に設けられ
ているため、パイロット穴形成のための幅が不要とな
り、条材の幅を低減することが可能となる。また、パイ
ロット穴は半導体装置用実装基板領域間に設けられてい
るため、長さを増大する必要もなく、本来の余剰領域に
設けられるため、材料の無駄が大幅に低減される。ま
た、半導体装置の微細化、高集積化に伴い、端子数が増
大し、リード幅も微細化してきており、板厚の微細化は
進む一方であるが、かかる構造であれば、搬送に際して
も、両端が複雑な形状となっていないため、力の不均衡
により条材の破壊を招くようなこともなく、グリッパを
用いて円滑に搬送することができる。また、位置決めの
ためにパイロット穴が必要な工程においては、半導体装
置用実装基板領域間に設けられたパイロット穴を用いれ
ばよく、実装が容易で信頼性の高い半導体装置用実装基
板を提供することが可能となる。According to this structure, since the pilot hole is provided within the range of the effective width as the semiconductor device mounting board, the width for forming the pilot hole is not necessary and the width of the strip is reduced. It becomes possible. Further, since the pilot holes are provided between the semiconductor device mounting substrate regions, there is no need to increase the length, and since the pilot holes are provided in the original surplus region, waste of material is greatly reduced. Also, with the miniaturization and high integration of semiconductor devices, the number of terminals is increasing and the lead width is also miniaturizing, and the miniaturization of the plate thickness is progressing. Since the both ends are not in a complicated shape, the strip material is not broken due to the imbalance of the force, and can be smoothly transported by using the gripper. Further, in a process requiring a pilot hole for positioning, a pilot hole provided between semiconductor device mounting board regions may be used, and a semiconductor device mounting board that is easy to mount and highly reliable is provided. Is possible.
【００１５】また望ましくは、前記半導体装置用実装基
板としての有効幅に相当する領域の両側にサイドレール
部を具備してなることを特徴とする。Further, it is preferable that side rail portions are provided on both sides of a region corresponding to an effective width as the semiconductor device mounting substrate.
【００１６】サイドレールは設けられてはいるが、パイ
ロット穴はサイドレールではなく、半導体装置用実装基
板領域間に設けられているため、条材幅の縮減を図るこ
とが可能となる。Although the side rails are provided, the pilot holes are provided not between the side rails but between the semiconductor device mounting substrate regions, so that the strip width can be reduced.
【００１７】望ましくは、前記条材は、リードフレーム
であり、チップ搭載領域のまわりに伸長するインナーリ
ードと、これに連設されたアウターリードとを具備して
なることを特徴とする。Preferably, the strip member is a lead frame, and is provided with an inner lead extending around a chip mounting region and an outer lead connected to the inner lead.
【００１８】リードフレームの場合、ステンレスなどの
条材をプレス加工あるいはエッチング加工によりパター
ニングして形成されるため、特に条材幅の縮減による収
率の向上により、材料コストの大幅な低減を図ることが
可能となる。In the case of a lead frame, a strip material such as stainless steel is formed by patterning by pressing or etching, so that the yield can be improved by reducing the strip width, thereby significantly reducing the material cost. Is possible.
【００１９】望ましくは、前記条材は、フィルムキャリ
アであり、前記フィルムキャリア表面に配設され、チッ
プ搭載領域のまわりに伸長するインナーリードと、これ
に連設されたアウターリードとを具備してなることを特
徴とする。Preferably, the strip member is a film carrier, and is provided with an inner lead arranged on the surface of the film carrier and extending around a chip mounting area, and an outer lead connected to the inner lead. It is characterized by
【００２０】条材幅の縮減による収率の向上により、材
料コストの大幅な低減を図ることが可能となる。また、
幅方向に配列可能な個数を増大することができ、ひいて
は実装作業性が大幅に向上する。By improving the yield by reducing the width of the strip, it is possible to significantly reduce the material cost. Also,
The number that can be arranged in the width direction can be increased, and the mounting workability is greatly improved.
【００２１】望ましくは、前記条材は、有効幅内に、複
数行複数列の半導体装置用実装基板がグループ化されて
連続形成されていることを特徴とする。Preferably, the strip is formed by continuously grouping a plurality of rows and columns of semiconductor device mounting boards within an effective width.
【００２２】かかる構成によれば、幅方向に配列可能な
個数を増大することができ、ひいては実装作業性が大幅
に向上する。With this structure, the number of elements that can be arranged in the width direction can be increased, and the mounting workability can be greatly improved.
【００２３】望ましくは、前記パイロット穴は、交互に
点対称位置に１個づつ配設されていることを特徴とす
る。Preferably, the pilot holes are alternately arranged one by one in a point symmetrical position.
【００２４】かかる構成によれば、方向性も維持するこ
とが可能である。According to this structure, it is possible to maintain the directivity.
【００２５】望ましくは、前記条材は、ＢＧＡ用基板で
あることを特徴とする。Preferably, the strip is a BGA substrate.
【００２６】望ましくは、前記条材は、ＭＡＰ用基板で
あることを特徴とする。Preferably, the strip is a MAP substrate.
【００２７】本発明によれば、半導体装置実装領域が所
定の間隔を隔てて連続的に配設せしめられ、パイロット
穴が、半導体装置用実装基板としての有効幅の範囲内に
設けられている条材を用意する工程と、前記前記半導体
装置実装領域に半導体チップを搭載し、電気的接続を行
う半導体チップ搭載工程と、前記半導体チップを封止す
る封止工程と、封止のなされた半導体チップを、前記パ
イロット穴を含む領域を切除することにより、個々に分
離し、半導体装置を形成する工程とを含むことを特徴と
する。かかる構成によれば、パイロット穴が、半導体装
置用実装基板としての有効幅の範囲内に設けられている
条材を用いて、半導体装置を実装し、封止のなされた半
導体チップを、パイロット穴を含む領域を切除するよう
にしているため、材料に無駄を生じることなく、信頼性
の高い半導体装置を提供することが可能となる。According to the present invention, the semiconductor device mounting regions are continuously arranged at a predetermined interval, and the pilot holes are provided within the effective width of the semiconductor device mounting substrate. A step of preparing a material, a semiconductor chip mounting step of mounting a semiconductor chip in the semiconductor device mounting area and making electrical connection, a sealing step of sealing the semiconductor chip, and a sealed semiconductor chip Is separated into individual parts by cutting out the region including the pilot hole to form a semiconductor device. According to this configuration, the pilot hole is provided in the range of the effective width as the mounting board for the semiconductor device, the semiconductor device is mounted by using the strip material, and the sealed semiconductor chip is attached to the pilot hole. Since the region including is cut off, it is possible to provide a highly reliable semiconductor device without wasting material.
【００２８】[0028]
【発明の実施の形態】以下、本発明の実施形態について
図面を参照しつつ詳細に説明する。本発明の第１の実施
形態のＢＧＡ基板について説明する。このＢＧＡ基板
は、図１に示すように、幅Ｗが６０ｍｍの条材２からな
り幅方向に３列の半導体装置用実装基板領域１が配列さ
れ、３行３列でグルーピングされており、この３行３列
の半導体装置用実装基板領域１の間に相当する領域に
は、この条材２の有効幅Ｗeff５０ｍｍの範囲内にパイ
ロット穴が１個づつ配設されている。また５は分割を容
易にするための破断線である。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The BGA substrate according to the first embodiment of the present invention will be described. As shown in FIG. 1, this BGA substrate is made up of a strip 2 having a width W of 60 mm, and three mounting substrate regions 1 for semiconductor devices are arranged in the width direction, and are grouped in three rows and three columns. In a region corresponding to the semiconductor device mounting substrate region 1 of 3 rows and 3 columns, one pilot hole is provided within the effective width W eff of 50 mm of the strip 2. Further, 5 is a breaking line for facilitating the division.
【００２９】かかる構成によれば、収率が８０％程度と
図１０に示した従来のＢＧＡ基板に比べて大幅に向上し
ていることがわかる。次に、このＢＧＡ基板の製造方法
について説明する。まず図２（ａ）に示すように、ポリ
イミドを基材とする条材２を用意し、これに所定の間隔
でパイロット穴４を形成する。According to this structure, the yield is about 80%, which is much higher than that of the conventional BGA substrate shown in FIG. Next, a method of manufacturing this BGA substrate will be described. First, as shown in FIG. 2A, a strip 2 having a polyimide base material is prepared, and pilot holes 4 are formed in the strip 2 at predetermined intervals.
【００３０】そして、このパイロット穴４を位置決め用
マークとして用い、所定の間隔をグリッパー（図示せ
ず）で把持しながら供給ローラ（図示せず）と巻き取り
ローラ（図示せず）との間で、搬送しながら、順次パタ
ーニングを行い、図２（ｂ）に示すように半導体装置用
実装基板領域を形成し、半田ボール７を搭載する。Then, using the pilot hole 4 as a positioning mark, a gripper (not shown) holds a predetermined space between the supply roller (not shown) and the take-up roller (not shown). Then, patterning is sequentially carried out while being transported to form a semiconductor device mounting substrate region as shown in FIG. 2B, and solder balls 7 are mounted.
【００３１】このときの１つの半導体装置用実装基板領
域１ｓは、図４に平面拡大図、図５に断面図を示すよう
に、表面全体に半田ボール７が形成されてなるものであ
る。この半導体装置用実装基板を用いて半導体装置の実
装を行うに際しては、図３に示すように、前記半導体装
置用実装基板領域の半導体装置搭載領域に半導体チップ
８をダイレクトボンディング法などにより実装し、封止
樹脂９で前記半導体チップ８を覆う樹脂封止工程を経
て、完了する。At this time, one semiconductor device mounting substrate region 1s has solder balls 7 formed on the entire surface as shown in a plan enlarged view of FIG. 4 and a sectional view of FIG. When mounting a semiconductor device using this semiconductor device mounting substrate, as shown in FIG. 3, the semiconductor chip 8 is mounted in the semiconductor device mounting region of the semiconductor device mounting substrate region by a direct bonding method or the like, This is completed after a resin sealing step of covering the semiconductor chip 8 with the sealing resin 9.
【００３２】そして最後に前記破断線５に従ってＤで示
すラインに従って分割し、さらに不要領域を切除しグル
ープ毎に分割する。このようにして形成される半導体装
置用実装基板によれば、パイロット穴４が、半導体装置
用実装基板としての有効幅Ｗeffの範囲内に設けられて
いるため、パイロット穴形成のための幅が不要となり、
条材２の幅を低減することが可能となる。Finally, division is made according to the line indicated by D along the breaking line 5, and unnecessary areas are cut off to divide into groups. According to the semiconductor device mounting board thus formed, since the pilot hole 4 is provided within the range of the effective width W eff as the semiconductor device mounting board, the width for forming the pilot hole is reduced. No longer needed
The width of the strip 2 can be reduced.
【００３３】また、パイロット穴４は半導体装置用実装
基板領域間に設けられているため、長さを増大する必要
もなく、本来は余剰である領域に設けられるため、材料
の無駄が大幅に低減される。Further, since the pilot hole 4 is provided between the semiconductor device mounting substrate regions, there is no need to increase the length, and since the pilot hole 4 is provided in the region that is originally an excess, waste of material is greatly reduced. To be done.
【００３４】また、半導体装置の微細化、高集積化に伴
い、端子数が増大し、リード幅も微細化してきており、
板厚の微細化は進む一方であるが、余剰領域が少なく、
搬送に際しても、幅方向の両端が複雑な形状となってい
ないため、力の不均衡により条材の破壊を招くようなこ
ともなく、グリッパを用いて円滑に搬送することができ
る。Further, with the miniaturization and high integration of semiconductor devices, the number of terminals has increased and the lead width has also been miniaturized.
Although the plate thickness is becoming finer, the surplus area is small,
Even at the time of conveyance, since both ends in the width direction do not have a complicated shape, the strip material is not broken due to the imbalance of forces, and the gripper can be used for smooth conveyance.
【００３５】また、位置決めのためにパイロット穴４が
必要な工程においては、半導体装置用実装基板領域間に
設けられたパイロット穴４を用いればよい。Further, in the process requiring the pilot hole 4 for positioning, the pilot hole 4 provided between the semiconductor device mounting substrate regions may be used.
【００３６】そして最後に、ダイシング工程において、
このパイロット穴４の部分は切除される領域であり、破
断線の一部としても利用可能である。かかる構成によれ
ば、実装が容易で信頼性の高い半導体装置用実装基板を
提供することが可能となる。Finally, in the dicing process,
The portion of the pilot hole 4 is a region to be cut off and can be used as a part of the break line. With this configuration, it is possible to provide a semiconductor device mounting board that is easy to mount and has high reliability.
【００３７】次に、本発明の第２の実施形態について説
明する。本発明の第２の実施形態として、リードフレー
ムについて説明する。この例では、図６に示すように、
銅あるいは鉄−ニッケル製の条材１２からなり幅方向に
３行３列に半導体装置用実装基板領域１１が配列され、
半導体装置用実装基板領域１１の間に相当する領域に
は、この条材１２の有効幅Ｗeff＝５０ｍｍの範囲内に
パイロット穴１４が１個づつ配設されている。Next, a second embodiment of the present invention will be described. A lead frame will be described as a second embodiment of the present invention. In this example, as shown in FIG.
The semiconductor device mounting substrate regions 11 are arranged in 3 rows and 3 columns in the width direction, which are made of copper or iron-nickel strip 12.
In the region corresponding to the semiconductor device mounting substrate region 11, one pilot hole 14 is provided within the effective width W eff of the strip 12 of 50 mm.
【００３８】そして各半導体装置用実装基板領域１１は
図９に示した従来例のリードフレームとほぼ同様に形成
されているがサイドレール１３が極めて細く、パイロッ
ト穴が形成されてはおらず、各リードフレームユニット
の間の領域に設けられている。Each semiconductor device mounting substrate region 11 is formed in substantially the same manner as the conventional lead frame shown in FIG. 9, but the side rails 13 are extremely thin, no pilot holes are formed, and each lead is formed. It is provided in the area between the frame units.
【００３９】このリードフレームは図７に示すように半
導体チップ搭載領域１８と、この半導体チップ搭載領域
１８から外方に伸長するリード１７と、半導体チップ搭
載領域を支持するためのサポートバー１９とを具備して
なるものである。As shown in FIG. 7, this lead frame has a semiconductor chip mounting area 18, leads 17 extending outward from the semiconductor chip mounting area 18, and a support bar 19 for supporting the semiconductor chip mounting area. It is equipped with.
【００４０】このリードフレームでは、図８（ａ）およ
び（ｂ）に要部拡大図を示すように、半導体チップ８を
搭載し、ボンディングワイヤ１６を用いてリード１７と
の電気的接続を行った後、エポキシ樹脂などの封止樹脂
９を用いて封止し、裏面にリード１７が露出してなる面
実装構造の半導体装置が形成される。In this lead frame, as shown in the enlarged view of the main part in FIGS. 8A and 8B, the semiconductor chip 8 is mounted, and the bonding wire 16 is used to electrically connect to the lead 17. After that, sealing is performed using a sealing resin 9 such as an epoxy resin to form a semiconductor device having a surface mounting structure in which the leads 17 are exposed on the back surface.
【００４１】かかる構成によれば、収率が９０％程度と
図９に示した従来のリードフレームに比べて大幅に向上
していることがわかる。なお前記第１および第２の実施
形態においては各半導体装置実装用基板領域の間に１個
づつパイロット穴を配設したが、１つに限定されること
なく、２つづつでもよく、数については適宜変更可能で
ある。また形状についても、丸穴に限定されることなく
三角形あるいは四角形としてもよい。三角形として、方
向も考慮することにより、高精度の位置決めを行うこと
が可能となる。According to this structure, the yield is about 90%, which is much higher than that of the conventional lead frame shown in FIG. In the first and second embodiments, one pilot hole is provided between the semiconductor device mounting board regions, but the number is not limited to one, and two pilot holes may be provided. It can be changed as appropriate. Further, the shape is not limited to the round hole and may be a triangle or a quadrangle. By considering the direction as a triangle, it is possible to perform highly accurate positioning.
【００４２】[0042]
【発明の効果】以上説明してきたように、本発明によれ
ば、パイロット穴が、半導体装置用実装基板としての有
効幅の範囲内に設けられているため、条材の幅を低減す
ることが可能となる。また、パイロット穴は半導体装置
用実装基板領域間に設けられているため、長さを増大す
る必要もなく、本来の余剰領域に設けられるため、材料
の無駄が大幅に低減される。As described above, according to the present invention, since the pilot hole is provided within the effective width of the semiconductor device mounting board, the width of the strip can be reduced. It will be possible. Further, since the pilot holes are provided between the semiconductor device mounting substrate regions, there is no need to increase the length, and since the pilot holes are provided in the original surplus region, waste of material is greatly reduced.
【００４３】また、搬送に際しても、両端が複雑な形状
となっていないため、力の不均衡により条材の破壊を招
くようなこともなく、グリッパを用いて円滑に搬送する
ことができる。Further, at the time of transportation, since the both ends are not complicated in shape, the strip material is not broken due to the imbalance of forces, and the transportation can be smoothly performed by using the gripper.
【００４４】また、位置決めのためにパイロット穴が必
要な工程においては、半導体装置用実装基板領域間に設
けられたパイロット穴を用いればよく、実装が容易で信
頼性の高い半導体装置用実装基板を提供することが可能
となる。Further, in the step requiring the pilot hole for positioning, the pilot hole provided between the semiconductor device mounting board regions may be used, and a mounting board for the semiconductor device which is easy to mount and has high reliability can be obtained. It becomes possible to provide.
【図１】本発明の第１の実施形態のＢＧＡ用基板を示す
図。FIG. 1 is a diagram showing a BGA substrate according to a first embodiment of the present invention.
【図２】本発明の第１の実施形態のＢＧＡ用基板の製造
工程を示す図。FIG. 2 is a diagram showing a manufacturing process of the BGA substrate according to the first embodiment of the present invention.
【図３】本発明の第１の実施形態のＢＧＡ用基板を用い
た半導体装置の実装工程を示す図。FIG. 3 is a diagram showing a process of mounting a semiconductor device using the BGA substrate according to the first embodiment of the present invention.
【図４】本発明の第１の実施形態のＢＧＡ基板を示す要
部拡大図。FIG. 4 is an enlarged view of a main part showing the BGA substrate according to the first embodiment of the present invention.
【図５】本発明の第１の実施形態のＢＧＡ基板を示す断
面図FIG. 5 is a sectional view showing a BGA substrate according to the first embodiment of the present invention.
【図６】本発明の第２の実施形態のリードフレームの製
造工程図。FIG. 6 is a manufacturing process drawing of the lead frame of the second embodiment of the present invention.
【図７】本発明の第２の実施形態のリードフレームの要
部拡大図。FIG. 7 is an enlarged view of a main part of a lead frame according to a second embodiment of the present invention.
【図８】本発明の第２の実施形態のリードフレームを用
いて実装された半導体装置を示す図。FIG. 8 is a diagram showing a semiconductor device mounted using the lead frame of the second embodiment of the present invention.
【図９】従来例のリードフレームを示す図。FIG. 9 is a diagram showing a conventional lead frame.
【図１０】従来例のＢＧＡ基板の製造工程図。FIG. 10 is a manufacturing process diagram of a conventional BGA substrate.
１ 半導体装置用実装基板領域 ２ 条材 ３ サイドレール ４ パイロット穴 ５ 破断線 ７ 半田ボール ８ 半導体チップ ９ 樹脂 １１ 半導体装置用実装基板領域 １２ 条材 １３ サイドレール １４ パイロット穴 １７ リード １８ 半導体素子搭載領域 １９ サポートバー 1 Semiconductor device mounting board area 2 strips 3 side rails 4 pilot holes 5 Break line 7 Solder balls 8 semiconductor chips 9 resin 11 Semiconductor device mounting board area 12 material 13 Side rail 14 Pilot hole 17 Lead 18 Semiconductor element mounting area 19 Support bar
───────────────────────────────────────────────────── フロントページの続き (72)発明者 時任 和浩 福岡県北九州市八幡西区小嶺二丁目10番 １号 株式会社 三井ハイテック内 (72)発明者 刀根 恵一 福岡県北九州市八幡西区小嶺二丁目10番 １号 株式会社 三井ハイテック内 (56)参考文献 特開 平６−177306（ＪＰ，Ａ) 特開 平８−204112（ＪＰ，Ａ) 特開 平10−135258（ＪＰ，Ａ) 特開 平10−284662（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/50 H01L 23/12 501 H05K 1/02 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhiro Toki, 2-10-10 Komine, Hachimansai-ku, Kitakyushu, Fukuoka Prefecture Mitsui High-Tech Co., Ltd. (72) Keiichi Tone 2--10 Komine, Hachimansai-ku, Kitakyushu, Fukuoka No. 1 within Mitsui High-Tech Co., Ltd. (56) Reference JP-A-6-177306 (JP, A) JP-A-8-204112 (JP, A) JP-A-10-135258 (JP, A) JP-A-10- 284662 (JP, A) (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 23/50 H01L 23/12 501 H05K 1/02
Claims (3)
の間隔を隔てて連続的に配設せしめられた条材と、前記
条材の長手方向に沿って隣接する前記半導体装置用実装
基板領域間に相当する領域に配設せしめられたパイロッ
ト穴とを具備し、前記パイロット穴が前記半導体装置用
実装基板領域間の破断線の一部として半導体装置用実装
基板としての有効幅の範囲内に設けられていることを特
徴とする半導体装置用実装基板。1. A semiconductor device mounting board, wherein a plurality of semiconductor device mounting board regions are continuously arranged at a predetermined interval and are adjacent to each other along the longitudinal direction of the strip material. And a pilot hole disposed in a region corresponding to the region, wherein the pilot hole is within a range of an effective width as a semiconductor device mounting substrate as a part of a break line between the semiconductor device mounting substrate regions. A semiconductor device mounting board, comprising:
半導体装置用実装基板がグループ化されて連続形成され
ていることを特徴とする請求項１に記載の半導体装置用
実装基板。Wherein said elongated member is in the effective width, mounting a semiconductor device according to claim 1, mounting substrate for a semiconductor device of the rows and columns is characterized in that it is continuously formed are grouped substrate.
１個づつ配設されていることを特徴とする請求項１又は
２に記載の半導体装置用実装基板。Wherein the pilot hole has claim 1 or, characterized in that it is one by one arranged in point symmetry positions alternately
2. The mounting board for a semiconductor device according to 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001242645A JP3524525B2 (en) | 2001-08-09 | 2001-08-09 | Mounting board for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001242645A JP3524525B2 (en) | 2001-08-09 | 2001-08-09 | Mounting board for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003060148A JP2003060148A (en) | 2003-02-28 |
| JP3524525B2 true JP3524525B2 (en) | 2004-05-10 |
Family
ID=19072885
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001242645A Expired - Fee Related JP3524525B2 (en) | 2001-08-09 | 2001-08-09 | Mounting board for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3524525B2 (en) |
-
2001
- 2001-08-09 JP JP2001242645A patent/JP3524525B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003060148A (en) | 2003-02-28 |
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