JP3522209B2 - Optimal voltage adjustment circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optimum voltage adjusting circuit for supplying an optimum voltage when power is supplied to an LSI.

[0002]

2. Description of the Related Art Conventionally, as an example of an optimum voltage adjusting circuit for supplying power to an LSI, there is a configuration described in Japanese Patent Laid-Open No. 4-360312.

A conventional optimum voltage adjusting circuit for supplying power to an LSI will be described with reference to FIG. In FIG. 5, 5
Reference numeral 01 denotes a ring oscillator, which is designed so that the oscillation cycle tDo is the same as the output cycle T from the crystal oscillator 500 under standard use conditions (process, temperature, power supply voltage: standard). At this time, the cycle T is set so that the operating characteristics of the ring oscillator 501 are optimized. Since the ring oscillator 501 and the logic circuit 504 are formed on the same chip and have the same operating conditions, they operate with the same characteristics when the same voltage is input. Here, from the power supply circuit 503 to the ring oscillator 501 and the logic circuit 5
04 is supplied with the same voltage, the period tDo of the ring oscillator 501 and the period T of the crystal oscillator 500 are compared by the comparison circuit 502, and the voltages are adjusted so that the two have the same period. The operating voltage has been supplied, and at the same time, the logic circuit 504 has been supplied with a voltage that enables optimum operation.

[0004]

However, in the above-mentioned conventional optimum voltage adjusting circuit, it is necessary to design the cycle tDo of the ring oscillator 501 to be the same as the output cycle T of the crystal oscillator 500. Even if you design it under usage conditions, there are variations in the process, so
There is a problem that it is difficult to secure the cycle of the ring oscillator 501 at the target tDo, and it becomes difficult to supply the optimum voltage to the logic circuit.

Therefore, it is an object of the present invention to provide an optimum voltage adjusting circuit which can stably provide an optimum voltage for the operation of a logic circuit without being affected by process variations.

[0006]

In order to achieve the above object, an optimum voltage adjusting circuit according to a first aspect of the present invention comprises a crystal oscillator for outputting a clock having a reference period, and a crystal oscillator for synchronizing with the clock. A first flip-flop for inputting an inverted value of its own output signal and a delay value for inputting the output signal of the first flip-flop and adding a margin to the cycle of the output clock of the crystal oscillator. It is composed of a designed delay circuit and a second flip-flop which receives the output signal of the delay circuit and operates in synchronization with the clock of the crystal oscillator. The same timing of the first flip-flop and the second flip-flop. It has a usage state detection circuit for comparing the output values of the above and detecting the excess or deficiency of the supplied voltage.

An optimum voltage adjusting circuit according to a second aspect of the present invention has a voltage value calculating circuit for controlling the rise and fall of the voltage according to the transition of the excess / deficiency state of the voltage detected by the use state detecting circuit.

An optimum voltage adjusting circuit according to a third aspect of the present invention has a power supply circuit that supplies an optimum voltage to a target logic circuit under the control of the voltage value calculating circuit. With the above configuration, an optimum voltage can be stably supplied without being affected by process variations. Further, even when the usage state detection circuit detects the fail state of the delay value of the delay circuit (T> delay value of the delay circuit), the delay value of the delay circuit is delayed before the logic circuit because the delay value has a margin. By controlling the power supply circuit by the voltage value calculation circuit so that the circuit becomes the fail state and the delay circuit does not become the fail state, it is possible to stably supply the minimum voltage necessary for the operation of the logic circuit.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an optimum voltage adjusting circuit of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a use state detecting circuit in the optimum voltage adjusting circuit of the present invention. Delay circuit 1
02 is formed between the flip-flop 100 of the first stage and the flip-flop 103 of the second stage, and the delay circuit 1
The delay value tD of 02 is less than the cycle T of the clock generated by the crystal oscillator 106 under the condition that the use condition is the slowest (process: slowest, temperature: maximum, power supply voltage: minimum level at which the switching operation of the inverter is possible) It is designed with a margin that increases by αT.

At this time, in order to compare the delay value tD of the delay circuit 102 with the period T of the clock generated by the crystal oscillator, two flip-flops 100 and 103 are used to rise the clock of the period T generated by the crystal oscillator. The flip-flop output 101 of the first stage is compared with the flip-flop output 104 of the second stage by operating at the edge, and when the output values are different, the pass state (T> tD), and when the output values are the same, fail State (T <tD). This usage state can be classified into the following four cases.

When the flip-flop output 101: 0 and the flip-flop output 104: 0, the fail state (T <
tD) Flip-flop output 10 1: 0 Flip-flop output 104: 1 when pass state (T> tD) Flip-flop output 101: 1 Flip-flop output 104: 0 pass state (T> tD) Flip-flop output 101: 1 When the flip-flop output 104: 1 is in the fail state (T <tD) Further, the delay value tD of the delay circuit 102 has a margin of αT under the condition that the use condition is the slowest, so that the logic circuit to which power is supplied is The delay value of the critical path is smaller than the cycle T of the clock generated by the crystal oscillator with a margin of αT at the moment when the delay value tD of the delay circuit 102 becomes a fail state (T = tD).

The voltage value calculation circuit 202 in FIG. 2 is a control signal that determines whether the voltage output from the power supply circuit rises or falls based on the state transition of the use state detection circuit 200 from the use state one clock before to the current use state. Is output.
In other words, when the current usage status is the fail status, a signal that raises the voltage is output, and when the fail status changes to the pass status, a signal that holds the voltage is output and the pass status changes to the pass status. When it does, it outputs a signal to lower the voltage. As a result, the voltage to be supplied can be controlled so that the voltage always converges to the minimum voltage required for operation. Specifically, it can be classified into the following four state transition patterns.

Pass → Pass: Voltage drop Pass → Fail: Voltage boost Fail → Pass: Voltage hold Fail → Fail: Voltage boost In FIG. 3, the optimum voltage adjusting circuit of the present invention supplies a voltage to a logic circuit. It is a block diagram at the time.

First, the usage state detection circuit 300 compares the delay value of a delay circuit provided in advance with the period of a reference crystal oscillator to determine whether the supplied power supply voltage is excessive or insufficient (pass / fail). Is detected and the detection result is output to the voltage value calculation circuit 301. Next, the voltage value calculation circuit 301 determines the value of the signal that controls the rise and fall of the power supply voltage to be supplied by the transition of the excess or deficiency (pass / fail) state of the supplied power supply voltage. Finally, based on the control signal of the voltage value calculation circuit 301, the power supply circuit 302 supplies a voltage to the logic circuit 303 to which power is supplied.

FIG. 4 is a state transition diagram showing the relationship between the delay value tD of the delay circuit and the supply voltage VDD supplied to the logic circuit in the optimum voltage adjusting circuit of the present invention. T is the period of the reference crystal oscillator, and when the delay value of the delay circuit is 403, the delay circuit is in a fail state, but the delay value of the delay circuit has an extra delay of αT under the slowest condition.
It can be seen that the delay value 404 of the critical path of the logic circuit at this time enters the path region and a sufficient voltage is supplied. Reference numerals 400, 401, and 402 denote delay calculation lines representing the relationship between the delay value tD of the delay circuit and the supply voltage VDD supplied to the logic circuit for each use condition, and the delay value tD of the delay circuit = the reference crystal oscillator period T. The voltage at that time is the minimum voltage required for the logic circuit. In the optimum voltage adjusting circuit of the present invention, the voltage supplied to the logic circuit is adjusted by the voltage value calculating circuit so as to converge to this value.

As described above, according to the optimum voltage adjustment circuit of the present invention, the optimum voltage adjustment can be stably performed without being affected by the process variations and the like. In addition, since the delay value of the delay circuit has a margin of αT under the use condition in which the delay value is the slowest, the critical path of the logic circuit enters a region passing by αT so that the minimum necessary voltage is always supplied. Become.

[0018]

In the optimum voltage adjusting circuit of the present invention, the period of the reference crystal oscillator is compared with the delay value of the delay circuit, and the voltage supplied to the logic circuit is adjusted based on the state transition of the comparison result. Therefore, the stable supply of the optimum voltage can be performed without being affected by the process variations and the like. The delay value of the delay circuit is αT under the slowest condition.
Therefore, if the voltage supplied by the voltage value calculation circuit is adjusted so that the delay value of the delay circuit converges to a value that the use state detection circuit barely passes, the critical path of the logic circuit is αT. Then, the minimum voltage necessary to operate always enters the area that passes only the margin of.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a usage state detection circuit of the present invention.

FIG. 2 is a block diagram showing a configuration of a voltage value calculation circuit of the present invention.

FIG. 3 is a block diagram in which an optimum voltage value adjusting circuit of the present invention supplies a voltage to a logic circuit.

FIG. 4 is a state transition diagram by the use state detection circuit of the present invention.

FIG. 5 is a block diagram showing a configuration of an optimum voltage adjusting circuit for supplying power to a conventional LSI.

[Explanation of symbols]

100 flip-flops 101 flip-flop output 102 delay circuit 103 flip-flop 104 flip-flop output 105 Usage status detector 106 crystal oscillator 200 Usage condition detection circuit 202 voltage value calculation circuit 203 power supply circuit 300 Usage condition detection circuit 301 voltage value calculation circuit 302 power supply circuit 303 Logic circuit to which power is supplied 400 delay calculation line 401 Delay calculation line 402 Delay calculation line 403 Delay value of delay circuit 404 Delay value of critical path of logic circuit 500 crystal oscillator 501 ring oscillator 502 Comparison circuit 503 power supply circuit 504 logic circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 10-49242 (JP, A) JP 2000-77999 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03L 1/00-7/14

Claims (3)

(57) [Claims] 1. A crystal oscillator that outputs a clock having a reference cycle, a first flip-flop that inputs an inverted value of its own output signal in synchronization with the clock, and an output signal of the first flip-flop. And a delay circuit designed to have a delay value with a margin added to the cycle of the output clock of the crystal oscillator, and an output signal of the delay circuit is input to operate in synchronization with the clock of the crystal oscillator. A second flip-flop that
Optimal voltage adjustment circuit having a usage state detection circuit that compares the output values of the flip-flop and the second flip-flop at the same timing to detect excess and deficiency of the supplied voltage. 2. The optimum voltage adjusting circuit according to claim 1, further comprising a voltage value calculating circuit that controls the rise and fall of the voltage according to the transition of the excess or deficiency state of the voltage detected by the use state detecting circuit. 3. The optimum voltage adjusting circuit according to claim 2, further comprising a power supply circuit which supplies an optimum voltage to a target logic circuit under the control of the voltage value calculating circuit.