JP3520003B2 - LCD drive circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD drive circuit, and more particularly to a technique for reducing current consumption in a microcomputer incorporating such an LCD drive circuit.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram for explaining a schematic configuration of a conventional microcomputer having a built-in LCD drive circuit.

In FIG. 3, reference numerals 1 and 2 denote display RAMs in the preceding stage.
Is a preparation latch in which the data from is input to the input terminal (L) and the write signal is input to the other input terminal (CK).
Reference numerals 3 and 4 are LCD latches to which the output data (Q) of the preparation latches 1 and 2 are input to one input terminal (L) and the COM sync signal is input to the other input terminal (CK).

Reference numerals 5 and 6 are LCD drivers to which the outputs (Q) of the LCD latches 3 and 4 are input. This L
The CD drivers 5 and 6 drive the LCD panel,
The output of the LCD latches 3 and 4 is level-converted to a predetermined high voltage, and each segment terminal (hereinafter referred to as SEG terminal).
Output to 1 and 2.

As described above, in the microcomputer having the LCD drive circuit built-in, the LCD latch 3 is provided for each SEG terminal because of the chip area problem and the efficiency problem.
It had 4 built-in one.

Generally, the LCD panel has a SEG signal output from the above-mentioned SEG terminal and a common terminal (hereinafter, C terminal).
Matrix driving is performed by a control signal (hereinafter, referred to as COM signal) for the common electrode output from the OM terminal). That is, the LCD is turned on when a predetermined potential difference is generated between the SEG signal and the COM signal.

Here, when the COM signal is one, the DC drive is performed, but when the COM signal is two or more, the AC drive is performed. Therefore, for example, when there are a plurality of COM signals, L
In order to drive the CD, segment data corresponding to COM1 to COMn (n = 1 or more, for example, n = 4) were sequentially required.

Therefore, when the LCD is driven, preparation latches 1 and 2 are provided in addition to the LCD latches 3 and 4, and data is read from a memory register such as a display RAM in advance to prepare for this. The data was written in the latches 1 and 2 for standby.

That is, when the COM1 is driven, the data corresponding to the COM1 is prepared in the LCD latches 3 and 4, and the data corresponding to the next COM2 is prepared in the preparation latches 1 and 2 in advance. Data corresponding to COM2 is prepared in the LCD latches 3 and 4, and data corresponding to the next COM3 is prepared in advance in the preparation latches 1 and 2. The data prepared at this time is read from a memory register such as a display RAM and latched and held in the preparation latches 1 and 2 by a data write signal.

FIG. 4 is a diagram showing operation waveforms in the conventional circuit, in which the COM1 to COM4 signals sequentially rise. C synchronized with the rising edge of each of these signals
Based on the OM sync signal, the LCD latches 3 and 4 are simultaneously sent via the LCD drivers 5 and 6 to the SEG terminal (SE
The segment signal is output to G1 to SEGn).

In each of the signal periods COM1 to COMn, data is periodically read from the display RAM based on the SEG1 to SEGn write signals and written in the preparation latches 1 and 2. Therefore, the memory register such as the display RAM always performs the reading operation during the LCD display.

[0012]

As described above, in the conventional circuit configuration, during the LCD display, the memory register such as the display RAM needs a periodic read operation. When the display RAM or the like is read, most of the system such as the RAM control circuit and the data bus control circuit operates. In particular, in the case of adopting a circuit configuration in which the data lines are precharged and then read out for speeding up the RAM, the current consumption becomes very large.

Therefore, periodically performing such an access operation of the display RAM has been an adverse effect on the microcomputer which attempts to realize low current consumption.

Therefore, it is an object of the present invention to provide an LCD drive circuit which can reduce current consumption.

[0015]

Therefore, the LCD of the present invention.
The drive circuit is a display RAM 10 as shown in FIG.
And a plurality of SEG terminals (SEG
1 to SEGn) and a plurality of Cs from which COM signals are output
OM terminals (COM1 to COM4) and first latches 11 and 1 provided for each of the SEG terminals and latching the data based on the segment write signal when the data of the display RAM 10 is changed, corresponding to the COM terminals.
2, 13, 14 and 31, 32, 33, 34, and this first
1 latches 11, 12, 13, 14 and 31, 32, 3
Second latches (LCD latches 15, 16, 17, 18 and 35, 36, 37, 38) for latching the outputs of 3, 34 based on the LCD change signal, and this LCD latch 1
A plurality of switch means 20, 21, 22, 23 and 40 for sequentially outputting the data of 5, 16, 17, 18 and 35, 36, 37, 38 based on a plurality of COM signals.
41, 42, 43 and the LCD latches 15, 16, 1
LCD driver 1 for level-converting data of 7, 18 and 35, 36, 37, 38 and outputting to the SEG terminal
9, 39 are provided.

According to the configuration of the LCD drive circuit, the display RAM required for a plurality of COM signals.
All the data can be prepared in the LCD latch in advance, and moreover, it is sufficient to write in the LCD latch only when the data in the display RAM is changed. As a result, it is not necessary to periodically access the RAM as in the circuit of the conventional example, and it is possible to greatly reduce the current consumption.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of an LCD drive circuit of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram for explaining a schematic configuration of a microcomputer incorporating the LCD drive circuit of the present invention.

In FIG. 1, reference numerals 11, 12, 13, and 14 denote signals from the preceding display RAM 10 which are input to one input terminal (L), and a segment (SEG) write signal when data is changed to the other input terminal (CK). The first latch input to
As many COM terminals (COM1 to COM4) as will be described later are provided in parallel corresponding to the SEG1 terminals.

The SEG write signal is generated when the data in the display RAM 10 is changed, and based on this signal, the changed data in the display RAM 10 is written in the first latches 11, 12, 13, and 14. Be done.

Outputs (Q) of the first latches 11, 12, 13, 14 are input to one input terminal (L) of 15, 16, 17, and 18, and an LCD change signal is input to the other input terminal (CK).
Is an LCD latch as a second latch that is input to.

Further, 19 is the LCD latches 15 and 1
It is an LCD driver for converting the output (Q) of 6, 17, 18 into a predetermined high voltage.

This LCD driver 19 receives the input C
Switch means 20 and 21, which are composed of transfer gates which are opened and closed based on the OM1 signal to the COM4 signal.
It is connected to the SEG1 terminal via 22 and 23.

The configuration corresponding to the SEGn terminal is also the same, and the signal from the display RAM 10 in the preceding stage is input to one input terminal (L) of the first latches 31, 32, 33, 34, and when data is changed. The SEG write signal is sent to the other input end (C
K) and the first latches 31, 32, 33,
The output (Q) of 34 is LCD latch 35, 36, 37, 3
8 is input to one input terminal (L), and the LCD change signal is input to the other input terminal (CK). The outputs (Q) of the LCD latches 35, 36, 37 and 38 are C
It is input to the LCD driver 39 via the switch means 40, 41, 42, 43 which are opened / closed based on the OM1 to COM4 signals, and the LCD driver 39 is SEGn.
It is connected to the.

FIG. 2 is a diagram showing operation waveforms in the above-mentioned invention circuit, and the features of the present invention will be more apparent when compared with the operation waveform diagram in the conventional circuit shown in FIG.

Display RA for each COM signal period as in the prior art
It is not necessary to perform the M read operation. That is, as shown in FIG. 2, when the data in the display RAM 10 is changed, S
An EG write signal is generated. Then, the data required during each COM signal period according to this signal is the first latches 11, 12, 13, 14 and 31, 32, 33, 3
Written to 4. The data of the first latch is L
It is transferred to the CD latch and output based on the LCD change signal. At this time, the switch means 20, 21, 22, 2
Since 3 and 40, 41, 42, 43 are provided,
The output data of the LCD latch corresponding to each COM signal is sequentially output to the LCD drivers 19 and 39 based on the COM1 to COM4 signals.

As described above, in the present invention, a circuit configuration in which LCD latches for COMn (n = 1 or more, for example, n = 4) necessary for one segment (SEG) terminal are prepared and the output is switched by the COM1 to COMn signals. As a result, the read operation from the display RAM is performed only when writing the data change, and the conventional register read operation of the display RAM or the like is eliminated. Therefore, the consumption current can be reduced and the voltage can be reduced.

Further, in the present embodiment, S when data is changed
First latches 11, 1 to which the EG write signal is input
2, 13, 14 and 31, 32, 33, 34 and LCD
LCD latches 15, 16, 17, to which change signals are input,
A circuit configuration provided with 18 and 35, 36, 37, 38 respectively is adopted, but this is a specification for collectively changing the LCD display, and is a low level in a microcomputer incorporating the LCD drive circuit of the present invention. In the case of only achieving the purpose of realizing current consumption reduction, the LCD latches 15, 16, 17, 18 and 3 are considered.
5, 36, 37, 38 may be omitted, and in this case, an increase in the number of parts can be suppressed.

[0029]

According to the present invention, a read operation from the display RAM is performed by providing a LCD latch for one COM terminal required for one segment terminal and switching the output based on each COM signal. Is only during writing of data change and does not perform the periodic read operation unlike the conventional circuit configuration, so that lower voltage and lower current consumption can be achieved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an LCD drive circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms of the LCD drive circuit of the present invention.

FIG. 3 is a circuit diagram showing a conventional LCD drive circuit.

FIG. 4 is a diagram showing operation waveforms of a conventional LCD drive circuit.

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-5-241532 (JP, A) JP-A-3-55594 (JP, A) JP-A-6-130901 (JP, A) JP-A-52-1 147093 (JP, A) JP 49-88558 (JP, A) JP 60-86594 (JP, A) JP 53-129683 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580

Claims (3)

(57) [Claims] 1. A display for RAM, and a plurality of SEG terminals plurality of SEG signal is output, a plurality of COM terminals plurality of COM signal is output, is provided for each of the SEG terminal, the display RAM Corresponding to the plurality of COM signals based on the segment write signal only when data is changed
Latch all required display RAM data ,
The number of LCD latches corresponding to COM terminals, and the LCD
A plurality of switch means for sequentially outputting the data in the latch based on a plurality of COM signals, and an LC for converting the level of the data in the LCD latch and outputting it to the SEG terminal.
An LCD drive circuit comprising a D driver. Wherein the display RAM, and a plurality of SEG terminals plurality of SEG signal is output, a plurality of COM terminals plurality of COM signal is output, the data of the display RAM is provided for each of the SEG pins Only when changing, it is necessary to correspond to the plurality of COM signals based on the segment write signal.
C, which latches all the necessary display RAM data
A number of first latches corresponding to OM terminals and a second latch for latching the output of the first latch based on an LCD change signal.
Data of the second latch and the data of the second latch into a plurality of COMs.
An LCD drive circuit comprising: a plurality of switch means for sequentially outputting based on a signal; and an LCD driver for level-converting the data of the second latch and outputting the level-converted data to the segment terminals. 3. The LCD drive circuit according to claim 1, which is incorporated in a microcomputer.