JP3509775B2 - Incremental signal processing method and apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an incremental signal processing method and apparatus, and more particularly, to changing the frequency of a driving clock signal in accordance with the rotational speed, that is, the frequency of the incremental signal so that even a low frequency clock signal can be processed. The present invention relates to a new improvement for improving the reliability against noise by making it possible to read twice.

[0002]

2. Description of the Related Art The structure shown in FIG. 2 has been adopted as an incremental signal processing method and device of this type which has been conventionally used. That is, what is indicated by reference numeral 1 in FIG. 2 is a well-known double-reading circuit unit (reads the incremental signal 3 twice with a time difference), and the double-reading circuit unit 1 includes a detecting unit 2 of the encoder. In addition to the waveform-shaped incremental signal 3 obtained in advance and being input in advance, the clock signal from the clock generation unit 4 is input as the driving clock signal 5. Therefore, the double reading circuit unit 1 is driven by the frequency of the driving clock signal 5 to read the incremental signal 3 twice, and the output signal 1a from the double reading circuit unit 1 performs the next processing. It is applied to the circuit 6.

[0003]

Since the conventional method and apparatus for processing an incremental signal are configured as described above, there are the following problems. That is, when the encoder rotation speed increases, the frequency of the incremental signal increases, so a high-frequency clock signal is used so that the incremental signal at the maximum rotation speed can be read twice, and the incremental signal at all rotation speeds is read twice. Was. Therefore, the double reading is generally more effective against noise when the frequency of the clock signal is lower. However, since the above-described conventional technique uses only the clock signal of high frequency, the incremental signal in the state of low rotation speed is used. Even in the double reading of, only the high frequency clock signal, which has a small effect on noise, could be used.

The present invention has been made to solve the above problems, and in particular, by changing the frequency of the driving clock signal according to the rotational speed, that is, the frequency of the incremental signal, a clock signal of a low frequency is obtained. However, it is an object of the present invention to provide an incremental signal processing method and apparatus that can improve the reliability against noise by enabling the double reading of the incremental signal with high accuracy.

[0005]

SUMMARY OF THE INVENTION An incremental signal processing method according to the present invention uses a clock signal having a frequency higher than the frequency of the incremental signal obtained from a detector.
Based on the double reading circuit section, the incremental
In an incremental signal processing method in which noise included in the incremental signal is removed by reading the mental signal twice, a drive for driving the double reading circuit unit according to an increase in the rotation speed of the incremental signal. The frequency of the clock signal for use is increased . Further, the incremental signal processing device of the present invention has a frequency of the incremental signal obtained from the detection unit.
Based on the clock signal having a frequency higher than the number, the twice reading circuit unit outputs the incremental signal in the state of time difference.
By reading once, in an incremental signal processing device configured to remove noise included in the incremental signal, a rotation speed detection circuit unit for detecting the rotation speed of the incremental signal, and the rotation speed detection circuit unit A rotation speed of the incremental signal is provided, comprising a selector to which the rotation speed detection value is input and a clock signal from the clock generation unit, and a drive clock signal to be input from the selector to the double reading circuit unit. In this configuration, the frequency of the driving clock signal is increased by the selector according to the increase of the.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of an incremental signal processing method and apparatus according to the present invention will be described below with reference to the drawings. In addition, the same or equivalent portions as those of the conventional example will be described using the same reference numerals. 1 is a well-known double reading circuit unit,
An incremental signal 3 obtained by a detector 2 of the encoder and subjected to waveform shaping in advance is input to the double reading circuit unit 1.

The incremental signal 3 is input to a rotational speed detection circuit unit 10 for detecting the rotational speed, that is, the frequency of the encoder, and the rotational speed detection value 10a obtained by detecting the rotational speed (that is, the frequency) of the incremental signal 3 is obtained. , And the clock signals 4a to 4n from the clock generation unit 4 are input to the selector 11 including a selection circuit. The clock signals 4a to 4n are composed of several kinds of frequencies corresponding to the lowest rotation speed and the highest rotation speed of the encoder.

The selector 11 is constructed so that it can select each of the clock signals 4a to 4n according to the detected rotation speed value 10a and input it as the driving clock signal 5 to the double reading circuit section 1. ing.

Therefore, in the above configuration, even when the rotational speed of the incremental signal 3, that is, the frequency is low or high, the clock signals 4a to 4a according to the rotational speed.
n is selected by the selector 11 and is input twice as the driving clock signal 5 to the reading circuit unit 1, and regardless of the speed or frequency of the incremental signal 3, it is most effective against noise and the like according to the frequency. You can read it twice.

FIG. 3 is a block diagram showing the configuration of the double reading circuit according to the present invention. FIG.
It is a timing chart which shows the content of operation of a degree reading circuit. In FIG. 3, the output Q1 of the D-FF1 is a, DF
When the output Q2 of F is b and the exclusive OR of outputs a and b is c, the clock pulse, the input of the double reading circuit, a, b,
c and the output of the double reading circuit are as shown in FIG.

That is, in FIG. 4, when there is noise surrounded by a broken line at the input, the output a is at the H level when the noise is at the H level and the clock is at the H level (clock of the third pulse). (This is the first reading). At this time, the output c of the exclusive OR becomes H level.

The output a input to the DI of the D-FF2 is at H level, and the output b of the D-FF2 is at H level when the clock is at H level (clock of the fourth pulse) (this is the second time. Read). At this time, since the noise included in the input of the twice reading circuit has returned to the L level, the output a becomes the L level at the rising edge of the clock of the fourth pulse. Then, when the fifth pulse clock rises after the regular signal is input to the double reading circuit,
The outputs a and b become H level and L level, respectively. At this time, the output c does not change and holds the L level.

When the clock of the sixth pulse rises, the output b also becomes H level. When the seventh pulse clock rises when both outputs a and b are at H level, the output of the double reading circuit changes to H level for the first time. By the operation of the double-reading circuit as described above, the output of the double-reading circuit is obtained by removing the noise contained in the input of the double-reading circuit. That is, read twice,
Furthermore, using their outputs and exclusive OR, the D-FF
By driving 3, the function like a digital filter can be ensured.

It should be noted that in the above configuration, the selector 1
Although the case where 1 is used is described, the rotation speed detection value 10a is obtained without using the selector 11.
It is also possible to change the frequency of the driving clock signal 5 continuously and variably from the clock generator 4 by using it as the time constant.

[0015]

Since the incremental signal processing method and apparatus according to the present invention is configured as described above, the following effects can be obtained. That is, since the driving clock signal is varied according to the rotation speed, that is, the frequency of the incremental signal, the most effective double reading can be performed from low rotation to high rotation, and a highly reliable encoder is obtained. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an incremental signal processing device according to the present invention.

FIG. 2 is a block diagram showing a conventional configuration.

FIG. 3 is a block diagram showing a configuration of a double reading circuit according to the present invention.

FIG. 4 is a timing chart showing the operation contents of the double reading circuit in the present invention.

[Explanation of symbols]

12 times reading circuit 2 detector 3 Incremental signal 4 Clock generator 5 Driving clock signal 10 Rotational speed detection circuit 11 selector

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Claims (2)

(57) [Claims] 1. A clock signal having a frequency higher than the frequency of the incremental signal (3) obtained from the detector (2).
Wherein in the state of the time difference in the twice-reading circuit (1) on the basis of
By reading incremental signals (3) twice, the in incremental signal processing method so as to remove the noise contained in the incremental signals (3), depending on the increase in the rotational speed of said incremental signal (3) Driving clock signal for driving the double reading circuit unit (1)
An incremental signal processing method characterized by increasing the frequency of (5). 2. A clock signal having a frequency higher than the frequency of the incremental signal (3) obtained from the detector (2)
Wherein in the state of the time difference in the twice-reading circuit (1) on the basis of
By reading incremental signal (3) twice, the incremental signal processing apparatus designed to remove noise contained in the incremental signal (3), for detecting the rotational speed of said incremental signal (3) Rotation speed detection circuit unit (10), and the rotation speed detection circuit unit
The selector (11) to which the rotation speed detection value (10a) of (10) is input and the clock signals (4a to 4n) from the clock generation unit (4) and the selector (11) With a driving clock signal (5) input to the reading circuit unit (1),
The frequency of the driving clock signal (5) is changed to the selector according to the increase in the rotation speed of the incremental signal (3).
Incremental signal processing device characterized by being configured to be high in (11).