JP3505605B2 - Automatic gain control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit (AGC circuit) used for a radio receiver, and more particularly to an automatic gain control circuit capable of high-speed response. It is. 2. Description of the Related Art A radio receiver is provided with an AGC circuit having a closed loop circuit configuration in order to reduce fluctuations in demodulation output due to fluctuations in reception input, so that the demodulation output becomes substantially constant. The gain of the amplifier is automatically controlled. FIG.
Is an example diagram of a conventional AGC circuit. In the figure, a part of the output of an AGC amplifier 1 is extracted by a signal distributor 2 and rectified by a detection circuit 3 to charge a capacitive element 4 which determines a time constant of the AGC circuit. The terminal voltage of the capacitive element 4 becomes a gain control voltage of the AGC amplifier 1 and discharges at a value of a time constant determined by a resistor provided inside the AGC amplifier 1 and the capacitive element 4. [0003] In recent years, digitization of mobile communication and adoption of a TDMA (Time Division Multiple Access) system have been studied. When the above-mentioned conventional AGC circuit is used for the radio receiver of this TDMA system,
There are the following problems. The features of the conventional AGC circuit are
Although the output has the advantage of increasing monotonically with the increase of the input, it takes time for the output level to reach a certain level and be stabilized by the AGC control operation because of the time constant circuit in the circuit loop. On the other hand, in a TDMA system, a received signal of a wireless receiver is a burst signal , and a high response speed of the receiver is required. [0004] Figure 4 is a waveform diagram of each part of a conventional AGC circuit shown in FIG. 3 shows the waveform when the burst received signal is input. In FIG. 4, a indicates the envelope of the burst reception signal. b is a terminal voltage of the capacitive element 4 and shows a control voltage waveform of the AGC amplifier 1. c is AG
4 shows a change in gain of the C amplifier 1. d indicates the envelope of the output signal of the AGC circuit. When the burst signal a is input to the AGC amplifier 1, the control voltage b is small,
Becomes a value close to the saturation voltage, and a flat portion where the AGC does not work is formed at the rising portion of the output voltage d. The flat part of the envelope d has a large gain of the amplifier 1 and saturates the amplifier 1 and contains many distortion components. For this reason, even if the signal in this portion is correctly demodulated (decoded), the error rate increases and correct data cannot be obtained. Reducing the time constant of the AGC operation in order that eliminate this drawback, when the reception level decreases, there is a problem that AGC operation is not performed. An object of the present invention is to solve the above problems, faster rise of AGC operation to the burst input signal, and to provide an automatic gain control circuit for sufficient AGC operation It is in. An automatic gain control circuit according to the present invention amplifies a reception input from a radio wave by an AGC amplifier, extracts and detects a part of the output, charges a capacitive element, and charges the capacitive element. In an automatic gain control circuit that obtains a substantially constant and stable output by controlling the gain by using the terminal voltage of the element as the control DC voltage of the AGC amplifier, in order to increase the response speed to a burst-like reception input, A signal distribution circuit for dividing the signal into two and inputting one output to the AGC amplifier, a level detection circuit for receiving the other output of the signal distribution circuit and outputting a signal indicating signal reception when the output is larger than a predetermined threshold value; it short pulse in synchronization with the rising time point and a trailing time of the signal from the level detection circuit
A pulse generating circuit for outputting the respective signals, and a control of the AGC amplifier.
A predetermined polarity that has the same polarity as the control DC voltage and is greater than the control DC voltage.
Gate and a power supply circuit for generating a DC voltage of, by said short pulses synchronized with the rising edge of the said pulse generating circuit
A first switch circuit for applying a predetermined DC voltage from the power supply circuit and over preparative to the capacitive element, the short time synchronized with the falling edge from the pulse generating circuit
Through a resistive element the charging voltage of the capacitor element by between pulses
And a second switch circuit for causing rapid discharge. Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram of each part of the circuit of FIG. Burst input <br/> force signal a is distributed into two signal distribution circuit 5. The signal following the upper path in the figure is the same as the conventional AGC circuit,
The signal is output via the AGC amplifier 1 and the signal distributor 2. The other output of the signal distributor 2 is detected by the detection circuit 3 to determine the time constant of the AGC loop and charge the capacitive element 4.
The terminal voltage of the capacitive element 4 is given to the amplifier 1 as a control DC voltage that determines the amplification factor of the AGC amplifier 1. The other output of the signal distribution circuit 5 is input to the level detection circuit 6. The level detection circuit 6 determines whether the input voltage a is higher than a threshold. This is done at the leading edge of waveform e in FIG. When the input voltage a is large, the information is given to the pulse generation circuit 7. The pulse generator 7 generates a pulse fi of a predetermined width based on information from the level detector 6. This pulse fi is input to the switch circuit 8.
The switch circuit 8 applies the DC voltage from the power supply circuit 9 to the capacitive element 4 for a time of a determined pulse width. As a result, the capacitive element 4 is rapidly charged, and becomes as shown by the waveform i in FIG. That is, as shown by the waveform i, the power supply circuit 9
Indicates the level detection DC output of the burst input signal a (detection circuit
Level detection DC output with the same polarity as the output voltage of path 3)
Generates a larger constant DC voltage. For example, in order to reduce the charging time to one third of the conventional case, the voltage of the power supply circuit 9 may be set to be three times the output voltage of the detection circuit 3. Thus, the level detection circuit 6, the pulse generation circuit 7, the power supply circuit 9
By adding a circuit including the switch circuit 8 and the switch circuit 8, desired characteristics can be satisfied. The charging time is determined by the voltage applied to the capacitor 4. In the above, the case of rising has been described.
Next, the case of falling will be described. In the case of a falling edge, the level detection circuit 6 detects the level when the envelope of the input signal a passes the threshold value downward. This case is determined by the trailing edge of waveform e in FIG. In this case, a part of the input voltage a may cause a level drop momentarily. In such a case, a malfunction from a level drop can be prevented by a signal from a higher-order system. When the level detection circuit 6 detects the level drop, the pulse generation circuit 7 generates a discharge pulse. This is shown by the waveform fs in FIG. This discharge pulse fs is input to the switch circuit 10 to discharge the terminal voltage of the capacitor 4 through the resistor R. This pattern is shown by the trailing edge of waveform g in FIG. A waveform h indicates a change in the gain of the AGC amplifier 1. [0009] As a result, the envelope of the output waveform becomes as shown in the waveform i in FIG. 2, the flat part of the rise of the waveform, i.e. the duration of the portion gain contains many large saturation to the distortion component Is shorter than the conventional circuit. Thus, by using the AGC circuit of the present invention, A
The time until the GC control is stabilized is shortened as compared with the conventional circuit, and the TDMA reception efficiency can be improved. As described above, by implementing the present invention, the response time of the AGC circuit can be increased. When the present invention is applied to a receiver of a TDMA communication system, the signal level input to the demodulation circuit for each burst can be suppressed to a constant level at a high speed. Can be reduced, and the practical effect is great.

[Brief description of the drawings] FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a waveform diagram of each part of the circuit of FIG. FIG. 3 is a diagram illustrating an example of a conventional circuit configuration. FIG. 4 is a waveform chart of each part of the circuit of FIG. 3; [Explanation of symbols] 1 AGC amplifier 2 Signal distributor 3 Detection circuit 4 Capacitance element 5 Signal distribution circuit 6 level detection circuit 7 pulse generation circuit 8,10 switch circuit 9 Power supply circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-108206 (JP, A) JP-A-59-128807 (JP, A) JP-A-51-120721 (JP, U) (58) Investigation Field (Int.Cl. ⁷ , DB name) H03G 1/00-3/18 H03G 3/20-3/34

Claims (1)

(57) [Claim 1] An input received from a radio wave is amplified by an AGC amplifier, a part of the output is extracted and detected, a capacitor is charged, and a terminal voltage of the capacitor is set to the AGC. An automatic gain control circuit that obtains a substantially constant and stable output by controlling the gain as a control DC voltage of an amplifier. In order to increase the response speed to a burst-like reception input, the reception input is divided into two. A signal distribution circuit for distributing and inputting one output to the AGC amplifier; a level detection circuit for receiving the other output of the signal distribution circuit and outputting a signal indicating signal reception when the output is larger than a predetermined threshold value; a pulse generating circuit which outputs a short pulse in synchronization with the rising time point and a trailing time of the signal from the circuit, control linear control DC voltage of the same polarity of the AGC amplifier
Power supply circuit that generates a predetermined DC voltage larger than the current voltage
And the short- circuit synchronized at the time of rising from the pulse generation circuit.
A first switch circuit for the plant <br/> constant DC voltage from the power supply circuit to which the gate is applied to the capacitive element by the time pulse, the synchronized with the falling edge from the pulse generating circuit
The charging voltage of the capacitive element is changed by a short pulse to the resistance element.
An automatic gain control circuit, comprising: a second switch circuit for causing a rapid discharge through the second switch circuit.