JP3505481B2 - Instruction processing unit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction processing device, and more particularly to an instruction processing device having a high-speed emulation function.

[0002]

2. Description of the Related Art FIG. 7 shows an example of a conventional instruction processing device. In such an instruction processing device, an instruction read device converts an instruction read from an external storage device (main memory) into an internal instruction by an instruction translation device, and an internal instruction processing device performs various calculations and memory space. The processing position is moved, and the information reading / writing device reads / writes data relating to the execution of the command. At this time, in the internal instruction processing device, since the instruction is read and executed based on a single instruction form, the instruction form placed in the memory differs for each internal instruction processing device. For this reason,
When executing programs of processors having different instruction forms, it is common to use means called soft emulation that imitates the processing structure inside another instruction processing device by means of logical processing means (software). There is.

Regarding emulation, Japanese Patent Laid-Open No. 6-
Japanese Patent Publication No. 83615 discloses a technique in which an instruction conversion circuit is provided to support a plurality of instruction systems.

Further, in Japanese Laid-Open Patent Publication No. 7-181844, an instruction which has been conventionally executed as an exception process in a part where an instruction is not defined in a certain instruction system is internally processed by using a variable configuration circuit (FPGA). Combine instructions,
A technique is disclosed in which the instruction system can be expanded by a circuit that constitutes an arbitrary instruction.

Further, in Japanese Laid-Open Patent Publication No. 11-306015, the bit length of an instruction is changed according to the appearance frequency of the instruction of a certain program, and a short bit is assigned to an instruction having a high appearance frequency, and a variable configuration circuit (FPGA) is used. ) Is used to convert one instruction system into another original instruction system and place it in memory, and at the time of execution, restore the original instruction and process it to reduce the capacity of the instruction memory. It is disclosed.

Further, Japanese Patent Application Laid-Open No. 2000-20305 discloses a technique in which an instruction processing apparatus having a specific instruction system can arbitrarily change the combination of each instruction to construct an instruction system arbitrarily.

Further, Japanese Patent Laid-Open No. 2000-29508 discloses a technique capable of arbitrarily constructing addition and modification of instructions or modification of instruction order by a variable configuration circuit (FPGA) in order to cope with a change in processing procedure in a network protocol. It is disclosed.

Further, a method is known in which the instruction conversion circuit unit is logically implemented by software to realize processing of a plurality of different instruction systems.

[0009]

However, if a program dedicated to each instruction processing device is developed like the conventional instruction processing device, it is necessary to develop the logic application processing means (software). Development costs will increase.
Further, as a result of the software emulation being imitated by the logical processing means, the processing speed cannot be reduced as compared with the case where the program is directly executed by the physical circuit.

In Japanese Patent Laid-Open No. 6-83615, a physical instruction conversion circuit is required for each instruction system, and the emulation mode is set by a program. There is a problem that the circuit scale becomes large because a plurality of conversion circuits are required for the number of instruction systems to be emulated.

Further, JP-A-7-181844, JP-A-11-306015, and JP-A-2000-203.
No. 05 and Japanese Patent Laid-Open No. 2000-29508 are intended to extend, change, or combine an existing instruction system, and it is impossible to input a program of another instruction system. .

From the above, the above-mentioned prior art has the following problems.

(A) Since the position of the information designating the instruction length on the instruction composed of multi-bit information differs depending on the instruction system, the reading of the instruction is not successful.

(B) Due to the problem of (a) above, there is a problem in changing from the internal instruction processing device to the program counter.

(C) Since the position of the information designating the operation method on the instruction composed of multi-bit information differs depending on the instruction system, the execution of the instruction is not successful.

(D) Due to the problem of (c) above, a problem occurs in the instruction from the internal instruction processing unit to the numerical logic operation circuit and the like.

(E) Since the position of the information designating the access destination on the instruction composed of multi-bit information differs depending on the instruction system, the data reading is not successful.

(E) With the problem of (e), there is a problem in changing from the internal instruction processing device to the stack pointer or the like.

(G) Since the bit structure and byte structure of the data differ depending on the instruction system, the data reading is not successful.

(H) Since the emulation program is switched for each different instruction system, it is not efficient.

In view of the above various problems, an object of the present invention is to emulate (mimic) a plurality of types of processing in an instruction processing device by arbitrarily changing an emulation circuit physically configured. An object of the present invention is to provide an instruction processing device which implements efficient management of the device and reduction of the circuit scale by implementing a plurality of types of functions in one circuit.

[0022]

The present invention employs the following means in order to solve the above problems.

The first means reads at least the instruction stored in the storage means by the instruction reading means, converts the read instruction into an internal instruction by the instruction translation means, and converts the internal instruction into the internal instruction by the internal instruction processing means. In the instruction processing device that performs various calculations and moves the processing position in the memory space based on the instruction reading means, the circuit configuration of the instruction reading means can be changed according to the instruction system of the instruction to be read. It is characterized by

[0024]

[0025]

The second means comprises, in the first means, a mimicking information storage means for storing information relating to a circuit configuration changed according to the command system of each of the means, and each of the means includes a circuit configuration. At the time of change, the change is made based on the circuit configuration information stored in the imitation information storage means.

[0027]

[0028]

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing the configuration of the instruction processing device according to this embodiment.

In the figure, 1 is an instruction processing apparatus main body, and 1 is
Reference numeral 1 processes an internal instruction (microcode), and includes a general register (not shown), a numerical operation circuit, a stack pointer,
An internal command processing device that executes information processing by instructing or setting a data pointer, a configuration changeable command reading device 13, an information reading device 14, a storage state management device 15, etc., which will be described later, and 12 will be described later according to a program counter. External storage device (main memory) 2 and high-speed internal storage device 16
The instruction translation device (instruction decoder) 13 for translating the external instruction read from the instruction into the internal instruction, 13 identifies the instruction system of the instruction to be currently executed by a program or the like in advance. ,
The circuit configuration can be changed, and a configuration changeable instruction reading device for reading an external instruction from the external storage device (main memory) 2 or the high-speed internal storage device 16 according to a program counter, and 14 for an external storage device (main An information reading / writing device for reading / writing data from a memory 2 or the like, and 15 indicates, from the external storage device (main memory) 2 or the like, where to read data in executing an instruction in the internal instruction processing device 11 according to the internal instruction processing device 11. The storage state management device 16 is a high-speed internal storage device 16 which internally stores an external command for speeding up the processing, and 2 is an external storage device (main memory) in which external commands and the like are stored.

The operation of the instruction processing device of this embodiment will be described below.

An external instruction is read from the external storage device (main memory) 2 or the high-speed internal storage device 16 by the reconfigurable instruction reading device 13, and the read external instruction is converted into an internal instruction by the instruction translation device 12. The internal instruction processing unit 11 performs various calculations and moves processing positions in the memory space. Here, the configuration changeable instruction reading device 13
Perform instruction processing with different instruction systems, for example, an instruction in a certain instruction system A has a 32-bit length, and the upper 2 bits indicate the length of information accompanying the instruction to be read. It is assumed that an instruction in another instruction system B has a length of 8 bits, and the upper 1 bit thereof indicates the presence or absence of accompanying information following the instruction. At this time,
The circuit configuration of the configuration changeable instruction reading device 13 is changed by specifying in advance by a program or the like what kind of instruction system the instruction currently being executed is. At this time, the processing in the instruction translation device 12 may be executed by software including a translation dedicated instruction and the like. As a result, the internal instruction processing device 11 follows the instruction system read from the external storage device (main memory) 2 and the like, and if the instruction is the instruction system A, inspects the upper 2 bits in 32 bit units and reads out the continuous information. , If the instruction is the instruction system B, the upper 1 bit is inspected in units of 8 bits, the information to be continued is read out, and the value for updating the program counter is presented to the instruction translation device 12 in accordance with the read instruction length. .

At this time, regardless of the instruction length, a non-technical technique may be used according to the instruction system that specifies the number of bits and the number of bytes of the information to be read. Further, by saving the information of various registers indicating the position in the memory space and the like for each instruction system when the process is switched, it is possible to prevent a difference in the position in the memory in the processing of a branch instruction or the like.

As described above, according to the invention of this embodiment, emulation can be performed quickly by arbitrarily changing the reconfigurable instruction reading device 13 physically configured for a plurality of types of processing in the instruction processing device. be able to.
Further, even if the position of the information designating the instruction length on the instruction composed of multi-bit information differs depending on the instruction system, the instruction can be read out smoothly, and it is composed of multi-bit information. Even if the position of the information designating the operation method on the instruction differs depending on the instruction system, the instruction can be executed well. Further, even if the position of the information for designating the access destination on the instruction, which is composed of multi-bit information, differs depending on the instruction system, the data can be read well.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 2 is a block diagram showing the configuration of the instruction processing device according to this embodiment.

In the figure, reference numeral 17 is an instruction reading device for reading an external instruction from the external storage device (main memory) 2 or high-speed internal storage device 16 according to the program counter, and 18 is an instruction system for the instruction to be executed at present. Is specified in advance by a program or the like, the circuit configuration can be changed, and a reconfigurable instruction translation device (instruction decoder) that translates the read external instruction into an internal instruction according to a program counter Is. Since other configurations correspond to the configurations of the same reference numerals shown in FIG. 1, description thereof will be omitted.

The operation of the instruction processing device of this embodiment will be described below.

The external instruction read from the external storage device (main memory) 2 or the high-speed internal storage device 16 by the instruction reading device 17 is converted into an internal instruction by the reconfigurable instruction translation device 18, and the internal instruction processing device 11 In, various calculations and movement of processing positions in the memory space are performed. Here, when the reconfigurable instruction translation device 18 performs instruction processing with different instruction systems, for example, an instruction in a certain instruction system A is an addition instruction consisting of 0xF10000AA,
Further, it is assumed that the instruction in the instruction system B is an addition instruction composed of 0xF1. On the other hand, it is assumed that the internal instruction in the internal instruction processing device 11 is 0xFF10. At this time, the reconfigurable instruction translation device 18 changes the structure of the reconfigurable instruction translation device 18 to the instruction system A or the instruction system B in advance, depending on which instruction system is the information to be executed by the current instruction. Set to the corresponding configuration. As a result, when the read instruction is set to the instruction system A, the addition instruction 0xF10000AA is converted to 0xFF10, and when the read instruction system B is set, the addition 0xF1 is set to 0xFF10. Converted and executed. As a result, the reconfigurable instruction translation device 18 instructs the internal instruction processing device 11 so that the program counter advances by 4 bytes in the case of the instruction system A, and the program counter advances by 1 byte in the case of the instruction system B. Translate into an order to issue.

The instructions for changing the stack pointer and the data pointer are also subjected to the same processing and appropriately changed. Further, the other instructions are also appropriately changed. The instructions may be read by software including read-only instructions.

Thus, according to the invention of this embodiment,
By configuring the instruction translation device 18 with a reconfigurable physical circuit, it becomes possible to perform emulation at a higher speed than processing by software. Further, even if the position of the information designating the instruction length on the instruction composed of multi-bit information is different depending on the instruction system, there is no problem in changing from the internal instruction execution device to the program counter. Further, even if the position of the information designating the operation method on the instruction composed of multi-bit information differs depending on the instruction system, there is no problem in the instruction from the internal instruction processing device to the numerical logic operation circuit or the like. Does not happen. Further, even if the position of the information designating the access destination on the instruction composed of multi-bit information differs depending on the instruction system, there is no problem in changing from the internal instruction processing device to the stack pointer or the like.

Next, a third embodiment of the present invention will be described with reference to FIG.

FIG. 3 is a block diagram showing the configuration of the instruction processing device according to this embodiment.

In the figure, reference numeral 19 indicates a circuit configuration changeable by specifying in advance by a program or the like what kind of instruction system the instruction to be executed at present is a data pointer or the like. The configuration changeable information reading / writing apparatus reads / writes data from / to the external storage device (main memory) 2 or the like. The other configurations correspond to the configurations of the same reference numerals shown in FIGS. 1 and 2, and the description thereof will be omitted.

Configuration changeable information reading device 1 of this embodiment
9 is composed of a reconfigurable physical circuit so that when the read instruction is executed, the data structure on the memory such as the external storage device (main memory) 2 can be dealt with even if the data structure differs depending on the processor. . For example, even if there is a difference in data structure with different meanings, such as big endian or little endian, in which the high-order byte on a memory address indicates a large value or a small value, the target instruction system is designed to handle these differences. It is realized by setting in the configuration changeable information reading device 19 which configuration should read information. in this case,
Instructions may be read and translated by software including read-only instructions and translation-only instructions. Further, the information stored in the internal high-speed storage device 16 can be expected to have a processing speed by having a data structure that can be easily processed internally.

Thus, according to the invention of this embodiment,
By arbitrarily setting the information reading / writing device 19 for reading information from the external storage device (main memory) 2 or the like using a reconfigurable physical circuit, it is possible to perform high-speed emulation by software. Further, even if the bit structure or byte structure of the data is different for each instruction system, the data can be properly read.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

FIG. 4 is a block diagram showing the configuration of the instruction processing device according to this embodiment.

In the figure, 20 is a variable instruction translation device consisting of a plurality of physical circuits having different instruction translation functions depending on the instruction system with high frequency of appearance, and 21 is a variable instruction translation function depending on the instruction system with high frequency of occurrence. A variable instruction reading device including a plurality of physical circuits included therein, and a variable information reading device 22 including a plurality of physical circuits including an information reading / writing function that differs depending on an instruction system that frequently appears. Note that the other configurations correspond to the configurations of the same reference numerals shown in FIG.

Thus, according to the invention of this embodiment,
In the first, second, and third embodiments described above, the command system of each of the configuration changeable instruction reading device 13, the configuration changeable instruction translation device 18, and the configuration changeable instruction reading device 19 changes. On the other hand, in the present embodiment, a predetermined physical unit is selected from the devices 20, 21 and 22 each including a plurality of physical circuits having respective functions for each instruction system having a high appearance frequency. Since it is only necessary to select a circuit, it is possible to reduce the switching processing time required for switching the emulation program for each different instruction system. The appearance frequency can be observed by counting the occupied range of the source code in the memory space, the number of instructions processed by the instruction system within 1 second, and the like.

Next, a fifth embodiment of the present invention will be described with reference to FIG.

FIG. 5 is a block diagram showing the configuration of the instruction processing device according to this embodiment.

In the figure, reference numeral 23 also includes information for judging which instruction system is suitable for reading an instruction from the current memory space in the management information, and is also used for executing the instruction in the internal instruction processing unit 11. It is a storage state management device that instructs where to read necessary instructions and data from the external storage device (main memory) 2 or the like. Note that the other configurations correspond to the configurations of the same reference numerals shown in FIG.

In the invention of this embodiment, unlike the configuration change in each device of the other embodiments described above designated by the program, the appearance frequency is based on the management information stored in the storage state management device 23. The variable instruction translation device 20, the variable instruction reading device 21, and the variable information reading device 22 which are composed of a plurality of switchable and selectable physical circuits provided for each high command system. By configuring the storage state management device 23 in this way, for example, when allocating the memory space, information indicating the instruction system occupying the memory space is added to the attribute of each divided memory space, and based on that information, When the instructions in each memory space are executed, the configurations of the variable instruction translation device 20, the variable instruction reading device 21, and the variable information reading device 22 are converted,
Switch.

The registration of the physical circuit of the device 20, 21, 22 consisting of a plurality of physical circuits for each instruction system is performed by observing the instruction system registered in the storage state management device 23 and registering the physical circuit frequently. It is possible to improve the processing performance by preferentially configuring the circuit with a wide memory occupation range, a large number of executions, and a long execution time. Further, when the switching of the command system is managed by the operating system and the next command system following the current command system can be predicted, the command system may be registered in advance. The index of which circuit configuration is selected is registered in the storage state management device 23 or the like when the program is copied from the external storage device 2 or the like on the memory, or is a number that specifies the command system in a specific area in the management information. Etc. may be added. Similarly, the variable instruction translation device 20 and the variable reading / writing device 22 can perform the same processing by performing circuit registration as needed in the memory space.

Thus, according to the invention of this embodiment,
It is possible to further reduce the switching processing time required for switching the emulation program for each different instruction system, as compared with the other embodiments.

A sixth embodiment of the present invention will be described with reference to FIG.

FIG. 6 is a block diagram showing the configuration of the instruction processing device according to this embodiment.

In the figure, reference numeral 24 is stored in a high-speed imitation information storage device 27, which will be described later, by specifying in advance what kind of instruction system the instruction to be executed at present by a program or the like. It is possible to change the circuit configuration by emulation information.
The configuration changeable instruction reading device that reads an external instruction from the storage devices 2 and 16, and 25 is a high-speed imitation information storage by specifying in advance by a program etc. what kind of instruction system the instruction to be executed at present is. Device 27
The internal instruction translation device (instruction decoder) 26 for translating an external instruction into an internal instruction, which can change the circuit configuration by emulation (imitation) information stored in, determines which instruction is currently being executed. It is possible to change the circuit configuration by emulation (imitation) information stored in the high-speed imitation information storage device 27 by specifying in advance by a program or the like an instruction of such an instruction system. An information reading device for reading and writing data from the storage device (main memory) 2 and the like, 27 is a configuration changeable command reading device 2
4. A high-speed imitation information storage device for storing emulation (imitation) information composed of different circuit configuration information for each command system of the configuration changeable command translation device 25 and the configuration changeable information reading device 26.

According to the invention of this embodiment, as compared with the case where the emulation (imitation) information related to the circuit configuration information is registered in the physical circuit of each device whose configuration can be changed,
By storing the emulation (imitation) information in the separately provided high-speed imitation information storage device 27, it is possible to reduce the circuit scale, improve the circuit efficiency, and improve the processing speed.

It should be noted that the information necessary for realizing the reconfigurable physical circuit in each device of each of the above-described embodiments is recorded in a storage medium, and the information is registered in the instruction processing device from this storage medium. The instruction processing device of the invention according to the embodiment can be easily realized.

Further, in order to further increase the speed of the instruction processing device, a plurality of general-purpose registers, stack pointers, data pointers, and program counters may be provided as is conventionally done.

[0064]

According to the first aspect of the present invention, emulation can be performed quickly by arbitrarily changing the instruction reading means which is a physical circuit capable of reconfiguring a plurality of types of processing in the instruction processing device. be able to. Also, even if the position of the information designating the instruction length on the instruction composed of multi-bit information differs depending on the instruction system,
Instructions can be read smoothly, and even if the position of the information designating the operation method on the instruction composed of multi-bit information differs depending on the instruction system, the instruction can be executed well. it can. Further, even if the position of the information for designating the access destination on the instruction, which is composed of multi-bit information, differs depending on the instruction system, the data can be read well.

[0065]

[0066]

According to the second aspect of the present invention, the circuit scale can be reduced and the circuit efficiency can be improved by storing the emulation (imitation) information in the separately provided imitation information storage means. While improving the processing speed, it is possible to improve the processing speed.

[0068]

[0069]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an instruction processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an instruction processing device according to a second exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an instruction processing device according to a third exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an instruction processing device according to a fourth exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an instruction processing device according to a fifth exemplary embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an instruction processing device according to a sixth exemplary embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional instruction processing device.

[Explanation of symbols]

1 Command Processing Device Main Body 11 Internal Command Processing Device 12 Command Translation Device (Instruction Decoder) 13 Configurable Command Reading Device 14 Information Reading Device 15 Storage State Management Device 16 External Storage Device (Main Memory) 17 Command Reading Device 18 Configuration Change Possible instruction translation device (instruction decoder) 19 Configuration changeable information reading device 20 Variable instruction translation device 21 Variable instruction reading device 22 Variable information reading device 23 Storage state management device 24 Configuration changeable instruction reading device 25 Configuration changeable instruction translation device ( Instruction decoder) 26 Configurable information reading device 27 High speed imitation information storage device

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Claims (2)

(57) [Claims] 1. At least an instruction stored in a storage means is read by an instruction reading means, the read instruction is converted into an internal instruction by an instruction translation means, and various kinds of internal instructions are processed by an internal instruction processing means based on the internal instruction. In an instruction processing device for performing a calculation or moving a processing position in a memory space, the instruction reading unit is configured such that a circuit configuration of the instruction reading unit can be changed according to an instruction system of the read instruction. A characteristic instruction processing device. 2. The instruction processing device according to claim 1, further comprising imitation information storage means for storing information relating to a circuit configuration changed according to an instruction system of each of the means, wherein each of the means has a circuit configuration. The instruction processing device is characterized in that, at the time of change, the change is made based on the circuit configuration information stored in the imitation information storage means.