JP3500631B2 - Switching power supply - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply device, and more particularly to a switching power supply device capable of reducing electrical stress applied to each element at the time of overload, load short circuit or start-up.

[0002]

2. Description of the Related Art FIG. 19 shows an example of a separately excited flyback type DC-DC converter as a switching power supply device which has been widely used conventionally. The separately excited flyback DC-DC converter shown in FIG. 19 is composed of a rectifying bridge circuit (1c) and an input smoothing capacitor (1d) connected to an AC power supply (1a) via an input filter circuit (1b). DC power supply (1), primary winding (2a) of transformer (2) connected in series to DC power supply (1), and M as a switching element
OS-FET (MOS field effect transistor) (3),
An output rectifying / smoothing circuit (6) comprising a rectifying diode (4) connected to the secondary winding (2b) of the transformer (2) and an output smoothing capacitor (5) and generating a DC output voltage V _OUT , and a DC output An output voltage detection circuit (7) as a voltage detection means for detecting the voltage V _OUT, and a detection signal V _FB from the output voltage detection circuit (7)
DC output voltage V _{OUT of the} output rectifying and smoothing circuit (6)
Control circuit (8) that controls the on / off period of the MOS-FET (3) so that the voltage is substantially constant, and the primary winding (2
a) or a current detecting resistor (9) as current detecting means for detecting the current _ID flowing in the MOS-FET (3) as a negative voltage
A starting resistor (10) as a starting means connected to the rectifying bridge circuit (1c) constituting the DC power supply (1) and supplying driving power to the control circuit (8) at the time of starting, and a transformer (2). 1
A drive winding (2c) electromagnetically coupled to the secondary winding (2a) and the secondary winding (2b), and a rectifying diode (1
1) and driving smoothing capacitor (12) and control circuit
And an auxiliary rectifying / smoothing circuit (13) for outputting a DC voltage V _IN for driving (8). The detection output of the output voltage detection circuit (7) is transmitted to the primary side of the transformer (2) via the light emitting element (14a) and the light receiving element (14b) which constitute the photocoupler (14), and the light receiving element (14b ) And the voltage V _FB generated at the connection point of the series resistor (15) are input to the control circuit (8) as a detection signal from the output voltage detection circuit (7).

The control circuit (8) includes a primary winding (2
a) or a reference voltage (16) as a reference voltage generating means for generating a reference voltage V _RC that defines the maximum current value flowing in the MOS-FET (3), and a negative voltage detected by the current detection resistor (9) Level shift resistors (17,18) that convert the level of
When the voltage level of the detection signal V _OCP of the current detection resistor (9) reaches the level of the reference voltage V _RC of the reference power supply (16), the MOS
-An overcurrent limiting comparator (19) as an overcurrent limiting means for outputting a high voltage (H) level signal V ₁ for turning off the FET (3), and a detection signal V of a current detecting resistor (9) _OCP
Of the detection signal V from the output voltage detection circuit (7)
Current mode control comparator (20) that outputs a high voltage (H) level signal V ₂ when the voltage level of _FB is reached
If an OR gate for outputting a logical sum signal V ₃ of the output signal V ₂ of the output signal V ₁ and current mode control comparator for overcurrent limit comparator (19) (20) (21 ), MOS-FE
A pulse generator (22) that outputs a pulse signal V ₄ each time a fixed time has elapsed since T (3) turned off, and a pulse generator (2
2) The pulse signal V ₄ causes a set state and MOS-FE
A high voltage (H) level ON signal V _{G is} applied to the gate terminal of T (3).
Of the R-S flip-flop (23) which outputs a low voltage (L) level off signal V _G to the gate terminal of the MOS-FET (3) by resetting the logical sum signal V ₃ of the OR gate (21). ) And the starting resistor (10) or auxiliary rectifying and smoothing circuit (13)
Drive DC power is supplied to each of the elements (16 to 23) constituting the control circuit (8) when the DC voltage V _IN from the device reaches the drive voltage V _SRT , and the DC voltage V _IN reaches the stop voltage V _STP. And a control power supply circuit (24) for stopping the supply of the driving DC power to each of the elements (16 to 23) when the voltage drops. As shown in FIG. 20, the control power supply circuit (24) controls the drive voltage V _SRT (18
[V]) and the stop voltage V _STP (10 [V]), and a reference power source (24a) that generates a reference voltage, and a DC voltage V _IN from the starting resistor (10) or the auxiliary rectifying / smoothing circuit (13). Reference power supply (24
Compared with the reference voltage of a), the DC voltage V _IN is the drive voltage V
Hysteresis comparator (24b) that outputs a high voltage (H) level drive signal when reaching _SRT , and outputs a low voltage (L) level stop signal when DC voltage V _IN drops to stop voltage V _STP And the hysteresis comparator (24
A regulator circuit (24c) that is driven by the drive signal from b) or is stopped by a stop signal and that generates a driving DC power of a voltage + V _CC to be supplied to each element (16 to 23) constituting the control circuit (8). Composed of and. The output voltage characteristic of the regulator circuit (24c) and the output current characteristic of the regulator circuit (24c) with respect to the DC voltage V _IN are shown in FIGS. 21 and 22, respectively.

FIGS. 23A to 23D show a MOS-FET (3).
Current I_D, OR gate (21) OR signal V₃, Pal
Pulse signal V of the pulse generator (22)_FourAnd the resistor for current detection (9)
The voltage at the connection point of the resistance (17,18) for level shifting the detection signal
Pressure V_OCPEach waveform of is shown. That is, in FIG. 23 (C)
Pulse signal V of the pulse generator (22) shown_FourIs an RS flip
It is input to the set terminal (S) of the flop (23), and MOS-FE
When T (3) is turned on, as shown in FIG.
Current I flowing through OS-FET (3)_DWhen increases linearly
Both for level shift of detection signal of current detection resistor (9)
Voltage V at the connection point of resistors (17, 18)_OCPIs shown in FIG.
So that it decreases linearly. Level shift resistors (17,18)
Voltage at the connection point of_OCPThe level of the reference voltage of the reference power source (16)
Pressure V_RCBelow the level of
High voltage (H) level signal V from₁Is output
It At this time, the detection signal V from the output voltage detection circuit (7)
_FBThe voltage level of is almost zero as shown in FIG.
Therefore, the current mode control comparator (20) does not work,
Low voltage (L) level signal V₂Is output. others
Therefore, as shown in FIG. 23 (B), a high voltage is applied from the OR gate (21).
Pressure (H) level OR signal V ₃Is output and R-S
It is input to the reset terminal (R) of the flip-flop (23) and the MOS-
The FET (3) is turned off. As a result, MOS-FE
Current I flowing through T (3) _DIs almost zero as shown in FIG.
Becomes A certain time has passed since the MOS-FET (3) was turned off.
Then, the pulse of the pulse generator (22) shown in Fig. 23 (C)
Signal V_FourIs the set terminal of RS flip-flop (23) again
(S) is input and the MOS-FET (3) is turned on again.
It Next, as shown in FIG. 23D, the output voltage detection circuit
Detection signal V from (7)_FBVoltage levels from zero to linear
Reference voltage V of the reference power supply (16)_RCAbove the level of
Then, the current mode control comparator (20) is activated and the
Voltage V at the connection point of bell-shift resistors (17,18)_OCPLevel of
Is the detection signal V from the output voltage detection circuit (7)_FBVoltage level
If it falls below the threshold, the current mode control comparator (20)
Higher voltage (H) level signal V₂Is output. This and
The low voltage (L) level from the overcurrent limiting comparator (19).
Bell signal V₁Is output, so it is shown in Fig. 23 (B).
High-voltage (H) level logical sum from OR gate (21)
Issue V₃Is output and the reset of the RS flip-flop (23) is output.
Input to the input terminal (R) and the MOS-FET (3) turns off.
Become. As described above, the detection from the output voltage detection circuit (7)
Signal V_FBThe voltage level of is the reference voltage V of the reference power supply (16)_RCof
If it is above the level, the comparator for current mode control (2
0) controls the ON period of MOS-FET (3) and outputs
DC output voltage V of rectifying and smoothing circuit (6)_OUTIs held approximately constant
Be done.

Separately-excited flyback type DC-shown in FIG.
The operation of the DC converter is as follows. At startup,
Auxiliary rectification smoothing circuit from DC power supply (1) through starting resistor (10)
A charging current flows through the smoothing capacitor (12) for driving of the path (13),
As shown in FIG. 24 (B), the charging smoothing capacitor (12) is charged.
Electric voltage V_INIs the drive voltage V_SRTReach the control circuit (8)
The control power supply circuit (24) is driven to form the control circuit (8).
Driving DC power is supplied to each of the elements (16 to 23). this
Drive the pulse generator (22), and the pulse generator (2
2) Pulse signal V_FourIs a set of RS flip-flop (23)
Input to the input terminal (S) to enter the set state, and the RS flip
From the flip-flop (23) to the gate terminal of the MOS-FET (3)
ON signal V of high voltage (H) level_GIs added to MOS-F
ET (3) is turned on. At this time, as shown in FIG.
Current I flowing through MOS-FET (3)_DIs linear
As it increases, as shown in Fig. 24 (E), the current detection resistance is increased.
Connection point of resistance (17,18) for level shift of detection signal of anti- (9)
Voltage V at_OCPDecreases linearly. Level shift resistance
The voltage V at the connection point of the anti (17,18)_OCPLevel of reference power (16)
Reference voltage V_RCWhen the level reaches
High voltage (H) level signal V from the palrator (19)₁Output
To be done. On the other hand, the output voltage detection circuit (7) detects
Outgoing signal V_FBThe voltage level of is approximately as shown in Fig. 24 (E).
Since it is zero, is it a comparator for current mode control (20)?
Lower voltage (L) level signal V₂Is output. to this
The OR of the high voltage (H) level from the OR gate (21)
Signal V ₃Is output to reset the RS flip-flop (23).
Input to the input terminal (R) to enter the reset state, and the RS
Gate terminal of the lip-flop (23) to the MOS-FET (3)
Low voltage (L) level off signal V_GIs granted MO
The S-FET (3) is turned off. At this time, FIG. 24 (A)
As shown in, current I flowing in MOS-FET (3) _DIs abbreviated
It will be b. A certain time after the MOS-FET (3) is turned off
When the time passes, the pulse signal V of the pulse generator (22)_FourIs again
Input to the set terminal (S) of RS flip-flop (23)
To the set state, and from the RS flip-flop (23)
High voltage (H) level is applied to the gate terminal of MOS-FET (3)
ON signal V_GIs given and the MOS-FET (3) is turned on again.
It becomes a state. ON / OFF operation of the above MOS-FET (3)
By repeating the above, the output rectifying and smoothing circuit (6) on the secondary side
Current output voltage V_OUTIs straight up as shown in FIG.
And the charging power of the driving smoothing capacitor (12)
Pressure V_INDecreases linearly as shown in FIG. 24 (B),
A voltage proportional to the voltage of the secondary winding (2b) of the transformer (2) is driven.
DC output voltage V because it occurs in the dynamic winding (2c) _OUTRise of
DC voltage V from the auxiliary rectifying and smoothing circuit (13)_INStraight
Rises linearly. Therefore, the control power supply in the control circuit (8)
DC voltage V applied to circuit (24)_INIs shown in FIG.
Stop voltage V_STPAfter dropping to the vicinity, straight again
Go up to. Therefore, after startup, auxiliary rectification
DC voltage V from smoothing circuit (13)_INIn the control circuit (8)
The control power supply circuit (24) is driven. Secondary side output rectification smoothing
DC output voltage V of circuit (6)_OUTOutput voltage
Detection signal V from the detection circuit (7)_FBVoltage is also shown in Fig. 24 (E).
As shown, it linearly rises from 0 [V].

As shown in FIG. 24 (E), the voltage level of the detection signal V _FB from the output voltage detection circuit (7) is the reference power supply (16).
Exceeds the level of the reference voltage V _RC of the level shift resistor (1
The level of the voltage V _OCP at the connection point of (7, 18) is the output voltage detection circuit.
When the voltage level of the detection signal V _FB from (7) is reached, the current mode control comparator (20) outputs a high voltage (H) level signal V ₂ . On the other hand, since the low voltage (L) level signal V ₁ is output from the overcurrent limiting comparator (19), the OR gate (21) outputs a high voltage (H) level logical sum signal V ₃ . It is input to the reset terminal (R) of the RS flip-flop (23) to enter the reset state, and R-
A low voltage (L) level off signal V _G is applied from the S flip-flop (23) to the gate terminal of the MOS-FET (3) to turn off the MOS-FET (3). As a result, FIG.
As shown in 4 (A), the current I _D flowing in the MOS-FET (3)
Is almost zero. At this time, the secondary winding (2
The output current I _OUT flows from b) to the load (not shown) through the output rectifying / smoothing circuit (6) and increases linearly as shown in FIG. 24 (D). Then, as shown in FIG. 24 (C), the DC output voltage V _{OUT of the} secondary side output rectifying / smoothing circuit (6) is a detection voltage determined by various constants of each element constituting the output voltage detecting circuit (7). (For example, set the voltage division ratio of the voltage dividing resistor between the output terminals to R
₂ / (R ₁ + R ₂ ), Zener voltage of Zener diode is V
_{Letting Z} [V] and the voltage between the base and emitter of the NPN transistor be V _BE (about 0.6 to 0.7) [V], {(R ₁ +
When R ₂ ) / R ₂ } × (V _Z + V _BE ) [V]) is reached, the starting state shifts to the normal operating state, and as shown in FIG. The DC voltage V _IN becomes substantially constant, and the DC output voltage V of the secondary side output rectifying and smoothing circuit (6)
_OUT becomes substantially constant as shown in FIG. At this time, as shown in FIG. 24 (E), since the voltage level of the detection signal V _FB from the output voltage detection circuit (7) is high, the voltage V _OCP at the connection point of the level shift resistors (17, 18) changes. The width becomes smaller, and the ON period of the MOS-FET (3) becomes shorter. Therefore, the maximum value of the current I _D flowing through the MOS-FET (3) becomes low as shown in FIG.

When an unillustrated load is overloaded,
24 (D) and (C), the secondary side output current I_OUT
DC output voltage V of the output rectifying and smoothing circuit (6)_OUT
Of the output voltage detection circuit (7).
Outgoing signal V_FBVoltage drops. For this reason, the transformer (2)
The voltage generated in the drive winding (2c) of the
Applied to the control power circuit (24) in the control circuit (8) as shown.
DC voltage V_INIs reduced. Secondary side output current I_OUT
The DC output of the output rectifying and smoothing circuit (6)
Voltage V_OUTFurther decreases, and the output is output as shown in Fig. 24 (E).
Detection signal V from the voltage detection circuit (7)_FBBased on the voltage level of
Reference voltage V of quasi power source (16)_RCBelow the level of
The comparator (20) for controlling the
Then, the overcurrent limiting comparator (19) is operated. level
Voltage V at the connection point of shift resistors (17,18)_OCPBased on
Reference voltage V of quasi power source (16)_RCReaches the level of overcurrent
High voltage (H) level signal from the limiting comparator (19)
V₁Is output and the MOS-FET (3) is turned off.
As shown in FIG. 24 (B), the control power supply circuit in the control circuit (8) is turned on.
DC voltage V applied to line (24)_INIs the stop voltage V_STPUntil
If it falls, the control power circuit (24) will stop operating and control
Of the driving DC power to each element (16 to 23) that constitutes the path (8)
The supply is stopped and the operation of the control circuit (8) is stopped. others
Therefore, as shown in Fig. 24 (C) and (D),
DC output voltage V of line (6)_OUTSuddenly drops to 0 [V]
Along with the secondary side output current I_OUTAlso decreases rapidly to zero
It In the overload state, the secondary side DC output voltage V_OUTIs above
Since it does not rise, the voltage of the drive winding (2c) of the transformer (2) also rises.
Does not rise. Therefore, the control power supply circuit in the control circuit (8)
DC voltage V applied to (24)_INIs the stop voltage V_STPUp to
Then, the DC power supply (1) is used to drive the start resistance (10).
The smoothing capacitor (12) for driving the auxiliary rectification smoothing circuit (13) is charged.
And the driving smoothing capacitor as shown in FIG. 24 (B).
Charge voltage V of (12)_INIs the drive voltage V_SRTControl is reached
The control power supply circuit (24) in the circuit (8) is driven again and the control circuit
Road (8) begins operation. According to the operation of the control circuit (8),
As shown in FIGS. 24C and 24D, the output rectifying / smoothing circuit
DC output voltage V of (6)_OUTAnd the output current I on the secondary side _OUTBut
Along with increasing linearly from zero, the auxiliary rectifying smoothing circuit (1
Voltage V of smoothing capacitor (12) for driving 3)_INIs shown in FIG.
As shown in. For driving auxiliary rectification smoothing circuit (13)
Voltage V of smoothing capacitor (12)_INIs the stop voltage V_STPUp to
When it goes down, the operation of the control circuit (8) stops and
And (D), the DC output of the output rectifying and smoothing circuit (6)
Voltage V_OUTRapidly decreases to 0 [V] and the secondary side
Output current I_OUTAlso decreases rapidly to zero. Therefore,
During load, the smoothing capacitor for driving the auxiliary rectifying and smoothing circuit (13)
Voltage (12) V_INIs the drive voltage V_SRTTo stop voltage V_STPWell
The intermittent oscillation state that the control circuit (8) operates only during the period when
It becomes a state.

[0008]

Other problems of the prior art shown in FIG.
In the excitation type flyback type DC-DC converter, as shown in FIG.
The output characteristics are as shown in. In FIG. 25, the solid line A
DC output voltage V_OUTIn the steady state when is constant
The operating state is shown and the load is not heavier in the section shown by the solid line B.
It shows the operating state at the time of overload. That is, on the solid line B
The operation status in the section shown is the detection signal of the current detection resistor (9).
Issue V_OCPBased on the overcurrent limit comparator (19)
The primary winding (2a) of the transformer (2) or the MOS-FET (3)
Current I_DIndicates that the value is limited to the set value. Tiger
The power P [W] transmitted from the primary side of the sensor (2) to the secondary side is
The oscillation frequency is f [Hz] and the inductance of the transformer (2) is
Let L [H] and the current flowing in the transformer (2) be I [A], P
= (1/2) / f / L / I²Generally known to be represented by the formula
Has been. Therefore, the section indicated by the solid line B is on the secondary side.
Output current I_OUTThe DC output voltage V_OUTIs lowered
Power P transmitted from the primary side to the secondary side of the transformer (2)
Shows a constant power characteristic that is limited to a constant value. Secondary side
Output current I_OUTIs further increased, the DC output voltage V_OUT
Is further reduced. Driving the control circuit (8) during normal operation
The dynamic power is generated in the drive winding (2c) of the transformer (2).
It is obtained by rectifying and smoothing the pressure with the auxiliary rectifying and smoothing circuit (13).
ing. The voltage of the drive winding (2c) and the voltage of the secondary winding (2b)
The output current I on the secondary side is proportional to each other._OUTBut
If it increases, the voltage of the drive winding (2c) will decrease. By this
Directly applied to the control power circuit (24) in the control circuit (8).
Current voltage V_INIs the stop voltage V_STPBelow the control circuit (8)
Operation stops and the secondary side output current I_OUTAnd DC output
Voltage V _OUTAre shown in solid line C in FIG.
It becomes a locus. After that, start resistance (10) from DC power supply (1)
And in the control circuit (8) through the driving smoothing capacitor (12)
Voltage V applied to the control power supply circuit (24) of_INWill drive again
Dynamic voltage V_SRTThe operation of the control circuit (8) is stopped until
Drive voltage V_SRTWhen it reaches, the operation starts again. Since
By repeating the above operation, intermittent vibration of the control circuit (8)
The work is done.

Therefore, the section shown by the solid line B in FIG.
That is, at the time of overload, the output current I _OUT on the secondary side excessively increases, so that the electrical stress applied to the rectifying diode (4) forming the output rectifying and smoothing circuit (6) becomes large, and in the worst case, The rectifier diode (4) was sometimes destroyed.

Therefore, an object of the present invention is to provide a switching power supply device capable of reducing the electrical stress applied to each component on the primary side and the secondary side at the time of overload, short circuit of load, or startup.

[0011]

A switching power supply device according to the present invention comprises a DC power supply (1), a primary winding (2a) of a transformer (2) connected in series with the DC power supply (1), and An output rectifying and smoothing circuit connected to the switching element (3) and the secondary winding (2b) of the transformer (2) and generating a DC output voltage (V _OUT ).
(6) and voltage detection means (7) for detecting the DC output voltage (V _OUT ).
And a control circuit for receiving the detection signal (V _FB ) from the voltage detection means (7) and controlling the on / off period of the switching element (3) so that the DC output voltage (V _OUT ) becomes substantially constant ( 8) and a current detecting means (9) for detecting a current ( _ID ) flowing through the primary winding (2a) of the transformer (2) or the switching element (3). The control circuit (8) has a first reference voltage (V that regulates the maximum current value flowing in the primary winding (2a) or the switching element (3).
_RC ) generating reference voltage generation means (16) and current detection means
The voltage level of the detection signal (V _OCP ) in (9) is the reference voltage generation means.
When the level of the first reference voltage (V _RC ) of (16) is reached, the overcurrent limiting means (1
9) and when the voltage level of the detection signal (V _FB ) of the voltage detection means (7) exceeds the level of the second reference voltage (V _RV ) at the time of overload, load short-circuit or start-up. Voltage level change signal to
The first reference voltage (V _RC ) of the reference voltage generation means (16) by the voltage level detection means (27) that outputs (V _CH ), and the voltage level change signal (V _CH ) of the voltage level detection means (27). Lowering the absolute value level of or the detection signal of the current detection means (9)
A voltage level changing means (28) for increasing the absolute value level of the voltage (V _OCP ).

When the voltage level of the detection signal (V _OCP ) of the current detection means (9) reaches the level of the reference voltage (V _RC ) of the reference voltage generation means (16) at the time of overload, load short-circuit or start-up. The switching element (3) is turned off by the overcurrent limiting means (19), and the primary side current ( _ID ) flowing through the primary winding (2a) of the transformer (2) or the switching element (3) is limited. It At this time, the DC output voltage (V _OUT ) drops and the voltage detection means (7)
When the voltage level of the detection signal (V _FB ) becomes lower than the level of the reference voltage (V _RV ), the voltage level change signal (V _CH ) is output from the voltage level detection means (27). Voltage level detection means (27)
When the voltage level change signal (V _CH ) is output from the voltage level change means (28), the absolute value level of the reference voltage (V _RC ) of the reference voltage generation means (16) decreases or the current detection means
The absolute value level of the voltage of the detection signal (V _OCP ) of (9) rises,
The switching element (3) is turned off with a small primary side current ( _ID ). As a result, the current flowing through the primary winding (2a) side and the secondary winding (2b) side of the transformer (2) at the time of overload, load short-circuit or startup is more strongly limited, so that the primary side The electrical stress applied to the switching element (3), the rectifying element (4) forming the secondary side output rectifying and smoothing circuit (6), and the smoothing capacitor (5) can be reduced.

In the embodiment of the present invention, the starting means (10) which is connected to the DC power source (1) and supplies driving power to the control circuit (8) at the time of starting, and the primary winding of the transformer (2). A drive winding (2c) electromagnetically coupled to (2a) and the secondary winding (2b), and a DC voltage (V _IN ) connected to the drive winding (2c) and driving the control circuit (8) And an auxiliary rectifying / smoothing circuit (13) for outputting. An embodiment in which the present invention is applied to a forward type switching power supply device is provided with a drive power supply circuit which is connected to a DC power supply (1) and supplies drive power to a control circuit (8). The voltage detecting means (7) in the present invention is the secondary winding (2b).
Side or drive winding (2c) side DC voltage is detected as DC output voltage (V _OUT ). Secondary winding (2b) of transformer (2)
Since a voltage proportional to the voltage of is generated in the drive winding (2c),
The DC voltage (V _IN ) generated on the drive winding (2c) side is the secondary winding (2
It is proportional to the DC output voltage (V _OUT ) generated on the b) side. Therefore, the amount of change in the DC output voltage (V _OUT ) on the secondary winding (2b) side can be detected on the drive winding (2c) side, so that the circuit configuration on the secondary side can be simplified.

[0014] In another embodiment of the present invention, delay means for receiving the output signal (V _CH) from the voltage level detection means (27), and outputs an output signal (V _CH) after a predetermined time has elapsed ( 33)
Equipped with. When the voltage on the secondary side instantaneously drops due to noise or the like, the voltage level changing means (28) does not operate, so that malfunction of the overcurrent limiting means (19) can be prevented. Also,
In the embodiment provided with the output signal prohibiting means (34) for prohibiting the output of the output signal (V _CH ) of the voltage level detecting means (27) only at the time of starting, the current limiting of the overcurrent limiting means (19) at the time of starting is performed. Since the amount is relaxed, a large current can be made to flow to the primary side and the secondary side only at the time of startup, and the switching power supply device can be quickly started.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments in which a switching power supply device according to the present invention is applied to a separately excited flyback type DC-DC converter will be described below with reference to FIGS. However, in these drawings, portions substantially the same as the portions shown in FIGS. 19 to 25 are denoted by the same reference numerals, and description thereof will be omitted.

The separately excited flyback type DC-DC converter according to the embodiment of the present invention is, as shown in FIG. 1, a DC power source (1) and a transformer connected in series to the DC power source (1). Output rectification that is connected to the primary winding (2a) of (2) and the MOS-FET (3) as a switching element, and the secondary winding (2b) of the transformer (2) and that generates a DC output voltage V _OUT a smoothing circuit (6), voltage detection means (output voltage detection circuit) for detecting a DC output voltage V _OUT and (7), receives the detection signal V _FB from the voltage detecting means (7) and the DC output voltage V _OUT ON-signal for controlling the ON-OFF period of the MOS-FET (3) or an ON-signal for generating an OFF signal V _{G so} that the level of V is almost constant.
A control circuit (8) having an off signal generating means (25) and a current detecting means for detecting a current _ID flowing through the primary winding (2a) of the transformer (2) or the MOS-FET (3) as a negative voltage ( Current detection resistor) (9), starting means (starting resistor) (10) connected to the DC power supply (1) and supplying driving power to the control circuit (8) at startup, and the transformer (2) Secondary winding (2a) and secondary winding
Drive winding (2c) electromagnetically coupled to (2b) and drive winding (2c)
And an auxiliary rectifying / smoothing circuit (13) that outputs a DC voltage V _IN that drives the control circuit (8). The control circuit (8) is the primary winding (2a) of the transformer (2) or MOS-FE.
The reference power source (16) as a reference voltage generating means for generating a reference voltage V _RC that defines the maximum current value flowing through T (3) and the voltage level of the detection signal V _{O CP} of the current detecting means (9) are the reference power source. (1
When the level of the reference voltage V _RC of 6) is reached, MOS-FE
The DC voltage V _IN from the overcurrent limiting means (overcurrent limiting comparator) (19) for turning off T (3) and the starting means (10) or the auxiliary rectifying / smoothing circuit (13) is the drive voltage V _{SR T.} Drive DC power to each element in the control circuit (8) is reached, and when the DC voltage V _IN drops to the stop voltage V _STP , drive DC power is supplied to each element. Control power supply circuit (24) for stopping the voltage and the detection signal V _{FB of the} voltage detection means (7)
Of the voltage level detection means (comparator for voltage level detection) (27) that outputs the voltage level change signal V _CH when the voltage level of the voltage level of the reference voltage V _RV is lower than the level of the reference voltage _VRV , and the voltage of the voltage level detection means (27). The level change signal V _CH lowers the absolute value level of the reference voltage V _RC of the reference power source (16) (solid line part) or raises the absolute value level of the voltage of the detection signal V _OCP of the current detecting means (9) ( And a voltage level changing means (voltage level changing circuit) (28).

Separately excited flyback type DC-D shown in FIG.
The detailed circuit configuration of the C converter is shown in FIG. That is, the separately excited flyback DC-DC converter according to the embodiment of the present invention shown in FIG. 2 has a reference voltage V that defines a voltage level for detecting the presence or absence of the detection signal V _FB of the output voltage detection circuit (7). Reference power supply (26) that generates _RV and output voltage detection circuit
Voltage level detecting means for outputting a voltage level change signal V _CH of high voltage (H) level when the voltage level of the detection signal V _FB of (7) becomes equal to or lower than the level of the reference voltage V _RV of the reference power supply (26) As a voltage level detecting comparator (27) and a voltage level changing means for decreasing the absolute value level of the reference voltage V _RC of the reference power source (16) by the voltage level changing signal V _CH of the voltage level detecting comparator (27). 19 in that the voltage level changing circuit (28) and the voltage level changing circuit (28) are provided in the control circuit (8), which is different from the conventional separately excited flyback type DC-DC converter shown in FIG. The current mode control comparator (2
0), the OR gate (21), the pulse generator (22) and the RS flip-flop (23) constitute the on / off signal generating means (25) shown in FIG. In addition, the level of the voltage V _OCP at the connection point of the level shift resistors (17, 18) shown in FIG. 2 is 0 [V] before the activation, and the current I flowing through the MOS-FET (3) after the activation.
Each resistance (17,18) so that it becomes 1.5 [V] when _D is zero.
It is set by appropriately selecting the resistance value of. Other configurations are the conventional separately-excited flyback type D shown in FIG.
It is the same as the C-DC converter. The absolute value level of the reference voltages V _RCL and V _RCH (FIG. 3) output from the reference power source (16) through the voltage level changing circuit (28) in the case shown in FIG. The level of the voltage V _OCP (Fig. 4 (E)) at the connection point of the level shift resistors (17, 18) when the current _ID (Fig. 4 (A)) flowing through (3) is zero (1.5 [ V])
And the reference voltage V output from the voltage level changing circuit (28)
_It is the difference between the _RCL and _VRCH levels. By the way, transformer (2)
Current I _D flowing in the primary winding (2a) or MOS-FET (3) of
When the voltage is detected as a positive voltage by the current detection resistor (9) (FIG. 15), the absolute value levels of the reference voltages V _RCL and V _RCH output from the reference power supply (16) through the voltage level changing circuit (28) Is the level itself of the reference voltages _VRCL and _VRCH output from the voltage level changing circuit (28).

As shown in FIG. 3, the voltage level changing circuit (28) has a voltage dividing resistor (29) having one end connected to the positive (+) side of the reference power source (16) and a voltage dividing resistor (29). The other end of the reference voltage (16)
Voltage dividing resistor (30) and NP connected in series with (-) side
N-transistor (31) and comparator for voltage level detection
The inverter (32) is connected between the output terminal of (27) and the base terminal of the NPN transistor (31). Therefore, when the voltage level change signal V _CH output from the voltage level detection comparator (27) is at a low (L) level, the NPN transistor (31) is turned on, and the voltage dividing resistor ( Lower reference voltage V from the voltage dividing point of 29, 30)
Generates _RCL . Further, when the voltage level of the voltage level change signal V _CH is high (H) level, the NPN transistor (3
Since 1) is turned off, the reference voltage V _RCH having a high value is generated from the voltage _dividing point of the voltage dividing resistor (29, 30). Here, the low reference voltage V _RCL is 0.6 [V] and the high reference voltage V _RCL is
Reference voltage V of reference power supply (16) so that _RCH becomes 1.0 [V]
The value of _RC and the resistance value of the voltage dividing resistors (29, 30) are appropriately selected. Therefore, when the voltage level change signal V _CH of the voltage level detection comparator (27) is at a high (H) level, from the voltage dividing point of the voltage dividing resistance (29, 30) of the voltage level changing circuit (28). The absolute value level of the output reference voltage V _RCH is 1.
5 [V] -1.0 [V] = 0.5 [V], and when the voltage level of the voltage level change signal _VCH is a low (L) level, the voltage dividing resistor (28) of the voltage level change circuit (28) ( The absolute value level of the reference voltage V _RCL output from the voltage dividing point of (29, 30) is 1.5 [V] -0.6.
[V] = 0.9 [V]. The reference voltage V _RV of the reference power source (26) is set to about 0.1 to 0.5 [V].

Next, the separately excited flyback type D shown in FIG.
The operation of the C-DC converter will be described with reference to FIGS.
It At startup, from the DC power supply (1) through the startup resistor (10)
Used for the smoothing capacitor (12) for driving the auxiliary rectifying and smoothing circuit (13).
An electric current flows, and as shown in FIG.
Charger voltage V of sensor (12)_INAt time t₀Drive voltage V
_SRTControl power circuit (24) in the control circuit (8)
Be moved. As a result, each element that constitutes the control circuit (8)
DC power for driving is supplied to (16 to 23), as shown in FIG.
The voltage V at the connection point of the level shift resistors (17, 18)_OCP
Changes from 0 [V] to 1.5 [V]. At this time, output voltage detection
Detection signal V of output circuit (7)_FBThe voltage level of the reference power supply (26)
Reference voltage V_RVSince it is almost 0 [V] below the level of
A high voltage (H) level is output from the pressure level detection comparator (27).
Voltage level change signal V_CHIs output and is shown in Fig. 4 (E).
As the voltage level change circuit (28) makes a reference of 1.0 [V]
Voltage V_RCHIs output. Supplied from the control power circuit (24)
The pulse generator (22) is driven by the driving DC power.
Pulse signal V of the pulse generator (22)_FourIs an RS flip
Input to the set terminal (S) of the flop (23) to set state
Then, from the RS flip-flop (23) to the MOS-FE
ON signal V of high voltage (H) level at the gate terminal of T (3)_G
Is added to turn on the MOS-FET (3). this
At this time, as shown in FIG. 4 (A), the current flows to the MOS-FET (3).
Current I_DIncreases linearly, as shown in Fig. 4 (E).
Resistance of the detection signal of the current detection resistor (9) for level shifting.
Voltage V at the connection point of anti- (17,18)_OCPDecreases linearly.
Voltage V at the connection point of the level shift resistors (17, 18)_OCPLevel
Is the reference voltage V of the voltage level change circuit (28)_RCHLevel of
Is reached, the high current from the overcurrent limiting comparator (19)
Pressure (H) level signal V₁Is output. On the other hand, at startup
Detection signal V from output voltage detection circuit (7)_FBVoltage level
Is approximately 0 [V] as shown in FIG.
Of low voltage (L) level from the comparator (20)
Signal V₂Is output. This allows the overcurrent limiting
High voltage (H) level OR signal V from the palletizer (19)
₃Is output from the OR gate (21), and the RS flip-flop is
Input to the reset terminal (R) of the
, R-S flip-flop (23) to MOS-FET
Off signal V of low voltage (L) level at the gate terminal of (3)_GBut
When applied, the MOS-FET (3) is turned off. This and
The current flowing in the MOS-FET (3) as shown in FIG.
Flow I _DIs almost zero. Is the MOS-FET (3) off?
A certain time (10 [μs] to 50 [μs]) elapses
And the pulse signal V of the pulse generator (22)_FourIs R-S free again
Set to the set terminal (S) of the flip-flop (23).
Then, the RS flip-flop (23) is turned on and the MOS-F is turned on.
High voltage (H) level ON signal at the gate terminal of ET (3)
V_GIs added and the MOS-FET (3) is turned on again.
It

By repeating the on / off operation of the MOS-FET (3), the DC output voltage V _{OUT of the} secondary side output rectifying / smoothing circuit (6) is linearly changed as shown in FIG. 4 (C). To rise. Along with this, the charging voltage V _IN of the driving smoothing capacitor (12) decreases linearly as shown in FIG. 4 (B).
Since a voltage proportional to the voltage of the secondary winding (2b) of the transformer (2) is generated in the drive winding (2c), the direct current from the auxiliary rectifying / smoothing circuit (13) increases as the direct current output voltage V _OUT increases. The voltage V _IN rises linearly. Therefore, the DC voltage V _IN applied to the control power supply circuit (24) in the control circuit (8) drops linearly again after it has dropped to around the stop voltage V _{ST P as} shown in FIG. 4 (B). To go. Therefore, after the start-up, the control power supply circuit (24) in the control circuit (8) is driven by the DC voltage V _IN from the auxiliary rectifying / smoothing circuit (13). As the DC output voltage V _OUT of the secondary side output rectifying / smoothing circuit (6) rises, the voltage of the detection signal V _FB from the output voltage detecting circuit (7) also becomes 0 [as shown in FIG. 4 (E). V] and then becomes higher than the level of the reference voltage V _RV of the reference power supply (26) at time t ₁ , the voltage level detection signal V of the low voltage (L) level is output from the voltage level detection comparator (27). _CH is output. Thus, V _{RC L} = 0 from V _RCH = 1.0 [V] so that the reference voltage output from the voltage level changing circuit (28) shown in FIG. 4 (E).
It is switched to 6 [V].

Further, as shown in FIG. 4 (E), output voltage detection
Detection signal V from circuit (7)_FBVoltage level is voltage level
Reference voltage V output from change circuit (28)_RCLThe level of
Exceeded, the voltage V at the connection point of the level shift resistors (17, 18)_OCP
Is the detection signal V from the output voltage detection circuit (7)_FBof
When the voltage level is reached, the comparator for current mode control
High voltage (H) level signal V from (20)₂Is output.
On the other hand, a low voltage is output from the overcurrent limiting comparator (19).
(L) level signal V₁Is output, the current mode control
High voltage (H) level logic from control comparator (20)
Sum signal V₃Is output from the OR gate (21), and R-S flip
Input to the reset terminal (R) of the
Then, the R-S flip-flop (23) turns on the MOS-
Low voltage (L) level off signal to the gate terminal of FET (3)
Issue V_GIs added to turn off the MOS-FET (3).
It As a result, as shown in FIG.
Current I flowing in (3)_DIs almost zero. At this time,
From the secondary winding (2b) of the switch (2) through the output rectifying and smoothing circuit (6)
Output current I to load not shown_OUTFlow, as shown in Fig. 4 (D)
Increase linearly. Time t₂At
As shown in 4 (C), the output rectifying and smoothing circuit (6) on the secondary side
Current output voltage V_OUTAre the elements that make up the output voltage detection circuit (7).
Detection voltage (for example, between output terminals
R is the voltage division ratio of₂/ (R₁+ R₂), Zena Daio
The zener voltage of V_Z[V], NPN transistor base
Voltage between the emitter and emitter is V_BE(About 0.6 to 0.7) [V]
Then, {(R ₁+ R₂) / R₂} × (V_Z+ V_BE) [V])
Then, the startup state shifts to the normal operation state, and the secondary side outputs
DC output voltage V of force rectifying / smoothing circuit (6)_OUTIs shown in Fig. 4 (C)
It becomes almost constant as shown below, and the auxiliary rectification smoothing circuit (13)
DC voltage V_INIs almost constant as shown in FIG. 4 (B).
It At this time, as shown in FIG. 4 (E), the output voltage detection circuit
Detection signal V from (7)_FBThe high voltage level of
Voltage V at the connection point of the resistor (17,18) for shifter_OCPChange width of
It becomes smaller, and the ON period of the MOS-FET (3) becomes shorter.
Therefore, as shown in FIG. 4 (A), the current flows to the MOS-FET (3).
Current I_DThe maximum value of becomes low. The secondary side at this time
The output characteristics are as shown in the solid line A of FIG.
DC output voltage V of line (6)_OUTIs a constant voltage characteristic
It

When the load (not shown) on the secondary side becomes heavy, the output current I _OUT on the secondary side increases and the detection signal from the output voltage detection circuit (7) increases as shown in FIGS. 4 (D) and (E). V
_{The FB} voltage drops. The load not shown becomes heavier,
When the overload condition occurs, as shown in FIGS. 4 (D) and 4 (C), 2
As the output current I _OUT on the secondary side further increases, the DC output voltage V _{OUT of the} output rectifying / smoothing circuit (6) decreases. For this reason,
The voltage generated in the drive winding (2c) of the transformer (2) also drops,
As shown in FIG. 4B, the control power supply circuit (2
The DC voltage V _IN applied to 4) decreases. As shown in FIG. 4 (E), at time t ₃ , the voltage level of the detection signal V _FB from the output voltage detection circuit (7) falls below the level of the reference voltage V _RCL output from the voltage level change circuit (28). Then, the current mode control comparator (20) does not operate, and the overcurrent limiting comparator (19) operates instead. The level of the voltage V _OCP at the connection point of the level shift resistors (17, 18) is the reference voltage V _RCL output from the voltage level changing circuit (28).
When it reaches the level of, the high voltage (H) level signal V ₁ is output from the overcurrent limiting comparator (19), and the MOS-F
ET (3) is turned off. At this time, the output characteristic on the secondary side shown in FIG. 5 shifts from the constant voltage characteristic region shown by the solid line A to the constant power characteristic region shown by the broken line D.

As shown in FIG. 4 (E), when the voltage level of the detection signal V _FB from the output voltage detection circuit (7) becomes equal to or lower than the level of the reference voltage V _RV of the reference power supply (26) at time t ₄ ,
A high voltage (H) level voltage level change signal V _CH is output from the voltage level detection comparator (27), and the reference voltage output from the voltage level change circuit (28) is V _RCL = 0.6.
[V] is switched to V _RCH = 1.0 [V]. As a result, the current limiting amount by the overcurrent limiting comparator (19) increases, and the maximum value of the current I _D flowing in the MOS-FET (3) becomes low as shown in FIG. 4 (A), and the transformer (2) also becomes smaller the output current I _OUT flows in the secondary side, the output characteristics of the secondary side shown in FIG. 5 is reduced to a maximum value I _MX1 suddenly I _MX2 output current I _OUT, constant power indicated by the solid line B Move to the area of characteristics. At this time, as shown in FIG. 4D, the increase in the output current I _OUT on the secondary side reaches a peak, but the output rectifying and smoothing circuit
The DC output voltage V _OUT of (6) rapidly decreases as shown in FIG. 4 (C), and the DC voltage V _IN applied to the control power supply circuit (24) in the control circuit (8) also increases. As shown in FIG. 4 (B), it decreases rapidly.

Thereafter, as shown in FIG. 4B, when the DC voltage V _IN applied to the control power supply circuit (24) in the control circuit (8) drops to the stop voltage V _STP at time t ₅ , the control power supply The operation of the circuit (24) stops, the supply of the driving DC power to the respective elements (16 to 23) forming the control circuit (8) stops, and the operation of the control circuit (8) stops. At this time, as shown in FIG.
As shown in (D), the DC output voltage V _OUT of the output rectifying / smoothing circuit (6) rapidly decreases to 0 [V], and the secondary output current I _OUT also rapidly decreases to zero. The output characteristic on the secondary side shown in FIG. 5 draws a locus returning from the region of the constant power characteristic shown by the solid line B to the origin O along the solid line C. Control circuit
(8) After the DC voltage V _{I N} applied to the control power supply circuit (24) in drops to the stop voltage V _STP, the DC power source (1) by starting resistor (10) auxiliary rectifier smoothing circuit via the ( When the driving smoothing capacitor (12) of 13) is charged and the charging voltage V _IN of the driving smoothing capacitor (12) reaches the driving voltage V _{S RT} at time t ₆ as shown in FIG. 4B, control is performed. The control power supply circuit (24) in the circuit (8) is driven again, and the control circuit (8) starts operating. In the overload state, the DC output voltage V _OUT on the secondary side does not rise, so the voltage of the drive winding (2c) of the transformer (2) also does not rise. Therefore, according to the operation of the control circuit (8), as shown in FIGS. 4C and 4D, the DC output voltage V _OUT and the output current I _{OUT of the} secondary side of the output rectifying / smoothing circuit (6) are zero. As shown in FIG. 4 (B), the voltage V _IN of the driving smoothing capacitor (12) of the auxiliary rectifying / smoothing circuit (13) decreases linearly. At time t ₇ , the auxiliary rectification smoothing circuit (1
The voltage V _IN of the driving smoothing capacitor (12) in 3) is the stop voltage V
_When it decreases to _STP, the operation of the control circuit (8) stops and Fig. 4
As shown in (C) and (D), the DC output voltage V _OUT of the output rectifying / smoothing circuit (6) sharply drops to 0 [V] and 2
The output current I _OUT on the secondary side also rapidly decreases to zero. Therefore, at the time of overload, the control circuit (8) operates intermittently only during the period when the voltage V _IN of the driving smoothing capacitor (12) of the auxiliary rectification smoothing circuit (13) decreases from the driving voltage V _SRT to the stop voltage V _STP. It becomes the oscillation state.

Actually, the change from the maximum point I _MX1 of the constant voltage characteristic region shown by the solid line A in FIG. 5 to the origin O through the constant power characteristic region shown by the solid line B is instantaneous, so that The output characteristic draws a so-called fold-shaped locus as shown in FIG. The output characteristics of the separately excited flyback type DC-DC converter shown in Fig. 2 when the output side of the output rectifying / smoothing circuit (6) is short-circuited are transmitted from the primary side to the secondary side of the transformer (2). Since the generated electric power is more strongly limited, a locus A smaller than the locus B drawn by the output characteristic of the conventional separately-excited flyback type DC-DC converter shown in FIG. Draw.

In this embodiment, when the voltage level of the detection signal V _OCP of the current detection resistor (9) reaches the level of the reference voltage V _RC of the reference power supply (16) at the time of overload, load short-circuit or start-up. , MOS-FE by overcurrent limiting comparator (19)
The T (3) is turned off, and the current _ID flowing through the primary winding (2a) of the transformer (2) or the MOS-FET (3) is limited. At this time, the DC output voltage V _{OUT of} the output rectifying / smoothing circuit (6) decreases, and the voltage level of the detection signal V _FB from the output voltage detection circuit (7) is equal to or lower than the reference voltage V _RV of the reference power supply (26). Then the high voltage from the voltage level detection comparator (27)
The (H) level voltage level change signal V _CH is output, and the reference voltage output from the voltage level change circuit (28) is V _RCL =
The voltage is switched from 0.6 [V] to V _RCH = 1.0 [V]. As a result, the absolute value level of the reference voltage V _RC of the reference power source (16) decreases, so that the MOS-FE can be supplied with a small primary side current I _D.
T (3) is turned off. Therefore, the current I _D flowing on the primary winding (2a) side of the transformer (2) and the current I _OUT flowing on the secondary winding (2b) side of the transformer (2) during overloading, load short-circuiting or starting are more strongly limited. Therefore, it is possible to reduce the electrical stress applied to the rectifying diode (4) and the output smoothing capacitor (5) that form the primary side MOS-FET (3) and the secondary side output rectifying and smoothing circuit (6). it can. Also, since the average input power from the AC power supply (1a) can be suppressed low when the load is short-circuited
Heat generation of the entire DC-DC converter at the time of load short circuit is suppressed, and when applied to an AC adapter, for example, the grade of the flame retardant material can be lowered, and various safety standards can be easily obtained. Furthermore, since it is possible to strongly limit the overcurrent that flows at the time of overload, load short circuit, or start-up, it is possible to realize sharp fold-back output characteristics that were difficult to achieve with the conventional separately excited flyback type DC-DC converter. Is possible.

The above embodiment can be modified. For example, the separately excited flyback type D of the embodiment shown in FIG.
The C-DC converter is a voltage level detection comparator.
Receiving a voltage level change signal V _CH from (27), the voltage level detection comparator shown in FIG. 2 the timer circuit (33) as a delay means for outputting a voltage level change signal V _CH after a predetermined time has elapsed ( It is connected between 27) and the voltage level changing circuit (28). Therefore, the voltage level changing circuit (28) is provided after a certain period of time has elapsed since the voltage level changing signal V _{CH of} the voltage level detecting comparator (27) was output.
When the DC output voltage V _OUT on the secondary side is momentarily lowered due to noise or the like, the voltage level changing circuit (28) does not operate and the overcurrent limiting comparator (19)
Can be prevented from malfunctioning. In the separately-excited flyback DC-DC converter shown in FIG. 8, the constant voltage characteristic region shown by the solid line A in the constant voltage characteristic region shown by the solid line A in FIG. Voltage level change circuit (28) shown by the solid line B via the region of power characteristics
Since the output characteristic returns to the origin O along the solid line C after shifting to the region of constant power characteristic after the operation of, the actual output characteristic draws the locus shown in FIG. By the way, when there is a peak load (overload) state in the printer power supply device or the like, the output characteristic shown in FIG. 25 (the constant power characteristic region shown by the solid line B in FIG. 25 may be used) is desirable. There is.
Therefore, the separately excited flyback type DC-D shown in FIG.
In the C converter, by extending the delay time of the output of the timer circuit (33), the output characteristic shown in FIG. 25 is obtained at the time of peak load, and the output characteristic shown in FIG. 6 is obtained when the peak load state continues for the delay time or longer. Therefore, the invention can be applied to a power supply device for a printer having a peak load state and the safety can be improved.

In the separately excited flyback type DC-DC converter of the embodiment shown in FIG. 11, the voltage level change signal V of the voltage level detecting comparator (27) is generated only at the time of starting.
An output signal prohibiting circuit (34) is provided as an output signal prohibiting means for prohibiting the output of _CH . The output signal inhibit circuit (34)
A one-shot pulse generator (35) that generates a single-shot pulse signal V ₅ when the device is started up, and the output signal V ₂ of the current mode control comparator (20) cause a set state and a high voltage.
(H) level to generate an output signal V _6, the one-shot pulse generator (35) R-S flip-flop for generating a low voltage (L) the output signal V ₆ level chip is reset by a pulse signal V ₅ of ( 36) and comparator for voltage level detection
AN which outputs a logical product signal V ₇ of the voltage level change signal V _{CH of} (27) and the output signal V ₆ of the RS flip-flop (36)
It has a D gate (37).

Separately-excited flyback type DC-shown in FIG.
In the DC converter, the output signal inhibition circuit (34)
The single-shot pulse generator (35)
Loose signal V_FiveIs output, and the RS flip-flop (36)
It is input to the reset terminal (R) to enter the reset state.
Therefore, low voltage (L) level output signal V₆Is output.
On the other hand, the detection signal V of the output voltage detection circuit (7) at startup_FB
The voltage level of is the reference voltage V of the reference power supply (26)_RVBelow the level
Since it is approximately 0 [V] below, the voltage level detection comparator
Voltage level change signal V of high voltage (H) level from
_CHIs output. Low from the RS flip-flop (36)
Output signal V of high voltage (L) level₆And for voltage level detection
High voltage (H) level voltage level from comparator (27)
Change signal V _CHIs input to the AND gate (37) and is low
AND signal V of voltage (L) level₇Is output. AND
Logical product of low voltage (L) level output from the gate (37)
Signal V ₇Voltage level via the inverter (32) shown in FIG.
Base terminal of NPN transistor (31) of circuit change circuit (28)
Is input to the NPN transistor (31) to turn it on.
, The reference voltage of 0.6 [V] from the voltage dividing point of the voltage dividing resistor (29, 30)
V_RCLIs output. After that, from the output voltage detection circuit (7)
Detection signal V_FBThe voltage level of the voltage level change circuit (28)
Reference voltage V output from_RCLBeyond the level of the level
Voltage V at the connection point of shift resistors (17,18)_OCPThe level of
Detection signal V from the force voltage detection circuit (7)_FBTo the voltage level of
Once reached, high from current mode control comparator (20)
Voltage (H) level signal V₂Is output, and RS flip-flop
It is input to the set terminal (S) of the rope (36) and
Output signal V of high voltage (H) level₆Is output
It This clears the function of the output signal inhibit circuit (34).
To be done. Therefore, at start-up,
Since the current limit amount by the palletizer (19) is relaxed, start
Large current can be applied to the primary and secondary sides only at times
Separately-excited flyback DC-DC converter
Can be reliably started.

In each of the embodiments shown in FIGS.
Voltage level change circuit (2
8) High reference voltage V_RCHBy outputting
Reference voltage V of reference power supply (16)_RCLower the absolute level of
However, the reference voltage V of the reference power supply (16) is used instead.
_RCFixed, and the detection signal V of the current detection resistor (9)_OCPVoltage
The absolute value level of may be increased. Figure 12 shows the current detection
Detection signal V of output resistor (9)_OCPWhen changing the voltage level of
An embodiment of a voltage level changing circuit (28) for the case is shown. Figure
The voltage level changing circuit (28) shown in FIG.
A PNP transistor connected in series with both ends of the resistor (17)
It consists of a resistor (38) and a resistor (39).
From the comparator (27) to the base end of the PNP transistor (38)
High voltage (H) level voltage level change signal V_CHWith
When applied, the connection point of the level shift resistors (17, 18)
Voltage V_OCPIncrease the absolute level of. I.e. overload
Comparator for voltage level detection during load, short circuit or start
High voltage (H) level voltage level change signal from the data (27)
V_CHIs output, the PNP transistor (38) turns off.
Connected in parallel with one level shift resistor (17)
Since the resistance (39) that has been
Voltage V at the connection point of the level shift resistors (17, 18)_OCPAbsolute of
Value level increases. This makes the resistance for current detection
Comparator for overcurrent limiting even when the detection voltage of (9) is low
(19) operates, so a small primary current I_DAt MO
The S-FET (3) is turned off. Therefore, in FIG.
In the illustrated embodiment, the overload is the same as in the embodiment shown in FIG.
Primary winding of transformer (2) during loading, load short-circuiting or starting
Current I flowing to (2a) side_DAnd the current flowing to the secondary winding (2b) side
Flow I _OUTIs more strongly restricted, so the primary side MOS-F
ET (3) and output side rectification smoothing circuit (6)
Current diode (4) and output smoothing capacitor (5)
Electrical stress can be reduced.

FIG. 13 shows another embodiment of the voltage level changing circuit (28) for changing the voltage level of the detection signal V _OCP of the current detecting resistor (9). The voltage level changing circuit (28) shown in FIG. 13 includes a voltage dividing resistor (29) connected between the detection potential side of the current detecting resistor (9) and the other level shifting resistor (18), and a voltage dividing resistor (29). A voltage dividing resistor (30) and a PNP transistor (38) connected in series between the connection point of the piezoresistor (29) and the other level shift resistor (18) and the reference potential side of the current detecting resistor (9). ) And the base-emitter resistor (40) connected between the base-emitter terminal of the PNP transistor (38)
And the collector terminal is connected to the base terminal of the PNP transistor (38) through the base resistor (41), and the emitter terminal is connected to the connection point of the current detection resistor (9) and the voltage dividing resistor (29). An NPN transistor (31) whose base terminal is connected to an output terminal of a voltage level detection comparator (27) through a base resistor (42), a level shift Zener diode (43) and an inverter (32), and an NPN transistor. (31)
It is composed of a base-emitter resistor (44) connected between the base-emitter terminal of. When a voltage level change signal V _{CH of} high voltage (H) level is output from the voltage level detection comparator (27) at the time of overload, load short-circuit or start-up, the inverter in the voltage level change circuit (28) (32), it is given to the base terminal of the NPN transistor (31) through the level shift Zener diode (43) and the base resistor (42), and the NPN transistor (31) is turned off. As a result, the PNP transistor (38) is turned off, and the voltage V _{DIV at} the voltage dividing point of the voltage dividing resistors (29, 30) changes to the current detecting resistor (9).
Is equal to the detection potential side voltage. Therefore, the absolute value level of the voltage V _OCP at the connection point of the level shift resistors (17, 18) increases, and the overcurrent limiting comparator (19) operates even if the detection voltage of the current detection resistor (9) is low. Because it works
The MOS-FET (3) is turned off with a small primary current I _D. Therefore, even in the embodiment shown in FIG.
The same effect as that of the embodiment shown in FIG. 2 can be obtained.

The embodiment of the present invention is not limited to the above-mentioned respective embodiments, and various modifications can be made as follows. [1] In each of the above embodiments, the output rectifying / smoothing circuit (6)
The detection signal V _FB of the DC output voltage V _OUT is transmitted from the output voltage detection circuit (7) on the secondary side to the primary side via the light emitting element (14a) and the light receiving element (14b) of the photocoupler (14). As shown in FIG. 14, the output voltage detection circuit (7) and the photocoupler (14) are omitted as shown in FIG. 14, and the control circuit (8) is used instead of the light receiving element (14b) constituting the photocoupler (14). Drive voltage V _STR
The Zener diode (45) having the above Zener voltage V _Z is connected and detected as the detection signal V _FB of the DC output voltage V _OUT of the output rectifying and smoothing circuit (6) on the drive winding (2c) side of the transformer (2). You may. That is, in the embodiment shown in FIG. 14, since a voltage proportional to the voltage of the secondary winding (2b) of the transformer (2) is generated in the drive winding (2c), it is generated in the drive winding (2c) side. DC voltage V _IN is the DC output voltage V generated on the secondary winding (2b) side.
Proportional to _OUT . Therefore, the amount of change in the DC output voltage V _OUT on the secondary winding (2b) side can be detected on the drive winding (2c) side, so that the circuit configuration on the secondary side can be simplified. [2] In each of the above-described embodiments, the current _ID flowing through the primary winding (2a) of the transformer (2) or the MOS-FET (3) is detected as a negative voltage by the current detection resistor (9), Although the voltage V _OCP at the connection point of the level shift resistors (17, 18) is input to the inverting input terminal (-) of the overcurrent limiting comparator (19), as shown in FIG. ) Primary winding (2a)
Alternatively, the current _ID flowing through the MOS-FET (3) is detected as a positive voltage by the current detection resistor (9), and this detection voltage V _OCP is applied to the non-inverting input terminal (+) of the overcurrent limiting comparator (19). You may enter it directly. In this case, the NPN transistor (31) in the voltage level changing circuit (28) is turned off when the voltage level changing signal V _{CH of the} low voltage (L) level is output from the voltage level detecting comparator (27). Voltage dividing resistor (2
A high level reference voltage V _RCH is generated from the voltage _dividing point of (9, 30), and a voltage level change signal V _{CH of a} high voltage (H) level is output from the voltage level detection comparator (27). The NPN transistor (31) in the changing circuit (28) may be turned on to generate the reference voltage _VRCL having a low value from the voltage dividing point of the voltage dividing resistors (29, 30). Therefore, in the embodiment shown in FIG. 15, the level shift resistors (17, 18) shown in FIG. 2 and the inverter (32) shown in FIG. 3 are unnecessary. [3] Instead of the reference power supply (26) and the voltage level detection comparator (27) in each of the above embodiments, an RS flip-flop (46) may be used as shown in FIG.
The RS flip-flop (46) shown in FIG. 16 is set by the output signal V ₁ of the overcurrent limiting comparator (19) and reset by the output signal V ₂ of the current mode control comparator (20). . Therefore, when the voltage level of the detection signal V _FB from the output voltage detection circuit (7) decreases at the time of overload, load short-circuit or start-up, the current mode control comparator (20) does not operate, but the overcurrent limiter does not fail. Since the use comparator (19) operates, the voltage level change circuit (28) can be driven. [4] Instead of the voltage level changing circuit (28) shown in FIG.
The voltage level changing circuit (28) shown in FIG. 17 may be used. The voltage level changing circuit (28) shown in FIG.
A voltage dividing resistor (29, 30) and a resistor (39) connected in series with (16), and an N-channel MOS-FET (47) whose drain and source terminals are connected to both ends of the resistor (39). And voltage level detection comparator (27) and N-channel MOS-F
It is composed of an inverter (32) connected between the gate terminal of ET (47). Therefore, when the low voltage (L) level voltage level change signal V _CH is output from the voltage level detecting comparator 27, the N channel MOS-FET
(47) is turned on, and the reference voltage V _RCL having a low value is output from the voltage dividing point of the voltage dividing resistor (29, 30). Further, when the voltage level change signal V _{CH of the} high voltage (H) level is output from the voltage level detection comparator (27), the N-channel MOS-FET (47) is turned off and the voltage dividing resistor (29, 30)
The reference voltage V _RCH having a high value is output from the voltage _dividing point of. An NPN transistor may be used instead of the N channel MOS-FET (47). On the contrary, instead of the NPN transistor (31) shown in FIG.
-It is also possible to use a FET. [5] Instead of the voltage level changing circuit (28) shown in FIG. 12, the voltage level changing circuit (28) shown in FIG. 18 may be used. The voltage level changing circuit (28) shown in FIG. 18 includes a resistor (39) connected between one level shift resistor (17) and the power supply + V _CC , a source terminal connected to the power supply + V _CC , and a drain. Terminal is a resistor (39) and one level shift resistor
The P-channel MOS-FET (48) is connected to the connection point of (17) and has its gate terminal connected to the output terminal of the voltage level detecting comparator (27). Therefore, when the voltage level change signal V _{CH of} high voltage (H) level is output from the voltage level detection comparator (27) at the time of overload, load short-circuit or start-up, the P channel MOS
-Since the FET (48) is turned off and the resistor (39) is connected in series with one of the level shift resistors (17), the voltage V at the connection point of the level shift resistors (17, 18) The absolute value level of _OCP increases. In addition, P-channel MOS-
A PNP transistor may be used instead of the FET (48). On the contrary, the PNP transistor shown in FIG.
It is also possible to use a P-channel MOS-FET instead of (38). Similarly, instead of the NPN transistor (31) and the PNP transistor (38) shown in FIG. 13, an N channel MOS-FET and a P channel MOS-FE, respectively.
It is also possible to use T. Furthermore, the voltage level changing circuit (28) is provided in FIG. 3, FIG. 12, FIG. 13, FIG.
Besides, various circuit configurations are possible. [6] In each of the above-described embodiments, the mode in which the ON period and the OFF period of the MOS-FET (3) are individually controlled is shown, but general PWM (pulse width modulation) control for controlling the on-duty is shown. A method or a quasi-resonant control (RCC) method in which the MOS-FET (3) is turned on when the discharge of the stored energy of the transformer (2) is completed may be used. [7] Further, the invention is not limited to the separately excited flyback DC-DC converter, and the separately excited forward DC-DC converter including a drive power supply circuit connected to a DC power supply and supplying driving power to the control circuit, The present invention can be applied to other switching power supply devices such as a resonance type DC-DC converter.

[0033]

According to the present invention, the current flowing through the primary winding side and the secondary winding side of the transformer is more strongly restricted at the time of overload, load short-circuit or start-up, and the primary side and the secondary side. Since it is possible to reduce the electrical stress applied to each element, it is possible to use a low-standard, inexpensive switching element or rectifying element, and it is possible to reduce the manufacturing cost.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment in which a switching power supply device according to the present invention is applied to a separately excited flyback type DC-DC converter.

FIG. 2 is an electric circuit diagram showing details of the circuit shown in FIG.

FIG. 3 is an electric circuit diagram showing the internal configuration of the voltage level changing circuit of FIG.

FIG. 4 is a timing chart showing currents and voltages of various parts of the circuit of FIG. 2 from startup to overload.

5 is a graph showing changes in output characteristics of the circuit of FIG.

FIG. 6 is a graph showing actual output characteristics of the circuit of FIG.

FIG. 7 is a graph showing output characteristics of the circuit of FIG. 2 when the output is short-circuited.

FIG. 8 is an electric circuit diagram showing another embodiment of the present invention.

9 is a graph showing changes in output characteristics of the circuit of FIG.

10 is a graph showing actual output characteristics of the circuit of FIG.

FIG. 11 is an electric circuit diagram showing another embodiment of the present invention.

FIG. 12 is an electric circuit diagram showing an embodiment of a voltage level changing circuit for changing the voltage level on the overcurrent detection side.

FIG. 13 is an electric circuit diagram showing a modified embodiment of FIG.

FIG. 14 is an electrical circuit diagram showing a first modified embodiment of the circuit of FIG.

FIG. 15 is an electric circuit diagram showing a second modified embodiment of the circuit of FIG.

16 is an electric circuit diagram showing a third modified embodiment of the circuit of FIG.

FIG. 17 is an electric circuit diagram showing another embodiment of the voltage level changing circuit of FIG.

FIG. 18 is an electric circuit diagram showing another embodiment of the voltage level changing circuit of FIG.

FIG. 19 is an electric circuit diagram showing a conventional separately-excited flyback DC-DC converter.

FIG. 20 is a block circuit diagram showing an internal configuration of a control power supply circuit.

FIG. 21 is a graph showing the output voltage characteristic of the regulator circuit.

FIG. 22 is a graph showing the output current characteristic of the regulator circuit.

FIG. 23 is a timing chart showing the current and voltage of each part in the control circuit.

FIG. 24 is a timing chart showing the current and voltage of each part of the circuit of FIG. 19 from startup to overload.

25 is a graph showing output characteristics of the circuit of FIG.

[Explanation of symbols]

(1) ・ ・ DC power supply, (1a) ・ ・ AC power supply, (1b) ・ ・ Input filter circuit, (1c) ・ ・ Rectification bridge circuit, (1d)
..Input smoothing capacitors, (2) .. Transformers, (2a) ..
・ Primary winding, (2b) ・ ・ Secondary winding, (2c) ・ ・ Drive winding, (3) ・ ・ MOS-FET (switching element),
(4) ・ ・ Rectifying diode, (5) ・ ・ Output smoothing capacitor, (6) ・ ・ Output rectifying / smoothing circuit, (7) ・ ・ Output voltage detection circuit (voltage detection means), (8) ・ ・ Control circuit, (9)
・ Current detection resistance (current detection means), (10) ・ ・ Starting resistance (starting means), (11) ・ ・ Rectifier diode, (12) ・
・ Smoothing capacitor for driving, (13) ・ ・ Auxiliary rectifying / smoothing circuit, (14) ・ ・ Photo coupler, (14a) ・ ・ Light emitting element,
(14b) ・ ・ Photodetector, (15) ・ ・ Series resistance, (16) ・ ・
Reference power supply (reference voltage generation means), (17,18) ・ Level shift resistor, (19) ・ Overcurrent limiting comparator (overcurrent limiting means), (20) ・ Current mode control comparator, ( 21) ・ ・ OR gate, (22) ・ ・ Pulse generator, (23) ・ ・ RS flip-flop, (24) ・ ・
Control power supply circuit, (24a) -reference power supply, (24b) -hysteresis comparator, (24c) -regulator circuit, (25) -on / off signal generating means, (26) -reference power supply, (27) ) ・ ・ Voltage level detection comparator (voltage level detection means), (28) ・ ・ Voltage level change circuit (voltage level change means), (29,30) ・ ・ Voltage resistance,
(31) .. NPN transistor, (32) .. inverter, (3
3) .. timer circuit (delay means), (34) .. output signal prohibition circuit (output signal prohibition means), (35) .. one-shot pulse generator, (36) .. RS flip-flop,
(37) .. AND gate, (38) .. PNP transistor, (39) .. resistance, (40) .. base-emitter resistance, (41) .. base resistance, (42) .. base resistance,
(43) ・ ・ Zener diode for level shift, (44) ・ ・
Base-emitter resistance, (45) -Zener diode, (46) -RS flip-flop, (47) -N
Channel MOS-FET, (48) ... P channel MOS-
FET,

Claims (6)

(57) [Claims] 1. A DC power supply, a primary winding of a transformer and a switching element connected in series to the DC power supply,
An output rectifying / smoothing circuit connected to the secondary winding of the transformer and generating a DC output voltage, a voltage detecting means for detecting the DC output voltage, and a DC output for receiving a detection signal from the voltage detecting means. The control circuit includes a control circuit that controls the on / off period of the switching element so that the voltage is substantially constant, and a current detection unit that detects a current flowing through the primary winding of the transformer or the switching element. Is a reference voltage generating means for generating a first reference voltage that defines a maximum current value flowing in the primary winding or the switching element; and a voltage level of a detection signal of the current detecting means of the reference voltage generating means. A switching power supply device comprising: an overcurrent limiting unit that turns off the switching element when the level of a first reference voltage is reached. When the road is overloaded, short-circuited or started,
When the voltage level of the detection signal of the voltage detecting means exceeds the level of the second reference voltage, the voltage level detecting means for outputting a voltage level changing signal, and the reference voltage by the voltage level changing signal of the voltage level detecting means First of voltage generation means
And a voltage level changing means for decreasing the absolute value level of the reference voltage or increasing the absolute value level of the voltage of the detection signal of the current detecting means. 2. A starter connected to the DC power supply and supplying drive power to the control circuit at start-up, and a drive winding electromagnetically coupled to the primary winding and the secondary winding of the transformer. 2. The switching power supply device according to claim 1, further comprising an auxiliary rectifying / smoothing circuit connected to the drive winding and outputting a DC voltage for driving the control circuit. 3. The switching power supply device according to claim 1, further comprising a drive power supply circuit connected to the DC power supply and supplying drive power to the control circuit. 4. The switching according to claim 1, wherein the voltage detecting unit detects a DC voltage generated on the secondary winding side or the driving winding side as the DC output voltage. Power supply. 5. The switching power supply according to claim 1, further comprising delay means for receiving the output signal from the voltage level detection means and outputting the output signal after a lapse of a fixed time. apparatus. 6. The switching power supply device according to claim 1, further comprising an output signal prohibiting unit that prohibits the output of the output signal of the voltage level detecting unit only at the time of start-up.