JP3500518B2 - Manufacturing method of ultrafine gold alloy wire - Google Patents

Manufacturing method of ultrafine gold alloy wire

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Publication number
JP3500518B2
JP3500518B2 JP22902095A JP22902095A JP3500518B2 JP 3500518 B2 JP3500518 B2 JP 3500518B2 JP 22902095 A JP22902095 A JP 22902095A JP 22902095 A JP22902095 A JP 22902095A JP 3500518 B2 JP3500518 B2 JP 3500518B2
Authority
JP
Japan
Prior art keywords
gold alloy
wire
ingot
ultrafine
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP22902095A
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Japanese (ja)
Other versions
JPH0974113A (en
Inventor
伸 高浦
和彦 安原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Denshi Kogyo KK
Original Assignee
Tanaka Denshi Kogyo KK
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Priority to JP22902095A priority Critical patent/JP3500518B2/en
Publication of JPH0974113A publication Critical patent/JPH0974113A/en
Application granted granted Critical
Publication of JP3500518B2 publication Critical patent/JP3500518B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/745Apparatus for manufacturing wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/43Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/43Manufacturing methods
    • H01L2224/432Mechanical processes
    • H01L2224/4321Pulling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
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    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
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    • H01L2924/0102Calcium [Ca]
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    • H01L2924/01029Copper [Cu]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、ICチップ電極と
外部リードとを接続するために使用される半導体装置用
金合金極細線の製造方法に関し、詳しくは、半導体装置
の金合金極細線のショート防止及び耐振動性に有用な半
導体装置用金合金極細線の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gold alloy extra fine wire for a semiconductor device, which is used for connecting an IC chip electrode and an external lead, and more specifically, to short-circuiting a gold alloy extra fine wire in a semiconductor device. The present invention relates to a method for manufacturing a gold alloy extra fine wire for semiconductor devices, which is useful for prevention and vibration resistance.

【0002】[0002]

【従来の技術】ICチップ等の半導体チップの電極と外
部リードとを接続する方法として、一般には直径0.0
1〜0.1mmの金合金極細線(ボンディングワイヤ)
で接続するワイヤボンディング方法が用いられている。
前記ワイヤボンディング方法は、ICチップ等の半導体
チップの電極面に金合金細線の先端を第1ボンディング
し、該金合金極細線をループ状に配線した後、外部リー
ド上に第2ボンディングするものである。この種のワイ
ヤボンディング方法は簡単な装置によって量産出来る方
法であるが、ループ状に配線された時、金合金極細線が
配線方向に対して左右に曲がり隣同士の極細線が接触し
てショートを起こしたり、振動によって金合金極細線が
断線するという問題がある。これらの問題に対応する方
法として、従来から、高純度金に1〜100重量ppm
という微量の元素を含有させた金合金極細線として対応
する方法が用いられている。
2. Description of the Related Art As a method for connecting an electrode of a semiconductor chip such as an IC chip and an external lead, generally, a diameter of 0.0
1-0.1mm gold alloy extra fine wire (bonding wire)
The wire bonding method of connecting with is used.
In the wire bonding method, the tip of a gold alloy fine wire is first bonded to an electrode surface of a semiconductor chip such as an IC chip, the gold alloy fine wire is wired in a loop shape, and then second bonding is performed on an external lead. is there. This kind of wire bonding method is a method that can be mass-produced by a simple device, but when wired in a loop, the gold alloy ultrafine wire bends left and right with respect to the wiring direction and adjacent ultrafine wires contact each other to cause a short circuit. There is a problem that the gold alloy ultrafine wire is broken due to vibration or vibration. As a method for dealing with these problems, conventionally, high purity gold has 1 to 100 ppm by weight.
A corresponding method is used as a gold alloy extra fine wire containing a trace amount of element.

【0003】一方、近年ICはより一層の高機能化、高
集積化が行われ、電極数が増加している。これに対応す
るため、前記ワイヤボンディング法のループ形成におい
て、長いループ(長ループ)で且つ配線密度が高くなっ
て来た。このため、前記金合金極細線(ループ)が配線
方向に対して左右に曲る許容量をさらに小さくして、上
記したショートの防止に対応する必要性が生じて来た
が、前記微量の元素を含有させるだけの手段ではこのよ
うな要求に十分に対応出来なくなって来た。
On the other hand, in recent years, ICs have been further enhanced in function and integration, and the number of electrodes has been increasing. In order to cope with this, in the loop formation of the wire bonding method, a long loop (long loop) and a wiring density have become high. Therefore, it has been necessary to further reduce the allowable amount of bending of the gold alloy ultrafine wire (loop) to the left and right with respect to the wiring direction to prevent the above-mentioned short circuit. It has become impossible to adequately meet such demands by means of only containing.

【0004】前記要求への対応方法として、特開平6−
61292号公報には、金合金線をパーフロロ3級アミ
ン等を含有した処理液に浸積して効率良く冷却すること
により、ループ異常等のトラブルの回避を図った冷却装
置が提案されている。該方法は、スプールに巻き取られ
た金合金極細線の巻きほどき性を良好にして、ループ異
常の発生を防止するために効果的であることが開示され
ている。しかし乍ら該方法では、金合金極細線材質に起
因する本質的なループ曲がりを小さくすることに未だ不
十分である。
As a method of responding to the above-mentioned demand, Japanese Patent Laid-Open No. 6-
Japanese Patent No. 61292 proposes a cooling device in which a trouble such as a loop abnormality is avoided by immersing a gold alloy wire in a treatment liquid containing a perfluoro tertiary amine or the like for efficient cooling. It is disclosed that the method is effective for improving the unwinding property of the gold alloy ultrafine wire wound on the spool and preventing the occurrence of loop abnormality. However, this method is still insufficient to reduce the essential loop bending caused by the gold alloy ultrafine wire material.

【0005】また、上記した2番目の問題である振動に
よる金合金極細線の断線を防止するという点は、近年益
々その信頼性を求められている。前述の如く、従来にお
いては前記断線を防止する方法として、高純度金に1〜
100重量ppmという微量の元素を含有させた金合金
細線が用いられている。例えば特開平5−179375
号には、高純度金に微量のAlやCa等を含有させて振
動による断線を抑制することが提案されている。しかし
乍ら、振動による断線を防止することに対して、前記高
純度金に微量の元素を含有させるだけでは未だ不十分
で、これに加えて更なる信頼性の向上が求められてい
る。
In addition, in order to prevent the gold alloy extra fine wire from being broken due to vibration, which is the second problem described above, reliability has been increasingly demanded in recent years. As described above, in the conventional method, high purity gold is
A gold alloy fine wire containing a trace amount of element of 100 ppm by weight is used. For example, JP-A-5-179375
JP-A No. 2003-242242 proposes that a trace amount of Al, Ca, or the like is contained in high-purity gold to suppress disconnection due to vibration. However, in order to prevent disconnection due to vibration, it is still insufficient to contain a trace amount of element in the high-purity gold, and further improvement in reliability is required.

【0006】[0006]

【発明が解決しようとする課題】本発明は、ICチップ
等の半導体チップの電極と外部リードとを金合金極細線
で配線する際、長ループで且つ配線密度が高くなった場
合においても、金合金極細線が配線方向に対して左右方
向に曲がる量(ループ曲がり量)を小さくして隣同士の
金合金極細線が接触してショートを起こすことを効果的
に防止することが出来ると共に、振動によって金合金極
細線が断線する程度を低減して信頼性を向上することが
出来る半導体装置用金合金極細線の製造方法を提供する
ことを目的とする。
DISCLOSURE OF THE INVENTION The present invention provides a gold alloy extra fine wire for wiring an electrode of a semiconductor chip such as an IC chip and an external lead even when a long loop and a high wiring density are provided. The amount by which the ultrafine alloy wire bends in the left-right direction with respect to the wiring direction (loop bend amount) can be reduced to effectively prevent short-circuiting due to contact between adjacent gold alloy ultrafine wires and vibration. It is an object of the present invention to provide a method for manufacturing a gold alloy ultrafine wire for a semiconductor device, which can improve the reliability by reducing the degree of disconnection of the gold alloy ultrafine wire.

【0007】[0007]

【課題を解決するための手段】本発明者等は鋭意検討を
行った結果、金合金極細線の中心部と外周部が均質であ
るものが前記課題に対して効果的であることを見出し、
本発明に至った。その要旨とするところは次の通りであ
る。
Means for Solving the Problems As a result of intensive investigations by the present inventors, it was found that a gold alloy ultrafine wire having a uniform central portion and outer peripheral portion is effective for the above problems.
The present invention has been completed. The main points are as follows.

【0008】すなわち本願第1発明は、金合金を溶解、
鋳造して鋳塊を得る工程と、前記鋳塊に粗加工を施した
後、ダイスを用いて伸線加工する工程と、次いで焼鈍処
理する工程を備える半導体装置用金合金極細線の製造方
法において、前記伸線加工用ダイスのアプローチ角度が
3〜7度又は8〜15度であることを特徴とする。また
本願第2発明は、上記鋳塊を得る工程が、溶解した金合
金の溶湯をルツボ内で下端から冷却して凝固させる工程
であることを特徴とする。さらに本願第3発明は、上記
焼鈍処理する工程後に得られた金合金極細線の中心部と
外周部の硬度比が、0.9〜1.0であることを特徴と
する。
That is, the first invention of the present application is to melt a gold alloy,
In the method of manufacturing a gold alloy extra fine wire for a semiconductor device, which comprises a step of casting to obtain an ingot, a step of performing a roughing process on the ingot, a step of wire drawing using a die, and a step of annealing treatment thereafter. The approach angle of the wire drawing die is 3 to 7 degrees or 8 to 15 degrees. Further, the second invention of the present application is characterized in that the step of obtaining the ingot is a step of cooling the molten metal of the molten gold alloy from the lower end in the crucible to solidify it. Furthermore, the third invention of the present application is characterized in that the hardness ratio between the central portion and the outer peripheral portion of the gold alloy extra fine wire obtained after the step of annealing is 0.9 to 1.0.

【0009】[0009]

【発明の実施の形態】以下、本発明に係る半導体装置用
金合金極細線の製造方法について詳細に説明する。本発
明に用いる金合金は、半導体装置用金合金極細線として
通常用いられる金合金組成のものが適用出来る。本発明
方法の概要について述べれば、まず金合金を溶解、鋳造
してインゴット(鋳塊)を製造し、そのインゴットに溝
ロール圧延等の粗加工を施した後伸線加工を施して所定
の線径に加工し、さらに所定の伸び率になるように焼鈍
処理を施して金合金極細線を製造するものである。
BEST MODE FOR CARRYING OUT THE INVENTION A method for manufacturing a gold alloy extra fine wire for a semiconductor device according to the present invention will be described in detail below. The gold alloy used in the present invention may have a gold alloy composition that is usually used as a gold alloy extra fine wire for semiconductor devices. The outline of the method of the present invention is as follows. First, a gold alloy is melted and cast to produce an ingot (ingot), and the ingot is subjected to roughing such as groove roll rolling and then wire drawing to give a predetermined wire. The gold alloy ultrafine wire is manufactured by processing into a diameter and further annealing treatment so as to obtain a predetermined elongation.

【0010】本発明においては、金合金を溶解、鋳造し
て鋳塊を得る工程において、該鋳造時にチル層が生成す
ることを抑制したインゴットが好ましく用いられる。該
インゴットを出発材料とすることにより、焼鈍した後に
金合金極細線の中心部と外周部がより均質な金合金極細
線が得られ、本発明の課題である配線の曲がり(ループ
曲がり)及び振動による断線防止に極めて優れた効果を
有するようになるため好ましく用いられる。前記チル層
の生成を抑制したインゴットを得る方法の一例を、図2
(a)を用いて説明する。図中の符号11は金合金溶
湯、12はルツボ、13は高周波加熱コイルを示す。ま
ず、高周波加熱コイル13を用いて、ルツボ12内で金
合金を溶解しその溶湯11を得る。次いで、高周波加熱
コイル13を該ルツボ12の下端から所定の速度で上方
に移動して、前記ルツボ12内で溶湯11を凝固させる
ようにする。前記溶湯11を凝固させる際の凝固速度と
して80mm/分以下、さらに好ましくは50mm/分
以下にする。このようにして、金合金溶湯11をルツボ
12内で下端から冷却して凝固させることにより、イン
ゴット表面部にチル層が生成することを抑制出来るよう
になって好ましい。ここで、ルツボ12の内面形状は、
ルツボ12内で凝固させたインゴットが溝ロール圧延等
の粗加工に供し易い形状であれば良い。ルツボ12内面
が、断面径辺の2倍より長いインゴットが得られる形状
であることが好ましく、さらに好ましくは円筒形であ
る。またルツボ材質としては黒鉛が好ましく用いられ
る。
In the present invention, in the step of melting and casting a gold alloy to obtain an ingot, an ingot which suppresses the formation of a chill layer during the casting is preferably used. By using the ingot as a starting material, a gold alloy ultrafine wire in which the central portion and the outer peripheral portion of the gold alloy ultrafine wire are more uniform after annealing can be obtained, and the bending of the wiring (loop bending) and vibration, which are the subjects of the present invention, can be obtained. Since it has an extremely excellent effect in preventing disconnection due to, it is preferably used. An example of a method for obtaining an ingot in which the formation of the chill layer is suppressed is shown in FIG.
An explanation will be given using (a). In the figure, reference numeral 11 is a molten gold alloy, 12 is a crucible, and 13 is a high-frequency heating coil. First, the high-frequency heating coil 13 is used to melt the gold alloy in the crucible 12 to obtain the molten metal 11. Next, the high frequency heating coil 13 is moved upward from the lower end of the crucible 12 at a predetermined speed so that the molten metal 11 is solidified in the crucible 12. The solidification rate when solidifying the molten metal 11 is 80 mm / min or less, more preferably 50 mm / min or less. In this way, by cooling the molten gold alloy 11 from the lower end in the crucible 12 and solidifying it, it is possible to suppress the formation of a chill layer on the surface of the ingot, which is preferable. Here, the inner surface shape of the crucible 12 is
It is sufficient that the ingot solidified in the crucible 12 has a shape that facilitates roughing such as groove roll rolling. The inner surface of the crucible 12 preferably has a shape capable of obtaining an ingot longer than twice the radial side of the cross section, and more preferably a cylindrical shape. Graphite is preferably used as the crucible material.

【0011】これに対して、通常用いられているインゴ
ットを得る方法である連続鋳造法を、図2(b)を用い
て説明する。図中の符号11は金合金溶湯、14はタン
ディッシュ、15は黒鉛鋳型、16は黒鉛鋳型冷却用水
冷パイプ、17は凝固したインゴット、矢印はインゴッ
ト引抜き方向である。まず、金合金溶湯11をタンディ
ッシュ14を用いて量を調整しつつ、黒鉛鋳型15に注
入する。黒鉛鋳型15は水冷パイプ16を接触させて冷
却されている。このため、金合金溶湯11は黒鉛鋳型1
5により強制冷却されて凝固し、矢印方向に引き抜かれ
る。従来、半導体装置用金合金極細線の製造においてイ
ンゴットを得る方法としては、生産性を考慮し、早い生
産速度が得られる図2(b)の連続鋳造法が一般的であ
る。該方法は鋳型材質として黒鉛や銅等を用い、300
mm/分以上の速度で溶湯11を凝固させている。この
ようにすると、溶湯11を鋳型15で強制冷却するため
に、インゴット17の表面部分にチル層が生成する。図
2(a)に示す如く溶湯11をルツボ12内で下端から
冷却して凝固させたインゴットを用いる方が、内面(中
心部)と外面(外周部)で差異の小さい均質な金合金極
細線を製造するために好ましいインゴットの組織になっ
ていると考えられる。
On the other hand, a continuous casting method, which is a method for obtaining a commonly used ingot, will be described with reference to FIG. In the figure, reference numeral 11 is a molten gold alloy, 14 is a tundish, 15 is a graphite mold, 16 is a water cooling pipe for cooling the graphite mold, 17 is a solidified ingot, and the arrow is the ingot drawing direction. First, the molten gold alloy 11 is poured into the graphite mold 15 while adjusting the amount using the tundish 14. The graphite mold 15 is cooled by contacting it with a water cooling pipe 16. Therefore, the molten gold alloy 11 is the graphite mold 1
It is forcibly cooled by 5 and solidifies, and is withdrawn in the direction of the arrow. Conventionally, as a method for obtaining an ingot in the production of a gold alloy ultrafine wire for a semiconductor device, a continuous casting method shown in FIG. This method uses graphite, copper, etc. as the mold material,
The molten metal 11 is solidified at a speed of mm / min or more. By doing so, the melt 11 is forcibly cooled by the mold 15, so that a chill layer is formed on the surface portion of the ingot 17. As shown in FIG. 2 (a), the use of an ingot in which the molten metal 11 is cooled and solidified in the crucible 12 from the lower end is a homogeneous gold alloy extra fine wire with a small difference between the inner surface (center portion) and the outer surface (outer peripheral portion). It is thought that it has a preferable ingot structure for producing

【0012】本発明になる金合金極細線の製造方法は、
鋳造工程で得られたインゴットを粗加工した後、直径
0.01〜0.1mmの極細線になるまで伸線加工が施
される。極細線の直径として最も一般的には0.02〜
0.05mmである。インゴットの粗加工としては、溝
ロール圧延方法が好ましく用いられる。
The method for producing a gold alloy ultrafine wire according to the present invention is as follows:
After roughly processing the ingot obtained in the casting step, wire drawing is performed until it becomes an ultrafine wire having a diameter of 0.01 to 0.1 mm. Most commonly, the diameter of the ultrafine wire is 0.02-
It is 0.05 mm. A groove roll rolling method is preferably used for roughing the ingot.

【0013】前記金合金極細線を伸線加工するに際し
て、従来から重要視されていることは、極細線であるが
ゆえに断線し易いため、この断線回数を少なくして生産
能率を上げることである。これの対応方法として従来に
おいては、ダイス引抜き力が極小になる様、伸線加工用
ダイスのアプローチ角度を7.5±0.2度に設定し
て、断線を抑制して生産能率の向上を図ってきた。ここ
で伸線加工用のダイスについて、その断面形状を図1を
用いて説明する。図中の符号1は伸線加工前の線、2は
伸線加工後の線、3は伸線加工用ダイス、4はダイスの
アプローチ部、5はダイスのベアリング部、αはアプロ
ーチ角度である。伸線加工される線はアプローチ部4で
減面され、ベアリング部5で線の形状を整えている。本
発明でいうアプローチ角度αは図1に示す通り、ダイス
軸線と平行な基準線Lに対する傾斜角度であり、実際の
ダイス3の傾斜角度の半角で表示している。
[0013] When wire-drawing the gold alloy extra-fine wire, it has been emphasized in the past that the wire is easily cut because it is an extra-fine wire. Therefore, the number of wire breakages is reduced to increase the production efficiency. . As a method of dealing with this, in the past, the approach angle of the wire drawing die was set to 7.5 ± 0.2 degrees so that the die drawing force would be minimized, and wire breakage was suppressed to improve production efficiency. I have been trying. Here, the cross-sectional shape of the wire drawing die will be described with reference to FIG. In the figure, reference numeral 1 is a wire before wire drawing, 2 is a wire after wire drawing, 3 is a wire drawing die, 4 is a die approach portion, 5 is a die bearing portion, and α is an approach angle. . The wire to be drawn is reduced in the approach portion 4, and the shape of the wire is adjusted in the bearing portion 5. The approach angle α in the present invention is an inclination angle with respect to a reference line L parallel to the die axis, as shown in FIG. 1, and is represented by a half angle of the actual inclination angle of the die 3.

【0014】前記アプローチ角度αと金合金線の引抜き
力の関係を図5に示す。横軸はアプローチ角度α、縦軸
は引抜き力を示す。図5から明らかな様に、アプローチ
角度αが7.5度において引抜き力が極小になる。前記
状況に対して、本発明においては前記アプローチ角度α
を3.0〜7.0度又は8.0〜15.0度に設定する
ことが必要である。伸線加工ダイスのアプローチ角度α
を本発明になる前記角度とした場合、次の工程である焼
鈍工程を経た後の金合金極細線は、半導体装置の配線に
用いた場合、左右方向に曲がる量を小さく出来ると共
に、振動によって金合金極細線が断線する程度を低減出
来るという優れた効果を有するようになってくる。さら
に好ましいアプローチ角度αは4.0〜7.0度又は
8.0〜12.5度である。この角度の時、焼鈍工程を
経た後の金合金極細線は、前記本発明の課題に対してさ
らに優れた効果を有するようになってくる。
FIG. 5 shows the relationship between the approach angle α and the drawing force of the gold alloy wire. The horizontal axis represents the approach angle α, and the vertical axis represents the pulling force. As is clear from FIG. 5, the pulling-out force becomes minimum when the approach angle α is 7.5 degrees. In contrast to the above situation, in the present invention, the approach angle α
Should be set to 3.0 to 7.0 degrees or 8.0 to 15.0 degrees. Approach angle α of wire drawing die
In the case of the angle according to the present invention, the gold alloy ultrafine wire that has undergone the annealing step that is the next step, when used for the wiring of the semiconductor device, can reduce the amount of bending in the left-right direction, and can reduce the amount of vibration due to vibration. It has an excellent effect that it is possible to reduce the degree of disconnection of the ultrafine alloy wire. A more preferable approach angle α is 4.0 to 7.0 degrees or 8.0 to 12.5 degrees. At this angle, the gold alloy ultrafine wire that has undergone the annealing step has a more excellent effect on the above-mentioned problems of the present invention.

【0015】また前記アプローチ角度αが3.0度未満
及び15.0度を越える時、断線回数が著しく増えるた
め、本発明のアプローチ角度αの下限値を3.0度、上
限値を15.0度とした。またアプローチ角度αが、従
来用いていた7.5±0.2度を含む7.1〜7.9度
の時、焼鈍工程を経た後の金合金極細線は、配線時に左
右方向に曲がる量が大きく、且つ振動によって金合金極
細線が断線し易い。このためアプローチ角度αを前記範
囲に定めた。
When the approach angle α is less than 3.0 degrees and more than 15.0 degrees, the number of wire breakages remarkably increases. Therefore, the lower limit value of the approach angle α of the present invention is 3.0 degrees and the upper limit value is 15. It was 0 degree. Further, when the approach angle α is 7.1 to 7.9 degrees including 7.5 ± 0.2 degrees which is conventionally used, the gold alloy ultrafine wire after the annealing step bends in the left and right direction at the time of wiring. Is large and the gold alloy ultrafine wire is easily broken due to vibration. Therefore, the approach angle α is set within the above range.

【0016】さらに、鋳塊を得る工程がルツボ内で下端
から冷却して凝固させる工程であり、これにより得られ
たインゴットを用いると、伸線加工時の断線回数を少な
く出来ると共に、本発明の課題であるループ状に配線し
た金合金細線の左右方向の曲がりと振動による断線に対
して、一段と優れた効果を示す様になる。
Further, the step of obtaining an ingot is a step of solidifying by cooling from the lower end in the crucible, and by using the ingot thus obtained, the number of wire breakages at the time of wire drawing can be reduced, and at the same time, according to the present invention. With respect to the problem, the gold alloy fine wire wired in a loop shape is more effectively exhibited against the bending in the left-right direction and the disconnection due to vibration.

【0017】上記のようにして伸線加工された金合金極
細線は、調質のために焼鈍が施される。通常は4%の伸
び率になる様に焼鈍が施される。焼鈍方法としては、炉
内に極細線の一端から順次通線して焼鈍する連続焼鈍方
式が好ましい。本発明の焼鈍温度としては350〜65
0℃が金合金の種類に応じて用いられる。また炉内滞留
時間としては0.4〜3.0秒が好ましく用いられる。
The gold alloy ultrafine wire drawn as described above is annealed for refining. Usually, annealing is performed so that the elongation rate becomes 4%. As the annealing method, a continuous annealing method is preferred in which the ultrafine wires are sequentially passed through the furnace and annealed. The annealing temperature of the present invention is 350 to 65.
0 ° C. is used depending on the type of gold alloy. The residence time in the furnace is preferably 0.4 to 3.0 seconds.

【0018】本発明の方法、すなわち上記アプローチ角
度αを3.0〜7.0度又は8.0〜15.0度に設定
した伸線加工用ダイスを用いて伸線加工することによ
り、またさらに好ましくはルツボ内で下端から冷却して
凝固させる工程で得られたインゴットを用いることによ
り、下記式で示す焼鈍後の金合金極細線の中心部と外周
部の硬度比が1.0に近い値となる。このような金合金
極細線の中心部と外周部の均質性が、本発明の課題に対
して優れた効果を示すようになると考えられる。該硬度
比は0.9〜1.0の範囲とすることが好ましい。
By the method of the present invention, that is, by performing wire drawing using a wire drawing die in which the approach angle α is set to 3.0 to 7.0 degrees or 8.0 to 15.0 degrees, More preferably, by using the ingot obtained in the step of cooling and solidifying from the lower end in the crucible, the hardness ratio between the central part and the outer peripheral part of the gold alloy ultrafine wire after annealing shown by the following formula is close to 1.0. It becomes a value. It is considered that the homogeneity of the central portion and the outer peripheral portion of such a gold alloy extra fine wire exhibits an excellent effect on the problem of the present invention. The hardness ratio is preferably in the range of 0.9 to 1.0.

【0019】ここで本発明になる硬度比を、図3を用い
て説明する。図3は上記焼鈍を施された後の金合金極細
線の縦割り状態を示す。図中に○印で示す極細線の中心
部と、×印で示す極細線の外周部とを各5点づつ硬度測
定して、前記中心部と外周部の硬度の平均値を求め、さ
らに次式<数1>から硬度比を求める。
Here, the hardness ratio according to the present invention will be described with reference to FIG. FIG. 3 shows a vertically split state of the gold alloy ultrafine wire after the annealing. In the figure, the hardness of the central portion of the ultrafine wire indicated by ○ and the outer peripheral portion of the ultrafine wire indicated by × are measured at 5 points each, and an average value of the hardness of the central portion and the outer peripheral portion is obtained. The hardness ratio is calculated from the formula <Equation 1>.

【数1】 [Equation 1]

【0020】而して、本発明の方法により得られた金合
金極細線が、本発明の課題に対して優れた効果を示す理
由は明らかではないが、前記金合金極細線の中心部と外
周部の均質性が向上するようになることが、半導体装置
に配線する際、複雑な歪みを内蔵することがないためル
ープ曲がりを小さくし、さらに振動を受ける環境に晒さ
れたとき金合金極細線の表面部に弱い箇所が生じにくく
なるため振動に対して強い金合金極細線が得られるよう
になったものと考えられる。
Thus, it is not clear why the gold alloy ultrafine wire obtained by the method of the present invention has an excellent effect on the problems of the present invention, but the central portion and outer circumference of the gold alloy ultrafine wire are not clear. It is possible to improve the homogeneity of the part, so that when wiring to a semiconductor device, there is no built-in complicated strain, so the loop bending is small, and when exposed to an environment subject to vibration, the gold alloy ultrafine wire It is considered that the gold alloy ultrafine wire, which is strong against vibration, can be obtained because the weak spots are less likely to occur on the surface part of.

【0021】[0021]

【実施例】以下、実施例に基づいて本発明をより詳細に
説明する。 (実施例1)5重量ppmのBeを含有し、残部が5N
(99.999 wt%)の高純度金である金合金を内径30m
m、長さ300mmの黒鉛ルツボ内で高周波加熱により
溶解した。次いで高周波加熱コイルを該ルツボの下端か
ら50mm/分の速度で上方に移動して、前記ルツボ内
で溶湯を冷却,凝固させてインゴットに鋳造した。該イ
ンゴットを溝ロールにて圧延した後、伸線加工を行い、
直径25μmの金合金極細線に仕上げた。伸線加工に用
いたダイスはアプローチ角度3度のものを用いた。該極
細線を伸び率4%となる様に焼鈍炉に通線して焼鈍し
た。この間、伸線加工時の単位重量当りの断線回数を計
測した。焼鈍後の極細線を用いて、硬度比、ループ曲り
量、破断迄の振動回数を測定した。前記した製造条件及
び測定結果を表1〜表2に示す。
The present invention will be described in more detail based on the following examples. (Example 1) Containing 5 ppm by weight of Be and the balance of 5N
(99.999 wt%) high-purity gold alloy with an inner diameter of 30 m
It was melted by high frequency heating in a graphite crucible having a length of m and a length of 300 mm. Next, the high-frequency heating coil was moved upward from the lower end of the crucible at a speed of 50 mm / min to cool and solidify the molten metal in the crucible and cast it into an ingot. After rolling the ingot with a groove roll, wire drawing is performed,
A gold alloy ultrafine wire having a diameter of 25 μm was finished. The die used for wire drawing had an approach angle of 3 degrees. The ultrafine wire was passed through an annealing furnace so as to have an elongation of 4% and annealed. During this time, the number of wire breakages per unit weight during wire drawing was measured. The hardness ratio, the amount of loop bending, and the number of vibrations until breakage were measured using an ultrafine wire after annealing. The above-mentioned manufacturing conditions and measurement results are shown in Tables 1 and 2.

【0022】測定方法は以下の通りとした。 (硬度比)前述の如く、図3中に○印で示す極細線の中
心部と、×印で示す極細線の外周部とを各5点づつ硬度
測定して、前記中心部と外周部の硬度の平均値を求め、
さらに上記式<数1>から硬度比を求める。極細線の長
さ方向10箇所で前記硬度比を求め、その平均値を測定
値とした。 (ループ曲がり量)ループ形成方法は新川社製の50型
ボンダーを用いて、ICチップ電極と外部端子間でワイ
ヤボンディングを行った。ICチップ電極上に最初のボ
ール接合を行った後、ループ形成と逆方向にキャピラリ
ーを一旦動かし、リバース変形を行い、その後、正規の
ループを形成した。ボンディング条件はループ高さ:2
00μm、チップ電極と外部端子間を5mmとした。こ
のようにしてループ形成を行い、チップ電極と外部端子
の接続点を結んだ直線から左右にループが最も離れた距
離を測定し、100個の平均値をループ曲がり量とし
た。 (破断迄の振動回数)試験方法の概要を図4に示す。銀
めっきしたリードフレーム(5mm×5mm)21上に
10cm長さの金合金極細線22をボールボンディング
して振動試験の材料とした。振動試験機械23を用い、
前記極細線22をクランプ24で保持し、軸25を中心
に左右両側へ振動させる振動試験を次の条件で行い、破
断に至る迄の振動回数を測定した。 スパン距離(L1 ):150μm 両側振幅 L2 :26μm 振動周波数:40Hz(1秒間に40回) 同様の試験を3回繰り返し、得られた平均値を破断迄の
振動回数として表示した。
The measuring method was as follows. (Hardness ratio) As described above, the hardness of the central portion of the ultrafine wire indicated by a circle in FIG. 3 and the outer peripheral portion of the ultrafine wire indicated by a cross in FIG. Obtain the average hardness value,
Further, the hardness ratio is obtained from the above formula <Equation 1>. The hardness ratio was obtained at 10 points in the length direction of the ultrafine wire, and the average value thereof was used as the measured value. (Bending amount of loop) As a loop forming method, a 50 type bonder manufactured by Shinkawa Co., Ltd. was used, and wire bonding was performed between the IC chip electrode and the external terminal. After the first ball bonding was performed on the IC chip electrode, the capillary was once moved in the direction opposite to the loop formation, reverse deformation was performed, and then a regular loop was formed. Bonding condition is loop height: 2
The distance between the chip electrode and the external terminal was 5 mm. The loop was formed in this manner, and the distance at which the loop was most distant from the straight line connecting the connection point of the chip electrode and the external terminal was measured, and the average value of 100 loops was taken as the loop bending amount. (Number of vibrations until breaking) An outline of the test method is shown in FIG. A gold alloy fine wire 22 having a length of 10 cm was ball-bonded on a silver-plated lead frame (5 mm × 5 mm) 21 to obtain a vibration test material. Using the vibration test machine 23,
A vibration test was carried out under the following conditions in which the ultrafine wire 22 was held by a clamp 24 and vibrated to the left and right around a shaft 25, and the number of vibrations until breakage was measured. Span distance (L 1 ): 150 μm Bilateral amplitude L 2 : 26 μm Vibration frequency: 40 Hz (40 times per second) The same test was repeated 3 times, and the obtained average value was displayed as the number of vibrations until breakage.

【0023】(実施例2〜14/比較例1〜9)製造条
件として金合金の種類、鋳造工程における凝固方式と凝
固速度、伸線工程におけるダイスアプローチ角度を表1
中に記載の様にしたこと以外は実施例1と同様にして金
合金極細線を製造し、測定を行った。製造条件及び測定
結果を表1〜表2に示す。
(Examples 2 to 14 / Comparative Examples 1 to 9) Table 1 shows the types of gold alloys as production conditions, solidification method and rate in the casting process, and die approach angle in the wire drawing process.
A gold alloy ultrafine wire was manufactured and measured in the same manner as in Example 1 except that the description was made therein. Manufacturing conditions and measurement results are shown in Tables 1 and 2.

【0024】[0024]

【表1】 [Table 1]

【0025】[0025]

【表2】 [Table 2]

【0026】以上の測定結果から、ダイスアプローチ角
度αが本発明の範囲である実施例1〜14と、従来の角
度(7.5±0.2度)である比較例3,6,8との対
比から、以下のことが判る。ルツボ内凝固方式で得られ
たインゴットを用いた時、硬度比は比較例が0.77〜
0.78であるのに対し実施例では0.96〜0.98
へ向上し、ループ曲がり量は比較例が36μmであるの
に対し実施例では15〜18μmへ向上し、振動回数は
比較例が9.7〜9.8×103 であるのに対し実施例
では13.0×103 以上へ向上している。連続鋳造方
式で得られたインゴットを用いた時、硬度比は比較例が
0.55であるのに対し実施例では0.90〜0.91
へ向上し、ループ曲がり量は比較例が55μmであるの
に対し実施例では23〜24μmへ向上し、振動回数は
比較例が7.9×103 であるのに対し実施例では1
1.9〜12.1×103 以上へ向上している。
From the above measurement results, there are Examples 1 to 14 in which the die approach angle α is within the range of the present invention, and Comparative Examples 3, 6 and 8 in which the conventional die angle is 7.5 ± 0.2 degrees. From the comparison of, the following can be understood. When an ingot obtained by the solidification method in the crucible was used, the hardness ratio was 0.77 to
0.78, whereas in the embodiment 0.96 to 0.98
In the comparative example, the amount of loop bending is 36 μm, whereas in the example, it is improved to 15 to 18 μm, and the vibration frequency is 9.7 to 9.8 × 10 3 in the comparative example. Then, it has improved to 13.0 × 10 3 or more. When an ingot obtained by the continuous casting method is used, the hardness ratio is 0.55 in the comparative example, but 0.90 to 0.91 in the example.
The loop bending amount is 55 μm in the comparative example, while it is improved to 23 to 24 μm in the example, and the vibration frequency is 1 in the example, while it is 7.9 × 10 3.
It has improved to 1.9 to 12.1 × 10 3 or more.

【0027】また、ダイスアプローチ角度αが本発明の
範囲と従来の角度との間にある比較例2,4,7,9
は、硬度比、ループ曲り量、振動回数において従来より
向上しているものの本発明実施例よりは劣り、本発明の
課題を満足し得ないことが判る。
Comparative examples 2, 4, 7 and 9 in which the die approach angle α is between the range of the present invention and the conventional angle.
Although the hardness ratio, the amount of loop bending, and the number of vibrations are improved as compared with the conventional examples, it is inferior to the examples of the present invention, and it is understood that the object of the present invention cannot be satisfied.

【0028】さらに比較例1,5と本発明実施例との対
比から、硬度比が0.9〜1.0の範囲内にあっても、
ダイスアプローチ角度αが本発明の下限値に満たない若
しくは上限値を越える場合は、伸線加工時の断線回数が
従来に比べて10倍以上であり、実用に供し得ないこと
が確認できた。
Further, from comparison between Comparative Examples 1 and 5 and Examples of the present invention, even if the hardness ratio is within the range of 0.9 to 1.0,
When the die approach angle α is less than the lower limit value or more than the upper limit value of the present invention, the number of wire breakages during wire drawing is 10 times or more as compared with the conventional one, and it was confirmed that it cannot be put to practical use.

【0029】また、実施例1,3,4,9〜11と実施
例12〜14との対比から、ダイスアプローチ角度αが
同じであっても、鋳塊を得る工程が溶湯をルツボ内で下
端から冷却して凝固させるルツボ内凝固方式を採用する
場合、ループ曲がり量はさらに小さくなり、振動試験に
よる破断回数がさらに増加するという優れた効果が生じ
てくることが判る。
Further, from the comparison between Examples 1, 3, 4, 9 to 11 and Examples 12 to 14, even if the die approach angle α is the same, the step of obtaining the ingot is the lower end of the molten metal in the crucible. It is understood that when the in- crucible solidification method of cooling and solidifying is adopted, the loop bending amount becomes further smaller, and the number of breaks by the vibration test is further increased.

【0030】尚、伸線加工時の断線回数について対比し
た場合、従来のダイスアプローチ角度である比較例3,
6,8に対して本発明実施例は同等若しくはやや劣るも
のの、実用に供し得ないものではなく、上記の如くそれ
に余りある効果が得られることを確認できた。
When the number of wire breaks during wire drawing is compared, Comparative Example 3, which is a conventional die approach angle, is used.
It was confirmed that the examples of the present invention were equivalent or slightly inferior to those of Examples 6 and 8, but they were not practically applicable, and that there were some effects as described above.

【0031】[0031]

【発明の効果】以上説明したように、本発明の金合金極
細線の製造方法は、金合金を溶解、鋳造して得られた鋳
塊に粗加工を施した後、アプローチ角度が3〜7度又は
8〜15度であるダイスを用いて伸線加工を施し、次い
で所定の伸び率になるよう焼鈍処理を施す新規な方法と
したので、焼鈍後の極細線の中心部と外周部の均質性が
向上し、半導体装置に配線する際、複雑な歪みを内蔵す
ることがないためループ曲がりを小さくし、さらに振動
を受ける環境に晒されたとき極細線の表面部に弱い箇所
が生じにくくなるため振動に対して強い金合金極細線が
得られる。従って、チップ電極と外部リードを配線する
際、長ループで且つ配線密度が高くなっても、隣同士の
極細線が接触してショートを起こすことを効果的に防止
出来ると共に、振動によって極細線が断線する程度を低
減して信頼性を向上することが出来、半導体装置の高機
能化、高集積化に有用な金合金極細線を製造し得る。
As described above, according to the method for producing a gold alloy ultrafine wire of the present invention, the approach angle is 3 to 7 after the ingot obtained by melting and casting the gold alloy is rough processed. Since a new method is used in which wire drawing is performed using a die having a temperature of 8 to 15 degrees, and then annealing treatment is performed so that a predetermined elongation is obtained. Characteristics, and when wiring to a semiconductor device, complicated distortion is not built in, so loop bending is reduced, and when exposed to an environment subject to vibration, weak spots are less likely to occur on the surface of ultrafine wires. Therefore, a gold alloy extra fine wire that is strong against vibration can be obtained. Therefore, when the chip electrode and the external lead are wired, it is possible to effectively prevent a short circuit due to contact between adjacent ultrafine wires even if the wire length is long and the wiring density is high, and the ultrafine wires are vibrated by vibration. It is possible to reduce the degree of disconnection and improve reliability, and it is possible to manufacture a gold alloy ultrafine wire useful for highly functional and highly integrated semiconductor devices.

【0032】また、上記鋳塊を得る工程が、溶解した金
合金の溶湯をルツボ内で下端から冷却して凝固させる工
程である場合は、インゴット表面部にチル層が生成する
ことが抑制され、均質な金合金極細線を製造するために
より好ましいインゴットの組織になって、焼鈍工程後に
得られた極細線のループ曲がり量はさらに小さくなり、
振動試験による破断回数がさらに増加して、前述の効果
をより実効あるものとし得る。
When the step of obtaining the ingot is the step of cooling the molten metal of the molten gold alloy from the lower end in the crucible to solidify it, generation of a chill layer on the surface of the ingot is suppressed, A more preferred ingot structure for producing a homogeneous gold alloy extra fine wire, the amount of loop bending of the extra fine wire obtained after the annealing step is further reduced,
The number of breaks by the vibration test can be further increased, and the above-mentioned effects can be made more effective.

【図面の簡単な説明】[Brief description of drawings]

【図1】伸線加工用ダイスによる伸線加工の概要を示す
断面図。
FIG. 1 is a cross-sectional view showing an outline of wire drawing by a wire drawing die.

【図2】鋳塊を得る工程を示す断面図で、(a)はルツ
ボ内凝固方式、(b)は連続鋳造方式を表す。
FIG. 2 is a cross-sectional view showing a process of obtaining an ingot, where (a) shows a solidification method in a crucible and (b) shows a continuous casting method.

【図3】金合金極細線の硬度比を測定する方法の概要を
示す断面図。
FIG. 3 is a sectional view showing an outline of a method for measuring the hardness ratio of a gold alloy ultrafine wire.

【図4】破断迄の振動回数の試験方法の概要を示す断面
図。
FIG. 4 is a cross-sectional view showing an outline of a method of testing the number of vibrations until breaking.

【図5】ダイスアプローチ角度と金合金線の引抜き力の
関係を示すグラフ。
FIG. 5 is a graph showing the relationship between the die approach angle and the gold alloy wire drawing force.

【符号の説明】[Explanation of symbols]

1:伸線加工前の金合金線 2:伸線加工後の金合金線 3:伸線加工用ダイス 4:アプローチ部 5:ベアリング部 α:アプローチ角度 11:金合金溶湯 12:ルツボ 13:高周波加熱コイル 14:タンディッシュ 15:鋳型 16:水冷パイプ 17:インゴット 21:リードフレーム 22:金合金極細線 23:振動試験機 1: Gold alloy wire before wire drawing 2: Gold alloy wire after wire drawing 3: Die for wire drawing 4: Approach section 5: Bearing part α: Approach angle 11: Gold alloy melt 12: crucible 13: High frequency heating coil 14: Tundish 15: Mold 16: Water cooling pipe 17: Ingot 21: Lead frame 22: Gold alloy extra fine wire 23: Vibration tester

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−34934(JP,A) 特開 平6−154840(JP,A) 特開 平6−328124(JP,A) 特開 昭48−34060(JP,A) 特開 平4−210814(JP,A) 特開 昭63−299810(JP,A) 特開 平6−226328(JP,A) 特開 平6−277745(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 301 B21C 3/02 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A 63-34934 (JP, A) JP-A 6-154840 (JP, A) JP-A 6-328124 (JP, A) JP-A 48- 34060 (JP, A) JP 4-210814 (JP, A) JP 63-299810 (JP, A) JP 6-226328 (JP, A) JP 6-277745 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60 301 B21C 3/02

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 金合金を溶解、鋳造して鋳塊を得る工程
と、前記鋳塊に粗加工を施した後、伸線加工する工程
と、次いで焼鈍処理する工程を備える半導体装置用金合
金極細線の製造方法において、前記伸線加工用ダイスの
アプローチ角度が3〜7度又は8〜15度であることを
特徴とする半導体装置用金合金極細線の製造方法。
1. A gold alloy for a semiconductor device, comprising: a step of melting and casting a gold alloy to obtain an ingot; a step of rough-working the ingot; then a wire drawing step; and a step of annealing. A method for manufacturing a gold alloy ultrafine wire for a semiconductor device, wherein an approach angle of the wire drawing die is 3 to 7 degrees or 8 to 15 degrees.
【請求項2】 上記鋳塊を得る工程が、溶解した金合金
の溶湯をルツボ内で下端から冷却して凝固させる工程で
あることを特徴とする請求項1記載の半導体装置用金合
金極細線の製造方法。
2. The gold alloy extra fine wire for a semiconductor device according to claim 1, wherein the step of obtaining the ingot is a step of cooling the molten metal of the molten gold alloy from the lower end in the crucible and solidifying the molten alloy. Manufacturing method.
【請求項3】 上記焼鈍処理する工程後に得られた金合
金極細線の中心部と外周部の硬度比が0.9〜1.0で
あることを特徴とする請求項1又は請求項2記載の半導
体装置用金合金極細線の製造方法。
3. The hardness ratio between the central portion and the outer peripheral portion of the gold alloy ultrafine wire obtained after the step of performing the annealing treatment is 0.9 to 1.0, wherein the hardness ratio is 0.9 to 1.0. Manufacturing method of gold alloy ultrafine wire for semiconductor device.
JP22902095A 1995-09-06 1995-09-06 Manufacturing method of ultrafine gold alloy wire Expired - Fee Related JP3500518B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22902095A JP3500518B2 (en) 1995-09-06 1995-09-06 Manufacturing method of ultrafine gold alloy wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22902095A JP3500518B2 (en) 1995-09-06 1995-09-06 Manufacturing method of ultrafine gold alloy wire

Publications (2)

Publication Number Publication Date
JPH0974113A JPH0974113A (en) 1997-03-18
JP3500518B2 true JP3500518B2 (en) 2004-02-23

Family

ID=16885501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22902095A Expired - Fee Related JP3500518B2 (en) 1995-09-06 1995-09-06 Manufacturing method of ultrafine gold alloy wire

Country Status (1)

Country Link
JP (1) JP3500518B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5311715B2 (en) * 2005-01-24 2013-10-09 新日鉄住金マテリアルズ株式会社 Gold wire for semiconductor element connection
JP4694908B2 (en) * 2005-07-14 2011-06-08 田中電子工業株式会社 Manufacturing method of Au fine wire for ball bonding
DE102006006728A1 (en) * 2006-02-13 2007-08-23 W.C. Heraeus Gmbh bonding wire
JP4947670B2 (en) * 2009-12-16 2012-06-06 田中電子工業株式会社 Heat treatment method for bonding wires for semiconductor devices

Also Published As

Publication number Publication date
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