JP3499481B2 - Data multiplier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data multiplication device that can be used in a signal generator.

[0002]

2. Description of the Related Art Conventionally, for example, waveform data is read from a waveform data ROM in which waveform data obtained by digitally converting a sine wave signal is stored, the read waveform data is multiplied by a predetermined multiplication factor, and a predetermined number of bits is set. There is a signal generator for testing the digital amplifier by obtaining the multiplied output of the digital amplifier and supplying the multiplied output to the digital amplifier.

As shown in FIG. 4, a conventional data multiplication device of this type for multiplying a predetermined multiplier, for example, from a waveform data ROM 1 in which waveform data obtained by converting a sine wave signal into 16-bit digital data is stored, Waveform data is read. A multiplier 63 multiplies both the read-out waveform data and the 16-bit multiplier value output from the level setting unit 62, which is a multiplier data setting unit for setting the level of the waveform data, and performs multiplication. The multiplication is performed by extracting 16 bits from the high-order side of the result and truncating the lower bits. Each data is a binary number with a sign in 2's complement.

Here, there is a case where it is desired to test whether the digital amplifier works properly even at an input of, for example, -96 dB. In such a case, by the multiplication device, for example,
The waveform data of 8000 (H) (the maximum value of the negative side of the 0 dB sine wave) is multiplied by 0001 (H), that is, a multiplier of -96 dB. The multiplication result at this time is 00008000
It becomes 32 bits of (H), the upper 16 bits are taken, and 0000 (H) is sent as a multiplication output value. Here, (H) indicates a hexadecimal number (the same applies hereinafter).

However, an error of 1/2 bit occurs in this calculation result, and 0.5 (decimal number) is originally rounded to 1
It should be 0, but it has become 0. Therefore, when the output waveform signal level is -96 dB, that is, when it is desired to test the digital amplifier with an input of -96 dB, the maximum value of the waveform signal becomes 0, which is inconvenient.

In the above, the multiplier is 0001.
(H) is obtained by the following calculation. 8000 (H) is 0
When calculated as dB, the multiplier −96 dB is 10 ^(−96/20) × 8000 (H) = 10 ^(−96/20) × 32768 = 0.000015849 × 32768 = 0.5193337801 (1), Rounding it to 1 gives the above multiplier of 00
It becomes 01 (H).

In the case of an example in which 7FFF (H) (maximum positive value of 0 dB sine wave) is multiplied by 0001 (H), that is, a multiplier of -96 dB, 7FFF (H) × 0001 (H) = 00007FFF
(H), and taking the 16 bits on the MSB side of the multiplication result, 000
It becomes 0 (H).

In the above, the multiplier is 0001.
It becomes (H) by the following calculation. 0 to 7FFF (H)
When calculated as dB, the multiplier -96 dB is 7FFF (H) x 10^(-96/20)= 32767 ×
10^(-96/20) = 32767 × 0.000015
849 = 0.5193321952 Then, when rounded off, it becomes 1, and in this case also the multiplier is
It becomes 0001 (H).

[0009]

As described above, the conventional data multiplication device has a problem that the calculation result becomes inconvenient because the rounding is not performed.

It is an object of the present invention to provide a data multiplication device used in a signal generation device, which can obtain a rounded multiplication result with a simple structure.

[0011]

[Means for Solving the Problems] Claim 1 according to the present invention
The described data multiplication device is used for a data generator.
And a waveform data ROM in which waveform data of a binary number with a sign by a two's complement obtained by digitally converting an analog waveform is stored, and a number of bits of the waveform data stored in the waveform data ROM including a sign bit. By a multiplier that multiplies the waveform data read from the waveform data ROM by the multiplier value set in the level setter, and a multiplier A first and a second register in which data for rounding based on the sign bit of the multiplication result is placed; and a selector for selecting the number of the first or second register based on the sign bit of the multiplication result,
Equipped with an addition data setting circuit that outputs the data from the selector and an adder that adds the data output from the addition data setting circuit to the multiplication result as an addition value, and outputs the output data of the upper predetermined number of bits from the addition output. It is characterized by doing.

According to the data multiplication device of the first aspect of the present invention, the waveform data read from the waveform data ROM and the multiplier value set in the level setting device are multiplied by the multiplication device, and the multiplication result is obtained. The register of the first or second register is selected by the selector based on the sign bit of the multiplication result, and the addition value output from the selector is added to the multiplication result by the adder to obtain the predetermined number of high-order bits in the addition output. Output data is sent out. An addition value for rounding is added to this output, and the output is rounded data.

A data multiplying apparatus according to a second aspect of the present invention is the data multiplying apparatus according to the first aspect, wherein the addition data setting circuit causes the level setting unit to output the waveform data stored in the waveform data ROM as it is. When a multiplier value for is set, a means for sending out the added value of the numerical value of 0 instead of the output from the selector is provided.

According to the data multiplying device of the second aspect of the present invention, when the multiplier for setting the level setter to output the waveform data stored in the waveform data ROM as it is, it is substantially set. The addition value of the number 0 is added by the adder, and rounding is not performed.

A data multiplication device according to a third aspect of the present invention is a data multiplication device for use in a signal generator capable of selecting either 24 bits or 16 bits of output data, and an analog waveform. Digitally converted 2
Waveform data ROM that stores 24-bit waveform data in signed binary number representation by the complement of, and a multiplier value of a bit number that is at least 1 bit larger than the bit number of the waveform data stored in the waveform data ROM that includes sign bits , A multiplier for multiplying the waveform data read from the waveform data ROM by the multiplier value set in the level setter, and multiplication by the multiplier when the number of bits of output data is 24 bits 1st and 2nd data with the data for rounding based on the resulting sign bit
When the number of bits of output data is 16 bits, the number of bits of output data is 24 bits, and the number of bits of output data is 24 bits. , A first selector that selects the register number of the first or second register based on the sign bit of the multiplication result; and a third selector based on the sign bit of the multiplication result when the number of bits of output data is 16 bits.
Or a second selector for selecting the register number of the fourth register,
When the number of bits of output data is 24 bits, the output from the first selector is selected, and the number of bits of output data is 16
When the bit is a bit, a third selector that selects the output from the second selector is provided, and the addition data setting circuit that outputs the data from the third selector and the data that is output from the addition data setting circuit are used as the addition value in the multiplication result. It is characterized in that it is provided with an adder for adding and outputs predetermined upper 24 bits or upper 16 bits of output data from the addition output based on the number of output bits of 24 bits and 16 bits.

According to the data multiplying apparatus of the third aspect of the present invention, the waveform data read from the waveform data ROM and the multiplier value set in the level setting unit are multiplied by the multiplier to obtain the output data. When the number of bits is 24 bits, the register number of the first or second register is selected by the first selector based on the sign bit of the result of multiplication by the multiplier, and when the number of bits of output data is 16 bits, the result of multiplication by the multiplier is The register number of the third or fourth register is selected by the second selector based on the sign bit, the output of the first or second selector is selected by the third selector based on the bit number of the output data, and is output from the third selector. The addition value is added to the multiplication result in the adder, and the output data of the upper predetermined number of bits in the addition output is transmitted. An addition value for rounding is added to this output, and the output is rounded data.

A data multiplying apparatus according to a fourth aspect of the present invention is the data multiplying apparatus according to the third aspect, wherein the addition data setting circuit causes the level setting unit to display the waveform data when the number of bits of the output data is 24 bits. When the multiplier value for outputting the waveform data stored in the ROM as it is is set, or when the output bit number is 16 bits and the predetermined upper 16 bits of the multiplication result are 7FFF.
In the case of (H) or 8000 (H), it is characterized in that it is provided with a means for substantially transmitting the added value of the numerical value 0 instead of the output from the third selector.

According to the data multiplying apparatus of the fourth aspect of the present invention, when the number of output bits is 24 bits, a multiplier value for causing the level setter to output the waveform data stored in the waveform data ROM as it is. When it is set, when the number of output bits is 16 and the predetermined upper 16 bits of the multiplication result are 7FFF (H) or 800
When it is 0 (H), the waveform data stored in the waveform data ROM is output as it is, and the addition value of the numerical value 0 is substantially added by the adder and rounding is not performed.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data multiplication device according to the present invention will be described below with reference to embodiments.

FIG. 1 is a block diagram showing the configuration of a data multiplication device according to an embodiment of the present invention.

The data multiplication device 31 according to the embodiment of the present invention exemplifies the case of 24-bit output.

As shown in FIG. 1, a data multiplication device 31 according to an embodiment of the present invention includes a waveform data ROM 1 in which 24-bit waveform data including a sign bit obtained by digitally converting a sine wave signal is stored. , A level setter 2 in which 26-bit multiplier data for setting the level of waveform data including a sign bit (the sign bit is always set to 0) is set, and a waveform data ROM
The multiplier 3 that multiplies the waveform data read from 1 and the multiplier data that is output from the level setter 2, and the output from the addition data setting circuit 5 that rounds the multiplication result by the multiplier 3 Is added, and the output of the upper 24 bits is taken out from the adder 14.

Further, the addition data setting circuit 5 is 000.
Register 6 in which 0003 (H) is registered, and 00000
The register 7 in which 01 (H) is set, and the register 6 in which the sign bit of the multiplication result is 0, and the register 7 in which the sign bit of the multiplication result is 1 are selected Selector 8, a register 9 in which 0000000 (H) is entered, and when the multiplier data set in the level setter 2 is not 0 dB (= × 1), the output of the selector 8 is selected and the multiplier data is A selector 10 for selecting the register number of the register 9 in the case of 0 dB is provided, and the output of the selector 10 is supplied to the adder 4 as an addition number and added with the multiplication result.

Here, the register 9 and the selector 10 are provided, and when the multiplier data is 0 dB, the register number 0000000 (H) of the register 9 is added to the multiplication output output from the multiplier 3 via the selector 10. Multiplier data is 0d
In the case of B, the waveform data stored in the waveform data ROM 1 is output as it is, and it is not necessary to round off.

Registers 6 and 7, which are selected based on the sign bit of the multiplication result, store the upper two bits in the output of the multiplication result.
Data for rounding off the last digit when four bits are represented by a decimal number 00000003 (H), 00000
The number 01 (H) is registered.

The data multiplication device 3 configured as described above
1, the waveform data stored in the waveform data ROM 1 and the multiplier data set in the level setter 2 are multiplied by the multiplier 3, and the effective bit of the multiplication output is sent to the adder 4 and the adder 4 In addition, it is added with the addition number output from the data generator 5.

Here, the waveform data stored in the waveform data ROM 1 is 24 bits and has, for example, 800000.
(H), the multiplier data set in the level setter 2 is 26
The number of bits (= sign bit 1 + valid bit 25) is, for example, 000010A (H), and the multiplication result by the multiplier 3 is 50 bits, and for example, 3FFFF7B00.
0000 (H), of which bit 47 to bit 2
26 bits FFFF7B0 (H) up to 2 are extracted as effective bits and sent to the adder 4.

The number of additions output from the addition data setting circuit 5 is 26 bits, and for example, 0007FC (H),
The addition result by the adder 14 is 26 bits, for example, FFFFFAC (H), and the higher-order 2 as the addition output.
4-bit FFFFFA (H) is extracted.

Here, the multiplier data is the lower 26 bits of the 28 bits, but is represented by 28 bits for easy understanding. The effective bit, the number of additions, and the addition result are expressed in 28 bits for the purpose of easy understanding.
6 bits are used for the operation.

Next, the number of additions output from the addition data setting circuit 5 will be described. The multiplication result is a decimal number of 0.5
Multiplier data is expressed by the following equation (2).

20 × log (0.5 / 800000 (H)) = 20 × log (0.5 / 8388608) = − 144.49 dB (2) Therefore, the multiplier data (level dB) is −144.4.
It is necessary to determine the number of additions for rounding so that the value after rounding is 000001 (H) and FFFFF (H) when it is dB, and the value after rounding is 000000 (H) when it is -144.5 dB. is there. Where -1
444.4 dB and -144.4 dB and -14
The reason why it is set to 4.5 dB is that the multiplier data by the level setting device 2 can be set to one digit after the decimal point in dB display.

Therefore, the maximum value of the waveform data (7FF
When the multiplier data is −144.4 dB with respect to FFF (H)) and the minimum value (800000 (H)), the multiplication results are as shown in Expressions (3) and (4).

7FFFFF (H) × 0000001 (H) = 00000007FFFFF (H) (3) 800000 (H) × 0000001 (H) = 3FFFFFF8000000 (H) (4) where the multiplier data 00000001 (H) is − 144.
It is the multiplier data when it is 4 dB.

Next, when the upper 24 bits are taken, the value which becomes 000001 (H) and FFFFFF (H) is 4 respectively.
Minimum value 0000100000 when expressed in 8 bits
0 (H), FFFFFFFFFFFF (H) to the values of the following equations (5) and (6), which are the values obtained by subtracting the upper 4 bits from the values of equation (3) and equation (4), respectively. The value based on this is the addition number.

0000001000000 (H) −00000007FFFFF (H) = 0000000008001 (H) (5) FFFFFFFFFFFF (H) −FFFFFF800000 (H) = 0000007FFFFF (H) (6), and when the sign bit is 0, the number of additions Is 00000
0800001 (H) or more, 000001800001
It must be less than (H), and when the sign bit is 1, the number of additions must be less than 00000007FFFFF (H).

The above value is a 48-bit value, and is 26
In order to satisfy the condition with bits, when the sign bit is 0, the upper 26 bits of 000001000000 (H) 0000 0000 0000 0000 0000 0000 0001 00 (B) to the upper 26 bits of 00000007 FFFFF (H) are 0000 0000 0000 0000 0000 0000 0000. The value obtained by subtracting 01 (B) is 0000 0000 0000 0000 0000 0000 11 (B). If this is shown in hexadecimal from the lower bit, 000
0003 (H), which is the number of additions when the sign bit is 0. This is registered in the register 6.

Similarly, when the sign bit is 1, the upper 26 bits 1111 1111 1111 1111 1111 1111 11 (B) of FFFFFFFFFFFF (H) to the upper 26 bits 1111 1111 1111 1111 1111 1111 10 (B) of FFFFFF800000 (H). The value obtained by subtracting is 0000 0000 0000 0000 0000 0000 01 (B). If this is shown in hexadecimal from the lower bit, 000
0001 (H), which is the number of additions when the sign bit is 1. This is registered in the register 7.

Therefore, the register of the register 6 or the register 7 is selected by the selector based on the sign bit of the multiplication result, is added to the multiplication output in the adder 4, and the upper 24 bits of the addition output are extracted and rounded off. Obtained data. When the multiplication data is 0 dB, the register number of the register 9 is selected, and the higher 24 bits of the multiplication result are output as they are.

In the data multiplying device 31 described above, the case where 26-bit multiplier data including a sign bit is set in the level setter 2 has been exemplified, but 25-bit multiplier data including a sign bit is set in the level setter 2. It does not matter if you set.

Next, a first modification of the data multiplication device according to the embodiment of the present invention will be described.

FIG. 2 is a block diagram showing the configuration of the first modification of the data multiplication device according to the embodiment of the present invention.

The first modification of the data multiplication device according to the embodiment of the present invention exemplifies the case of 16-bit output.

As shown in FIG. 2, the data multiplying device 32 of the first modified example includes a waveform data ROM 11 in which 16-bit waveform data including a sign bit obtained by digitally converting a sine wave signal is stored, and a sign bit. A level setter 12 in which 18-bit multiplier data for setting the level of waveform data, including (the sign bit is always set to 0), and waveform data read from the waveform data ROM 11 are included. A multiplier 13 for multiplying the multiplier data output from the level setter 12 and an adder 14 for adding the output from the addition data setting circuit 15 for rounding the multiplication result by the multiplier 13 as an addition number are provided. The output of the upper 16 bits is taken out from the adder 14.

Further, the addition data setting circuit 15 uses 00
The register 16 in which 003 (H) is registered, and 00001
The register 17 in which (H) is registered and the register 16 in which the sign bit of the multiplication result is 0 is selected, and the register 17 in which the sign bit of the multiplication result is 1 is selected. The selector 18, the register 19 in which 000000 (H) is registered, and the output of the selector 18 is selected when the multiplier data set in the level setter 12 is not 0 dB (= × 1), and the multiplier data is 0 dB. In this case, a selector 20 for selecting the register number of the register 19 is provided, and the output of the selector 20 is supplied to the adder 14 as an addition number to be added to the multiplication result.

Here, a register 19 and a selector 20 are provided, and when the multiplier data is 0 dB, the register number 000000 (H) of the register 19 is multiplied by the multiplier 13 via the selector 20.
The addition with the multiplication output output from is that when the multiplier data is 0 dB, the waveform data stored in the waveform data ROM 11 is output as it is, and rounding is not necessary.

Data 00003 (H) for rounding off the last digit when the upper 16 bits in the output of the multiplication result are represented by a decimal number are stored in the registers 16 and 17 selected based on the sign bit of the multiplication result. ), 00001
(H) is registered.

Data multiplication device 3 configured as described above
2, the waveform data stored in the waveform data ROM 11 and the multiplier data set in the level setting unit 12 are multiplied by the multiplier 13, and the effective bit of the multiplication output is sent to the adder 14 and the adder 14 Data generator 1 at
It is added with the number of additions output from 5.

The values stored in the registers 16 and 17 in the data multiplication device 32 are obtained in the same manner as in the case of 24-bit output.

As a result, the register 18 or the register 17 is selected by the selector 18 on the basis of the sign bit of the multiplication result, is added to the multiplication output in the adder 14, and the upper 16 bits of the addition output are taken out. Rounded data is obtained. When the multiplication data is 0 dB, the register number of the register 19 is selected, and the upper 16 bits of the multiplication result are output as they are.

In the data multiplying device 32 described above, the case where the 18-bit multiplier data including the sign bit is set in the level setter 12 has been exemplified, but the 17-bit multiplier data including the sign bit is set in the level setter 12. It does not matter if you set.

Next, a second modified example of the data multiplication device according to the embodiment of the present invention will be described.

FIG. 3 is a block diagram showing the configuration of a second modification of the data multiplication device according to the embodiment of the present invention.

A second modified example of the data multiplication device according to the embodiment of the present invention exemplifies a case where 24-bit output and 16-bit output are selected to enable output.

As shown in FIG. 3, the data multiplying device 33 of the second modified example includes a waveform data ROM 1 in which 24-bit waveform data including a sign bit obtained by digitally converting a sine wave signal is stored, and a sign bit. Level setting device 2 in which 26-bit multiplier data for setting the level of waveform data, including (the sign bit is always set to 0), and waveform data read from waveform data ROM 1 A multiplier 3 for multiplying the multiplier data output from the level setting device 2; an adder 4 for adding the output from the addition data setting circuit 30 for rounding the multiplication result by the multiplier 3 as an addition number; A selector 29 for selecting and outputting the upper 24 bits and the upper 16 bits in the output of the container 4; Take out the output of Tsu door.

The addition data setting circuit 30 has 000000
Register 6 in which 3 (H) is registered, and 0000001
(H) is a register 7 having a register number, and when the sign bit of the multiplication result is 0, the register number of the register 6 is selected, and when the sign bit of the multiplication result is 1, the register number of the register 7 is selected. Selector 8, register 22 in which 0000200 (H) is registered, register 23 in which 00001FF (H) is registered, and the register of register 22 is selected when the sign bit of the multiplication result is 0, and multiplication is performed. The selector 24 that selects the register number of the register 23 when the resulting sign bit is 1, and the selector 2 that selects the output of the selector 8 when the 24-bit output is selected and the selector 2 when the 16-bit output is selected.
And a selector 25 for selecting the output of No. 4 of FIG.

The addition data setting circuit 30 further adds 00
When the 16-bit output is selected and the register 26 in which 00000 (H) is registered, the higher order of the multiplication result output from the multiplier 3 is 8000 (H) or 7FF.
When the comparator 27 detects the coincidence with F (H) and produces an output, and when the comparator 27 produces an output,
Or 24-bit output is selected and level setter 2
When the multiplication data set in step 2 is 0 dB, the register number of the register 26 is selected, otherwise the selector 25 is selected.
And a selector 28 for selecting the output of
The output of 8 is supplied to the adder 4 as an addition number and added with the multiplication result.

Here, a comparator 27, a register 26 and a selector 28 are provided, and when the 24-bit output is selected and the multiplier data is 0 dB, the register number 0000000 (H) of the register 26 is multiplied via the selector 28. When the 24-bit output is selected and the multiplier data is 0 dB, the waveform data ROM1 is added to the multiplication result output from 3
This is because the waveform data stored in is output as it is, and it is not necessary to round it off, and the multiplication output is output as it is.

Further, when the 16-bit output is selected and the higher order of the multiplication result output from the multiplier 3 matches 8000 (H) or 7FFF (H), the maximum value of the 16-bit output or For the minimum value,
This is detected by the comparator 27, and the register number of the register 26 is selected at this time. It is not necessary to round off when the multiplication result is the maximum value or the minimum value of the 16-bit output when the 16-bit output is selected. This is because the multiplication output is output as it is.

Registers 6 and 7, which are selected based on the sign bit of the multiplication result, have the upper two bits in the output of the multiplication result.
Data for rounding off the last digit when four bits are represented by a decimal number 00000003 (H), 00000
The number 01 (H) is registered. This is the data multiplication device 31
It is similar to the case of.

Data 0000200 (H) for rounding off the last digit when the upper 16 bits in the output of the multiplication result are represented by a decimal number are stored in the registers 22 and 23 selected based on the sign bit of the multiplication result. ), 000
01FF (H) is registered. This value is for 16-bit output. Register 1 in the case of the data multiplier 32.
It differs from the numbers 6 and 17. This is because the waveform data ROM1 stores 24-bit waveform data.
This is because the calculation is performed based on the 4-bit waveform data and the output is a 16-bit output.

Data multiplication device 3 configured as described above
3, the waveform data stored in the waveform data ROM 1 and the multiplier data set in the level setter 2 are multiplied by the multiplier 3, and the effective bit of the multiplication output is sent to the adder 4 and the adder 4 In, the sum is added to the number of additions output from the data generator 5, and the upper 24 bits or the upper 16 bits of the addition result are selected and output.

Next, the registers 6 and 7 selected when the 24-bit output is selected by the selector 29.
Since the register number of is the same as that of the data multiplication device 31, the description thereof is omitted. The numbers of the registers 22 and 23 selected when the 16-bit output is selected by the selector 29 will be described.

Even when 16-bit output is selected by the selector 29, the waveform data stored in the waveform data ROM 1 is 24 bits, for example 800
000 (H), the multiplier data set in the level setting unit 2 is 26 bits (= sign bit 1 + valid bit 25), for example, 000010A (H), the multiplication result by the multiplier 3 is 50 bits, For example, 3FFFF7B
26 bits FFFF7B0 (H) from bit 47 to bit 22 are extracted as valid bits and sent to the adder 4.

The number of additions output from the addition data setting circuit 5 is 26 bits, and for example, 0007FC (H),
The addition result by the adder 14 is 26 bits, for example, FFFFFAC (H), and the higher-order 2 as the addition output.
4-bit FFFFFA (H) is extracted.

Here, the multiplier data is the lower 26 bits of 28 bits, but is represented by 28 bits for easy understanding. The effective bit, the number of additions, and the addition result are expressed in 28 bits for the purpose of easy understanding.
6 bits are used for the operation.

Next, when the selector 29 selects 16-bit output data, the number of additions output from the addition data setting circuit 30, that is, the registers 22 and 2.
The number of 3 will be described. The result of multiplication is 0.
Multiplier data that becomes 5 is obtained by the following equation (7).

20 × log (0.5 / 8000 (H)) = 20 × log (0.5 / 32768) = − 96.33 dB (7) Therefore, the multiplier data (level dB) is −96.3d.
When B, the value after rounding is 0001 (H) and FFF
It becomes F (H), and when -96.4 dB, it is necessary to find the number of additions for rounding so that the value after rounding becomes 0000 (H). Here, the reason why -96.3 dB and -96.4 dB are used instead of -96.33 dB is that the multiplier data by the level setting device 2 can be set to one digit after the decimal point in dB display.

Therefore, the maximum value of the waveform data (7FF
When the multiplier data is −96.33 dB with respect to FFF (H)) and the minimum value (800000 (H)), the multiplication results are as shown in Expressions (8) and (9).

7FFFFF (H) × 0000100 (H) = 000007FFFFF00 (H) (8) 800000 (H) × 0000100 (H) = 3FFFF80000000 (H) (9) where the multiplier data 0000100 (H) is − 96.3
This is multiplier data when the level is 3 dB.

Next, when the upper 16 bits are taken, 0001 (H) and FFFF (H) are represented by 48 bits.
(H) and FFFFFFFFFFFF (H) are respectively based on the values of the following equations (10) and (11), which are values obtained by subtracting the values obtained by removing the upper 4 bits from the values of equations (8) and (9), respectively. The value becomes the addition number.

0000100000000 (H) -00007FFFFF00 (H) = 0000800000100 (H) (10) FFFFFFFFFFFF (H) -FFFF80000000 (H) = 00007FFFFFFF (H) (11), and when the sign bit is 0, the number of additions Is 00008
0000100 (H) or higher, 00018000100
It must be less than (H), and when the sign bit is 1, the number of additions must be 00007FFFFFFF (H) or less.

The above value is a 48-bit value, and is 26
In order to satisfy the condition with bits, when the sign bit is 0, the upper 26 bits of 000100000000 (H) 0000 0000 0000 0001 0000 0000 00 (B) to the upper 26 bits of 00007FFFFFFF (H) 0000 0000 0000 0000 0111 1111 The value obtained by subtracting 11 (B) is 0000 0000 0000 0000 1000 1000 0000 00 (B). If this is shown in hexadecimal from the lower bit, 000
It becomes 0200 (H), which is the number of additions when the sign bit is 0. This is registered in the register 22.

Similarly, when the sign bit is 1, the upper 26 bits 1111 1111 1111 1111 1111 1111 11 (B) of FFFFFFFFFFFF (H) to the upper 26 bits 1111 1111 1111 1111 1111 1111 11 (B) of FFFF80000000 (H). The value is 0000 0000 0000 0000 0111 1111 11 (B). If this is shown in hexadecimal from the lower bit, 000
01FF (H), which is the number of additions when the sign bit is 1. This is registered in the register 23.

Therefore, when the output of 24 bits is selected by the selector 29 and the multiplication data set by the level setter 2 is not 0 dB, the register 6 or the register 6 is selected based on the sign bit of the multiplication result of the multiplier 3. The register number 7 is selected by the selector 8 and supplied to the adder 4 via the selectors 25 and 28, and is added to the multiplication output in the adder 4 to obtain the higher 24 of the addition output.
The bits are taken out to obtain rounded data.

When the output of 24 bits is selected by the selector 29 and the multiplication data set by the level setter 2 is 0 dB, the register number of the register 26 is selected by the selector 28 and supplied to the adder 4. Are added to the multiplication output in the adder 4, and the higher 2 of the addition output
Waveform data ROM by extracting 4 bits
The data of 1 is output as it is.

When the selector 29 selects the output of 16 bits and the comparator 27 detects that the upper bit of the output of the multiplier 3 is not 8000 (H) or 7FFF (H), the multiplier 3 outputs. The register 24 or the register 23 is selected by the selector 24 based on the sign bit of the multiplication result, is supplied to the adder 4 via the selectors 25 and 28, and is added to the multiplication output in the adder 4 to obtain the addition output. The upper 16 bits of are taken out to obtain rounded data.

The selector 29 selects the output of 16 bits, and the comparator 27 sets the upper bit of the output of the multiplier 3 to 8000 (H) or 7FFF.
When it is detected to be (H), the register 26 register number is selected by the selector 28 and supplied to the adder 4, and is added to the multiplication output in the adder 4 to extract the upper 16 bits of the addition output. As a result, the data in the waveform data ROM 1 is output as it is.

In the data multiplying device 33 described above, the case where 26-bit multiplier data including a sign bit is set in the level setter 2 has been exemplified, but 25-bit multiplier data including a sign bit is set in the level setter 2. It does not matter if you set.

[0079]

As described above, according to the data multiplying apparatus of the present invention, it is possible to obtain the result of rounding when the output data is 16 bits and 24 bits with a simple structure. The effect is obtained. Further, according to the data multiplication device of the present invention, it is possible to obtain a more accurate calculation result than in the case of truncation. Further, in the data multiplying device according to the present invention, when 24 bits and 16 bits can be selected as output data, even when 16 bits are required for the output data, 2
Since it is multiplied by 4 bits, the calculation error can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data multiplication device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a first modification of the data multiplication device according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a second modified example of the data multiplication device according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional data multiplication device.

[Explanation of symbols]

1 and 11 Waveform data ROM 2 and 12 Level setting device 3 and 13 Multiplier 4 and 14 Adder 5, 15 and 30 Addition data setting circuit 6, 7, 9, 10, 16, 17, 19, 22, 23 and 26 Registers 8, 10, 18, 20, 24, 25 and 28 Selectors 31, 32 and 33 Data multiplication device

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Claims (4)

(57) [Claims] 1.Data multiplier used for signal generator
There Signed with 2's complement that digitally converted analog waveform
Waveform data RO that stores the waveform data in binary notation
M and Waveforms including sign bit and stored in waveform data ROM
Bits that are at least 1 more than the number of bits of data
A level setter to which the multiplier value of the number is set, Waveform data and level read from waveform data ROM
A multiplier that multiplies the multiplier value set in the setter, Rounded based on the sign bit of the multiplication result by the multiplier
First and second regis with data for
And the first or second based on the sign bit of the multiplication result
And a selector for selecting the register number
An addition data setting circuit that outputs the data from Use the data output from the addition data setting circuit as the addition value.
Equipped with an adder that adds to the multiplication result by
The output data of a predetermined number of upper bits is transmitted.
Data multiplication device. 2. The data multiplication device according to claim 1, wherein
The addition data setting circuit causes the level setting device to display the waveform data RO
Data multiplication comprising means for sending out an added value of a numerical value of 0 instead of an output from a selector when a multiplier value for outputting the waveform data stored in M as it is is set. apparatus. 3. The number of bits of output data is 24 bits and 16 bits.
A data multiplication device for use in a signal generation device capable of selecting any of the bits, wherein 24-bit waveform data represented by a binary number with a sign by 2's complement obtained by digitally converting an analog waveform is stored. Waveform data ROM, a level setter for setting a multiplier value of the number of bits including the sign bit, which is at least 1 bit larger than the number of bits of the waveform data stored in the waveform data ROM, and read from the waveform data ROM. The multiplier for multiplying the waveform data and the multiplier value set in the level setter, and when the number of bits of the output data is 24 bits, the data for rounding based on the sign bit of the multiplication result by the multiplier is registered. The first and second registers are rounded off based on the sign bit of the multiplication result by the multiplier when the number of bits of output data is 16 bits. Third and fourth registers in which the data for registering are registered, and a first selector that selects the register in the first or second register based on the sign bit of the multiplication result when the number of bits of the output data is 24 bits, A second selector that selects the register number of the third or fourth register based on the sign bit of the multiplication result when the number of bits of output data is 16 bits, and an output from the first selector when the number of bits of output data is 24 bits When is selected and the number of bits of output data is 16 bits, the second
A third selector for selecting an output from the selector,
An addition data setting circuit that outputs the data from the third selector and an adder that adds the data output from the addition data setting circuit to the multiplication result as an addition value are provided, and the number of output bits of 24 bits and 16 bits is increased. On the basis of the addition output, a predetermined upper 24 bits or upper 16 bits of output data is sent out based on the above. 4. The data multiplication device according to claim 3,
The addition data setting circuit is used when the multiplier for setting the level setter to output the waveform data stored in the waveform data ROM as it is when the number of bits of the output data is 24 bits, or when the bit of the output data is set. Number is 16
In the case of bits and when the predetermined upper 16 bits of the multiplication result is 7FFF (H) or 8000 (H), it is provided with a means for substantially changing the output from the third selector and transmitting the addition value of the numerical value 0. A data multiplication device characterized by the above.