JP3499056B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having two or more layers disposed above a semiconductor substrate and a method of manufacturing the same. 2. Description of the Related Art EEPROMs are known as nonvolatile memories. FIG. 3 shows a part of a process flow of a conventional EEPROM manufacturing process. As shown in FIG. 3A,
First, a gate oxide film 4, a polysilicon film 6, an ONO film 8, and a polysilicon film 10 are formed on a semiconductor substrate 2 in this order. [0003] Next, as shown in FIGS. 3B and 4A, after a resist 12 is patterned on the polysilicon film 10, the polysilicon film 10, the ONO film 8, and the polysilicon film 6 are anisotropically patterned. Perform an etching step. By performing the anisotropic etching step, the control gate 18, the interlayer film 16, and the floating gate 14 are formed.
To form [0004] As the anisotropic etching process proceeds, side protection films 28 are formed on the side surfaces of the control gate 18 and the floating gate 14. Therefore, the side surfaces of the control gate 18 and the floating gate 14 are not etched by the isotropic etching performed at the final stage of the anisotropic etching process. For this reason,
The control gate 18 and the floating gate 14 can be formed to have the same width so as to overlap. After completion of the anisotropic etching step, a sidewall 20 is formed, and thereafter, an oxide film 22 and a BPSG2
4. Aluminum wirings 26 are sequentially formed. [0006] However, the conventional EEPROM manufacturing process as described above has the following problems. Since the control gate 18 and the floating gate 14 are formed so as to be overlapped with the same width, the undulation of the BPSG 24 and the aluminum wiring 26 formed via the oxide film 22 becomes steep. Therefore, BPSG2
4 and the coverage of the aluminum wiring 26 is degraded, which may lead to a disconnection accident of the aluminum wiring 26 or the like. The present invention relates to such a conventional EEPRO.
To solve the problems of semiconductor device manufacturing methods such as
It is an object of the present invention to provide a semiconductor device having good coverage of an interlayer insulating film such as G24 and an upper wiring such as an aluminum wiring 26 and a method of manufacturing the semiconductor device. [0008] (1) The semiconductor of the present invention
The method for manufacturing a device includes the steps of: forming a first conductive film above a semiconductor substrate;
Is formed, and a second layer is formed above the first conductor film via an interlayer film.
A second conductor film and a first conductor film
Is etched by an anisotropic etching process,
A semiconductor forming a second conductor layer and a first conductor layer
The method for manufacturing a device, wherein a second step is performed until the interlayer film is exposed.
Etching the conductive film of the anisotropic etching process,
Removal of the sidewall protective film adhered to the etched section of the second conductor film
Then, the interlayer film and the first conductor film are anisotropically etched.
Etching according to the process, isotropic etching process
The etching of the second conductor film having the exposed cross section is advanced.
The width of the second conductor layer is smaller than the width of the first conductor layer.
Formed in such a manner that (2) The semiconductor device of the present invention is a semiconductor device.
First conductive layer, first conductive layer disposed above a plate
A second conductor layer disposed above the first conductor layer via an interlayer film.
In the semiconductor device having
2 is etched by an anisotropic etching process,
The sidewall protective film adhered to the etched section of the second conductor film is removed.
And anisotropically etch the interlayer film and the first conductor film
Etching by process and etching by isotropic etching process
The etching of the second conductor film with the cut section exposed is advanced.
The width of the second conductor layer is smaller than the width of the first conductor layer.
Formed in such a manner that (3) The semiconductor device of the present invention is a semiconductor device.
First conductive layer, first conductive layer disposed above a plate
A second conductor layer disposed above the first conductor layer via an interlayer film.
In the semiconductor device having
Etching the second conductive film, forming the interlayer film and the first conductive film.
Etching and isotropic etching process exposes the etched section
As the etching of the second conductor film is advanced, the second
The width of the conductor layer is smaller than the width of the first conductor layer.
Has been achieved. The semiconductor device according to the present invention is characterized in that the width of at least one layer arranged above is narrower than the width of at least one layer arranged below. Therefore, the BP is further added above the second layer.
When an interlayer insulating film such as SG or an upper wiring such as an aluminum wiring is formed, the undulation of the interlayer insulating film or the upper wiring becomes gentle. That is, the coverage of the interlayer insulating film and the upper wiring is improved. According to the method of manufacturing a semiconductor device of the present invention , the sidewall protective film attached to the etched cross section of the second conductive film formed by the anisotropic etching step is removed, and the first conductive film is formed differently. It is characterized by being etched by an isotropic etching process. Therefore, the etched section of the second conductor film is exposed by removing the side wall protective film attached to the etched section of the second conductor film. On the other hand, in the initial stage of the subsequent anisotropic etching step for the first conductor film, a sidewall protective film is sequentially attached to the etched cross section of the first conductor film. Therefore, the isotropic etching performed at the final stage of the anisotropic etching process for the first conductive film further etches the etched cross section of the second conductive film, while the first conductive film is etched. No further etching is performed on the etched cross section of the conductor film by the sidewall protective film. As a result, at the end of the anisotropic etching step for the first conductor film, the width of the second conductor layer is smaller than the width of the first conductor layer. Therefore, the second
In the case where an interlayer insulating film such as BPSG or an upper wiring such as an aluminum wiring is further formed above the conductor layer of FIG. That is, the coverage of the interlayer insulating film and the upper wiring is improved. FIG. 1B shows a part of a sectional structure of an EEPROM 30 which is a semiconductor device according to an embodiment of the present invention. As shown in FIG.
A gate oxide film 34, a floating gate 36 as a first conductive layer, an interlayer film 38,
A control gate 40 as a second conductor layer is arranged to be stacked in this order, and sidewalls 4 are formed on both sides.
2 and an oxide film 44, BPSG4
6. It is configured by arranging the aluminum wiring 48 so as to be further stacked. The width of the control gate 40 depends on the thickness of the interlayer film 3.
8, a floating gate 36 formed below
Narrower than the width. For this reason, B formed further above
The ups and downs of the PSG 46 and the aluminum wiring 48 are gentle. Therefore, coverage of the BPSG 46 and the aluminum wiring 48 is good. Next, based on FIGS. 2 and 1, EE
A method for manufacturing the PROM 30 will be described. First, as shown in FIG. 2A, a gate oxide film 34 made of a silicon oxide film, a polysilicon film 50 as a first conductor film, an ONO film 52, and a second conductor A polysilicon film 54 as a film is formed so as to be stacked in this order. Next, as shown in FIG. 2B, after a resist 56 is patterned on the polysilicon film 54, the polysilicon film 54 is etched by anisotropic etching using the resist 56 as a mask. By anisotropic etching,
A sidewall protection film (not shown) is sequentially attached to the etched cross section 54a of the polysilicon film 54. The anisotropic etching stops once the ONO film 52 is exposed. Then, the polysilicon film 5
The sidewall protective film attached to the etched cross section 54a of No. 4 is removed by plasma etching, wet etching or the like. Thereby, the etched cross section 54a of the polysilicon film 54 is exposed. Next, as shown in FIG. 1A, the anisotropic etching is restarted, and the ONO is
Etching is performed on the film 52 and the polysilicon film 50. When the anisotropic etching reaches the polysilicon film 50, the sidewall protection film 58 is formed on the etched section 50a of the polysilicon film 50.
Adhere sequentially. On the other hand, since the anisotropic etching has progressed beyond the ONO film 52 to the polysilicon film 50, the etched cross section 54a of the polysilicon film 54 separated from the polysilicon film 50 (see FIG. 2B). In addition, the sidewall protective film does not adhere again. Therefore, the etched section 54 is formed by the isotropic etching performed at the final stage of the anisotropic etching.
The polysilicon film 54 where a is exposed is further etched and becomes narrower. On the other hand, the etching of the polysilicon film 50 having the sidewall protection film 58 adhered to the etched cross section 50a does not proceed further. By this series of steps, the floating gate 36, the interlayer film 38, the control gate 40
Is formed. Next, as shown in FIG. 1B, after forming a sidewall 42, an oxide film 44 is deposited, and a BPSG 46 and an aluminum wiring 48 are stacked in this order.
After removing the resist 56, a silicon oxide film is deposited on the sidewall 42 so as to cover the entire substrate.
It is formed by performing isotropic etching on the deposited silicon oxide film. Thus, the EEPROM 30
Is formed. In the above embodiment, the polysilicon film 50 and the polysilicon film 54 have been described as examples of the first conductor film and the second conductor film. As the second conductor film, a polysilicon film, a polycide film, a silicide film, or the like can be used. Further, as a semiconductor device, an EEPROM 3
Although 0 has been described as an example, the present invention is not limited to the EEPROM.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a part of a manufacturing process of an EEPROM as a semiconductor device according to an embodiment of the present invention. FIG. 2 is a view showing a part of a manufacturing process of an EEPROM which is a semiconductor device according to an embodiment of the present invention; FIG. 3 is a view showing a part of a manufacturing process of a conventional EEPROM. FIG. 4 is a diagram showing a part of a manufacturing process of a conventional EEPROM. [Explanation of Symbols] 36 Floating gate 38 Interlayer film 40 Control gate 46 BPSG 48 ······························································································· ... Resist 58 ... Sidewall protective film

Continuation of the front page (56) References JP-A-5-13775 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/312 H01L 21/314 H01L 21/316 H01L 21 / 318 H01L 21/3205 H01L 21/8247 H01L 27/115

Claims (1)

(57) [Claim 1] A first conductor film is formed above a semiconductor substrate, and a second conductor film is formed above the first conductor film via an interlayer film. And etching the second conductor film and the first conductor film by an anisotropic etching process to form the second conductor layer and the first conductor film.
A method of manufacturing a semiconductor device, comprising: etching a second conductive film by an anisotropic etching process until an interlayer film is exposed; The sidewall protective film attached to the etched section is removed, the interlayer film and the first conductor film are etched by an anisotropic etching step, and the second conductive layer having the etched section exposed by an isotropic etching step. A method of manufacturing a semiconductor device, characterized in that the etching of a body film proceeds so that the width of the second conductive layer is smaller than the width of the first conductive layer.