JP3495754B2 - Solid-state imaging device and control method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for converting an optical image into an electric signal and its control method.

[0002]

2. Description of the Related Art In a conventional image pickup device such as a video camera, a charge amount photoelectrically converted for each pixel is sequentially transferred using a CCD, and each charge amount is guided to a voltage converting means to be converted into a voltage. Is sampled and held to form a continuous electric signal, and then various signal processes (for example, Knee, γ, white balance, matrix process, etc.) are performed in the signal processing circuit. In some cases, the signal processing may be performed by analog-to-digital conversion after sample-holding without performing analog processing and then digital signal processing is performed on the digital data.

Such a technique is disclosed in, for example, Japanese Patent Laid-Open No. 2-28.
It is disclosed in Japanese Patent No. 8691, Japanese Patent Laid-Open No. 2-288696, and the like.

Conventionally, there is an adder for combining and adding a plurality of digital video signals at an arbitrary ratio for the purpose of image quality correction and special effects. Such an adder is constructed as shown in FIG. 14, for example.

In FIG. 14, reference numerals 30, 33 and 38 are coefficient units having coefficient values K1, K2 and K2, 36 is an adder and 37 is a D / A converter. Also, 31, 34, 3
9 and 32, 35, 40 are the coefficient units 30, 33, 3 described above.
8 is a barrel shifter and an adder, which are the components.

In the adder configured as described above, first, referring to FIG. 3A, when two digital video signals A and B are supplied to the coefficient multipliers 30 and 33, the respective signals A and B are changed. For example 13/16 and 3 / respectively
Compressed to 4.

Next, the two digital video signals compressed by the adder 36 are added and combined, converted into an analog signal by the D / A converter 37, and then output.

The coefficient values K1 and K2 of the coefficient units 30 and 33 are obtained by widely known shift and addition. By appropriately setting the shift amounts of the barrel shifters 31 and 34, the input signal is set to two power values (1/2, 1/4).
And 1/16), and by adding the converted outputs by adders 32 and 35, K1 = 13/1
6, the coefficient value of K2 = 3/4 is obtained.

In order to change the coefficient values K1 and K2, it is possible to some extent by selectively switching the shift amounts of the barrel shifters 31 and 34 which are the constituent elements of the coefficient units 30 and 33. , The coefficient value K2 of the coefficient unit 33 is set to 3 / for the purpose of finely adjusting the addition ratio, for example.
When finely changing from 4 (= 96/128) to 95/128, it is necessary to increase the number of barrel shifters 39 and adders 40 as shown in FIG.

[0010]

Information for each pixel of an optical image obtained from a conventional solid-state image pickup device is obtained by repeating charge by a switch circuit of a CCD or a MOS transistor or by long-distance transfer before reaching a signal processing circuit. Going through the process. In this process, the amount of charge is repeatedly stored while being stored as much as possible, or long-distance transfer is performed, but the transfer efficiency cannot be 100%, which causes deterioration of image quality such as S / N deterioration. ing.

In particular, digital signal processing is performed in order to reduce image quality deterioration even if complicated signal processing is performed. However, despite such digital signal processing, analog signal processing is performed in the preceding stage. Due to the charge transfer, the advantages of digital signal processing have not been fully utilized.

Further, in the conventional adder of FIG. 14, in order to change the coefficient value of the coefficient unit finely, it is necessary to greatly increase the number of barrel shifters and adders. Since the number of bits of the barrel shifter and the adder must be increased in order to ensure the calculation accuracy, there is a drawback that the circuit scale and power consumption increase.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a solid-state image pickup device capable of directly obtaining digital data for each pixel and a control method thereof.

[0014]

A feature of the solid-state image pickup device of the present invention is that a first plurality of photoelectric conversion elements arranged vertically and a plurality of photoelectric conversion elements of the first plurality are provided. A second plurality of vertically arranged photoelectric conversion elements arranged in a horizontal direction; and a first plurality of vertically arranged analog-digital conversion means for converting an analog signal into a digital signal. A second plurality of analog-to-digital conversion means arranged in the vertical direction and arranged in the horizontal direction with respect to the first plurality of analog-to-digital conversion means, for converting an analog signal into a digital signal, A first common data bus commonly provided for the first plurality of analog / digital converting means and a common common data bus for the second plurality of analog / digital converting means. The second common data bus and the first plurality of analog-to-digital conversion means selectively output signals to the first common data bus, and the second plurality of analog-to-digital conversions. Selecting means for selectively outputting a signal from the means to the second common data bus, the number of the first plurality of analog-to-digital converting means is the same as the first plurality of photoelectric converting means. The number of the elements is smaller than the number of the elements, and each of the first plurality of analog-digital conversion means is provided in common to the plurality of photoelectric conversion elements included in the first plurality of photoelectric conversion elements. The number of the second plurality of analog-digital conversion means is smaller than the number of the second plurality of photoelectric conversion elements, and each of the second plurality of analog-digital conversion means has the second plurality of photoelectric conversion elements. Photoelectric conversion In that provided in common to a plurality of photoelectric conversion elements included in the child.

Further, a feature of the control method of the solid-state image pickup device of the present invention is that the first plurality of photoelectric conversion elements are arranged vertically, and the first plurality of photoelectric conversion elements are horizontally arranged. A plurality of vertically arranged photoelectric conversion elements arranged in a vertical direction, and a plurality of vertically arranged analog-digital conversion means for converting an analog signal into a digital signal, A second plurality of vertically arranged analog-to-digital converters arranged in a horizontal direction with respect to the first plurality of analog-to-digital converters for converting analog signals into digital signals; A first common data bus commonly provided for the first plurality of analog / digital converting means and a common common data bus for the second plurality of analog / digital converting means. A second common data bus that is, the number of said first plurality of analog-digital conversion means,
Fewer than the first plurality of photoelectric conversion elements, each of the first plurality of analog-to-digital conversion means,
The plurality of photoelectric conversion elements included in the first plurality of photoelectric conversion elements are commonly provided, and the number of the second plurality of analog / digital conversion units is the same as that of the second plurality of photoelectric conversion elements. The solid-state imaging is less than the number of elements, and each of the second plurality of analog-digital conversion means is provided in common to the plurality of photoelectric conversion elements included in the second plurality of photoelectric conversion elements. A method of controlling an element, wherein a signal is selectively output from the first plurality of analog / digital converting means to the first common data bus, and the second plurality of analog / digital converting means outputs the signal. The point is to control so as to selectively output a signal to the second common data bus.

[0016]

According to the present invention, the information of a pixel which has undergone processing such as sub-sampling or addition necessary for signal processing on the image pickup device on a pixel-by-pixel basis is subjected to analog / digital conversion and then output as digital data. By doing so, S / N deterioration due to analog charge transfer can be prevented.

[0017]

[0018]

FIG. 1 shows a first embodiment of the present invention. Figure 1
The subscripts a, b, and c attached to the symbols 1 to 6 in FIG. 1 are for identifying a plurality of blocks or circuit elements having the same function. In the following description of the configuration and operation,
Explanation without the above subscripts, and subscripts a, b, and
An explanation will be given by adding c.

In FIG. 1, 101 is a photoelectric conversion element for converting light into electric charges, 102 is an operational amplifier forming an integrator for integrating the electric charges generated in the photoelectric conversion element 101,
Reference numeral 103 is a capacitor forming the integrator, 104 is a switch for discharging the capacitor 103 to initialize the integrator, and 105 is a reference voltage source of the integrator. 101
Reference numerals 1 _a , 1 _b , and 1 _{c, which} are composed of 105 to 105, are light amount sensors that output a signal according to the integrated amount of the light amount applied to each photoelectric conversion element 101.

Reference numeral 2 is a reference voltage source, 3 is a comparator for comparing the output from the light quantity sensor 1 with the reference voltage of the reference voltage source 2, and the comparator outputs the comparison result. 4 is a value of a clock / data bus 7 which will be described later. A latch 5 for holding the output of the comparator 3 is a read gate for sequentially reading the output of the latch 4 according to the value of an address bus 8 which will be described later. A reference numeral 6 is a decode gate for decoding the address data of the address bus 8. It is an address decoder that generates a control signal.

Reference numeral 7 is a count clock and a clock / data bus of, for example, 4 bits for reading data in the latch 4, and 8 is an address bus for selecting the latch 4 to be read. Although only three photoelectric conversion elements 101 are shown in the figure, a large number of photoelectric conversion elements 101 are actually arranged two-dimensionally.

Next, the operation in the case of taking out an optical image as still image information in the above configuration will be described with reference to the timing chart of FIG.

First, S1, S2, the diaphragm, and the mechanical shutter in FIG. 2 will be described. S1 is an output waveform of a switch (“H” when ON) which is turned on by operating the first stroke of the release button (not shown), and S2 is a switch (O which is turned on by operating the second stroke of the release button).
The output waveform of N is "H"), the diaphragm is a waveform showing the operation of the optical diaphragm, and the normal state (the lowest level in the figure) is open,
At the time of image capturing, the aperture value is narrowed down to a predetermined aperture value (rising in the figure), and at the end of imaging, the initial open position is restored (falling in the figure). The overshoot after rising in the figure is due to inertia when the diaphragm blade is stopped at a predetermined shift value.

The mechanical shutter indicates the operation of a shutter such as a focal plane shutter, and the lowest level in the drawing indicates the closed state and the highest level indicates the open state.

First, when S1 is turned on, the brightness of the subject is measured by a known photometric sensor, and the aperture value and the exposure time are calculated so as to give a necessary and sufficient amount of light to the image plane on which the photoelectric conversion elements 101 are arranged. To do. Next, when S2 is turned on, first the aperture is stopped down to the aperture value calculated while only S1 is on.

Next, the reset switch 104 of the integrator is turned off.
Open from N to OFF to reset the integral and open the mechanical shutter. As a result, each photoelectric conversion element 101
The subject image is radiated on, and the integration of photoelectrons for each pixel starts.

When the calculated exposure time elapses while S1 is ON, the mechanical shutter is closed and exposure, that is, integration of photoelectrons for each pixel is stopped. The state of integration for each pixel at this time, that is, the output of each integrator is shown in Co of FIG.
mp a in, Comp b in, Comp c in.

Next, after the mechanical shutter is closed, uniform white light (auxiliary light in FIG. 2) is applied to the surface on which the photoelectric conversion element group is arranged on the back side of the mechanical shutter as viewed from the subject side. Clock / Data bus 7
The value of 4 bits is decremented at regular time intervals (clock / data 0, 1, 2, 3 in FIG. 2). At this time, the address bus 8 is kept in a state of an address that does not exist (address 000 in the example of FIG. 2), and the read gate 5
All outputs are in high impedance state.

As described above, when the uniform white light is irradiated, the light quantity sensor 1 group again performs integration of photoelectrons for each pixel. The comparator 3 compares the output of the light amount sensor 1 group with the reference voltage of the reference voltage source 2 and outputs the output voltage of the light amount sensor 1 group (Comp a, b, c in in FIG. 2) to the reference voltage (Comp a in FIG. 2). ,
When it becomes higher than the level of the one-dot chain line added to b and c in), the output of the comparator 3 is set to “H” (Co in FIG. 2).
mp a out, Comp b out, Comp c ont). Comparator 3
The latch 4 latches the value of the clock / data bus 7 at that time by the rising edge of the output of.

[0030] In the example of FIG. 2, the output of the comparator 3 _a state of the clock / data bus 7 is "H" when the 0010 latch 4 _a holds 0010, the comparator 3 _b output Is clock / data bus 7
Since it is "H" when the state is 1100, the latch 4 _b holds 1100. Similarly, the latch 4 _c holds 1001. Then, when the clock / data bus 7 decrements to 0000, the counting operation (decrement operation of the clock / data bus 7) is stopped, and the irradiation of the auxiliary light to the light quantity sensor 1 group is stopped.

After that, the drive circuit of the clock / data bus 7 is set to the high impedance state (HiZ in FIG. 2), and the value of the address bus 8 is set to the address corresponding to the light quantity sensor 1 to be read. In the example of FIG. 2, this address is simply incremented as 001, 010, 011, 100, ....

As a result, the designated address decoder 6
The read gate 5 is opened by the signal output from
The data in the latch 4 at the designated address can be read out via the clock / data bus 7. In the example of Figure 2 by sequentially changing the value of the address bus 8 which is held in the latch circuit _{4 a, 4 b, 4 c} 0010,110
Data of 0, 1001 and addresses 001, 010, 01
1 corresponds to each other _{, and} the contents of each latch 4 _a, 4 _b, 4 c can be read.

Although a photoelectric conversion element, an integrator, and a comparator are used as the light quantity sensor 1 in this embodiment, a large number of potential wells having uniform charge capacities such as CCD are formed and each well is formed. The same function can be realized by providing a means for detecting the overflow of electric charges and knowing that a certain amount of light has been integrated.

Considering the photoelectric conversion efficiency of the subject image, it is desirable to cover the image forming surface of the solid-state image pickup element only with the photoelectric conversion element 101. In that case, other latches, buses, etc. will be provided in a place other than the image plane. In other words, it can be said that a three-dimensional integrated circuit in which the components other than the light receiving portion are arranged in the depth direction with respect to the image plane is desirable.

Further, although the clock / data bus 7 and the address bus 8 are separately provided in this embodiment, it goes without saying that the number of wirings can be reduced by using them both.

FIG. 3 is a block diagram showing the second embodiment, and FIG. 4 is a timing chart for explaining the operation.

The light amount sensor 1 _a to 1 _e in FIG. 3 FIG. 1
It has the same configuration as that of. Reference numeral 10 denotes a sample-and-hold circuit (hereinafter referred to as S / H circuit) that samples and holds the output of the light amount sensor 1 by a control signal, 107 denotes a switch that is turned on / off by the control signal and samples the output of the light amount sensor 1, 108 Is a capacitor that holds the output of the sampled light amount sensor 1, and 11 is S
AD converter (hereinafter referred to as ADC) for digitizing the output of the light amount sensor 1 held by the / H circuit 10, 12 is an ADC
It is a shift register that performs parallel / serial conversion by inputting and holding the output of 11 in bit parallel and outputting in bit serial according to a clock.

The operation of the above configuration will be described with reference to FIG. The functions of S1, S2 and the diaphragm in FIG. 4 are the same as those in FIG.

The process is the same as that of the first embodiment until S1 is turned on, the aperture and the exposure time are calculated, and until S2 is turned on until the aperture value calculated previously is narrowed down.

Next, integration is started by opening the reset switch 104 of the integrator. In the case of this embodiment, since the mechanical shutter is not provided, the reset switch 10
4, the exposure is started. The exposure time is counted from this time, and when the exposure time has elapsed, the S / H circuit 10 is given a control signal for performing a sampling operation to perform sampling. The output value of the light amount sensor 1 at the time when the control signal is given is held so that the effect of the subject image with which the light amount sensor 1 is irradiated can be avoided. By this operation, the exposure time when there is no mechanical shutter can be controlled.

After the above sampling, when the S / H circuit 10 enters the hold state, the AD conversion operation by the ADC 11 starts. Since the AD conversion here is performed on the output of the S / H circuit 10, the AD conversion speed is arbitrary.
Therefore, although the image signal is handled, the successive approximation ADC
Can be used. After the time required for AD conversion has elapsed, the load signal LOAD is added to the shift register 12. ADC 11 when this signal LOAD is added
The output of the above is latched in the shift register 12.

Next, when the shift clock SCLK is applied to the shift register 12, all the data in the shift register 12 connected in series can be read from one output of the shift register at the final stage.

Since the S / H circuit 10 is provided in this embodiment,
Although it has been stated that the conversion speed of the ADC 11 is arbitrary, conversely A
If the conversion speed of the DC 11 is sufficiently high and the amount of change in the output of the light amount sensor 1 during the conversion period is negligible even in the light amount sensor 1 corresponding to the high brightness portion of the subject image, the S / H circuit 10 may be omitted. The good news is clear.

FIG. 5 shows a third embodiment, which is different from the first embodiment in the following two points. That is, in the first embodiment, after the light is blocked by the mechanical shutter, the time until the integrated value in the integrator becomes a constant value by the auxiliary light (reintegration operation time) is counted. The first difference is that the electric charge to be re-integrated until is reached by using the current source 106 that is switched by the switches 111 to 114 instead of the auxiliary light.

The second difference is that, when reading the value of the clock / data bus 7 latched by the output of the comparator 3, the latch 4 is connected in parallel and read in parallel. To this end, the multiplexer (MPX) 1
3, 14 and control lines 15, 16 are provided.

Next, a schematic operation will be described with reference to FIG. When S2 is turned on, the operation until the aperture is stopped down to the predetermined value is the same as in the first and second embodiments. When the aperture reaches a predetermined value, the switch 114 that resets the photoelectric conversion element 101 is turned off to turn on the photoelectric conversion element 1.
The accumulation of charges in the junction capacitance of 01 is started. At this time,
Switch 11 for connecting photoelectric conversion element 101 to an integrator
2, 113 and the switch 111 that connects the current source 106 at the time of re-integration to the integrator are OFF, and the reset switch 104 of the integrator is ON.

When the exposure time calculated while the S1 is ON from the start of exposure elapses, the switch 104 is turned off and the switch 104 is turned off in order to transfer the charge accumulated in the junction capacitance of the photoelectric conversion element 101 to the integrator. 112, 113
Turn on. The charges in the photoelectric conversion element 101 are transferred to the integrator, and when the transfer is completed, the switches 112 and 113 are immediately turned off. At about the same time as this, the photoelectric conversion element 101
The switch 114 for resetting is turned on. This is for the following reason.

Since this embodiment does not have a mechanical shutter as in the case of the second embodiment, the photoelectric conversion element 10 remains even after the end of exposure.
1 is continuously exposed to light. Therefore, when the photoelectric conversion element 101 generates a charge exceeding the junction capacitance of itself, the charge may leak to other portions on the element and may have an adverse effect. To avoid this, the switch 114 is turned on. In this case, it is obvious that the anode and cathode of the device may be grounded instead of being short-circuited.

Next, the current source 106 re-integrates the integrator and decrements the clock / data bus 7. At this time, the count / read control line 15 is "L", and the MPX 13 is in a state of connecting the output of the comparator 3 to the load terminal of the latch 4 and the MPX 14 is connecting the clock / data bus 7 to the data input terminal of the latch 4. ing. Therefore, the output of the comparator 3 becomes "H" when the reintegration value becomes a constant value (the one-dot chain line added to COMP a to d in in FIG. 6) as in the first embodiment, and this edge causes The value of the clock / data bus 7 is taken into the latch 4. When the value of the clock / data bus 7 is decremented to zero, the countdown is stopped and the current injection by the current source 106 to the integrator is stopped.

Then, the control line 15 is set to "H" to set MPX.
13 and MPX 14 are switched to connect the shift clock control line 16 to the load terminal of the latch 4, and connect the output of the latch 4 to the input of the latch 4 in the next stage. When a data shift pulse is applied to the control line 16 in this state, the data in each latch 4 is output to the series in bit parallel in this figure.

FIG. 7 shows a fourth embodiment, and FIG. 8 is a timing chart showing its operation. As a method for digitizing the output of the light amount sensor 1, sample-and-hold is performed and AD conversion is performed as in the second embodiment.

As a method for reading out the digitized data, the data at an arbitrary address is read out by placing the necessary data on the data bus line 19 by addressing as in the first embodiment. Therefore, the description of the operation of digitizing the output of the light amount sensor 1 and the operation of reading the digitized data will be omitted.

The difference between the fourth embodiment and the other embodiments is as follows. That is, the output of the light amount sensor 1 is added by the addition & S / H circuit 17 by 2 pixels in the vertical direction via the switch 18 controlled by the field controller 20, and then AD conversion is performed by the ADC 11. The difference is that the field interlaced reading can be performed from the reading gate 23 controlled by the load circuit 21 by changing the combination of two pixels that add this operation for each screen.

There is also a difference in the wiring of the address lines in FIGS. 7 and 1. In FIG. 7, the address line controlled by the read address controller 22 for one pixel (in this example, one pixel is added) is a vertical V line according to the addresses v _n and h _n of each light amount sensor 1. ₀ , V
₁ and horizontal H ₀ and H ₁ are advantageous in designing the device. In the first embodiment of FIG. 1, since it is necessary to wire all address lines for all pixels, for example, about 26
Eighteen address lines are required for an image sensor of 10,000 pixels. Further, in FIG. 1, an address decoder for all address lines is also required for each pixel.

In the fourth embodiment, the output of the read address controller 22 of FIG. 8 shows the address (capital letter) for the data after addition, as can be easily seen from FIG.

FIG. 9 shows the fifth embodiment, and the digitized signal reading method is the same as that of the first embodiment. The capacitor 10 after sample-and-holding the charge injection of the integrator of the light quantity sensor 1 in the third embodiment
8 is different from that of the third embodiment.

Other Modifications In each of the above embodiments, the output of the light amount sensor is digitized by counting the time until the overflow or a predetermined level after re-integration after exposure, shading or sample-and-hold. , The same result can be obtained even if instead of re-integrating, discharging is performed by decreasing the charge at a constant rate and the time until the charge becomes zero (the voltage becomes less than a predetermined voltage) is measured. To be In that case, it is better to count up the time from the start of discharge.

In the second and fourth embodiments, nondestructive read-out is possible at any necessary timing even during the exposure, which has the advantage that real-time photometry is possible.

In the second and fourth embodiments, the ADC 11
By making the value of the reference resistance string of the above non-linear, the object can be digitized non-linearly in order to obtain the characteristics of γ and Knee. Furthermore, in other embodiments, the intervals of the clocks for counting the time are unequal. The same effect can be obtained by setting the intervals. Further, the same effect can be obtained by discharging a part of the electric charges that are being accumulated in the photoelectric conversion element 101 and the integrator during the accumulation period.

Sixth embodiment to ninth embodiment shown in FIGS. 10 to 13.
In this embodiment, an adding device to which a digital signal is input will be described.

In FIG. 10, reference numerals 41 and 42 denote switch circuits each composed of a plurality of switches 43 which are switch-controlled by the digital data of the digital video signals A and B, respectively. 44 and 45 are switch circuits 41 and 4, respectively.
2 is a current source circuit composed of a plurality of current sources 46 which are connected to one end of 2 and whose current is controlled by current control signals A and B from the outside. 47 is a switch circuit 4
It is a resistance circuit composed of a plurality of resistors 48, 49 connected to the other ends of 1, 42. 50 is an analog signal output terminal.

Next, the operation will be described. The digital data (for example, 8 bits of D17 to D10) of the digital video signal A input to the switch circuit 41 controls the switch 43, which is a constituent element of the switch circuit 41, according to the data. Since the current source circuit 44 is connected to one end of the switch circuit 41, the switch circuit 41 operates together with the current source circuit 44 as a current switch that controls the current supply to the load according to the data of the digital video signal A. Here, the load is the resistance circuit 47 connected to the other end of the switch circuit 41.

The resistor circuits 47 are each R as shown.
And resistors 48 and 49 having a resistance value of 2R, and the current switch described above is connected to the intermediate tap thereof. In this resistance circuit 47, the impedance is equal to 2R regardless of which direction the resistors 48 and 49 connected to which intermediate tap are viewed, as is generally known as the R-2R resistance network. ,
Current having a value equal J which is controlled by each bit of the digital data of the digital video signal A is binary weighted according to each bit in the analog signal output terminal ^{50 (2 0/3 × J~2} -7 / 3 × J), and flows through the resistor 49 connected to the analog signal output terminal 50, so that a voltage proportional to the digital value of the digital video signal A is output.

On the other hand, another current switch similar to the above-mentioned current switch is connected to the resistance circuit 47. That is, it is a current switch including a switch circuit 42 and a current source circuit 45 which are controlled by the digital data of the digital video signal B (8 bits of D27 to D20).

These two current switches share the resistance circuit 47 as a load. In this case as well, due to the property of the resistance circuit 47 described above, the current controlled by each bit of the data of the digital video signal B is distributed by each bit so as to be binary weighted, and the analog signal output is performed. It flows through the resistor 49 connected to the terminal 50. At this time, the digital video signal A has already been
Since the distribution current due to the current is flowing, the current controlled by the digital video signals A and B is distributed by the resistance circuit 47 so as to be binary weighted independently. As a result, the voltage obtained by adding the digital values represented by the video digital signals A and B is output as an analog video signal.

The current source circuits 44 and 45 are constructed so that the current value can be continuously controlled by the current control signals A and B, respectively, and the conversion gain at the time of converting the digital value into the analog value (voltage) is obtained. Since each can be controlled continuously, the addition ratio of the digital video signals A and B can be adjusted freely. In the above description, the case where the number of current switches is two is shown as an example, but it goes without saying that a plurality of current switches are generally provided.

FIG. 11 shows a seventh embodiment. In the figure, 41 to 50 are the same as those shown in FIG. 5
1 is resistors 48 and 49 having resistance values of R and 2R, respectively.
And a switch circuit 41,
Two current switches, each composed of 42 and current source circuits 44 and 45, are connected to different terminals as shown in FIG.

Analog signal output terminal 50 of resistance circuit 51
Focusing on, the impedance as viewed in the direction of the resistor 48 having the resistance value R on the right side is 2R, so for the current switch controlled by the digital data of the digital video signal A, the resistance circuit shown in FIG. The load is completely equivalent to 47, and the analog signal output terminal 50
The same is true for the current distributed by the resistor 49 connected to. Similarly, since the impedance of the resistor 48 having a resistance value R on the left side of the analog signal output terminal 50 is 2R, the current distribution by the digital video signal B is also the same. Eventually, the configuration of FIG. 11 is equivalent to that of FIG. 10 in operation and the same effect can be obtained.

FIG. 12 shows the eighth embodiment. In the figure, 41 to 50 are the same as those shown in FIG. 52
Is a switch circuit composed of a switch 43 controlled by the digital data of the digital video signal C, and 53 is a current source circuit composed of a plurality of current sources 46 connected to the switch circuit 52. Reference numeral 54 is a resistance circuit composed of resistors 48 and 49 having resistance values of R and 2R, respectively, and three current switches each composed of switch circuits 41, 42 and 52 and current source circuits 44, 45 and 53. Are connected to different terminals as shown in the figure.

The circuit of FIG. 12 shows an example in which the configuration of FIG. 11 is expanded and three digital video signals A, B and C are added at an arbitrary addition ratio. Impedance in any direction is 2R
Therefore, it can be seen that current distribution is performed in the same manner as described with reference to FIG.

FIG. 13 shows a ninth embodiment. In the figure, 41 and 42 are switch circuits similar to those shown in FIG. 10, 55 and 56 are respectively connected to one ends of the switch circuits 41 and 42, and by a current source 46 which can be controlled by current control signals A and B from the outside. It is a configured current source circuit. However, in the current source circuits 55 and 56, they are connected to the switch 43 which is a constituent element of the switch circuits 41 and 42. The number of current sources 46 is weighted. Reference numeral 57 is a resistance circuit composed of resistors 48, 49, 58 and 59 having weighted resistance values of R, 2R, 4R and 8R, which are connected to the other ends of the switch circuits 41 and 42, respectively.

Next, the operation will be described. As described above, the current source circuit 55 is connected to one end of the switch circuit 41,
Also, by connecting the other end of the switch circuit 41 to the intermediate tap of the resistance circuit 57, the resistance circuit 57 is used as a load,
A current switch is configured to control the current supply to the load according to the digital data of the digital video signal A.

In the resistance circuit 57, the resistance values of the constituent resistors 48, 49, 58 and 59 are binary weighted as shown in the figure, so that switching is performed by the lower bit of the digital video signal A. Each of the controlled currents having the same value J flows through the resistance circuit 57 to generate a binary weighted voltage at the analog signal output terminal 50 according to each bit. Further, regarding the current controlled by the upper 3 bits of the digital video signal A, since the number of the current sources 46 of the current source circuit 55 is binary weighted, the analog signal output terminal 50 is also assigned to each bit. A corresponding binary weighted voltage is generated. As described above, by weighting the resistance value and the current value respectively, a voltage proportional to the digital value indicated by the digital video signal A is output to the analog signal output terminal 50.

On the other hand, the resistance circuit 57 is connected to a current switch composed of a switch circuit 42 and a current source circuit 56 which are controlled by the digital video signal B and have the same configuration as the above-mentioned current switch. Although these two current switches share the resistance circuit 57 as a load, they operate independently of each other, so that a voltage proportional to the digital data indicated by the digital video signal B is applied to the analog signal output terminal 50 as described above. Occur. At this time, since the voltage due to the digital video signal A has already been generated, in the end,
The voltage of the analog video signal generated by adding the digital video signals A and B is generated. Further, the current source circuits 55 and 56 are configured such that the current value can be continuously controlled by the current control signals A and B, respectively, and the conversion gain when converting the digital value into the analog value (voltage) is continuously obtained. Since it can be controlled, the addition ratio of the digital video signals A and B can be adjusted freely.

In this embodiment also, three or more current switches can be provided. According to the sixth to ninth embodiments described above, the plurality of current switches whose currents are controlled by the digital signals are connected to the resistance circuit, so that the plurality of digital signals can be added at any desired addition ratio. It is possible to convert into an analog signal while adding in.
Further, since the current control is possible in a relatively wide range, the dynamic range is wide, and the current switch can be switched at high speed, an adder having excellent frequency characteristics can be obtained. In addition, because of the relatively simple configuration in which a plurality of current switches are provided, it is also advantageous in terms of circuit scale and power consumption.

[0076]

As described above, according to the present invention,
Analog that corresponds to each photoelectric conversion element of the solid-state image sensor
Since the digital conversion means is provided, it is possible to reduce the analog information transmission portion, and thus it is possible to prevent the image quality deterioration due to the analog information transmission.

[0077]

[0078]

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation.

FIG. 3 is a configuration diagram showing a second embodiment.

FIG. 4 is a timing chart showing an operation.

FIG. 5 is a configuration diagram showing a third embodiment.

FIG. 6 is a timing chart showing an operation.

FIG. 7 is a configuration diagram showing a fourth embodiment.

FIG. 8 is a timing chart showing an operation.

FIG. 9 is a configuration diagram showing a fifth embodiment.

FIG. 10 is a configuration diagram showing a sixth embodiment.

FIG. 11 is a configuration diagram showing a seventh embodiment.

FIG. 12 is a configuration diagram showing an eighth embodiment.

FIG. 13 is a configuration diagram showing a ninth embodiment.

FIG. 14 is a block diagram showing a conventional adder.

[Explanation of symbols]

101 photoelectric conversion element 102 operational amplifier 103 capacitor 4 latch 5 readout gate 6 Address decoder 7 clock / data bus 11 AD converter 41, 42 switch circuit 44, 45 Current source circuit 47, 51, 54 resistance circuit 55, 56 Current source circuit 57 resistance circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A 2-60380 (JP, A) JP-A 61-90569 (JP, A) JP-A 5-48460 (JP, A) JP-A 5- 161068 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/335 H03M 1/00-1/88

Claims (4)

(57) [Claims] 1. A first plurality of photoelectric conversion elements arranged in a vertical direction, and a second plurality of photoelectric conversion elements arranged in a horizontal direction with respect to the first plurality of photoelectric conversion elements and arranged in a vertical direction. A photoelectric conversion element; a first plurality of vertically arranged analog-digital conversion means for converting an analog signal into a digital signal; and a first plurality of the above-mentioned first plurality for converting an analog signal into a digital signal Second analog / digital converting means arranged in the vertical direction and arranged in the horizontal direction with respect to the analog / digital converting means, and common to the first plurality of analog / digital converting means. A first common data bus, a second common data bus commonly provided to the second plurality of analog-digital conversion means, and the first plurality of analogs. The digital-to-digital conversion means selectively outputs a signal to the first common data bus, and the second plurality of analog-to-digital conversion means selectively outputs the signal to the second common data bus. The number of the first plurality of analog-digital conversion means is smaller than the number of the first plurality of photoelectric conversion elements,
Each of the first plurality of analog-to-digital conversion means is commonly provided to the plurality of photoelectric conversion elements included in the first plurality of photoelectric conversion elements, and the second plurality of analog The number of digital converting means is the second
Less than the number of photoelectric conversion elements of the second plurality of analog-to-digital conversion means,
And a plurality of photoelectric conversion elements included in the plurality of photoelectric conversion elements. 2. The method according to claim 1, further comprising a plurality of addition output means for adding the signals of the plurality of photoelectric conversion elements and outputting the added signals to the corresponding analog / digital conversion means. Solid-state image sensor. 3. The selecting means selectively outputs a signal from the first plurality of analog-digital converting means to the first common data bus according to a predetermined address designation, and the second common data bus. 3. The solid-state image pickup device according to claim 1, wherein a signal is selectively output from a plurality of analog / digital conversion means to the second common data bus. 4. A first plurality of photoelectric conversion elements arranged in the vertical direction, and a second plurality of photoelectric conversion elements arranged in the horizontal direction with respect to the first plurality of photoelectric conversion elements and arranged in the vertical direction. A photoelectric conversion element; a first plurality of vertically arranged analog-digital conversion means for converting an analog signal into a digital signal; and a first plurality of the above-mentioned first plurality for converting an analog signal into a digital signal Second analog / digital converting means arranged in the vertical direction and arranged in the horizontal direction with respect to the analog / digital converting means, and common to the first plurality of analog / digital converting means. A first common data bus, a second common data bus commonly provided to the second plurality of analog-digital conversion means, and the first plurality of analogs. The number of digital-to-digital conversion means is smaller than the number of the first plurality of photoelectric conversion elements,
Each of the first plurality of analog-digital conversion means is provided in common to the plurality of photoelectric conversion elements included in the first plurality of photoelectric conversion elements, and the second plurality of analog-digital conversion means is provided. The number of digital converting means is the second
Less than the number of photoelectric conversion elements of the second plurality of analog-to-digital conversion means,
A method for controlling a solid-state image sensor provided in common to a plurality of photoelectric conversion elements included in a plurality of photoelectric conversion elements, wherein the first plurality of analog / digital conversion means are selectively operated by the first plurality of analog / digital conversion means. A signal is output to one common data bus, and control is performed so that the signal is selectively output from the second plurality of analog-digital conversion means to the second common data bus. Method for controlling solid-state image sensor.