JP3492342B2 - Inter-block signal relay buffer and its layout method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to power supply of an inter-block signal relay buffer incorporated in a layout block in a semiconductor integrated circuit device (hereinafter referred to as LSI).

[0002]

2. Description of the Related Art In recent years, as the scale of LSI has increased,
In this layout, the signal wiring length between layout blocks becomes long, and the signals between blocks may be attenuated. Therefore, an inter-block signal relay buffer is inserted into a layout block on the signal wiring path between the blocks to perform layout to suppress signal attenuation and perform signal wiring on the shortest path.

An LSI in which a conventional inter-block signal relay buffer is inserted will be described with reference to the drawings. FIG. 8 is a block diagram of a conventional inter-block signal relay buffer.

As shown in the figure, a buffer insertion block 801 is provided on the signal wiring path between the blocks in order to suppress the signal wiring between layout blocks and to perform the signal wiring along the shortest path. 802 is inserted.

However, in the configuration of the conventional inter-block signal relay buffer, the power of the inter-block signal relay buffer 802 inserted in the buffer insertion block 801 is supplied from the power source 803 of the buffer insertion block, so the power source of the buffer insertion block 801 is supplied. When the signal is disconnected, the inter-block signal relay buffer 802 does not operate, so that signal propagation between blocks cannot be performed normally, and there is a problem that the power source of the buffer insertion block 801 alone cannot be controlled.

[0006]

In order to solve the above problems, the inter-block signal relay buffer and the layout method thereof according to the present invention are provided for each layout block while securing the power supply to the inter-block signal relay buffer. The purpose is to realize power supply control.

[0007]

In order to achieve this object, an inter-block signal relay buffer according to claim 1 comprises:
An inter-block signal relay buffer for driving a signal propagating between a plurality of layout blocks in a semiconductor integrated circuit, which belongs to a buffer insertion layout block supplied with power from a first power supply, and which has a power supply other than the buffer insertion layout block. By supplying power from the second power supply that supplies the signal, even if the operation of the buffer insertion layout block is stopped by stopping the supply of the first power supply, It is characterized by being able to drive.

An inter-block signal relay buffer according to a second aspect is an inter-block signal relay buffer that drives a signal propagating between a plurality of layout blocks in a semiconductor integrated circuit, and is supplied with power from a first power supply. Belongs to a buffer insertion layout block, and is supplied with power from a third power supply that supplies power to a signal supply block that supplies a signal to an inter-block signal relay buffer,
Even if the supply of the first power supply is stopped and the operation of the buffer insertion layout block is stopped, the signal propagating between the plurality of layout blocks can be driven.

An inter-block signal relay buffer according to a third aspect is an inter-block signal relay buffer for driving a signal propagating between a plurality of layout blocks in a semiconductor integrated circuit, and is supplied with power from a first power supply. Belonging to a buffer insertion layout block, which supplies power from a fourth power supply which supplies power to a signal reception block which receives a signal from an inter-block signal relay buffer, thereby stopping the supply of the first power Even if the operation of the buffer insertion layout block is stopped, the signal propagating between the plurality of layout blocks can be driven.

According to a fourth aspect of the present invention, there is provided an inter-block signal relay buffer layout method based on an initial hierarchical netlist when laying out an inter-block signal relay buffer received from a layout block other than the layout block to which the power supply of the semiconductor integrated circuit belongs. A step of performing a floor plan of the semiconductor integrated circuit and determining layout positions of layout blocks and wirings between layout blocks; Inserting into a hierarchy to generate a hierarchical netlist for layout, and performing layout within each layout block, and previously setting an arrangement area and a wiring area of the inter-block signal relay buffer for a layout block including inter-block signal relay buffer You And a step of arranging and wiring each of the layout blocks as a top-level layout, arranging the inter-block signal relay buffer in the arranging region, and wiring the power and signals of the inter-block relay buffer in the first-term wiring region. Have.

A layout method of an inter-block signal relay buffer according to a fifth aspect is the layout method of an inter-block signal relay buffer according to the fourth aspect, wherein a layout block including only the inter-block signal relay buffer is formed. It is characterized by performing layout.

An inter-block signal relay buffer according to claim 6 is the inter-block signal relay buffer according to claim 1, 2 or 3, wherein the signal wiring of the inter-block signal relay buffer is: By wiring the second power source in a laminated manner by using a wiring layer different from that of the signal wiring, the signal wiring is shielded and mutual interference of the signal wiring is prevented.

As described above, the power supply control can be realized for each layout block while the power supply to the inter-block signal relay buffer is secured.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An inter-block signal relay buffer and its layout method in an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a conceptual diagram of an inter-block signal relay buffer according to the first embodiment of the present invention. In the figure, the inter-block signal relay buffer 102 is arranged and wired in the buffer insertion block 101. The power supply for the inter-block signal relay buffer 102 is the buffer insertion block power supply 10 that supplies power to the buffer insertion block.
Instead of 3, the power is being supplied to the other blocks or the power 104 that is the power dedicated to the inter-block signal relay buffer 102 is drawn into the buffer insertion block 101 and supplied. Therefore, since the power supply of the inter-block signal relay buffer 102 is different from the power supply supplying the power to the buffer insertion block 101, even if the supply of the buffer insertion block power supply 103 is stopped in order to save power consumption, the inter-block signal The relay buffer 102 is supplied with power from the power source 104, and the inter-block signal relay buffer 102 continues to operate.

FIG. 2 is a conceptual diagram of an inter-block signal relay buffer according to the second embodiment of the present invention. In the figure, the inter-block signal relay buffer 202 is arranged and wired in the buffer insertion block 201. The power supply for the inter-block signal relay buffer 202 is the buffer insertion block power supply 20 that supplies power to the buffer insertion block.
3, the power supply 213 of the signal supply block of the signal supply block 211 in which the inter-block signal supply buffer 212 supplying the signal to the inter-block signal relay buffer 202 is arranged and wired is pulled in and supplied into the buffer insertion block 201. ing. Therefore, the power source of the inter-block signal relay buffer 202 is the buffer insertion block 201.
Since the power is different from the power supplied to the block, the power of the inter-block signal relay buffer 202 is supplied to the inter-block signal supply buffer 212 of the previous stage even if the supply of the buffer insertion block power 203 is stopped to save power consumption. Power is supplied from the power supply 213, and the inter-block signal relay buffer 202 continues to operate.

FIG. 3 is a conceptual diagram of an inter-block signal relay buffer according to the third embodiment of the present invention. In the figure, the inter-block signal relay buffer 302 is arranged and wired in the buffer insertion block 301. The power supply of the inter-block signal relay buffer 302 is the buffer insertion block power supply 30 that supplies power to the buffer insertion block.
3, the signal supply block power supply 323 of the signal reception block 321 in which the inter-block signal reception buffer 322 for relaying the signal by the inter-block signal relay buffer 302 is arranged and wired is pulled in and supplied into the buffer insertion block 301. Therefore, since the power supply of the inter-block signal relay buffer 302 is different from the power supply that supplies power to the buffer insertion block 301, even if the supply of the buffer insertion block power supply 303 is stopped to save power consumption, the inter-block signal The power of the relay buffer 302 is supplied from the power source 323 that supplies power to the inter-block signal reception buffer 322 in the subsequent stage, and the inter-block signal relay buffer 302 continues to operate.

FIG. 4 is a process diagram showing a layout method of an inter-block signal relay buffer according to the fourth embodiment of the present invention, and FIG. 5 is a conceptual diagram of the inter-block signal relay buffer according to the fourth embodiment of the present invention. 4 and FIG. 5, an inter-block signal relay buffer and its layout method in the fourth embodiment will be described.

First, the upper layer layout 5 is created by using the initial layer netlist 401 for laying out the LSI.
The floor plan examination process of 51 is performed (S402), and the arrangement position of the blocks included in the initial hierarchical netlist 401 and the wiring route between the blocks are determined. Next, step S4
In consideration of the arrangement position and the wiring route determined in 02, inter-block signal relay buffer insertion processing is performed for a signal that needs to be relayed in the signal wiring between blocks (S40
3) The initial hierarchical netlist 401 is updated to generate the layout hierarchical netlist 404. By this step, the arrangement position of the blocks, the arrangement position of the inter-block signal relay buffer, and the wiring route between the blocks are determined. Next, a block layout process is performed on the blocks included in the layout hierarchical netlist 404 (S40).
5). At this time, the layout of the buffer insertion block 501 is performed with the relay buffer placement area 541 for placing the inter-block signal relay buffer 502 and the relay buffer wiring area 542 secured in advance. Next, the layout of the completed blocks is arranged, and the inter-block signal relay buffer 502 is arranged on the relay buffer arrangement area 541 of the buffer insertion block 501. The wiring between the completed blocks and the buffer insertion block 502 are arranged. By wiring the relay buffer input signal 505 and the relay buffer output signal 506 on the relay buffer wiring area 542 (S406), the layout of the LSI is completed. At this time, the inter-block signal relay buffer 50
Since the power supply No. 2 is supplied from a power supply 504 different from the buffer insertion block power supply 503 which is supplying power to the buffer insertion block 501, it is assumed that the supply of the buffer insertion block power supply 503 is stopped to save power consumption. Also, the power of the inter-block signal relay buffer 502 is supplied from the power source 504, and the inter-block signal relay buffer 5
02 continues to operate.

FIG. 6 is a process diagram showing a layout method of an inter-block signal relay buffer according to the fifth embodiment of the present invention, and FIG. 7 is a conceptual diagram of the inter-block signal relay buffer according to the fifth embodiment of the present invention. 6 and FIG. 7, an inter-block signal relay buffer and its layout method in the fifth embodiment will be described.

First, the upper layer layout 7 is created by using the initial layer netlist 601 for laying out the LSI.
The floor plan examination process of 51 is performed (S602), and the layout position of the blocks included in the initial hierarchical netlist 601 and the wiring route between the blocks are determined. Next, step S6
The inter-block signal relay buffer 702 is inserted for the signal that needs to be relayed in the signal wiring between the blocks in consideration of the arrangement position and the wiring route determined in 02 (S60).
3). Further, the inserted inter-block signal relay buffer 702 is hierarchized to be a block equivalent to the buffer insertion block 701 (S604), whereby the initial hierarchical netlist 601 is changed and the layout hierarchical netlist 605 is generated. By this step, the arrangement position of the blocks, the arrangement position of the inter-block signal relay buffer, and the wiring route between the blocks are determined. Next, the block layout of the blocks included in the layout hierarchical netlist 605 is performed (S606). At this time, the layout of the buffer insertion block 701 is performed with the relay buffer arrangement area 741 for arranging the signal relay buffer block 752 and the relay buffer wiring area 742 secured in advance, and the layout of the signal relay buffer block 752. Processing is also performed. Next, the layout of the completed blocks and the buffer insertion block 70
The signal relay buffer block 752 is arranged on the second relay buffer arrangement area 741 and the wiring between the arranged blocks and the relay buffer input signal 705 and the relay buffer output on the relay buffer wiring area 742 of the buffer insertion block 702 are arranged. By wiring the signal 706, the layout of the LSI is completed (S607). At this time, the power of the inter-block signal relay buffer 702 is supplied from a power supply 704 different from the power supply 703 of the buffer insertion block that supplies power to the buffer insertion block 701. Even if the supply of the power source 703 is stopped, the power of the inter-block signal relay buffer 702 is supplied from the power source 704, and the inter-block signal relay buffer 702 continues to operate.

As described above, it becomes possible to realize the power supply control for each layout block while ensuring the power supply to the inter-block signal relay buffer. In addition, as the inter-block signal relay buffer according to the sixth embodiment, the signal wiring is shielded by wiring the power supply wiring to the signal wiring of the inter-block signal relay buffer using a wiring layer different from the signal wiring. Therefore, mutual interference can be prevented.

[0023]

As described above, according to the inter-block signal relay buffer and its layout method of the present invention, by supplying another power source other than the power source supplied to the buffer insertion block to the inter-block signal relay buffer, Even if the power supply to the buffer insertion block is stopped to save power consumption, the power supply for the inter-block signal relay buffer continues to be supplied from another power supply, so the power supply for the inter-block signal relay buffer is maintained. Power supply control can be realized for each layout block.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of an inter-block signal relay buffer according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram of an inter-block signal relay buffer according to the second embodiment of the present invention.

FIG. 3 is a conceptual diagram of an inter-block signal relay buffer according to the third embodiment of the present invention.

FIG. 4 is a process diagram showing a layout method of an inter-block signal relay buffer according to the fourth embodiment of the present invention.

FIG. 5 is a conceptual diagram of an inter-block signal relay buffer according to the fourth embodiment of the present invention.

FIG. 6 is a process diagram showing a layout method of an inter-block signal relay buffer according to the fifth embodiment of the present invention.

FIG. 7 is a conceptual diagram of an inter-block signal relay buffer according to the fifth embodiment of the present invention.

FIG. 8 is a block diagram of a conventional inter-block signal relay buffer.

[Explanation of symbols]

101 buffer insertion block 102 Inter-block signal relay buffer 103 power supply 104 power supply 105 Relay buffer input signal 106 Relay buffer output signal 201 buffer insertion block 202 Inter-block signal relay buffer 203 power supply 211 Signal supply block 212 Inter-block signal supply buffer 213 power supply 301 buffer insertion block 302 Inter-block signal relay buffer 303 power supply 305 Relay buffer input signal 306 Relay buffer output signal 321 Signal reception block 322 Inter-block signal reception buffer 323 power supply 401 Initial hierarchy netlist 404 Layout Hierarchical Netlist 501 buffer insertion block 502 Inter-block signal relay buffer 503 power supply 504 power supply 505 Relay buffer input signal 506 Relay buffer output signal 541 Relay buffer placement area 542 Relay buffer wiring area 551 Higher layer layout 601 Initial hierarchy netlist 605 Layout hierarchical netlist 701 buffer insertion block 702 Inter-block signal relay buffer 703 power supply 704 power supply 705 Relay buffer input signal 706 Relay buffer output signal 741 Relay buffer placement area 742 Relay buffer wiring area 751 Higher-level layout 752 Signal relay buffer block 801 buffer insertion block 802 Inter-block signal relay buffer 803 power supply

Claims (6)

(57) [Claims] 1. An inter-block signal relay buffer for driving a signal propagating between a plurality of layout blocks in a semiconductor integrated circuit, which belongs to a buffer insertion layout block which is supplied with power from a first power supply, Even if the supply of the first power supply is stopped and the operation of the buffer insertion layout block is stopped by being supplied with power from the second power supply that supplies power to a layout block other than the layout block An inter-block signal relay buffer, which is capable of driving a signal propagating to a circuit. 2. An inter-block signal relay buffer for driving a signal propagating between a plurality of layout blocks in a semiconductor integrated circuit, which belongs to a buffer insertion layout block supplied with power from a first power supply, and which is an inter-block signal. Even if the supply of the first power supply is stopped and the operation of the buffer insertion layout block is stopped by being supplied with power from the third power supply that supplies power to the signal supply block that supplies a signal to the relay buffer. An inter-block signal relay buffer capable of driving a signal propagating between the plurality of layout blocks. 3. An inter-block signal relay buffer for driving a signal propagating between a plurality of layout blocks in a semiconductor integrated circuit, which belongs to a buffer insertion layout block supplied with power from a first power supply, and which is an inter-block signal. Even if the supply of the first power supply is stopped and the operation of the buffer insertion layout block is stopped by supplying power from the fourth power supply that supplies power to the signal reception block that receives the signal from the relay buffer. An inter-block signal relay buffer capable of driving a signal propagating between the plurality of layout blocks. 4. When laying out an inter-block signal relay buffer that receives power supply from a layout block other than the layout block to which the semiconductor integrated circuit belongs, a floor plan of the semiconductor integrated circuit is performed based on the initial hierarchical netlist, and layout positions of layout blocks are determined. A step of determining a layout inter-block wiring, and a step of inserting an inter-block signal relay buffer into the highest hierarchy for the inter-block wiring whose driving capability is insufficient due to the result of the floor plan, and generating a layout hierarchical netlist A step of performing a layout in each layout block and presetting an arrangement area and a wiring area of the inter-block signal relay buffer with respect to a layout block including the inter-block signal relay buffer in the previous period; and each layout block as a layout of the highest hierarchy. Layout wiring of the inter-block signal relay buffer and arranging the inter-block signal relay buffer in the placement area, and wiring the power and signals of the inter-block relay buffer in the previous wiring area. 5. The layout method of the inter-block signal relay buffer according to claim 4, wherein a layout block including only the inter-block signal relay buffer is formed to perform the layout. 6. The signal wiring is shielded by wiring the second power source to the signal wiring of the inter-block signal relay buffer using a wiring layer different from that of the signal wiring to shield the signal wiring. 4. The interblock signal relay buffer according to claim 1, 2 or 3, wherein mutual interference between the blocks is prevented.