JP3492254B2 - アクセスを制限したテストにおいて目標コンポーネントを選択するための方法及び装置 - Google Patents

アクセスを制限したテストにおいて目標コンポーネントを選択するための方法及び装置

Info

Publication number
JP3492254B2
JP3492254B2 JP29033299A JP29033299A JP3492254B2 JP 3492254 B2 JP3492254 B2 JP 3492254B2 JP 29033299 A JP29033299 A JP 29033299A JP 29033299 A JP29033299 A JP 29033299A JP 3492254 B2 JP3492254 B2 JP 3492254B2
Authority
JP
Japan
Prior art keywords
nodes
node
subset
test
equation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP29033299A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000121697A (ja
Inventor
ロドニー・エイ・ブローウェン
チェリフ・アーリケンチェイク
ウィリアム・ピー・ダービー
ジョン・イー・マクダーミッド
ケイ・シー・ラネン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2000121697A publication Critical patent/JP2000121697A/ja
Application granted granted Critical
Publication of JP3492254B2 publication Critical patent/JP3492254B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
JP29033299A 1998-10-09 1999-10-12 アクセスを制限したテストにおいて目標コンポーネントを選択するための方法及び装置 Expired - Fee Related JP3492254B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US169777 1998-10-09
US09/169,777 US6263476B1 (en) 1998-10-09 1998-10-09 Method and apparatus for selecting targeted components in limited access test

Publications (2)

Publication Number Publication Date
JP2000121697A JP2000121697A (ja) 2000-04-28
JP3492254B2 true JP3492254B2 (ja) 2004-02-03

Family

ID=22617134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29033299A Expired - Fee Related JP3492254B2 (ja) 1998-10-09 1999-10-12 アクセスを制限したテストにおいて目標コンポーネントを選択するための方法及び装置

Country Status (4)

Country Link
US (1) US6263476B1 (US06263476-20010717-M00021.png)
EP (1) EP0992802B8 (US06263476-20010717-M00021.png)
JP (1) JP3492254B2 (US06263476-20010717-M00021.png)
DE (1) DE69934467T2 (US06263476-20010717-M00021.png)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6567956B1 (en) * 2000-05-08 2003-05-20 Hewlett-Packard Development Company, L.P. Method for performing electrical rules checks on digital circuits with mutually exclusive signals
US6532568B1 (en) * 2000-10-30 2003-03-11 Delphi Technologies, Inc. Apparatus and method for conditioning polysilicon circuit elements
US7393755B2 (en) * 2002-06-07 2008-07-01 Cadence Design Systems, Inc. Dummy fill for integrated circuits
US7774726B2 (en) * 2002-06-07 2010-08-10 Cadence Design Systems, Inc. Dummy fill for integrated circuits
US7712056B2 (en) * 2002-06-07 2010-05-04 Cadence Design Systems, Inc. Characterization and verification for integrated circuit designs
US20030229875A1 (en) * 2002-06-07 2003-12-11 Smith Taber H. Use of models in integrated circuit fabrication
WO2003104921A2 (en) * 2002-06-07 2003-12-18 Praesagus, Inc. Characterization adn reduction of variation for integrated circuits
US7152215B2 (en) * 2002-06-07 2006-12-19 Praesagus, Inc. Dummy fill for integrated circuits
US7124386B2 (en) * 2002-06-07 2006-10-17 Praesagus, Inc. Dummy fill for integrated circuits
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
US7853904B2 (en) * 2002-06-07 2010-12-14 Cadence Design Systems, Inc. Method and system for handling process related variations for integrated circuits based upon reflections
DE102004040177A1 (de) * 2004-08-18 2006-03-09 Infineon Technologies Ag Verfahren zur Verbesserung der Aussageschärfe von Diagnosen technischer Anordnungen
WO2008125998A1 (en) * 2007-04-12 2008-10-23 Nxp B.V. Analog circuit testing and test pattern generation
US10073750B2 (en) * 2012-06-11 2018-09-11 Tektronix, Inc. Serial data link measurement and simulation system
CN105593858B (zh) * 2013-07-30 2017-12-01 Ess技术有限公司 用于电气元件的串联和并联组合的系统和方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0451371B1 (en) * 1990-04-13 1997-11-26 Koninklijke Philips Electronics N.V. A method for organizing and accessing product describing data pertaining to an engineering process
US5172377A (en) * 1990-09-07 1992-12-15 Genrad, Inc. Method for testing mixed scan and non-scan circuitry
US5448166A (en) * 1992-01-03 1995-09-05 Hewlett-Packard Company Powered testing of mixed conventional/boundary-scan logic
US5870590A (en) * 1993-07-29 1999-02-09 Kita; Ronald Allen Method and apparatus for generating an extended finite state machine architecture for a software specification
US5808919A (en) 1993-11-23 1998-09-15 Hewlett-Packard Company Diagnostic system
US5391993A (en) * 1994-01-27 1995-02-21 Genrad, Inc. Capacitive open-circuit test employing threshold determination
US5530372A (en) * 1994-04-15 1996-06-25 Schlumberger Technologies, Inc. Method of probing a net of an IC at an optimal probe-point
US5838583A (en) * 1996-04-12 1998-11-17 Cadence Design Systems, Inc. Optimized placement and routing of datapaths

Also Published As

Publication number Publication date
DE69934467D1 (de) 2007-02-01
EP0992802A2 (en) 2000-04-12
EP0992802B1 (en) 2006-12-20
US6263476B1 (en) 2001-07-17
DE69934467T2 (de) 2007-04-19
JP2000121697A (ja) 2000-04-28
EP0992802B8 (en) 2007-02-28
EP0992802A3 (en) 2003-12-17

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