JP3491618B2 - Netlist generation method and program for integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit netlist generation method and program for generating a circuit netlist of an input / output (I / O) portion of an integrated circuit.

[0002]

2. Description of the Related Art Conventionally, LSI (Large Scale Integration)
CAD when designing integrated circuits such as ated circuits)
Automatic design using (Computer Aided Design) is performed (for example, Japanese Patent Laid-Open No. 2000-105782,
JP 2000-340753 A, JP 11-30
See Japanese Patent No. 7644 and Japanese Patent No. 3024593. ). When designing an integrated circuit, a macro that is a unit block that performs a certain set of operations is used.
Macros are divided into hard macros and soft macros.

The hard macro defines the layout and wiring position (layout) of the individual circuit elements forming the circuit on the semiconductor chip. Each element is formed by combining individual elements such as transistors and resistors on the semiconductor chip. Elements arranged and wiring connected between elements, NAND, NO
There is one in which basic logic circuits such as R and flip-flops (FF) are combined, each logic circuit is arranged, and each logic circuit is wired.

On the other hand, the soft macro does not define the arrangement between the circuit elements like the hard macro does, but describes only the connection relationship of individual circuits such as a netlist, and the layout is laid out. It does not include the layout information or wiring information that is the information of the result. by the way,
The aforementioned Japanese Patent Laid-Open No. 2000-105782 discloses an invention for efficiently creating a netlist of a circuit of an I / O portion of a single-bit (single) I / O primitive configuration in a standard cell LSI logic design. Has been done.

[0005]

However, according to the invention described in the above publication, the source synchronous I / O is used.
(I / O configured such that a data transmitting side transmits data and the transfer clock signal to a data receiving side in synchronization with a transfer clock, and the data receiving side receives the data in synchronization with the transfer clock. ) Is configured with a soft macro, the area that can be placed on the base is limited, and from the viewpoint of delay design, assignment (external net to I / O pad, allocation of I / O primitive) deviation is not allowed, and it is accurate. Since it is difficult to assign to a macro, there is a problem that it cannot correspond to a macro that covers a plurality of bits such as a source synchronous I / O.

FIG. 11 is a schematic diagram showing an example in which an assignment shift occurs. FIG. 11 shows an example of 4-bit source synchronous I / O, and 1101 is an I / O pad of the LSI,
Reference numerals 102 and 1103 indicate allocation of source synchronous macros that cover a plurality of bits, and 1104 indicates a background of the LSI. In FIG. 7A, the source synchronous I / O macro is properly assigned, but in FIG. 8B, the same macro as in FIG. (Allocation) Misalignment has occurred.

Further, in the source synchronous I / O, it is necessary to accurately connect not only data pins (plurality of bits) but also transfer clocks (positive polarity, negative polarity) and reference signals at the time of signal connection. However, there is a problem that the invention described in the above publication cannot cope with the problem. On the other hand, in order to solve the above-mentioned assignment shift, there is a method of making the source synchronous I / O into a hard macro. However, even if it is logically a few types, there are variations in the assignment to the I / O pad. However, there is a problem in that it is necessary to create a large number of hard macros, resulting in a large number of man-hours.

An object of the present invention is to enable proper and efficient placement and allocation in a placeable area on a base in the creation of a netlist of a circuit of a source synchronous I / O portion having a soft macro structure.

[0009]

According to the present invention, in an integrated circuit netlist generation method for generating a netlist of a source synchronous I / O partial circuit, each external terminal of the integrated circuit to be logically designed. Integrated circuit external net information storage means for storing external net information regarding the above, an I / O partial circuit connection information storage means for storing connection information inside the I / O partial circuit for which a net list is generated, and a net list I / O macro specification information storage means for storing information on the specifications of the I / O soft macro used to generate the I / O soft macro;
Reading means for reading the external net information, connection information inside the I / O partial circuit, and information regarding the specifications of the I / O soft macro from the O partial circuit connection information storing means and the I / O macro specification information storing means, and the reading means. Based on the information read by the means, an inspection means for inspecting the appropriateness of the arrangement and allocation of the I / O soft macro, and the inspection means
And a netlist generating means for generating a netlist of the I / O partial circuit based on the information read by the reading means when the placement and allocation of the O soft macro are judged to be proper. An integrated circuit netlist generation method is provided.

The integrated circuit external net information storage means stores external net information regarding each external terminal of the integrated circuit which is the object of logic design. The I / O partial circuit connection information storage means stores connection information inside the I / O partial circuit which is a target for generating a netlist. The I / O macro specification information storage means is an I / O macro specification information storage means used to generate a netlist.
Stores information about the specifications of the O soft macro. The reading means is the integrated circuit external net information storage means,
The external net information, the connection information inside the I / O partial circuit, and the information regarding the specifications of the I / O soft macro are read from the I / O partial circuit connection information storage means and the I / O macro specification information storage means. The inspecting means inspects the suitability of the arrangement and allocation of the I / O soft macro based on the information read by the reading means. The netlist generating means generates a netlist of the I / O partial circuit based on the information read by the reading means when the checking means determines that the placement and allocation of the I / O soft macro is appropriate.

Here, in the integrated circuit external net information storage means, at least a plurality of external net names and a plurality of I / O soft macro names that can be arranged in a predetermined area and are associated with the external net names are stored. The I / O partial circuit connection information storage means stores at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names. The I / O macro specification information storage means stores at least a plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names, and the reading means at least First, a plurality of external net names read from the integrated circuit external net information storage means and a plurality of allocable information associated with the external net names are stored. A table, at least the I / O
A second table for storing the plurality of external net names read from the partial circuit connection information storage means and the plurality of I / O soft macro names associated with the external net names;
At least the plurality of I / O soft macro names read from the I / O macro specification information storage means and the I / O
A third table for storing a plurality of external net names associated with soft macro names is stored in the storage means, and the inspection means stores the second net table for each external net name in the second table. The first table is searched based on the external net name of the table, and the I / O soft macro name included in the allocable information of the first table corresponding to the external net name of the second table is extracted. , An appropriate placement when the I / O soft macro name associated with the external net name in the second table and the I / O soft macro name included in the placement possible information in the first table match It may be configured to determine that.

[0012] Further, each of the allocable information includes allocation information indicating an allocation type, and the inspection means searches the first table based on the external net name of the second table. Then, there is provided allocation information storage means for extracting and storing allocation information included in the allocable information of the first table corresponding to the external net name of the second table, and each of the external parts of the second table. About net name, 1
External net of the second table obtained by searching the first table based on the external net name of the second table after storing the allocation information of the net in the allocation information storage means. When the allocation information included in the allocable information of the first table corresponding to the name matches the allocation information stored in the allocation information storage means, the allocation of the I / O soft macro is judged to be proper. You may comprise.

Further, in the integrated circuit external net information storage means, a transfer clock net name which is information relating to a transfer clock, a reference net name which is information relating to a reference signal, and a distribution clock which are associated with the external net name. The I / O partial connection information storage means stores the net name to the internal logic associated with the I / O soft macro name. The specification information storage means may be configured to store a distribution clock name, a reference name, and a net name for internal logic associated with the I / O soft macro name.

Further, according to the present invention, in the netlist generation method of the integrated circuit for generating the netlist of the source synchronous I / O partial circuit, at least a plurality of external net names and the external net names are arranged in association with each other. First storage means for storing external net information regarding each external terminal of an integrated circuit which is a target of logic design, including a plurality of allocable information having allocation information indicating a possible I / O soft macro name and allocation type. And at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names, and stores connection information inside the I / O partial circuit which is a target for generating a net list. A second storage means and at least a plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names; I / O to be used to generate the Ttorisuto
Third storage means for storing information regarding the specifications of the soft macro, inspection means for checking whether the arrangement and allocation of the I / O soft macro are proper, and an allocation for storing the allocation information included in the allocable information. The information storage means and the netlist generation means for generating a netlist of the I / O partial circuits when the inspection means determines that the I / O soft macros are properly arranged and allocated. Means for each external net name of the second storage means,
Based on the external net name, the first storage means is searched to extract the allocable information of the first storage means corresponding to the external net name of the second storage means, and the second storage means. When the I / O soft macro name associated with the external net name and the I / O soft macro name included in the allocable information of the first storage unit match, it is determined that the allocation is proper, The allocation information of the first net included in the allocable information is stored in the allocation information storage means, the allocation information is stored in the allocation information storage means, and then, based on the external net name of the second storage means, The allocation information included in the allocable information of the first storage means corresponding to the external net name of the second storage means, which is obtained by searching the first storage means, is stored in the allocation information storage means. Match the assigned information When the netlist generation method of the integrated circuit, characterized in that to determine the proper allocation of I / O software macros are provided.

The first storage means stores at least a plurality of external net names and a plurality of allocable information having allocation information indicating a I / O soft macro name that can be allocated in association with the external net names and allocation type. It stores external net information about each external terminal of the integrated circuit that is the target of the logic design. The second storage means stores at least a plurality of external net names and a plurality of I's associated with the external net names.
It stores the connection information inside the I / O partial circuit that is the target for generating the netlist, including the / O soft macro name. The third storage means includes at least a plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names, and stores the I / O soft macros used to generate the netlist. Stores information about specifications. The allocation information storage means stores the allocation information included in the allocable information. The netlist generating means is I
When the inspecting means for inspecting whether the arrangement and the allocation of the I / O soft macro is proper determines the arrangement and the allocation of the I / O soft macro, the net list of the I / O partial circuit is generated. The checking means searches the external net name of the second storage means for the first storage means based on the external net name and corresponds to the external net name of the second storage means. The allocable information of one storage means is extracted, and the I / O soft macro name associated with the external net name of the second storage means and the I included in the allocable information of the first storage means are extracted. When the / O soft macro names match, it is determined that the allocation is proper, and the allocation information of the first net included in the allocation possible information is stored in the allocation information storage means, and the allocation information is stored in the allocation information storage means. After storing, it is obtained by searching the first storage means based on the external net name of the second storage means,
The first corresponding to the external net name of the second storage means
When the allocation information included in the allocable information of the storage means of No. 1 matches the allocation information stored in the allocation information storage means, the allocation of the I / O soft macro is judged to be proper.

The net list generating means generates a connection rule based on the external net information, the connection information inside the I / O partial circuit, and the information about the specifications of the I / O soft macro, and the signal line connection rule generating means. According to the connection rule generated by the signal line connection rule generation means, the I / O soft macros are connected and the I
The entire I / O soft macro is assembled as a hierarchy of I / O partial circuits, and the connection / layer assembling means for generating a netlist and the netlist generated by the connection / layer assembling means are expanded to the primitive block level to obtain a desired one. It may be configured so as to include a hierarchical expansion means for generating a level netlist.

Further, according to the present invention, a computer
An integrated circuit external net information storage unit that stores external net information about each external terminal of the integrated circuit that is the target of logic design, and an I that stores connection information inside the I / O partial circuit that is the target of net list generation. / O partial circuit connection information storage means, I / O macro specification information storage means for storing information on specifications of I / O soft macros used for generating a netlist, the integrated circuit external net information storage means, I / O Reading means for reading the external net information, connection information inside the I / O partial circuit, and information regarding the specifications of the I / O soft macro from the O partial circuit connection information storing means and the I / O macro specification information storing means, and the reading means. An inspection means for inspecting the suitability of the arrangement and allocation of the I / O software macros based on the information read by the means, and the inspection means is the I / O software. Provided is a program for causing a netlist generating unit to generate a netlist of the I / O partial circuit based on the information read by the reading unit when the black arrangement and allocation are determined to be appropriate. To be done.

By executing the program according to the present invention on a computer, the computer causes the integrated circuit external net information storage means for storing external net information regarding each external terminal of the integrated circuit which is the object of logic design, and a net list. I / O partial circuit connection information storage means that stores connection information inside the I / O partial circuit that is the target of generation of the I / O partial circuit, and I that stores information regarding the specifications of the I / O soft macro used to generate the netlist. / O macro specification information storage means, the integrated circuit external net information storage means, I / O
Reading means for reading the external net information, connection information inside the I / O partial circuit, and information regarding the specifications of the I / O soft macro from the O partial circuit connection information storing means and the I / O macro specification information storing means, and the reading means. Based on the information read by the means, an inspection means for inspecting the appropriateness of the arrangement and allocation of the I / O soft macro, and the inspection means
When it is determined that the arrangement and the allocation of the O soft macro are proper, it functions as a net list generating unit that generates a net list of the I / O partial circuit based on the information read by the reading unit.

Here, in the integrated circuit external net information storage means, at least a plurality of external net names and a plurality of I / O software which can be arranged in a predetermined area in association with the external net names are arranged in the computer. Arrangement information including a macro name is stored, and at least the plurality of external net names and a plurality of I / O soft macro names associated with the external net names are stored in the I / O partial circuit connection information storage means. The I / O macro specification information storage means stores at least a plurality of I / O soft macro names and the I / O.
A plurality of external net names associated with soft macro names are stored, and the reading means is associated with at least the plurality of external net names read from the integrated circuit external net information storage means and the external net names. A first table storing a plurality of allocable information, a plurality of external net names read from at least the I / O partial circuit connection information storage means, and a plurality of I / O software programs associated with the external net names A second table storing macro names, a plurality of I / O soft macro names read from at least the I / O macro specification information storage means, and a plurality of external nets associated with the I / O soft macro names And a third table for storing the names of the external net names in the second table. Te, the second by searching the first table based on an external net name of the second table
I / O software macro name included in the allocable information of the first table corresponding to the external net name of the second table is extracted, and the I / O software associated with the external net name of the second table is extracted. The program may be configured so as to function so as to determine an appropriate arrangement when the macro name and the I / O soft macro name included in the arrangement possible information of the first table match.

Further, in the computer, the allocation information indicating the allocation type is included in each of the allocable information, and the inspecting means sets the first table based on the external net name of the second table. There is an allocation information storage unit that retrieves and stores allocation information included in the allocable information of the first table that corresponds to the external net name of the second table and stores each of the second tables. The external net name is obtained by searching the first table based on the external net name of the second table after storing the allocation information of the first net in the allocation information storage means. When the allocation information included in the allocable information of the first table corresponding to the external net name of the second table matches the allocation information stored in the allocation information storage means,
The program may be configured to function so as to determine that the allocation of the I / O soft macro is appropriate.

Further, the computer, further, in the integrated circuit external net information storage means, a transfer clock net name which is information relating to a transfer clock and a reference net name which is information relating to a reference signal are associated with the external net name. And a distribution clock name which is information relating to the distribution clock, and the I / O partial connection information storage means stores the net name to the internal logic associated with the I / O soft macro name. The / O macro specification information storage means may be configured with a program so as to function to store the distribution clock name, the reference name, and the net name to the internal logic associated with the I / O soft macro name. Good.

Further, according to the present invention, a computer is
An integrated circuit that is a target of logical design, including at least a plurality of external net names, a plurality of placeable information having an I / O soft macro name that can be arranged in association with the external net name and that can be arranged, and allocation information indicating a type of allocation And a first storage unit for storing external net information about each external terminal, and a net list including at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names. A second storage unit for storing connection information inside the I / O partial circuit which is an object to be executed, and at least a plurality of I's.
/ O soft macro name and a plurality of external net names associated with the I / O soft macro name, and third storage means for storing information regarding the specifications of the I / O soft macro used to generate the net list An inspection means for inspecting whether the arrangement and the allocation of the I / O soft macro are proper, an allocation information storage means for storing the allocation information included in the allocable information, and the inspection means for the I / O soft macro. And a netlist generating means for generating a netlist of the I / O partial circuits when the arrangement and the allocation are determined to be appropriate. Regarding the external net name, the first storage means is searched to extract the allocable information of the first storage means corresponding to the external net name of the second storage means, and the second storage means When the I / O soft macro name associated with the external net name in the storage means matches the I / O soft macro name included in the allocable information in the first storage means, it is determined that the layout is proper. At the same time, the allocation information of the first net included in the allocable information is stored in the allocation information storage means, the allocation information is stored in the allocation information storage means, and then based on the external net name of the second storage means. The allocation information included in the allocable information of the first storage means corresponding to the external net name of the second storage means obtained by searching the first storage means with the allocation information storage means When it matches the allocation information stored in
There is provided a program characterized by causing the / O soft macro to be assigned appropriately.

By executing the program according to the present invention on a computer, the computer displays at least a plurality of external net names and I / O soft macro names that can be arranged in association with the external net names and the allocation types. First storage means for storing external net information regarding each external terminal of an integrated circuit which is a target of logic design, including a plurality of allocable information having allocation information, and at least a plurality of external net names and the external net names. A second storage unit including a plurality of associated I / O soft macro names and storing connection information inside the I / O partial circuit which is a target for generating a netlist, and at least a plurality of I / O softwares. I / O software including a macro name and a plurality of external net names associated with the I / O software macro name and used for generating a netlist Third storage means for storing information on black specifications, inspection means for inspecting whether the arrangement and allocation of I / O soft macros are proper, and allocation information for storing allocation information included in the allocable information. The inspection means comprises a storage means and a netlist generation means for generating a netlist of the I / O partial circuits when the inspection means determines that the placement and allocation of the I / O soft macro is appropriate. For each of the external net names in the second storage means, searches the first storage means based on the external net name to find the first storage corresponding to the external net name in the second storage means. I, which is associated with the external net name of the second storage means, is extracted by extracting the allocable information of the means.
When the / O soft macro name and the I / O soft macro name included in the arrangable information of the first storage unit match, it is determined that the arrangement is proper, and the first net included in the arrangable information. It is obtained by storing the allocation information in the allocation information storage means, storing the allocation information in the allocation information storage means, and then searching the first storage means based on the external net name of the second storage means. Further, when the allocation information included in the allocable information of the first storage means corresponding to the external net name of the second storage means matches the allocation information stored in the allocation information storage means, I / I Functions to judge that the allocation of O soft macro is appropriate.

In the computer, the netlist generating means generates a signal line connection rule for generating a connection rule based on the external net information, the connection information inside the I / O partial circuit, and the information about the specifications of the I / O soft macro. Means and the I / O soft macros are connected in accordance with the connection rule generated by the signal line connection rule generation means, and the entire connected I / O soft macros are assembled as a hierarchy of I / O partial circuits. A connection / hierarchical assembling unit for generating a list and a function as a hierarchy expanding unit for expanding the netlist generated by the connection / hierarchical assembling unit to a primitive block level to generate a netlist of a desired level. The program may be configured to function.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION A netlist generation method and program for an integrated circuit according to an embodiment of the present invention will be described below. FIG. 1 is a block diagram of an automatic netlist generation system for an integrated circuit used in an embodiment of the present invention, in which source synchronous I / O (a data transmission side synchronizes data and the transfer clock signal with a transfer clock). A source-synchronous I / O portion for transmitting to a data receiving side and generating a netlist for a circuit of the I / O portion configured so that the data receiving side receives the data in synchronization with the transfer clock. 1 shows an example of a netlist automatic generation system for a circuit.

In FIG. 1, a netlist generation system of an integrated circuit stores a data processing device 1 as a data processing means for generating a netlist, information necessary for the data processing device 1 to generate a netlist, and The data processing device 1 comprises a storage device 2 as a storage means for storing the netlist generated by the data processing device 1. The data processing device 1 can be configured by a computer including a central processing unit (CPU) and a storage device storing a program, and the storage device 2 is configured by various storage media such as a magnetic disk and a semiconductor memory. be able to. In the present embodiment, the program processed by the CPU is stored in the storage device 2.

The storage device 2 stores the LSI external net information 31.
And an integrated circuit external net information storage means for storing in advance,
I / O partial circuit connection information storage means in which I / O partial circuit connection information 32 is stored in advance, I / O macro specification information storage means in which I / O macro specification information 33 is stored in advance, and I / O macro netlist 34 The I / O macro net list storage means for storing the data in advance and the library storage means for storing the library 35 in advance are provided.
An I / O partial circuit netlist storage means is provided as an output destination of the netlist generated in (3). The I / O partial circuit netlist storage unit stores the I / O partial circuit netlist 36 generated by the data processing device 1.

The LSI external net information 31, the I / O partial circuit connection information 32, and the I / O macro specification information 33 are used when the data processing apparatus 1 generates a net list.
The I / O macro netlist 34 and the library 35 are various types of information used to generate various types of connection information (connection rules). Information.

The LSI external net information 31 is the external net information of the LSI which is the target of the logic design. For each of the LSI external terminals, the external terminal name, the net name of the external net connected to the external terminal, the external signal name, It is information for each product type including source synchronous I / O allocable information, transfer clock net name, and reference net name. The allocable information includes information (at least a macro name) indicating an I / O soft macro that can be allocated in the corresponding area. still,
As will be described later, the external net name can be described in one line by designating a start bit and an end bit like X (start bit-end bit).

The I / O partial connection information 32 is the internal connection information of the circuit of the source synchronous I / O part which is the target for generating the netlist, and is the source synchronous I / O.
It is the connection information of the circuit of the I / O portion defined at the macro (I / O buffer) level. I / O macro specification information 33
Is information about the specifications of the source synchronous I / O macro used to generate the netlist. The macro name and the signal name in the macro (external signal, internal logic) are defined for each type of source synchronous I / O. Connected signals, distributed clock signals, reference signals).

The I / O macro netlist 34 is a netlist of source synchronous I / O soft macros.
This is information stored in advance. The library 35 contains I /
Primitive block containing O buffer (leaf cell;
(Specific AND gate or OR gate of target circuit)
And the terminal name information of the terminals of the primitive block are stored in advance. The I / O partial circuit netlist 36 is a netlist of circuits of the source block synchronous I / O macro output from the data processing device 1 and of the primitive block level synchronous I / O part.

The data processing device 1 has a file reading means 20 for reading a necessary file from the storage device 2 and an I / O unit.
An arrangement and assignment check means 21 for checking the arrangement and assignment of O soft macros, a signal line connection rule generation means 22 for generating various connection rules, and a connection / layer assembly means 2 for generating a netlist of I / O partial circuits.
3 and a hierarchy expanding means 24. The file reading means 20 reads information from the LSI external net information 31, the I / O partial circuit connection information 32 and the I / O macro specification information 33, and sets the information in a table provided therein. The file reading means 20 is provided with a reading storage means (not shown), and the LSI external net information 31, the I / O partial circuit connection information 32, and the I / O are stored in the reading storage means as described later. Two association tables (table 1, table 3) and one list table (table 2) are prepared corresponding to the macro specification information 33. It should be noted that the portion storing the table 1 of the read storage means and the LSI external net information storage means constitute a first storage means, and the portion storing the table 2 of the read storage means and the I / O partial circuit connection. The information storage means constitutes a second storage means, and a portion for storing the table 3 of the read storage means and the I / O.
The macro specification information storage means constitutes the third storage means.

The layout and assignment check means 21 is L
According to the source synchronous I / O allocable information of the SI external net information 31 and the transfer clock net name, it is checked whether the source synchronous I / O soft macro of the correct type is allocated and assigned to an appropriate area, and the transfer clock is checked. (Positive or negative transfer clock) Check the suitability of net connectivity. The arrangement and assignment check means constitutes inspection means for inspecting the adequacy of the arrangement and assignment.

The signal line connection rule generation means 22 uses the I / O.
With reference to the partial circuit connection information 32 and the LSI external net information 31, connection information is created in the form of a connection rule and output to the connection / hierarchical assembling unit 23. The connection / layer assembling unit 23 connects the I / O macros according to the connection rule created by the signal line connection rule generating unit 22, and the connected I / O macro as a whole is a layer of the circuit of the I / O part. And build a netlist. At this time, the external terminal of the circuit of the I / O part is also generated.

The hierarchical expansion means 24 refers to the I / O macro netlist 34 and the library 35 as appropriate to the netlist of the circuit of the I / O portion created by the connection / hierarchical assembly means 23, and hierarchically reaches the primitive block level. To expand. This output is the I / O partial circuit netlist 36. The hierarchical expansion means 24 outputs the generated I / O partial circuit netlist 36 to the storage device 2, and the I / O partial circuit netlist storage means of the storage device 2 stores the I / O partial circuit netlist 36.

Next, an outline of the operation of the circuit automatic generation system for the source synchronous I / O portion constructed as described above will be explained. This system uses the I / O
Assignment of I / O Primitives to I / O Pads
If I decide, I / O
Since it is obvious that the primitives are placed near the I / O pads, the placement check and the assignment check are performed at the logic design stage. Here, the layout means the layout of I / O primitives on the layout, and the assignment means to which I / O pad an external net or I / O primitive is allocated.

According to this system, in the source synchronous I / O partial circuit netlist generation method for outputting the netlist of the circuit of the source synchronous I / O portion in the integrated circuit, it is necessary for generating the netlist of connection information and the like. Information is input into a database such as spreadsheet software in advance, source synchronous I / O software macro placement check and assignment check are performed, and then each signal is connected to the source synchronous I / O. A configuration is provided that can output a netlist of partial circuits. Here, the source synchronous I / O soft macro is a soft macro that covers transfer of a plurality of bits and has pins such as a transfer clock, a reference signal, and a distribution clock in addition to the transfer data pin.

In the LSI external net information 31, in addition to the I / O net name, source synchronous I / O allocable information, which is information of the source synchronous I / O macros that can be allocated, transfer clock net name, and , A reference net name that is a net name of a reference signal to be distributed, and a distributed clock net name. The placement / assignment check means 21 obtains the corresponding source synchronous I / O placement availability information from the external net of the I / O partial circuit connection information 32, and determines the validity and assignment shift of the macro being used. The connection relationship of signals is processed by the signal line connection rule generation means 22. At this time, a rule for connecting the reference net or distributed clock of the source synchronous I / O soft macro to the net to be distributed is output.

In the I / O partial circuit connection information 32, the netlist is actually generated by the connection / layer assembling means 23 and the layer expanding means 2 for connecting the nets in accordance with the connection rules.
4 is output. In this way, it is possible to output the source synchronous I / O partial circuit netlist whose placement and assignment are checked from the I / O partial circuit connection information 32 in which only the external net and the net to the internal logic are input. . In addition, the signal line connection rule generation means 22, the connection
The hierarchy assembling means 23 and the hierarchy expanding means 24 constitute a netlist generating means.

2 to 4 are flowcharts showing the processing in the embodiment of the present invention, FIG. 2 is a flowchart showing the overall processing, and FIGS. 3 and 4 are flowcharts showing the details of the branch processing in FIG. Is. 5 is a table showing the contents of the LSI external net information 31, FIG.
Is a table showing the contents of the I / O partial circuit connection information 32,
7 is a table showing the contents of the I / O macro specification information 33, and FIG. 8 is a diagram showing the first table, Table 1,
FIG. 9 is a diagram showing Table 2 which is the second table, and FIG.
0 is a diagram showing Table 3 which is the third table.

The overall operation of this embodiment will be described in detail below with reference to FIGS. In FIG. 1, the file reading means 20 is the LS of the storage device 2.
The I external net information 31, the I / O partial circuit connection information 32, and the I / O macro specification information 33 are read. The file reading means 20 analyzes these files and sets them in the association table and the list table (step A1 in FIG. 2). The associative table is a table having a data structure in which a key value and related data or a set of data are stored in association with each other. Therefore, after storing the data, the key can be used to retrieve the data associated with the key.

At step A1, the file reading means 20 uses the name of the external net connected to the external terminal of the LSI from the LSI external net information 31 as a key, as shown in FIG.
As shown in Table 1, the external net name (column A), source synchronous I / O allocable information (column B), transfer clock net name (column C), reference net name (D)
Column), and the distributed clock (column E) input to the I / O macro is set in the associative table 1. Here, the format of the source synchronous I / O allocable information is the corresponding I
Sharp source synchronous I / O macro names (SSX1, SSX2 in FIG. 8) that may be placed in the I / O area and unique identification symbols (ID) (0, 1 in FIG. 8) unique to all I / O macros It is connected with the symbol '#'.
The macro name is information indicating the type of macro, and the ID is allocation information indicating the type of allocation to the I / O pad.

Further, the file reading means 20 is shown in FIG.
As shown in Table 2 of the above, I / O partial circuit connection information 3
From 2, external net, source synchronous I / used
The O macro name and the net guided to the internal logic are set in the list table 2, and as shown in table 3 of FIG.
From the I / O macro specification information 33, the source synchronous I
An external net name, a distributed clock net name, a reference net name, and a net name guided to internal logic are set in the associative table 3 using the / O macro name as a key. Next, the process of steps A3 to A7 is repeated for each element of Table 2. The following process is repeated for each external net of the connection information of the source synchronous I / O currently referred to in Table 2 (steps A4 to A7).

That is, first, the placement / assignment check means 21 searches the table 1 by using the external net name of the table 2, and records from the table 1 corresponding to the external net name (placement information, transfer clock name, Get the reference name, the distribution clock name). Further, the placement and assignment check means 21 searches the table 3 using the macro name (used macro name) corresponding to the external net name in the table 2, and records (external net name, distributed clock name, A reference name and a net name to internal logic) are obtained (step A4).

Next, the arrangement and assignment check means 21
Checks the match between the used macro name and the macro name of the allocable information obtained from Table 1 (step A5, FIG. 3).
Step B1) of step 1), if they do not match, a placement error indicating that the placement is inappropriate is output. (Step B2).
If they match, it is determined that the arrangement is proper and the process proceeds to the next process. As a result, the placement / assignment checking means 21 can select an appropriate macro corresponding to the placeable information and perform an appropriate placement check.

The placement / assignment checking means 21 determines that the current external net is the first net (the processing for the first external net name in Table 2).
Stores the ID of the arrangeable information obtained from the table 1 in the allocation information storage means (not shown) provided in the storage device 2 (steps B3 and B4). The placement and assignment check means 21 checks the second net and the subsequent nets for a match with the ID stored in the first net (step B5), and if they do not match, gives an assignment error indicating that an assignment shift has occurred. Output (step B6). If they match, it is determined that the assignment is proper and the process proceeds to the next step. As a result, the placement / assignment checking means 21 selects the macro to which the same ID is assigned, and therefore checks whether the assignment is proper,
You can check the assignment deviation.

The arrangement / assignment checking means 21 determines the external net names in the table 2 in order from the first external net name (first net) in the table 2.
The placement check process and the assignment check process are performed. The above processing enables the placement and assignment check means 21 to inspect the I / O primitives for proper placement and assignment at the logic design stage.

Next, the signal line connection rule generation means 22
The transfer clock name obtained from table 1 and the transfer clock name in the source synchronous I / O macro obtained from table 3 are checked for coincidence (steps A6, C1, C2). If they do not match, the transfer clock connection is inappropriate. A transfer clock connection error indicating that is is output (step C3).
Next, the signal line connection rule generation means 22 generates a net connection rule. That is, the external net in the record macro of Table 3 is connected to the external net of interest at present, the clock net in the macro and the reference net are connected to the distributed clock and the reference in Table 1, and the net guided to the internal logic is displayed in the table. A rule for connecting to the net corresponding to the record 2 is generated (step A7).

Next, the connection / hierarchy assembling means 23 receives the signal line connection rule and the I / O macro netlist as input, and according to the signal line connection rule, the I / O
The macros are connected to each other, and the entire connected I / O macro is
Assemble as a circuit hierarchy of the / O part and create a netlist. At this time, an input external terminal is automatically generated for the source open net and an output external terminal is automatically generated for the load open net. The hierarchy expanding means 24
I / O created by connection / layer assembly means 23
With reference to the I / O macro netlist 34 and the library 35, the netlist of the partial circuit is expanded to the primitive block level, and is output to the storage device 2 as the I / O partial circuit netlist 36. The storage device 2 is I
The / O partial circuit netlist 36 is stored.

A more detailed description will be given below. As shown in FIGS. 5, 6, and 7, the LSI external net information 31, I
/ O partial circuit connection information 32, I / O macro specification information 33
Are respectively input by, for example, spreadsheet software and prepared in advance. Now, it is assumed that these are given from the storage device 2 to the file reading means 20. The file reading means 20 uses the LSI external net information 31 shown in FIG.
From the 3rd to 13th rows of, using the external net name in the A column as a key,
The source synchronous I / O allocable information in column B, the transfer clock in column C, the reference net name in column D, and the distributed clock in column E are set in the associative table 1 (see FIG. 8).

Further, the file reading means 20 uses the I / O
From the 3rd to 4th rows of the O partial circuit connection information 32, the external net in the B column, the I / O macro name in the A column, and the net to the internal logic in the C column are set in the list table 2 (see FIG. 9). At this time, a bus description such as X (start bit-end bit) can be made in columns B and C. For example, in the example of FIG. 6, A (0-15) = A (0), A (1), ..., A (15) D (16-23) = D (16) ,. 23).

The file reading means 20 uses the I / O
The 3rd to 4th lines of the O macro specification information 33 are associated with the external net of the B column, the distributed clock of the C column, the reference net name of the D column, and the net to the internal logic of the E column by using the macro name of the A column as a key. Set on Table 3 (see FIG. 10).
The above is the file reading means 20 in step A1.
Processing. Table 2 of FIG. 9 which is a list table
Looking at the record in the third row of, the external net is A (0
-15), X2SCKT, and X2SCCK. Now, expand the bus description A (0-15) to
(0), A (1), ..., A (15), X2SCK
Obtain T, X2SCCK. The first external net A (0) is searched for the association table 1 (see FIG. 8), and the external net is A
The data of (0) is obtained.

Further, when the association table 3 (see FIG. 10) is searched using the I / O macro (that is, the macro in the third row of table 2) SSX2 used as a key,
The data whose macro name is SSX2 is obtained (step A4).
Since the allocable macro name SSX2 of the source synchronous I / O allocable information (9th row and Bth column) obtained from Table 1 matches the used macro name SSX2,
It is confirmed by the placement check that the placement is proper (step B1). Since the assignment check is the first net, ID1 is stored (steps B3 and B4). The transfer clock connectivity check is not processed because the transfer clock (9th row and C column) obtained from Table 1 is empty (steps A6 and C1).

Next, the external net D in the macro of Table 3
(0) to A (0), net to internal logic is DAT
(0) corresponds to ADR (0) of the corresponding table 2, distribution clock CLK, and reference net REF corresponds to distribution clock XCLK + of table 1 (9th row, D column, E column).
00 and a reference net XREF + 02, respectively, to generate rules (step A7). Such processing is repeated for the external net set (step A3 to
A7). Further, the processing for this 1-source synchronous I / O is repeated until the end of the list table 2 (steps A2 to A7).

Finally, the connection / layer assembly means 23
According to the signal line connection rule, the I / O macro netlist is connected, the hierarchy of the I / O partial circuits is assembled, and the netlist is created. Further, the hierarchical expansion means 24 expands the netlist of the circuit of the I / O part created by the connection / hierarchical assembly means 23 to the primitive block level and outputs it to the storage device 2 as the I / O partial circuit netlist 36. .

As described above, the netlist generation method of the integrated circuit according to the present embodiment is at least the netlist generation method of the integrated circuit for generating the netlist of the source synchronous I / O partial circuit. A plurality of external net names and associated external net names,
Arrangement information including a plurality of I / O soft macro names that can be arranged in a predetermined area and allocation information indicating allocation types is stored, and external net information regarding each external terminal of an integrated circuit that is a target of logic design is stored. An integrated circuit external net information storage means and at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names are stored, and an I that is a target for generating a net list.
I / O partial circuit connection information storage means for storing connection information inside the I / O partial circuit, and at least a plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names Is stored in the memory, and I / O macro specification information storage means for storing information about specifications of I / O soft macros used for generating a netlist, the integrated circuit external net information storage means, and I / O partial circuit connection information storage. From the integrated circuit external net information storage means by reading the external net information, the connection information inside the I / O partial circuit, and the information about the specifications of the I / O soft macro from the means and the I / O macro specification information storage means. A first table storing a plurality of the read external net names and a plurality of arrangable information associated with the external net names; A second table for storing the plurality of external net names read from the I / O partial circuit connection information storage means and the plurality of I / O soft macro names associated with the external net names, and at least the I / O A third table for storing the plurality of I / O soft macro names read from the macro specification information storage means and the plurality of external net names associated with the I / O soft macro names is stored in the read storage means. Reading means, inspecting means for inspecting whether the arrangement and allocation of the I / O soft macro are proper, and the reading means when the inspecting means judges that the arrangement and allocation of the I / O soft macro are proper. And a netlist generating means for generating a netlist of the I / O partial circuit based on the read information.
The checking unit searches the first table for each external net name of the second table based on the external net name of the second table and corresponds to the external net name of the second table. The I / O soft macro name included in the allocable information of the first table is extracted, and the I / O associated with the external net name of the second table is extracted.
When the O soft macro name and the I / O soft macro name included in the allocable information of the first table match, it is determined that the layout is proper, and the inspecting means sets the second soft macro.
The first table is searched based on the external net name of the table and the allocation information included in the allocable information of the first table corresponding to the external net name of the second table is extracted and stored. Allocation information storage means, for each external net name in the second table, after storing the allocation information of the first net in the allocation information storage means, based on the external net name in the second table Allocation information stored in the allocation information storage means is allocation information included in the allocable information of the first table corresponding to the external net name of the second table obtained by searching the first table. It is characterized in that the allocation of the I / O soft macro is judged to be appropriate when it matches the information. Therefore, the external net for connecting to the macro can be allocated by referring to the source synchronous I / O macro allocable information of the LSI external net information 31, and the validity of the allocation and allocation can be automatically checked. In the preparation of the I / O partial circuit netlist including the source synchronous I / O of the soft macro structure, it is possible to properly and efficiently allocate to the predetermined allocable area on the base of the integrated circuit.

Further, according to the present embodiment, the transfer clock net name previously described in the LSI external net information 31 and the transfer clock net name in the actually connected source synchronous I / O macro are associated with each other. Therefore, the transfer clock (positive polarity, negative polarity) of the source synchronous I / O can be accurately connected. Further, since the connection is automatically made based on the reference net name to be actually connected which is described in advance in the LSI external net information 31, the connection of the reference signal which is a common signal of the source synchronous I / O is performed. The / O partial circuit netlist creator can be connected without describing.

Further, since the soft macro structure is possible, there is an effect that the source synchronous I / O does not need to be made into a hard macro. Moreover, the program according to the present embodiment is configured to cause the computer to function as described above. Therefore, it is possible to obtain the above-mentioned effects by causing the computer to execute the program.

[0059]

As described above, according to the present invention, it is possible to accurately and efficiently allocate a nettable of a source synchronous I / O partial circuit having a soft macro structure to a distributable area on a base. In addition, source synchronous I / O
This has the effect of eliminating the need for hard macro conversion.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 4 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 5 is a diagram showing LSI external net information used in the embodiment of the present invention.

FIG. 6 is a diagram showing I / O partial circuit connection information used in the embodiment of the present invention.

FIG. 7 is a diagram showing I / O macro specification information used in the embodiment of the present invention.

FIG. 8 is a diagram showing a table 1 memory image used in the embodiment of the present invention.

FIG. 9 is a diagram showing a table 2 memory image used in the embodiment of the present invention.

FIG. 10 is a table 3 used in the embodiment of the present invention.
It is a figure which shows a memory image.

FIG. 11 is a schematic diagram for explaining a conventional assignment shift.

[Explanation of symbols]

1 ... Data processing device as data processing means 2 ... Storage device 20 as storage means ... File reading means 21 ... Arrangement and assignment check means 22 as inspection means ... Netlist generation means Signal line connection rule generating means 23 constituting the ..., connection / layer stacking means constituting the net list generating means 24, layer expanding means 31 constituting the net list generating means ... as integrated circuit external net information LSI external net information 32 ... I / O partial circuit connection information 33 ... I / O macro specification information 34 ... I / O macro net list 35 ... Library 36 ... I / O partial circuit net list

Claims (4)

(57) [Claims] 1. A netlist generation method of an integrated circuit for generating a netlist of a source synchronous I / O partial circuit, which is information about each external terminal of an integrated circuit which is a target of logic design, and which is at least a plurality of external terminals. A plurality of external net names connected to the terminals and associated with the external net names,
Multiple source synchronous I / Os that can be placed in a predetermined area
I / O soft macro name and I / O, which is information indicating a macro
An integrated circuit external net information storage means for storing external net information, which is information including allocable information including allocation information indicating the type of allocation to an O pad, and at least a plurality of external net names and the external net names. I / O partial circuit connection information storage means for storing connection information inside the I / O partial circuit which is a target for generating a netlist and has a plurality of attached I / O soft macro names; I / O soft macro name and I / O
An I / O macro specification information storage unit having a plurality of external net names associated with the O soft macro name, which stores information about the specifications of the I / O soft macro used to generate the netlist; From the net information storage means, the I / O partial circuit connection information storage means, and the I / O macro specification information storage means, the external net information, the connection information inside the I / O partial circuit, and the information about the specifications of the I / O soft macro are stored. A first table that stores at least the plurality of external net names read from at least the integrated circuit external net information storage means and a plurality of allocable information associated with the external net names; and at least the I / O A plurality of external net names read from the partial circuit connection information storage means and a plurality of I / O software associated with the external net names A second table storing macro names, a plurality of I / O soft macro names read from at least the I / O macro specification information storage means, and a plurality of external nets associated with the I / O soft macro names Third to store first name
And a second reading means for storing the first table on the basis of the external net name of the second table for each external net name of the second table. I included in the allocable information of the first table corresponding to the external net name of the table
/ O soft macro name is extracted and the I / O soft macro name associated with the external net name in the second table and the I / O soft macro name included in the arrangable information in the first table are extracted.
When the / O soft macro names match, it is determined that the placement is proper, and the first table is searched based on the external net name of the second table to correspond to the external net name of the second table. There is an allocation information storage unit that extracts and stores the allocation information included in the allocable information of the first table, and the allocation information of the first net is stored for each external net name of the second table. The first net corresponding to the external net name of the second table obtained by searching the first table based on the external net name of the second table after storing in the allocation information storage means. If the allocation information included in the table allocable information matches the allocation information stored in the allocation information storage means,
An inspecting unit that determines the allocation of the I / O soft macro as appropriate and inspects whether the I / O soft macro is arranged and allocated based on the information read by the reading unit, and the inspecting unit is the I / O software. An integrated circuit comprising: a netlist generating means for generating a netlist of the I / O partial circuit based on the information read by the reading means when the macro placement and allocation are judged to be proper. Circuit netlist generation method. 2. The netlist generating means stores information about the external net information stored in the first, second and third tables, connection information inside an I / O partial circuit, and information about specifications of an I / O soft macro. Signal line connection rule generating means for generating a connection rule based on the above, and connecting the I / O soft macros according to the connection rule generated by the signal line connection rule generating means,
The connected I / O soft macro is assembled as a hierarchy of I / O partial circuits, and a connection / layer assembly means for creating a netlist, and the netlist created by the connection / layer assembly means are expanded to the primitive block level. 2. A netlist generation method for an integrated circuit according to claim 1, further comprising a hierarchical expansion means for generating a netlist of a predetermined level. 3. A computer, which is information about each external terminal of an integrated circuit that is a target of logic design, and is associated with at least a plurality of external net names connected to a plurality of external terminals and the external net name.
Multiple source synchronous I / Os that can be placed in a predetermined area
I / O soft macro name and I / O, which is information indicating a macro
Integrated circuit external net information storage means for storing external net information, which is information including placeable information including allocation information indicating allocation type to O pad, and I / O partial circuit for generating net list I / O partial circuit connection information storage means for storing at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names, which is internal connection information, and generation of a net list I / O macro that stores at least a plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names, which is information regarding the specifications of the I / O soft macros used for From the specification information storage means to the integrated circuit external net information storage means, the I / O partial circuit connection information storage means, the I / O macro specification information storage means to the external network The information, the connection information inside the I / O partial circuit, and the information regarding the specifications of the I / O soft macro are read to correspond to at least the plurality of external net names and the external net names read from the integrated circuit external net information storage means. A first table storing a plurality of pieces of allocable information attached thereto, a plurality of external net names read from at least the I / O partial circuit connection information storage means, and a plurality of Is associated with the external net names. A second table for storing I / O soft macro names, a plurality of I / O soft macro names read from at least the I / O macro specification information storage means, and a plurality of I / O soft macro names associated with the I / O soft macro names. And a third table for storing the external net name of the To test the suitability of the arrangement and assignment of the I / O software macros based on the information,
For each external net name of the second table, the first table is searched based on the external net name of the second table to correspond to the external net name of the second table. Included in the deployable information of
/ O soft macro name is extracted and the I / O soft macro name associated with the external net name in the second table and the I / O soft macro name included in the arrangable information in the first table are extracted.
When the / O soft macro names match, it is determined that the placement is proper, and the first table is searched based on the external net name of the second table to correspond to the external net name of the second table. There is an allocation information storage unit that extracts and stores the allocation information included in the allocable information of the first table, and the allocation information of the first net is stored for each external net name of the second table. The first net corresponding to the external net name of the second table obtained by searching the first table based on the external net name of the second table after storing in the allocation information storage means. If the allocation information included in the table allocable information matches the allocation information stored in the allocation information storage means,
An inspecting unit that determines that the I / O soft macro allocation is proper; and the I / O based on the information read by the reading unit when the inspecting unit determines that the I / O soft macro arrangement and allocation are proper. A program which functions as a netlist generating means for generating a netlist of O partial circuits. 4. The net list generating means stores the external net information stored in the first, second, and third tables, connection information inside the I / O partial circuit, and information about specifications of the I / O soft macro. And a connected I / O soft macro according to the connection rule generated by the signal line connection rule generation means and the signal line connection rule generation means for generating a connection rule based on the I / O soft macro. The whole is assembled as a hierarchy of I / O partial circuits,
A connection / hierarchical assembling unit for generating a netlist, and a hierarchical expansion unit for expanding the netlist generated by the connection / hierarchical assembling unit to a primitive block level to generate a netlist of a predetermined level. 4. The program according to claim 3, which causes the computer to function.