JP2002269164A - Net list generating system and program for integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable proper and efficient location and assignment to an array enable area on the base when preparing the net list of a circuit in the source synchronous I/O part of soft macro configuration. SOLUTION: After an array and assign check means 21 judges the array and assignment of I/O soft, macro is proper by using external LSI net information 31, I/O part circuit connection information 32 and I/O macro specification information 33 read from a storage device 2 by a file reading means 20, a signal line connection rule generating means 22 generates connection rules, a connection/hierarchy assembling means 23 generates the net list by assembling the entire I/O soft macro as a hierarchy of I/O part circuits, and a hierarchy expanding means 24 generates an I/O part circuit net list 36 by expanding the hierarchy to a primitive block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit netlist generation method and a program for generating a netlist of circuits in an input / output (I / O) portion of an integrated circuit.

[0002]

2. Description of the Related Art Conventionally, LSI (Large Scale Integr
CAD) when designing integrated circuits such as
Automatic design using (Computer Aided Design) is performed (for example, Japanese Patent Application Laid-Open No. 2000-105782,
JP-A-2000-340753, JP-A-11-30
No. 7644 and Japanese Patent No. 3024593. ). When designing an integrated circuit, it is performed using a macro, which is a unit block that performs a certain operation.
Macros are divided into hard macros and soft macros.

A hard macro defines the arrangement and wiring position (layout) of individual circuit elements constituting a circuit on a semiconductor chip. Each element such as a transistor and a resistor is combined on a semiconductor chip to form each circuit element. A device in which devices are arranged and wires are connected between the devices, NAND, NO
There is a type in which basic logic circuits such as R, flip-flop (FF) are combined, each logic circuit is arranged, and wiring between the logic circuits is performed.

On the other hand, the soft macro does not define the arrangement between the circuit elements unlike the hard macro, and for example, describes only the connection relationship between the individual circuits, such as a netlist, and has a layout. It does not include the placement information and the wiring information which are the information of the result of the above. by the way,
The above-mentioned Japanese Patent Application Laid-Open No. 2000-105782 discloses an invention for efficiently creating a netlist of a circuit of an I / O portion of a single-bit (single) I / O primitive configuration in an LSI logic design of a standard cell system. Have been.

[0005]

However, in the invention described in the above publication, the source synchronous I / O
(I / O configured such that a data transmission side transmits data and the transfer clock signal to a data reception side in synchronization with a transfer clock, and the data reception side receives the data in synchronization with the transfer clock. ) Is composed of a soft macro, the area that can be arranged on the base is limited, and assignment (assignment of external nets and I / O primitives to I / O pads) is not allowed from the viewpoint of delay design. Since it is difficult to assign a macro to a plurality of bits, such as source synchronous I / O, there is a problem that it is not possible to deal with macros.

FIG. 11 is a schematic diagram showing an example of a case where an assignment shift occurs. FIG. 11 shows an example of a 4-bit source synchronous I / O.
Reference numerals 102 and 1103 denote assignments of a source synchronous macro covering a plurality of bits, and reference numeral 1104 denotes an LSI base. In FIG. 11A, the source synchronous I / O macros are properly assigned, but in FIG. 10B, the same macros as those in FIG. 9A are used, but the assignments are made incorrectly. (Assignment) misalignment has occurred.

In the source synchronous I / O, when connecting signals, not only data pins (a plurality of bits), but also transfer clocks (positive and negative) and reference signals must be accurately connected. However, there is a problem that the invention described in the above publication cannot cope with the problem. On the other hand, in order to solve the above-described assignment deviation, there is a method of converting the source synchronous I / O into a hard macro. There is a problem that a large number of hard macros need to be created and a large number of work steps are required.

An object of the present invention is to make it possible to properly and efficiently arrange and allocate a circuit in a placeable area on a base in creating a netlist of a circuit of a source synchronous I / O portion having a soft macro configuration.

[0009]

According to the present invention, in an integrated circuit netlist generation system for generating a netlist of source synchronous I / O partial circuits, each external terminal of an integrated circuit to be logically designed is provided. Integrated circuit external net information storage means for storing external net information related to I / O partial circuit connection information storage means for storing connection information inside an I / O partial circuit for which a net list is to be generated; I / O macro specification information storage means for storing information on the specifications of I / O soft macros used for generating the
Reading means for reading the external net information, connection information inside the I / O partial circuit, and information on the specifications of the I / O soft macro from the O partial circuit connection information storage means and the I / O macro specification information storage means; Checking means for checking the placement and allocation of I / O soft macros based on the information read by the means;
And a netlist generating means for generating a netlist of the I / O partial circuit based on the information read by the reading means when the arrangement and allocation of the O soft macros are determined to be proper. A netlist generation method for an integrated circuit is provided.

The integrated circuit external net information storage means stores external net information relating to each external terminal of the integrated circuit to be logically designed. The I / O partial circuit connection information storage means stores connection information inside the I / O partial circuit for which a net list is to be generated. The I / O macro specification information storage means stores the I / O macro specification information used for generating the netlist.
O Stores information on the specifications of the soft macro. Reading means, the integrated circuit external net information storage means,
From the I / O partial circuit connection information storage means and I / O macro specification information storage means, the external net information, the connection information inside the I / O partial circuit, and the information on the specifications of the I / O soft macro are read. The inspecting unit inspects the placement and allocation of the I / O soft macros based on the information read by the reading unit. The netlist generation means generates a netlist of the I / O partial circuit based on the information read by the reading means when the inspection means determines that the arrangement and allocation of the I / O soft macros are appropriate.

Here, the integrated circuit external net information storage means stores at least a plurality of external net names and a plurality of I / O soft macro names which can be arranged in a predetermined area and are associated with the external net names. The I / O partial circuit connection information storage means stores at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names, At least a plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names are stored in the I / O macro specification information storage means. A first storing a plurality of the external net names read from the integrated circuit external net information storage means and a plurality of allocable information associated with the external net names; A table, at least the I / O
A second table storing a plurality of external net names read from the partial circuit connection information storage means and a plurality of I / O soft macro names associated with the external net names;
At least a plurality of I / O soft macro names read from the I / O macro specification information storage means and the I / O
A third table for storing a plurality of external net names associated with the soft macro names, and storing the read third table in the storage means, wherein the inspection means determines, for each external net name in the second table, Searching the first table based on the external net name of the table and extracting an I / O soft macro name included in the allocable information of the first table corresponding to the external net name of the second table; An appropriate arrangement when the I / O soft macro name associated with the external net name in the second table matches the I / O soft macro name included in the arrangement enable information of the first table. May be determined.

[0012] Each of the allocable information includes allocation information indicating a type of allocation, and the inspection means searches the first table based on an external net name of the second table. And allocation information storage means for extracting and storing allocation information included in the allocable information of the first table corresponding to the external net name of the second table. About net name 1
After storing the allocation information of the net in the allocation information storage means, the external network of the second table obtained by searching the first table based on the external net name of the second table When the allocation information included in the allocable information of the first table corresponding to the name matches the allocation information stored in the allocation information storage means, the allocation of the I / O soft macro is determined to be appropriate. You may comprise.

Further, the integrated circuit external net information storage means stores a transfer clock net name which is information relating to a transfer clock, a reference net name which is information relating to a reference signal, and a distribution clock which are associated with the external net name. The I / O partial connection information storage means stores a net name to internal logic associated with the I / O soft macro name, and The specification information storage means may be configured to store a distribution clock name, a reference name, and a net name to internal logic associated with the I / O soft macro name.

According to the present invention, in an integrated circuit netlist generation method for generating a netlist of a source synchronous I / O partial circuit, at least a plurality of external net names and an arrangement corresponding to the external net names are arranged. First storage means for storing external net information relating to each external terminal of an integrated circuit to be logically designed, including a plurality of allocable information having allocation information indicating a possible I / O soft macro name and an allocation type And at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names, and store connection information inside an I / O partial circuit for which a net list is to be generated. A second storage means, including at least a plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names; I / O to be used to generate the Ttorisuto
Third storage means for storing information related to the specifications of the soft macros, checking means for checking whether the arrangement and allocation of the I / O soft macros are appropriate, and allocation for storing the allocation information included in the allocable information Information storage means; and netlist generation means for generating a netlist of the I / O partial circuit when the inspection means determines that the arrangement and allocation of the I / O soft macros are proper. Means for each external net name of the second storage means,
Searching the first storage means based on the external net name, extracting the allocable information of the first storage means corresponding to the external net name of the second storage means, When the I / O soft macro name associated with the external net name and the I / O soft macro name included in the allocable information in the first storage means match, it is determined that the arrangement is proper, After storing the allocation information of the first net included in the allocable information in the allocation information storage means, and storing the allocation information in the allocation information storage means, based on the external net name of the second storage means, Assignment information, which is obtained by searching the first storage means and is included in the allocable information of the first storage means corresponding to the external net name of the second storage means, is stored in the assignment information storage means. Matches the assigned information When the netlist generation method of the integrated circuit, characterized in that to determine the proper allocation of I / O software macros are provided.

[0015] The first storage means stores at least a plurality of external net names, a plurality of I / O soft macro names which can be arranged in association with the external net names, and a plurality of arrangement possible information having allocation information indicating the type of allocation. And external net information relating to each external terminal of the integrated circuit to be logically designed. The second storage means stores at least a plurality of external net names and a plurality of I
Contains the / O soft macro name and stores connection information inside the I / O partial circuit for which the netlist is to be generated. The third storage means includes at least a plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names, and stores the I / O soft macro names used for generating the netlist. Stores information about specifications. The allocation information storage unit stores the allocation information included in the allocable information. The net list generating means is I
When the checking means for checking whether the arrangement and allocation of the I / O soft macros are appropriate determines that the arrangement and allocation of the I / O soft macros are appropriate, a net list of the I / O partial circuit is generated. For each external net name of the second storage unit, the inspection unit searches the first storage unit based on the external net name, and searches the first storage unit corresponding to the external net name of the second storage unit. And extracting I / O soft macro names associated with the external net names in the second storage means and I / O soft macro names included in the first storage means. When the / O soft macro name matches, it is determined that the layout is proper, and the allocation information of the first net included in the layout possible information is stored in the allocation information storage means, and the allocation information is stored in the allocation information storage means. After storing, obtained by searching the first storage means based on the external net name of the second storage means,
The first storage unit corresponding to the external net name in the second storage unit;
When the allocation information included in the arrangement possible information of the storage unit of the storage unit matches the allocation information stored in the allocation information storage unit, the allocation of the I / O soft macro is determined to be appropriate.

[0016] The net list generating means includes signal line connection rule generating means for generating a connection rule based on the external net information, connection information inside the I / O partial circuit, and information on the specifications of the I / O soft macro. The I / O soft macros are connected according to the connection rule generated by the signal line connection rule generation means, and the connected I / O soft macros are connected.
The entire I / O soft macro is assembled as a hierarchy of I / O partial circuits, a connection / hierarchy assembling means for generating a netlist, and the netlist generated by the connection / hierarchy assembling means is expanded to a primitive block level, and And a hierarchy expanding means for generating a level netlist.

According to the present invention, a computer is
Integrated circuit external net information storage means for storing external net information relating to each external terminal of an integrated circuit which is a target of logic design; and I which stores connection information inside an I / O partial circuit for which a net list is generated / O partial circuit connection information storage means, I / O macro specification information storage means for storing information relating to specifications of I / O soft macros used for generating a netlist, and the integrated circuit external net information storage means, Reading means for reading the external net information, connection information inside the I / O partial circuit, and information on the specifications of the I / O soft macro from the O partial circuit connection information storage means and the I / O macro specification information storage means; Inspection means for inspecting the I / O software macro for proper placement and assignment based on the information read by the means; A program is provided, which, when it is determined that the arrangement and assignment of the crosses are appropriate, function as a net list generating means for generating a net list of the I / O partial circuit based on the information read by the reading means. Is done.

By executing the program according to the present invention on a computer, the computer comprises: an integrated circuit external net information storage means for storing external net information relating to each external terminal of the integrated circuit to be logically designed; I / O partial circuit connection information storage means for storing connection information inside the I / O partial circuit for which the generation of the I / O is performed, and I for storing information relating to the specifications of the I / O soft macro used for generating the netlist. / O macro specification information storage means, the integrated circuit external net information storage means,
Reading means for reading the external net information, connection information inside the I / O partial circuit, and information on the specifications of the I / O soft macro from the O partial circuit connection information storage means and the I / O macro specification information storage means; Checking means for checking the placement and allocation of I / O soft macros based on the information read by the means;
When it is determined that the arrangement and allocation of the O soft macros are proper, it functions as a net list generating means for generating a net list of the I / O partial circuit based on the information read by the reading means.

Here, the computer may be provided in the integrated circuit external net information storage means with at least a plurality of external net names and a plurality of I / O software which can be arranged in a predetermined area associated with the external net names. The I / O partial circuit connection information storage means stores at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names. The I / O macro specification information storage means stores at least a plurality of I / O soft macro names and the I / O macro name.
A plurality of external net names associated with the soft macro name are stored, and the reading unit is associated with the plurality of external net names and the external net names read from at least the integrated circuit external net information storage unit. A first table for storing a plurality of allocable information; a plurality of external net names read from at least the I / O partial circuit connection information storage means; and a plurality of I / O software associated with the external net names A second table for storing macro names, at least a plurality of I / O soft macro names read from the I / O macro specification information storage means, and a plurality of external networks associated with the I / O soft macro names; A third table for storing the names of the external nets in the second table; Te, the second by searching the first table based on an external net name of the second table
The I / O software macro name included in the allocable information of the first table corresponding to the external net name of the table is extracted, and the I / O software associated with the external net name of the second table is extracted. The program may be configured to function so as to determine an appropriate arrangement when a macro name matches the I / O soft macro name included in the arrangement possible information of the first table.

[0020] Further, the computer may be arranged such that each of the allocable information includes allocation information indicating a type of allocation, and the inspection means reads the first table based on the external net name of the second table. An allocation information storage unit for searching and extracting allocation information included in the allocable information of the first table corresponding to the external net name of the second table, and storing the extracted allocation information; For the external net name, after storing the allocation information of the first net in the allocation information storage means, the second table obtained by searching the first table based on the external net name of the second table, When the allocation information included in the allocable information of the first table corresponding to the external net name of the second table matches the allocation information stored in the allocation information storage means,
The program may be configured to function so as to determine that the allocation of the I / O soft macro is appropriate.

The integrated circuit external net information storage means further includes a transfer clock net name as information relating to a transfer clock and a reference net name as information relating to a reference signal, which are associated with the external net name. And a distribution clock name, which is information relating to the distribution clock, and the I / O partial connection information storage means stores a net name to internal logic associated with the I / O soft macro name. The program may be configured so that the / O macro specification information storage means functions to store a distribution clock name, a reference name, and a net name to internal logic associated with the I / O soft macro name. Good.

According to the present invention, a computer is
An integrated circuit to be subjected to logical design, including at least a plurality of external net names and a plurality of allocable information having allocation information indicating a type of allocation and an I / O soft macro name which can be allocated in association with the external net name; A first storage unit for storing external net information relating to each external terminal, and at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names, and generating a net list. A second storage unit for storing connection information inside an I / O partial circuit to be performed;
Third storage means for storing information relating to the specifications of an I / O soft macro used for generating a netlist, the information including a / O soft macro name and a plurality of external net names associated with the I / O soft macro name Checking means for checking whether the arrangement and allocation of the I / O soft macros are proper; allocation information storing means for storing allocation information included in the allocable information; And a net list generating means for generating a net list of the I / O partial circuit when it is determined that the placement and allocation of the external nets are appropriate. , The first storage means is searched based on the external net name, and the allocable information of the first storage means corresponding to the external net name of the second storage means is extracted; When the I / O soft macro name associated with the external net name in the storage unit and the I / O soft macro name included in the arrangement possible information in the first storage unit match, it is determined that the arrangement is proper. At the same time, the allocation information of the first net included in the allocable information is stored in the allocation information storage means, and after the allocation information is stored in the allocation information storage means, based on the external net name of the second storage means. The allocation information included in the allocable information of the first storage means corresponding to the external net name of the second storage means, which is obtained by searching the first storage means, When it matches the assignment information stored in
A program is provided which causes the assignment of the / O soft macro to be determined to be appropriate.

By executing the program according to the present invention on a computer, the computer indicates at least a plurality of external net names, I / O soft macro names that can be arranged in association with the external net names, and types of allocation. First storage means including a plurality of allocable information having allocation information and storing external net information on each external terminal of the integrated circuit to be logically designed; and at least a plurality of external net names and the external net names Second storage means for storing connection information inside an I / O partial circuit for which a net list is to be generated, including a plurality of associated I / O software macro names, and at least a plurality of I / O software macro names I / O software used for generating a netlist, including a macro name and a plurality of external net names associated with the macro name Third storage means for storing information relating to black specifications, inspection means for checking whether the arrangement and allocation of I / O soft macros are appropriate, and allocation information for storing allocation information included in the layout possible information Storage means; and netlist generation means for generating a netlist of the I / O partial circuit when the inspection means determines that the arrangement and allocation of the I / O soft macros are appropriate. Retrieves, for each external net name of the second storage means, the first storage means based on the external net name, and retrieves the first storage corresponding to the external net name of the second storage means. Means that can be arranged by the means is extracted, and the I information associated with the external net name in the second storage means is extracted.
When the / O soft macro name and the I / O soft macro name included in the allocable information in the first storage unit match, it is determined that the arrangement is appropriate, and the first net included in the allocable information is determined. After storing the allocation information in the allocation information storage means and storing the allocation information in the allocation information storage means, the allocation information is obtained by searching the first storage means based on the external net name of the second storage means. When the allocation information included in the allocable information of the first storage device corresponding to the external net name of the second storage device matches the allocation information stored in the allocation information storage device, O Functions to determine that the assignment of the soft macro is appropriate.

The computer may be configured such that the net list generating means generates a connection rule based on the external net information, the connection information inside the I / O partial circuit, and the information on the specifications of the I / O soft macro. Means for connecting the I / O soft macros in accordance with the connection rule generated by the signal line connection rule generation means, and assembling the entire connected I / O soft macro as a hierarchy of I / O partial circuits; A connection / hierarchy assembling means for generating a list, and a netlist generated by the connection / hierarchy assembling means are expanded to a primitive block level to have a function as a hierarchy expanding means for generating a netlist of a desired level. The program may be configured to function.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a netlist generation method and a program for an integrated circuit according to an embodiment of the present invention will be described. FIG. 1 is a block diagram of a system for automatically generating a netlist of an integrated circuit used in an embodiment of the present invention. The source synchronous I / O (a data transmitting side synchronizes a data and a transfer clock signal with a transfer clock). A source synchronous I / O part for transmitting to a data receiving side and generating a netlist of an I / O) part circuit configured such that the data receiving side receives the data in synchronization with the transfer clock. 1 shows an example of a circuit netlist automatic generation system.

In FIG. 1, a net list generation system for an integrated circuit stores a data processing device 1 as data processing means for generating a net list, and information necessary for the data processing device 1 to generate a net list. And a storage device 2 as storage means for storing the netlist generated by the data processing device 1. The data processing device 1 can be configured by a computer including a central processing unit (CPU) and a storage device storing a program, and the storage device 2 is configured by various storage media such as a magnetic disk and a semiconductor memory. be able to. In the present embodiment, a program processed by the CPU is stored in the storage device 2.

The storage device 2 stores LSI external net information 31
An integrated circuit external net information storage means in which
I / O partial circuit connection information storage means in which I / O partial circuit connection information 32 is stored in advance, I / O macro specification information storage means in which I / O macro specification information 33 is stored in advance, and I / O macro netlist 34 And an I / O macro net list storing means for storing the library 35 in advance, and a library storing means for storing the library 35 in advance.
An I / O partial circuit netlist storage means is provided as an output destination of the netlist generated in step (1). The I / O partial circuit netlist 36 generated by the data processing device 1 is stored in the I / O partial circuit netlist storage means.

The LSI external net information 31, I / O partial circuit connection information 32, and I / O macro specification information 33 are used when the data processing apparatus 1 generates a net list.
The I / O macro netlist 34 and the library 35 are various types of information used for generating various types of connection information (connection rules). Information.

The LSI external net information 31 is external net information of the LSI to be logically designed. For each of the LSI external terminals, an external terminal name, a net name of an external net connected to the external terminal, an external signal name, This is information for each product type including source synchronous I / O allocable information, a transfer clock net name, and a reference net name. The allocable information includes information (at least a macro name) indicating an I / O soft macro allocable to the corresponding area. still,
The external net name can be described in one line by specifying a start bit and an end bit, such as X (start bit-end bit), as described later.

The I / O partial connection information 32 contains the source synchronous I / O connection information of the circuit of the source synchronous I / O part for which the netlist is generated.
This is the connection information of the circuit of the I / O part defined at the macro (I / O buffer) level. I / O macro specification information 33
Is information relating to the specification of the source synchronous I / O macro used for generating the netlist. The macro name, the signal name in the macro (external signal, internal logic) defined for each type of source synchronous I / O. Connected signals, a distribution clock signal, and a reference signal).

The I / O macro netlist 34 is a netlist of source synchronous I / O soft macros.
This is information stored in advance. Library 35 contains I /
Primitive blocks containing O-buffers (leaf cells;
(Specific AND gate and OR gate of the target circuit)
, And terminal name information of the terminal of the primitive block are stored in advance. The I / O partial circuit netlist 36 is a netlist of circuits of the synchronous I / O part at the primitive block level, in which the source synchronous I / O macro is expanded and output from the data processing device 1.

The data processing device 1 includes a file reading means 20 for reading a necessary file from the storage device 2,
An arrangement and assignment check unit 21 for checking the arrangement and assignment of O soft macros, a signal line connection rule generation unit 22 for generating various connection rules, and a connection / hierarchy assembling unit 2 for generating a netlist of I / O partial circuits
3 and a hierarchy expanding means 24. The file reading means 20 reads information from the LSI external net information 31, I / O partial circuit connection information 32, and I / O macro specification information 33, and sets the information in a table provided therein. The file reading means 20 is provided with a reading storage means (not shown). As described later, the reading storage means includes LSI external net information 31, I / O partial circuit connection information 32, and I / O Two association tables (table 1 and table 3) and one list table (table 2) are prepared corresponding to the macro specification information 33. The part storing the table 1 of the read storage means and the LSI external net information storage means constitute a first storage means, and the part storing the table 2 of the read storage means and the I / O partial circuit connection. The information storage means constitutes a second storage means, and a portion for storing the table 3 of the read storage means and the I / O
The macro specification information storage means constitutes a third storage means.

The arrangement and assignment checking means 21 includes L
According to the source synchronous I / O allocable information of the SI external net information 31 and the transfer clock net name, it is checked whether a correct type of source synchronous I / O soft macro is allocated and assigned to an appropriate area, and the transfer clock is determined. (Positive or negative transfer clock) Check the suitability of net connectivity. The arrangement and assignment checking means constitutes inspection means for inspecting the suitability of the arrangement and assignment.

The signal line connection rule generation means 22 has an I / O
With reference to the partial circuit connection information 32 and the LSI external net information 31, connection information is created in the form of a connection rule and output to the connection / hierarchy assembling means 23. The connection / hierarchy assembling means 23 connects the I / O macros in accordance with the connection rules created by the signal line connection rule generating means 22, and connects the entire connected I / O macros to the circuit hierarchy of the I / O part. And create a netlist. At this time, an external terminal of the I / O circuit is also generated.

The hierarchy expanding means 24 refers to the I / O macro netlist 34 and the library 35 as needed to convert the netlist of the circuit of the I / O part created by the connection / hierarchy assembling means 23 to the primitive block level. To expand. This output is the I / O partial circuit netlist 36. The hierarchy expanding means 24 outputs the generated I / O partial circuit netlist 36 to the storage device 2, and the I / O partial circuit netlist storage means of the storage device 2 stores the I / O partial circuit netlist 36.

Next, an outline of the operation of the circuit automatic generation system for the source synchronous I / O portion configured as described above will be described. In the case of the circuit of the I / O part,
/ O Primitive Assignment to I / O Pad (Assign)
Is decided, I / O can be done without layout design.
Considering that it is obvious that the primitive is arranged near the I / O pad, the arrangement check and the assignment check are performed at the logic design stage. Here, the arrangement means the arrangement of I / O primitives on the layout, and the assignment means to which I / O pad the external net and I / O primitive are assigned.

According to the present system, in the source synchronous I / O partial circuit netlist generation method for outputting the netlist of the circuit of the source synchronous I / O part in the integrated circuit, it is necessary to generate a netlist such as connection information. Information is input in advance to a database such as a spreadsheet software, a source synchronous I / O soft macro arrangement check and an assignment check are performed, and each signal is connected to the source synchronous I / O. A configuration is provided that can output a netlist of a partial circuit. Here, the source synchronous I / O soft macro is a soft macro that supports transfer of a plurality of bits and has pins for a transfer clock, a reference signal, a distribution clock, and the like in addition to a transfer data pin.

The LSI external net information 31 includes, in addition to the I / O net name, source synchronous I / O allocable information which is information on allocable source synchronous I / O macros, a transfer clock net name, and , A reference net name which is a net name of a reference signal to be distributed, and a distribution clock net name. The arrangement and assignment checking means 21 obtains the corresponding source synchronous I / O arrangement possible information from the external net of the I / O partial circuit connection information 32, and judges the validity and the assignment deviation of the macro used. The connection relation of the signals is processed by the signal line connection rule generation unit 22. At this time, the rules for connecting the reference net and the distribution clock of the source synchronous I / O soft macro to the net to be distributed are output.

In the I / O partial circuit connection information 32, the net list is actually generated by the connection / hierarchy assembling means 23 and the hierarchy expanding means 2 for connecting the nets in accordance with the connection rules.
4 output. In this way, it is possible to output a source synchronous I / O partial circuit netlist whose arrangement and assignment have been checked from the I / O partial circuit connection information 32 input only to external nets and nets to internal logic. . Note that the signal line connection rule generation means 22,
The hierarchy assembling means 23 and the hierarchy expanding means 24 constitute a net list generating means.

FIGS. 2 to 4 are flowcharts showing the processing in the embodiment of the present invention. FIG. 2 is a flowchart showing the overall processing, and FIGS. 3 and 4 are flowcharts showing the details of the branch processing in FIG. It is. FIG. 5 is a table showing the contents of the LSI external net information 31, and FIG.
Is a table showing the contents of the I / O partial circuit connection information 32;
FIG. 7 is a table showing the contents of the I / O macro specification information 33, FIG. 8 is a view showing Table 1, which is a first table,
FIG. 9 is a diagram showing Table 2 which is a second table.
0 is a diagram showing Table 3, which is the third table.

Hereinafter, the overall operation of the present embodiment will be described in detail with reference to FIGS. In FIG. 1, the file reading means 20
It reads I external net information 31, I / O partial circuit connection information 32, and I / O macro specification information 33. The file reading means 20 analyzes these files and sets them in the association table and the list table (step A1 in FIG. 2). The associative table is a table having a data structure of a method of storing a key value and related data or a set of data in association with each other. Therefore, after storing the data, the key can be used to obtain data associated with the key.

At step A1, the file reading means 20 uses the name of the external net connected to the external terminal of the LSI as a key from the LSI external net information 31 as shown in FIG.
As shown in Table 1, the external net name (column A), source synchronous I / O allocable information (column B), transfer clock net name (column C), and reference net name (D
Column) and the distribution clock (column E) to be input to the I / O macro are set in the association table 1. Here, the format of the source synchronous I / O allocable information is the
The source synchronous I / O macro names (SSX1 and SSX2 in FIG. 8) which may be arranged in the / O area and the unique identification symbols (ID) (0 and 1 in FIG. 8) for all I / O macros are sharpened. They are connected by the symbol '#'.
The macro name is information indicating the type of macro, and the ID is allocation information indicating the type of allocation to the I / O pad.

Also, the file reading means 20
As shown in Table 2, I / O partial circuit connection information 3
From 2, external net, source synchronous I / O used
The O macro name and the net leading to the internal logic are set in the list table 2, and as shown in Table 3 of FIG.
From the I / O macro specification information 33, the source synchronous I
Using the / O macro name as a key, an external net name, a distribution clock net name, a reference net name, and a net name guided to the internal logic are set in the association table 3. Next, the processing of steps A3 to A7 is repeated for each element of table 2. The following processing is repeated for each external net of the connection information of the source synchronous I / O currently referred to in Table 2 (steps A4 to A7).

That is, first, the arrangement and assignment checking means 21 searches the table 1 using the external net name of the table 2, and from the table 1, records corresponding to the external net name (arrangement information, transfer clock name, Reference name, distribution clock name). Further, the arrangement and assignment checking means 21 searches the table 3 using a macro name (used macro name) corresponding to the external net name in the table 2, and records (an external net name, a distribution clock name, Reference name, net name to internal logic) are obtained (step A4).

Next, arrangement and assignment checking means 21
Checks whether the used macro name matches the macro name of the allocable information obtained from Table 1 (step A5, FIG. 3).
In step B1), if they do not match, an arrangement error indicating improper arrangement is output. (Step B2).
If they match, it is determined that the arrangement is proper, and the process proceeds to the next processing. As a result, the arrangement and assignment checking means 21 can select an appropriate macro corresponding to the arrangement possible information and perform an appropriate arrangement check.

The arrangement and assignment checking means 21 determines that the current external net is the first net (when the process is for the first external net name in Table 2).
Stores the ID of the allocable information obtained from the table 1 in the allocation information storage means (not shown) provided in the storage device 2 (steps B3 and B4). The arrangement and assignment checking means 21 checks the coincidence with the ID stored in the first net in the case of the second and subsequent nets (step B5), and in the case of non-match, assigns an assignment error indicating that an assignment deviation has occurred. Output (Step B6). If they match, it is determined that the assignment is proper, and the process proceeds to the next process. As a result, the arrangement and assignment checking means 21 selects a macro to which the same ID is assigned, and checks whether or not the assignment is proper, and
It is possible to check the assignment deviation.

The arrangement and assignment checking means 21 sequentially checks each external net name in Table 2 from the first external net name (first net) in Table 2.
The arrangement check processing and the assignment check processing are performed. By the above processing, the arrangement and assignment checking means 21 can check at the logic design stage so that the I / O primitive is properly arranged and assigned.

Next, the signal line connection rule generation means 22
It is checked whether the transfer clock name obtained from Table 1 matches the transfer clock name in the source synchronous I / O macro obtained from Table 3 (steps A6, C1, C2). If they do not match, the transfer clock connection is inappropriate. Is output (step C3).
Next, the signal line connection rule generation unit 22 generates a net connection rule. That is, the external net in the record macro of the table 3 is connected to the external net of interest at present, the clock net in the macro and the reference net are connected to the distribution clock and the reference in the table 1, and the net led to the internal logic is connected to the table. Then, a rule for connecting to the net corresponding to the record 2 is generated (step A7).

Next, the connection / hierarchy assembling means 23 receives the signal line connection rule and the I / O macro net list as inputs, and according to the signal line connection rule, the I / O macro netlist.
Macros are connected, and the entire connected I / O macro is
A netlist is created by assembling the circuit hierarchy of the / O portion. At this time, an input external terminal is automatically generated for the source open net, and an output external terminal is automatically generated for the load open net. The hierarchy expanding means 24 includes:
I / O created by connection / hierarchy assembling means 23
With reference to the I / O macro netlist 34 and the library 35, the hierarchy of the partial circuit netlist is expanded to the primitive block level, and is output to the storage device 2 as the I / O partial circuit netlist 36. The storage device 2 is I
The / O partial circuit netlist 36 is stored.

The following is a more detailed description. As shown in FIGS. 5, 6, and 7, the LSI external net information 31, I
/ O partial circuit connection information 32, I / O macro specification information 33
Are input and prepared in advance using spreadsheet software, for example. Now, it is assumed that these are given from the storage device 2 to the file reading means 20. The file reading means 20 stores the LSI external net information 31 shown in FIG.
From rows 3 to 13 of the above, using the external net name in column A as a key,
The source synchronous I / O allocable information in column B, the transfer clock in column C, the reference net name in column D, and the distribution clock in column E are set in the association table 1 (see FIG. 8).

Further, the file reading means 20 outputs the I /
From the third and fourth rows of the O partial circuit connection information 32, an external net in column B, an I / O macro name in column A, and a net to the internal logic in column C are set in the list table 2 (see FIG. 9). At this time, a bus description such as X (start bit-end bit) can be written in the columns B and C. For example, in the example of FIG. 6, A (0-15) = A (0), A (1),..., A (15) D (16-23) = D (16),. 23)

Further, the file reading means 20 outputs
From the third and fourth rows of the O macro specification information 33, the macro net in column A is used as a key to associate the external net in column B, the distribution clock in column C, the reference net name in column D, and the net to the internal logic in column E. Set on table 3 (see FIG. 10).
The above is the file reading means 20 in step A1.
This is the process. Table 2 of FIG. 9 which is a list table
Paying attention to the record in the third row, the external net is A (0
-15), X2SCKT and X2SCKC. From now on, the bus description A (0-15) will be expanded to A
(0), A (1), ..., A (15), X2SCK
T, X2SCKC is obtained. The first external net A (0) searches the association table 1 (see FIG. 8) and finds that the external net is A
The data of (0) is obtained.

Further, when the associative table 3 (see FIG. 10) is searched using SSX2, which is the used I / O macro (ie, the macro in the third row of table 2), as a key,
The data having the macro name SSX2 is obtained (step A4).
Since the assignable macro name SSX2 of the source synchronous I / O allocable information (9 rows and B columns) obtained from Table 1 matches the macro name SSX2 used,
An appropriate arrangement is confirmed by an arrangement check (step B1). Since the assignment check is the first net, ID1 is stored (steps B3 and B4). The transfer clock connectivity check is not processed because the transfer clock (9 rows and C columns) obtained from Table 1 is empty (steps A6 and C1).

Next, the external net D in the macro of Table 3
(0) to A (0), net to internal logic is DAT
(0) is the distribution clock CLK and the reference net REF are the distribution clock XCLK + of the corresponding table 1 (9 rows, D columns, E columns).
00, rules for connecting to the reference net XREF + 02 are generated (step A7). Such processing is repeated for the external net set (steps A3 to A3).
A7). Further, the processing for one source synchronous I / O is repeated until the end of the list table 2 (steps A2 to A7).

Finally, the connection / hierarchy assembling means 23
According to the signal line connection rule, the I / O macro netlist is connected, the hierarchy of the I / O partial circuit is assembled, and the netlist is created. Further, the hierarchy expanding means 24 expands the netlist of the circuit of the I / O part created by the connection / hierarchy assembling means 23 to the primitive block level, and outputs it to the storage device 2 as the I / O partial circuit netlist 36. .

As described above, the netlist generation method for an integrated circuit according to the present embodiment is, at least, in the netlist generation method for an integrated circuit for generating a netlist of a source synchronous I / O partial circuit. A plurality of external net names and associated with the external net names,
Placeable information including a plurality of I / O soft macro names that can be placed in a predetermined area and allocation information indicating a type of allocation is stored, and external net information regarding each external terminal of the integrated circuit to be logically designed is stored. Integrated circuit external net information storage means, and at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names are stored, and an I / O target for which a net list is to be generated is stored.
I / O partial circuit connection information storage means for storing connection information inside the / O partial circuit, and at least a plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names I / O macro specification information storage means for storing information on the specifications of I / O soft macros used for generating a netlist, the integrated circuit external net information storage means, and I / O partial circuit connection information storage Reading the external net information, the connection information inside the I / O partial circuit, and the information on the specification of the I / O soft macro from the I / O macro specification information storage means, and reading the information from at least the integrated circuit external net information storage means. A first table storing a plurality of read external net names and a plurality of allocable information associated with the external net names; A second table storing a plurality of external net names read from the I / O partial circuit connection information storage means and a plurality of I / O soft macro names associated with the external net names; The plurality of I / O soft macro names read from the macro specification information storage means and a third table storing a plurality of external net names associated with the I / O soft macro names are read and stored in the storage means. Reading means, checking means for checking whether the arrangement and allocation of the I / O soft macros are appropriate, and reading means when the checking means determines that the arrangement and allocation of the I / O soft macros are appropriate. Net list generating means for generating a net list of the I / O partial circuit based on the read information,
The inspection unit searches the first table for each external net name in the second table based on the external net name in the second table, and corresponds to the external net name in the second table. An I / O soft macro name included in the allocable information of the first table is extracted, and an I / O soft macro name associated with the external net name of the second table is extracted.
When the O soft macro name matches the I / O soft macro name included in the allocable information of the first table, it is determined that the I / O soft macro is correct.
The first table is searched based on the external net name of the table, and the allocation information included in the allocable information of the first table corresponding to the external net name of the second table is extracted and stored. Having an assignment information storage means, for each of the external net names in the second table, after storing the assignment information of the first net in the assignment information storage means, based on the external net name in the second table; Allocation information included in the allocable information of the first table, which is obtained by searching the first table and corresponds to the external net name of the second table, is stored in the allocation information storage means. When the information matches, the allocation of the I / O soft macro is determined to be appropriate. Therefore, the external net for connecting to the macro can be allocated by referring to the source synchronous I / O macro allocable information of the LSI external net information 31, and the validity of the allocation and allocation can be automatically checked. In creating an I / O partial circuit netlist including a source synchronous I / O having a soft macro configuration, it is possible to appropriately and efficiently allocate the I / O partial circuit netlist to a predetermined allocable area on a base of an integrated circuit.

Further, according to the present embodiment, the transfer clock net name previously described in the LSI external net information 31 is matched with the transfer clock net name in the source synchronous I / O macro actually connected. Therefore, the transfer clock (positive polarity, negative polarity) of the source synchronous I / O can be accurately connected. Further, since the connection is automatically made based on the reference net name to be actually connected which is described in advance in the LSI external net information 31, the connection of the reference signal which is a common signal of the source synchronous I / O is set to I The connection can be made without the description of the / O partial circuit netlist creator.

Also, since a soft macro configuration is possible, there is an effect that it is not necessary to convert the source synchronous I / O into a hard macro. Further, the program according to the present embodiment is configured to cause a computer to function as described above. Therefore, the above-described effects can be obtained by causing the computer to execute the program.

[0059]

According to the present invention, when creating a netlist of source synchronous I / O partial circuits having a soft macro structure, it is possible to accurately and efficiently allocate the netlist to a placeable area on a base. Also, source synchronous I / O
Is not required to be converted into a hard macro.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 4 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 5 is a diagram showing LSI external net information used in the embodiment of the present invention.

FIG. 6 is a diagram showing I / O partial circuit connection information used in the embodiment of the present invention.

FIG. 7 is a diagram showing I / O macro specification information used in the embodiment of the present invention.

FIG. 8 is a diagram showing a table 1 memory image used in the embodiment of the present invention.

FIG. 9 is a diagram showing a table 2 memory image used in the embodiment of the present invention.

FIG. 10 is a table 3 used in the embodiment of the present invention.
It is a figure showing a memory image.

FIG. 11 is a schematic diagram for explaining a conventional assignment deviation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Data processing device as data processing means 2 ... Storage device as storage means 20 ... File reading means 21 ... Arrangement and assignment check means as inspection means 22 ... Net list generation means 23... Connection / layer stacking means constituting the netlist generating means 24... Hierarchical developing means constituting the netlist generating means 31... As integrated circuit external net information LSI external net information 32 ... I / O partial circuit connection information 33 ... I / O macro specification information 34 ... I / O macro net list 35 ... Library 36 ... I / O partial circuit net list

Claims (12)

[Claims] 1. An integrated circuit netlist generation method for generating a netlist of a source synchronous I / O partial circuit, comprising: an external circuit for storing external net information relating to each external terminal of an integrated circuit to be logically designed; Net information storage means, I / O partial circuit connection information storage means for storing connection information inside an I / O partial circuit for which a net list is generated, and an I / O soft macro used for generating a net list I / O macro specification information storage means for storing information relating to the specification of the integrated circuit; and said external net information from the integrated circuit external net information storage means, I / O partial circuit connection information storage means, and I / O macro specification information storage means. Reading means for reading connection information inside the I / O partial circuit and information relating to the specification of the I / O soft macro; Based on the elaborate information, I / O
Inspection means for inspecting whether the arrangement and allocation of the soft macros are appropriate; and when the inspection means determines that the arrangement and allocation of the I / O soft macros are appropriate, the I / O based on the information read by the reading means. A net list generating means for generating a net list of a partial circuit. 2. The integrated circuit external net information storage means includes at least a plurality of external net names and a plurality of I which can be arranged in a predetermined area and are associated with the external net names.
The I / O partial circuit connection information storage means stores at least a plurality of external net names and a plurality of I / O software associated with the external net names. The I / O macro specification information storage means stores at least:
A plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names are stored, and the reading unit reads at least the plurality of the integrated circuit external net information storage units. A first table for storing an external net name and a plurality of allocable information associated with the external net name;
A second table storing a plurality of external net names read from the O partial circuit connection information storage means and a plurality of I / O soft macro names associated with the external net names, and at least the I / O macro specifications A plurality of I / O soft macro names read from the information storage means and the I / O soft macro names;
And a third table storing a plurality of external net names associated with the / O soft macro name, and storing the read third table in the storage means, wherein the inspection means determines, for each external net name in the second table, The first table is searched based on the external net name of the second table, and the I / O soft macro name included in the allocable information of the first table corresponding to the external net name of the second table is retrieved. I / O extracted and associated with the external net name in the second table
2. The integrated circuit netlist according to claim 1, wherein when the O soft macro name matches the I / O soft macro name included in the allocable information of the first table, it is determined that the layout is proper. Generation method. 3. The arrangement information includes allocation information indicating a type of allocation, and the inspection unit searches the first table based on an external net name of the second table. And allocation information storage means for extracting and storing allocation information included in the allocable information of the first table corresponding to the external net name of the second table. The second name obtained by storing the allocation information of the first net in the allocation information storage means for the net name, and then searching the first table based on the external net name of the second table. If the allocation information included in the allocable information of the first table corresponding to the external net name of the table matches the allocation information stored in the allocation information storage means, the allocation of the I / O soft macro is properly performed. Netlist generation method of an integrated circuit according to claim 2, wherein the determining. 4. The integrated circuit external net information storage means includes a transfer clock net name that is information relating to a transfer clock, a reference net name that is information relating to a reference signal, and a distribution clock that are associated with the external net name. And the I / O partial connection information storage means,
The I / O macro specification information storage means stores a distribution clock name, a reference name, and an internal name associated with the I / O macro name. 4. The netlist generation method for an integrated circuit according to claim 1, wherein a net name for the logic is stored. 5. An integrated circuit netlist generation method for generating a netlist of source synchronous I / O partial circuits, comprising: at least a plurality of external net names; and I / O software which can be arranged in association with the external net names. First storage means for storing external net information relating to each external terminal of an integrated circuit to be logically designed, including a plurality of allocable information having allocation information indicating a macro name and an allocation type; Second storage means for storing connection information inside an I / O partial circuit for which a net list is to be generated, including a net name and a plurality of I / O soft macro names associated with the external net name; At least a plurality of I / O soft macro names and said I / O
Third storage means for storing information relating to specifications of an I / O soft macro used for generating a net list, including a plurality of external net names associated with the soft macro name; Checking means for checking whether or not the allocation is appropriate; allocation information storing means for storing allocation information included in the allocable information; when the checking means determines that the allocation and allocation of the I / O soft macros are appropriate And a net list generating means for generating a net list of the I / O partial circuit, wherein the checking means checks each of the external net names in the second storage means based on the external net names. The first storage unit is searched to extract the allocable information of the first storage unit corresponding to the external net name of the second storage unit, and the extracted information is stored in the external net name of the second storage unit. When the associated I / O soft macro name and the I / O soft macro name included in the allocable information in the first storage unit match, it is determined that the arrangement is appropriate and included in the allocable information. After storing the allocation information of the first net to be allocated in the allocation information storage means and storing the allocation information in the allocation information storage means, the first storage means is stored on the basis of the external net name of the second storage means. Allocation information included in the allocable information of the first storage unit corresponding to the external net name of the second storage unit obtained by the search matches the allocation information stored in the allocation information storage unit. A method of generating a netlist for an integrated circuit, wherein the assignment of an I / O soft macro is determined to be appropriate. 6. The netlist generating means includes: the external net information, connection information inside an I / O partial circuit, and an I / O
Connecting the I / O soft macros according to a connection rule generated by the signal line connection rule generating means for generating a connection rule based on information on the specification of the soft macro;
A connection / hierarchy assembling means for assembling the entire connected I / O soft macro as an I / O partial circuit hierarchy, and a netlist generated by the connection / hierarchy assembling means is expanded to a primitive block level. 6. The netlist generation method for an integrated circuit according to claim 1, further comprising: a hierarchy expanding means for generating a netlist of a desired level. 7. An integrated circuit external net information storage means for storing external net information relating to each external terminal of an integrated circuit to be logically designed, and an I / O partial circuit for generating a net list. I / O partial circuit connection information storage means for storing internal connection information; I / O macro specification information storage means for storing information on specifications of I / O soft macros used for generating a netlist; From the external net information storage means, the I / O partial circuit connection information storage means, and the I / O macro specification information storage means, the external net information, the connection information inside the I / O partial circuit, and the information on the specification of the I / O soft macro. Reading means for reading the I / O, based on the information read by the reading means,
Inspection means for inspecting whether the arrangement and allocation of the soft macros are appropriate; and when the inspection means determines that the arrangement and allocation of the I / O soft macros are appropriate, the I / O based on the information read by the reading means. A program for causing a computer to function as a netlist generating means for generating a netlist of a partial circuit. 8. The computer according to claim 1, wherein said integrated circuit external net information storage means includes at least a plurality of external net names and a plurality of I / O soft macros which can be arranged in a predetermined area associated with said external net names. The I / O partial circuit connection information storage means stores at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names. The I / O macro specification information storage means includes at least:
A plurality of I / O soft macro names and a plurality of external net names associated with the I / O soft macro names are stored, and the read unit reads at least the integrated circuit external net information storage unit. A first table for storing an external net name and a plurality of allocable information associated with the external net name;
A second table storing a plurality of external net names read from the O partial circuit connection information storage means and a plurality of I / O soft macro names associated with the external net names, and at least the I / O macro specifications A plurality of I / O soft macro names read from the information storage means and the I / O soft macro names;
And a third table storing a plurality of external net names associated with the / O soft macro name, and storing the read third table in the storage means, wherein the inspection means determines, for each external net name in the second table, The first table is searched based on the external net name of the second table, and the I / O soft macro name included in the allocable information of the first table corresponding to the external net name of the second table is retrieved. I / O extracted and associated with the external net name in the second table
8. The program according to claim 7, wherein when the O / soft macro name matches the I / O soft macro name included in the allocable information of the first table, the I / O soft macro name is determined to be appropriate. . 9. The computer according to claim 6, wherein each of said allocable information includes allocation information indicating a type of allocation, and said checking means reads said first table based on an external net name of said second table. An allocation information storage unit for searching and extracting allocation information included in the allocable information of the first table corresponding to the external net name of the second table, and storing the extracted allocation information; For the external net name, after storing the allocation information of the first net in the allocation information storage means, the second table obtained by searching the first table based on the external net name of the second table, When the allocation information included in the allocable information of the first table corresponding to the external net name of the second table matches the allocation information stored in the allocation information storage means, the I / O soft macro According to claim 8, wherein the program for causing a function to determine with proper. 10. A computer, further comprising: a transfer clock net name as information relating to a transfer clock, and a reference net name as information relating to a reference signal, wherein the integrated circuit external net information storage means is associated with the external net name. And a distribution clock name which is information on the distribution clock.
The O partial connection information storage means stores a net name to the internal logic associated with the I / O soft macro name, and the I / O macro specification information storage means stores the net name for the I / O soft macro name. The program according to any one of claims 7 to 9, wherein the program is operable to store an associated distribution clock name, reference name, and net name to internal logic. 11. A computer comprising: at least a plurality of external net names; a plurality of I / O soft macro names associated with the external net names; and a plurality of allocable information having allocation information indicating a type of allocation. First storage means for storing external net information relating to each external terminal of an integrated circuit to be logically designed; at least a plurality of external net names and a plurality of I / O soft macro names associated with the external net names Second storage means for storing connection information inside an I / O partial circuit for which a netlist is generated, at least a plurality of I / O soft macro names and the I / O
Third storage means for storing information relating to specifications of an I / O soft macro used for generating a net list, including a plurality of external net names associated with the soft macro name; Checking means for checking whether or not the allocation is appropriate; allocation information storing means for storing allocation information included in the allocable information; when the checking means determines that the allocation and allocation of the I / O soft macros are appropriate And a net list generating means for generating a net list of the I / O partial circuit, wherein the checking means checks each of the external net names in the second storage means based on the external net names. The first storage unit is searched to extract the allocable information of the first storage unit corresponding to the external net name of the second storage unit, and the extracted information is stored in the external net name of the second storage unit. When the associated I / O soft macro name and the I / O soft macro name included in the allocable information in the first storage unit match, it is determined that the arrangement is appropriate and included in the allocable information. After storing the allocation information of the first net to be allocated in the allocation information storage means and storing the allocation information in the allocation information storage means, the first storage means is stored on the basis of the external net name of the second storage means. Allocation information included in the allocable information of the first storage unit corresponding to the external net name of the second storage unit obtained by the search matches the allocation information stored in the allocation information storage unit. A program for causing the I / O soft macro to be properly assigned. 12. The computer, wherein the net list generating means includes the external net information,
A signal line connection rule generating means for generating a connection rule based on the connection information inside the / O partial circuit and information on the specification of the I / O soft macro; and a connection rule generated by the signal line connection rule generating means. Connect between I / O soft macros,
A connection / hierarchy assembling means for assembling the entire connected I / O soft macro as an I / O partial circuit hierarchy, and a netlist generated by the connection / hierarchy assembling means is expanded to a primitive block level. 12. The program according to claim 7, wherein the program has a function as a hierarchy expanding unit that generates a netlist of a desired level.